1/* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
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100 const seg_entry *seg; /* segment for memory operands (if given) */
101
102 /* PREFIX holds all the given prefix opcodes (usually null).
103 PREFIXES is the size of PREFIX. */
104 /* richfix: really unsigned? */
105 unsigned char prefix[MAX_PREFIXES];
106 unsigned int prefixes;
107
108 /* RM and IB are the modrm byte and the base index byte where the
109 addressing modes of this insn are encoded. */
110
111 modrm_byte rm;
112 base_index_byte bi;
113 };
114
115typedef struct _i386_insn i386_insn;
116
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297 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
298 static const char f32_14[] =
299 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
300 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
301 static const char f32_15[] =
302 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
303 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
304 static const char f16_4[] =
305 {0x8d,0xb6,0x00,0x00}; /* lea 0w(%si),%si */
306 static const char f16_5[] =
307 {0x90, /* nop */
308 0x8d,0xb6,0x00,0x00}; /* lea 0w(%si),%si */
309 static const char f16_6[] =
310 {0x89,0xf6, /* mov %si,%si */
311 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
312 static const char f16_7[] =
313 {0x8d,0x76,0x00, /* lea 0(%si),%si */
314 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
315 static const char f16_8[] =
316 {0x8d,0xb6,0x00,0x00, /* lea 0w(%si),%si */
317 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
318 static const char *const f32_patt[] = {
319 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
320 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
321 };
322 static const char *const f16_patt[] = {
323 f32_1, f32_2, f32_3, f16_4, f16_5, f16_6, f16_7, f16_8,
324 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
--- 103 unchanged lines hidden (view full) ---
428 flag_16bit_code = new_16bit_code_flag;
429}
430
431const pseudo_typeS md_pseudo_table[] =
432{
433#ifndef I386COFF
434 {"bss", s_bss, 0},
435#endif
436#ifndef OBJ_AOUT
437 {"align", s_align_bytes, 0},
438#else
439 {"align", s_align_ptwo, 0},
440#endif
441 {"ffloat", float_cons, 'f'},
442 {"dfloat", float_cons, 'd'},
443 {"tfloat", float_cons, 'x'},
444 {"value", cons, 2},
--- 352 unchanged lines hidden (view full) ---
797 * the beginning of the section instead of the symbol. Basically we need
798 * to make sure that the dynamic relocations are done correctly, so in
799 * some cases we force the original symbol to be used.
800 */
801int
802tc_i386_fix_adjustable(fixP)
803 fixS * fixP;
804{
805#ifndef OBJ_AOUT
806 /* Prevent all adjustments to global symbols. */
807 if (S_IS_EXTERN (fixP->fx_addsy))
808 return 0;
809 if (S_IS_WEAK (fixP->fx_addsy))
810 return 0;
811#endif /* ! defined (OBJ_AOUT) */
812 /* adjust_reloc_syms doesn't know about the GOT */
813 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
--- 14 unchanged lines hidden (view full) ---
828/* This is the guts of the machine-dependent assembler. LINE points to a
829 machine dependent instruction. This function is supposed to emit
830 the frags/bytes it assembles to. */
831
832void
833md_assemble (line)
834 char *line;
835{
836 /* Holds template once we've found it. */
837 template *t;
838
839 /* Count the size of the instruction generated. */
840 int insn_size = 0;
841
842 /* Possible templates for current insn */
843 templates *current_templates = (templates *) 0;
844
845 int j;
846
847 /* Initialize globals. */
848 memset (&i, '\0', sizeof (i));
849 for (j = 0; j < MAX_OPERANDS; j++)
850 i.disp_reloc[j] = NO_RELOC;
851 memset (disp_expressions, '\0', sizeof (disp_expressions));
852 memset (im_expressions, '\0', sizeof (im_expressions));
853 save_stack_p = save_stack; /* reset stack pointer */
854
855 /* Fist parse an opcode & call i386_operand for the operands.
856 We assume that the scrubber has arranged it so that line[0] is the valid
857 start of a (possibly prefixed) opcode. */
858 {
859 char *l = line;
860
861 /* 1 if operand is pending after ','. */
862 unsigned int expecting_operand = 0;
863 /* 1 if we found a prefix only acceptable with string insns. */
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899 RESTORE_END_STRING (l);
900 /* check for repeated prefix */
901 for (q = 0; q < i.prefixes; q++)
902 if (i.prefix[q] == prefix->prefix_code)
903 {
904 as_bad ("same prefix used twice; you don't really want this!");
905 return;
906 }
907 if (i.prefixes == MAX_PREFIXES)
908 {
909 as_bad ("too many opcode prefixes");
910 return;
911 }
912 i.prefix[i.prefixes++] = prefix->prefix_code;
913 if (prefix->prefix_code == REPE || prefix->prefix_code == REPNE)
914 expecting_string_instruction = 1;
915 /* skip past PREFIX_SEPERATOR and reset token_start */
916 token_start = ++l;
917 }
918 }
919 END_STRING_AND_SAVE (l);
920 if (token_start == l)
921 {
922 as_bad ("expecting opcode; got nothing");
--- 203 unchanged lines hidden (view full) ---
1126 continue;
1127
1128 /* try reversing direction of operands */
1129 overlap0 = i.types[0] & t->operand_types[1];
1130 overlap1 = i.types[1] & t->operand_types[0];
1131 if (!MATCH (overlap0, i.types[0]) ||
1132 !MATCH (overlap1, i.types[1]) ||
1133 !CONSISTENT_REGISTER_MATCH (overlap0, overlap1,
1134 t->operand_types[0],
1135 t->operand_types[1]))
1136 {
1137 /* does not match either direction */
1138 continue;
1139 }
1140 /* found a reverse match here -- slip through */
1141 /* found_reverse_match holds which of D or FloatD we've found */
1142 found_reverse_match = t->opcode_modifier & COMES_IN_BOTH_DIRECTIONS;
1143 } /* endif: not forward match */
--- 16 unchanged lines hidden (view full) ---
1160 break; /* we've found a match; break out of loop */
1161 } /* for (t = ... */
1162 if (t == current_templates->end)
1163 { /* we found no match */
1164 as_bad ("operands given don't match any known 386 instruction");
1165 return;
1166 }
1167
1168 /* Copy the template we found (we may change it!). */
1169 i.tm = *t;
1170 t = &i.tm; /* alter new copy of template */
1171
1172 /* If the matched instruction specifies an explicit opcode suffix,
1173 use it - and make sure none has already been specified. */
1174 if (t->opcode_modifier & (Data16|Data32))
1175 {
1176 if (i.suffix)
1177 {
1178 as_bad ("extraneous opcode suffix given");
1179 return;
1180 }
1181 if (t->opcode_modifier & Data16)
1182 i.suffix = WORD_OPCODE_SUFFIX;
1183 else
1184 i.suffix = DWORD_OPCODE_SUFFIX;
1185 }
1186
1187 /* If there's no opcode suffix we try to invent one based on register
1188 operands. */
1189 if (!i.suffix && i.reg_operands)
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1270 i.reg_operands--;
1271 if (overlap1 & ImplicitRegister)
1272 i.reg_operands--;
1273 if (overlap2 & ImplicitRegister)
1274 i.reg_operands--;
1275 if (overlap0 & Imm1)
1276 i.imm_operands = 0; /* kludge for shift insns */
1277
1278 if (found_reverse_match)
1279 {
1280 unsigned int save;
1281 save = t->operand_types[0];
1282 t->operand_types[0] = t->operand_types[1];
1283 t->operand_types[1] = save;
1284 }
1285
1286 /* Finalize opcode. First, we change the opcode based on the operand
1287 size given by i.suffix: we never have to change things for byte insns,
1288 or when no opcode suffix is need to size the operands. */
1289
1290 if (!i.suffix && (t->opcode_modifier & W))
1291 {
1292 as_bad ("no opcode suffix given and no register operands; can't size instruction");
1293 return;
1294 }
1295
1296 if (i.suffix && i.suffix != BYTE_OPCODE_SUFFIX)
1297 {
1298 /* Select between byte and word/dword operations. */
1299 if (t->opcode_modifier & W)
1300 t->base_opcode |= W;
1301 /* Now select between word & dword operations via the
1302 operand size prefix. */
1303 if ((i.suffix == WORD_OPCODE_SUFFIX) ^ flag_16bit_code)
1304 {
1305 if (i.prefixes == MAX_PREFIXES)
1306 {
1307 as_bad ("%d prefixes given and 'w' opcode suffix gives too many prefixes",
1308 MAX_PREFIXES);
1309 return;
1310 }
1311 i.prefix[i.prefixes++] = WORD_PREFIX_OPCODE;
1312 }
1313 }
1314
1315 /* For insns with operands there are more diddles to do to the opcode. */
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1326
1327
1328 /* If we found a reverse match we must alter the opcode direction bit
1329 found_reverse_match holds bit to set (different for int &
1330 float insns). */
1331
1332 if (found_reverse_match)
1333 {
1334 t->base_opcode |= found_reverse_match;
1335 }
1336
1337 /* The imul $imm, %reg instruction is converted into
1338 imul $imm, %reg, %reg. */
1339 if (t->opcode_modifier & imulKludge)
1340 {
1341 /* Pretend we saw the 3 operand case. */
1342 i.regs[2] = i.regs[1];
1343 i.reg_operands = 2;
1344 }
1345
1346 /* The clr %reg instruction is converted into xor %reg, %reg. */
1347 if (t->opcode_modifier & iclrKludge)
1348 {
1349 i.regs[1] = i.regs[0];
1350 i.reg_operands = 2;
1351 }
1352
1353 /* Certain instructions expect the destination to be in the i.rm.reg
1354 field. This is by far the exceptional case. For these
1355 instructions, if the source operand is a register, we must reverse
1356 the i.rm.reg and i.rm.regmem fields. We accomplish this by faking
1357 that the two register operands were given in the reverse order. */
1358 if ((t->opcode_modifier & ReverseRegRegmem) && i.reg_operands == 2)
1359 {
1360 unsigned int first_reg_operand = (i.types[0] & Reg) ? 0 : 1;
1361 unsigned int second_reg_operand = first_reg_operand + 1;
1362 reg_entry *tmp = i.regs[first_reg_operand];
1363 i.regs[first_reg_operand] = i.regs[second_reg_operand];
1364 i.regs[second_reg_operand] = tmp;
1365 }
1366
1367 if (t->opcode_modifier & ShortForm)
1368 {
1369 /* The register or float register operand is in operand 0 or 1. */
1370 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
1371 /* Register goes in low 3 bits of opcode. */
1372 t->base_opcode |= i.regs[op]->reg_num;
1373 }
1374 else if (t->opcode_modifier & ShortFormW)
1375 {
1376 /* Short form with 0x8 width bit. Register is always dest. operand */
1377 t->base_opcode |= i.regs[1]->reg_num;
1378 if (i.suffix == WORD_OPCODE_SUFFIX ||
1379 i.suffix == DWORD_OPCODE_SUFFIX)
1380 t->base_opcode |= 0x8;
1381 }
1382 else if (t->opcode_modifier & Seg2ShortForm)
1383 {
1384 if (t->base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1)
1385 {
1386 as_bad ("you can't 'pop cs' on the 386.");
1387 return;
1388 }
1389 t->base_opcode |= (i.regs[0]->reg_num << 3);
1390 }
1391 else if (t->opcode_modifier & Seg3ShortForm)
1392 {
1393 /* 'push %fs' is 0x0fa0; 'pop %fs' is 0x0fa1.
1394 'push %gs' is 0x0fa8; 'pop %fs' is 0x0fa9.
1395 So, only if i.regs[0]->reg_num == 5 (%gs) do we need
1396 to change the opcode. */
1397 if (i.regs[0]->reg_num == 5)
1398 t->base_opcode |= 0x08;
1399 }
1400 else if ((t->base_opcode & ~DW) == MOV_AX_DISP32)
1401 {
1402 /* This is a special non-modrm instruction
1403 that addresses memory with a 32-bit displacement mode anyway,
1404 and thus requires an address-size prefix if in 16-bit mode. */
1405 uses_mem_addrmode = 1;
1406 default_seg = &ds;
1407 }
1408 else if (t->opcode_modifier & Modrm)
1409 {
1410 /* The opcode is completed (modulo t->extension_opcode which must
1411 be put into the modrm byte.
1412 Now, we make the modrm & index base bytes based on all the info
1413 we've collected. */
1414
1415 /* i.reg_operands MUST be the number of real register operands;
1416 implicit registers do not count. */
1417 if (i.reg_operands == 2)
1418 {
1419 unsigned int source, dest;
1420 source = ((i.types[0]
1421 & (Reg
--- 135 unchanged lines hidden (view full) ---
1557 {
1558 seg_index = (i.rm.mode << 3) | i.rm.regmem;
1559 default_seg = one_byte_segment_defaults[seg_index];
1560 }
1561 }
1562 }
1563
1564 /* Fill in i.rm.reg or i.rm.regmem field with register
1565 operand (if any) based on
1566 t->extension_opcode. Again, we must be careful to
1567 make sure that segment/control/debug/test/MMX
1568 registers are coded into the i.rm.reg field. */
1569 if (i.reg_operands)
1570 {
1571 unsigned int op =
1572 ((i.types[0]
1573 & (Reg | SReg2 | SReg3 | Control | Debug
1574 | Test | RegMMX))
1575 ? 0
1576 : ((i.types[1]
1577 & (Reg | SReg2 | SReg3 | Control | Debug
1578 | Test | RegMMX))
1579 ? 1
1580 : 2));
1581 /* If there is an extension opcode to put here, the
1582 register number must be put into the regmem field. */
1583 if (t->extension_opcode != None)
1584 i.rm.regmem = i.regs[op]->reg_num;
1585 else
1586 i.rm.reg = i.regs[op]->reg_num;
1587
1588 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
1589 we must set it to 3 to indicate this is a register
1590 operand int the regmem field */
1591 if (!i.mem_operands)
1592 i.rm.mode = 3;
1593 }
1594
1595 /* Fill in i.rm.reg field with extension opcode (if any). */
1596 if (t->extension_opcode != None)
1597 i.rm.reg = t->extension_opcode;
1598 }
1599
1600 if (i.rm.mode != 3)
1601 uses_mem_addrmode = 1;
1602 }
1603
1604 /* GAS currently doesn't support 16-bit memory addressing modes at all,
1605 so if we're writing 16-bit code and using a memory addressing mode,
--- 24 unchanged lines hidden (view full) ---
1630 return;
1631 }
1632 i.prefix[i.prefixes++] = i.seg->seg_prefix;
1633 }
1634 }
1635 }
1636
1637 /* Handle conversion of 'int $3' --> special int3 insn. */
1638 if (t->base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3)
1639 {
1640 t->base_opcode = INT3_OPCODE;
1641 i.imm_operands = 0;
1642 }
1643
1644 /* We are ready to output the insn. */
1645 {
1646 register char *p;
1647
1648 /* Output jumps. */
1649 if (t->opcode_modifier & Jump)
1650 {
1651 unsigned long n = i.disps[0]->X_add_number;
1652
1653 if (i.disps[0]->X_op == O_constant)
1654 {
1655 if (fits_in_signed_byte (n))
1656 {
1657 p = frag_more (2);
1658 insn_size += 2;
1659 p[0] = t->base_opcode;
1660 p[1] = n;
1661 }
1662 else
1663 { /* It's an absolute word/dword displacement. */
1664
1665 /* Use only 16-bit jumps for 16-bit code,
1666 because text segments are limited to 64K anyway;
1667 use only 32-bit jumps for 32-bit code,
1668 because they're faster. */
1669 int jmp_size = flag_16bit_code ? 2 : 4;
1670 if (flag_16bit_code && !fits_in_signed_word (n))
1671 {
1672 as_bad ("16-bit jump out of range");
1673 return;
1674 }
1675
1676 if (t->base_opcode == JUMP_PC_RELATIVE)
1677 { /* pace */
1678 /* unconditional jump */
1679 p = frag_more (1 + jmp_size);
1680 insn_size += 1 + jmp_size;
1681 p[0] = (char) 0xe9;
1682 md_number_to_chars (&p[1], (valueT) n, jmp_size);
1683 }
1684 else
1685 {
1686 /* conditional jump */
1687 p = frag_more (2 + jmp_size);
1688 insn_size += 2 + jmp_size;
1689 p[0] = TWO_BYTE_OPCODE_ESCAPE;
1690 p[1] = t->base_opcode + 0x10;
1691 md_number_to_chars (&p[2], (valueT) n, jmp_size);
1692 }
1693 }
1694 }
1695 else
1696 {
1697 if (flag_16bit_code)
1698 {
1699 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1700 insn_size += 1;
1701 }
1702
1703 /* It's a symbol; end frag & setup for relax.
1704 Make sure there are more than 6 chars left in the current frag;
1705 if not we'll have to start a new one. */
1706 frag_grow (7);
1707 p = frag_more (1);
1708 insn_size += 1;
1709 p[0] = t->base_opcode;
1710 frag_var (rs_machine_dependent,
1711 6, /* 2 opcode/prefix + 4 displacement */
1712 1,
1713 ((unsigned char) *p == JUMP_PC_RELATIVE
1714 ? ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE)
1715 : ENCODE_RELAX_STATE (COND_JUMP, BYTE)),
1716 i.disps[0]->X_add_symbol,
1717 (offsetT) n, p);
1718 }
1719 }
1720 else if (t->opcode_modifier & (JumpByte | JumpDword))
1721 {
1722 int size = (t->opcode_modifier & JumpByte) ? 1 : 4;
1723 unsigned long n = i.disps[0]->X_add_number;
1724 unsigned char *q;
1725
1726 /* The jcx/jecx instruction might need a data size prefix. */
1727 for (q = i.prefix; q < i.prefix + i.prefixes; q++)
1728 {
1729 if (*q == WORD_PREFIX_OPCODE)
1730 {
1731 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1732 insn_size += 1;
1733 break;
1734 }
1735 }
1736
1737 if ((size == 4) && (flag_16bit_code))
1738 {
1739 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1740 insn_size += 1;
1741 }
1742
1743 if (fits_in_unsigned_byte (t->base_opcode))
1744 {
1745 FRAG_APPEND_1_CHAR (t->base_opcode);
1746 insn_size += 1;
1747 }
1748 else
1749 {
1750 p = frag_more (2); /* opcode can be at most two bytes */
1751 insn_size += 2;
1752 /* put out high byte first: can't use md_number_to_chars! */
1753 *p++ = (t->base_opcode >> 8) & 0xff;
1754 *p = t->base_opcode & 0xff;
1755 }
1756
1757 p = frag_more (size);
1758 insn_size += size;
1759 if (i.disps[0]->X_op == O_constant)
1760 {
1761 md_number_to_chars (p, (valueT) n, size);
1762 if (size == 1 && !fits_in_signed_byte (n))
--- 4 unchanged lines hidden (view full) ---
1767 }
1768 else
1769 {
1770 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
1771 i.disps[0], 1, reloc (size, 1, i.disp_reloc[0]));
1772
1773 }
1774 }
1775 else if (t->opcode_modifier & JumpInterSegment)
1776 {
1777 if (flag_16bit_code)
1778 {
1779 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1780 insn_size += 1;
1781 }
1782
1783 p = frag_more (1 + 2 + 4); /* 1 opcode; 2 segment; 4 offset */
1784 insn_size += 1 + 2 + 4;
1785 p[0] = t->base_opcode;
1786 if (i.imms[1]->X_op == O_constant)
1787 md_number_to_chars (p + 1, (valueT) i.imms[1]->X_add_number, 4);
1788 else
1789 fix_new_exp (frag_now, p + 1 - frag_now->fr_literal, 4,
1790 i.imms[1], 0, BFD_RELOC_32);
1791 if (i.imms[0]->X_op != O_constant)
1792 as_bad ("can't handle non absolute segment in long call/jmp");
1793 md_number_to_chars (p + 5, (valueT) i.imms[0]->X_add_number, 2);
1794 }
1795 else
1796 {
1797 /* Output normal instructions here. */
1798 unsigned char *q;
1799
1800 /* First the prefix bytes. */
1801 for (q = i.prefix; q < i.prefix + i.prefixes; q++)
1802 {
1803 p = frag_more (1);
1804 insn_size += 1;
1805 md_number_to_chars (p, (valueT) *q, 1);
1806 }
1807
1808 /* Now the opcode; be careful about word order here! */
1809 if (fits_in_unsigned_byte (t->base_opcode))
1810 {
1811 FRAG_APPEND_1_CHAR (t->base_opcode);
1812 insn_size += 1;
1813 }
1814 else if (fits_in_unsigned_word (t->base_opcode))
1815 {
1816 p = frag_more (2);
1817 insn_size += 2;
1818 /* put out high byte first: can't use md_number_to_chars! */
1819 *p++ = (t->base_opcode >> 8) & 0xff;
1820 *p = t->base_opcode & 0xff;
1821 }
1822 else
1823 { /* opcode is either 3 or 4 bytes */
1824 if (t->base_opcode & 0xff000000)
1825 {
1826 p = frag_more (4);
1827 insn_size += 4;
1828 *p++ = (t->base_opcode >> 24) & 0xff;
1829 }
1830 else
1831 {
1832 p = frag_more (3);
1833 insn_size += 3;
1834 }
1835 *p++ = (t->base_opcode >> 16) & 0xff;
1836 *p++ = (t->base_opcode >> 8) & 0xff;
1837 *p = (t->base_opcode) & 0xff;
1838 }
1839
1840 /* Now the modrm byte and base index byte (if present). */
1841 if (t->opcode_modifier & Modrm)
1842 {
1843 p = frag_more (1);
1844 insn_size += 1;
1845 /* md_number_to_chars (p, i.rm, 1); */
1846 md_number_to_chars (p,
1847 (valueT) (i.rm.regmem << 0
1848 | i.rm.reg << 3
1849 | i.rm.mode << 6),
--- 235 unchanged lines hidden (view full) ---
2085 }
2086
2087 exp = &im_expressions[i.imm_operands++];
2088 i.imms[this_operand] = exp;
2089 save_input_line_pointer = input_line_pointer;
2090 input_line_pointer = ++op_string; /* must advance op_string! */
2091 SKIP_WHITESPACE ();
2092 exp_seg = expression (exp);
2093 input_line_pointer = save_input_line_pointer;
2094
2095 if (exp->X_op == O_absent)
2096 {
2097 /* missing or bad expr becomes absolute 0 */
2098 as_bad ("missing or invalid immediate expression '%s' taken as 0",
2099 operand_string);
2100 exp->X_op = O_constant;
--- 53 unchanged lines hidden (view full) ---
2154 if (i.mem_operands == MAX_MEMORY_OPERANDS)
2155 {
2156 as_bad ("more than 1 memory reference in instruction");
2157 return 0;
2158 }
2159 i.mem_operands++;
2160
2161 /* Determine type of memory operand from opcode_suffix;
2162 no opcode suffix implies general memory references. */
2163 switch (i.suffix)
2164 {
2165 case BYTE_OPCODE_SUFFIX:
2166 i.types[this_operand] |= Mem8;
2167 break;
2168 case WORD_OPCODE_SUFFIX:
2169 i.types[this_operand] |= Mem16;
2170 break;
--- 154 unchanged lines hidden (view full) ---
2325 char *save_input_line_pointer;
2326 exp = &disp_expressions[i.disp_operands];
2327 i.disps[this_operand] = exp;
2328 i.disp_reloc[this_operand] = NO_RELOC;
2329 i.disp_operands++;
2330 save_input_line_pointer = input_line_pointer;
2331 input_line_pointer = displacement_string_start;
2332 END_STRING_AND_SAVE (displacement_string_end);
2333#ifndef LEX_AT
2334 {
2335 /*
2336 * We can have operands of the form
2337 * <symbol>@GOTOFF+<nnn>
2338 * Take the easy way out here and copy everything
2339 * into a temporary buffer...
2340 */
2341 register char *cp;
2342 if ((cp = strchr (input_line_pointer,'@')) != NULL) {
2343 char tmpbuf[BUFSIZ];
2344
2345 if(!GOT_symbol)
2346 GOT_symbol = symbol_find_or_make(GLOBAL_OFFSET_TABLE_NAME);
2347
2348 if (strncmp(cp+1, "PLT", 3) == 0) {
2349 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
2350 *cp = '\0';
2351 strcpy(tmpbuf, input_line_pointer);
2352 strcat(tmpbuf, cp+1+3);
2353 *cp = '@';
2354 } else if (strncmp(cp+1, "GOTOFF", 6) == 0) {
2355 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
2356 *cp = '\0';
2357 strcpy(tmpbuf, input_line_pointer);
2358 strcat(tmpbuf, cp+1+6);
2359 *cp = '@';
2360 } else if (strncmp(cp+1, "GOT", 3) == 0) {
2361 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
2362 *cp = '\0';
2363 strcpy(tmpbuf, input_line_pointer);
2364 strcat(tmpbuf, cp+1+3);
2365 *cp = '@';
2366 } else
2367 as_bad("Bad reloc specifier '%s' in expression", cp+1);
2368 input_line_pointer = tmpbuf;
2369 }
2370 }
2371#endif
2372 exp_seg = expression (exp);
2373
2374#ifdef BFD_ASSEMBLER
2375 /* We do this to make sure that the section symbol is in
2376 the symbol table. We will ultimately change the relocation
2377 to be relative to the beginning of the section */
2378 if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF)
2379 {
--- 298 unchanged lines hidden (view full) ---
2678md_apply_fix3 (fixP, valp, seg)
2679 fixS *fixP; /* The fix we're to put in. */
2680 valueT *valp; /* Pointer to the value of the bits. */
2681 segT seg; /* Segment fix is from. */
2682{
2683 register char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
2684 valueT value = *valp;
2685
2686#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
2687 /*
2688 * This is a hack. There should be a better way to
2689 * handle this.
2690 */
2691 if (fixP->fx_r_type == BFD_RELOC_32_PCREL && fixP->fx_addsy)
2692 {
2693#ifndef OBJ_AOUT
2694 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
2695 value += fixP->fx_where + fixP->fx_frag->fr_address;
2696#endif
2697#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2698 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2699 && (S_GET_SEGMENT (fixP->fx_addsy) == seg
2700 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0))
2701 {
2702 /* Yes, we add the values in twice. This is because
2703 bfd_perform_relocation subtracts them out again. I think
2704 bfd_perform_relocation is broken, but I don't dare change
2705 it. FIXME. */
2706 value += fixP->fx_where + fixP->fx_frag->fr_address;
2707 }
2708#endif
2709 }
2710
2711 /* Fix a few things - the dynamic linker expects certain values here,
2712 and we must not dissappoint it. */
2713#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2714 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2715 && fixP->fx_addsy)
2716 switch(fixP->fx_r_type) {
--- 333 unchanged lines hidden (view full) ---
3050 bfd_reloc_code_real_type code;
3051
3052 switch(fixp->fx_r_type)
3053 {
3054 case BFD_RELOC_386_PLT32:
3055 case BFD_RELOC_386_GOT32:
3056 case BFD_RELOC_386_GOTOFF:
3057 case BFD_RELOC_386_GOTPC:
3058 code = fixp->fx_r_type;
3059 break;
3060 default:
3061 switch (F (fixp->fx_size, fixp->fx_pcrel))
3062 {
3063 MAP (1, 0, BFD_RELOC_8);
3064 MAP (2, 0, BFD_RELOC_16);
3065 MAP (4, 0, BFD_RELOC_32);
--- 109 unchanged lines hidden ---
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
--- 89 unchanged lines hidden (view full) ---
100 const seg_entry *seg; /* segment for memory operands (if given) */
101
102 /* PREFIX holds all the given prefix opcodes (usually null).
103 PREFIXES is the size of PREFIX. */
104 /* richfix: really unsigned? */
105 unsigned char prefix[MAX_PREFIXES];
106 unsigned int prefixes;
107
108 /* RM and IB are the modrm byte and the base index byte where the
109 addressing modes of this insn are encoded. */
110
111 modrm_byte rm;
112 base_index_byte bi;
113 };
114
115typedef struct _i386_insn i386_insn;
116
--- 180 unchanged lines hidden (view full) ---
297 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
298 static const char f32_14[] =
299 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
300 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
301 static const char f32_15[] =
302 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
303 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
304 static const char f16_4[] =
305 {0x8d,0xb6,0x00,0x00}; /* lea 0w(%si),%si */
306 static const char f16_5[] =
307 {0x90, /* nop */
308 0x8d,0xb6,0x00,0x00}; /* lea 0w(%si),%si */
309 static const char f16_6[] =
310 {0x89,0xf6, /* mov %si,%si */
311 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
312 static const char f16_7[] =
313 {0x8d,0x76,0x00, /* lea 0(%si),%si */
314 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
315 static const char f16_8[] =
316 {0x8d,0xb6,0x00,0x00, /* lea 0w(%si),%si */
317 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
318 static const char *const f32_patt[] = {
319 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
320 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
321 };
322 static const char *const f16_patt[] = {
323 f32_1, f32_2, f32_3, f16_4, f16_5, f16_6, f16_7, f16_8,
324 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
--- 103 unchanged lines hidden (view full) ---
428 flag_16bit_code = new_16bit_code_flag;
429}
430
431const pseudo_typeS md_pseudo_table[] =
432{
433#ifndef I386COFF
434 {"bss", s_bss, 0},
435#endif
436#ifndef OBJ_AOUT
437 {"align", s_align_bytes, 0},
438#else
439 {"align", s_align_ptwo, 0},
440#endif
441 {"ffloat", float_cons, 'f'},
442 {"dfloat", float_cons, 'd'},
443 {"tfloat", float_cons, 'x'},
444 {"value", cons, 2},
--- 352 unchanged lines hidden (view full) ---
797 * the beginning of the section instead of the symbol. Basically we need
798 * to make sure that the dynamic relocations are done correctly, so in
799 * some cases we force the original symbol to be used.
800 */
801int
802tc_i386_fix_adjustable(fixP)
803 fixS * fixP;
804{
805#ifndef OBJ_AOUT
806 /* Prevent all adjustments to global symbols. */
807 if (S_IS_EXTERN (fixP->fx_addsy))
808 return 0;
809 if (S_IS_WEAK (fixP->fx_addsy))
810 return 0;
811#endif /* ! defined (OBJ_AOUT) */
812 /* adjust_reloc_syms doesn't know about the GOT */
813 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
--- 14 unchanged lines hidden (view full) ---
828/* This is the guts of the machine-dependent assembler. LINE points to a
829 machine dependent instruction. This function is supposed to emit
830 the frags/bytes it assembles to. */
831
832void
833md_assemble (line)
834 char *line;
835{
836 /* Holds template once we've found it. */
837 template *t;
838
839 /* Count the size of the instruction generated. */
840 int insn_size = 0;
841
842 /* Possible templates for current insn */
843 templates *current_templates = (templates *) 0;
844
845 int j;
846
847 /* Initialize globals. */
848 memset (&i, '\0', sizeof (i));
849 for (j = 0; j < MAX_OPERANDS; j++)
850 i.disp_reloc[j] = NO_RELOC;
851 memset (disp_expressions, '\0', sizeof (disp_expressions));
852 memset (im_expressions, '\0', sizeof (im_expressions));
853 save_stack_p = save_stack; /* reset stack pointer */
854
855 /* Fist parse an opcode & call i386_operand for the operands.
856 We assume that the scrubber has arranged it so that line[0] is the valid
857 start of a (possibly prefixed) opcode. */
858 {
859 char *l = line;
860
861 /* 1 if operand is pending after ','. */
862 unsigned int expecting_operand = 0;
863 /* 1 if we found a prefix only acceptable with string insns. */
--- 35 unchanged lines hidden (view full) ---
899 RESTORE_END_STRING (l);
900 /* check for repeated prefix */
901 for (q = 0; q < i.prefixes; q++)
902 if (i.prefix[q] == prefix->prefix_code)
903 {
904 as_bad ("same prefix used twice; you don't really want this!");
905 return;
906 }
907 if (i.prefixes == MAX_PREFIXES)
908 {
909 as_bad ("too many opcode prefixes");
910 return;
911 }
912 i.prefix[i.prefixes++] = prefix->prefix_code;
913 if (prefix->prefix_code == REPE || prefix->prefix_code == REPNE)
914 expecting_string_instruction = 1;
915 /* skip past PREFIX_SEPERATOR and reset token_start */
916 token_start = ++l;
917 }
918 }
919 END_STRING_AND_SAVE (l);
920 if (token_start == l)
921 {
922 as_bad ("expecting opcode; got nothing");
--- 203 unchanged lines hidden (view full) ---
1126 continue;
1127
1128 /* try reversing direction of operands */
1129 overlap0 = i.types[0] & t->operand_types[1];
1130 overlap1 = i.types[1] & t->operand_types[0];
1131 if (!MATCH (overlap0, i.types[0]) ||
1132 !MATCH (overlap1, i.types[1]) ||
1133 !CONSISTENT_REGISTER_MATCH (overlap0, overlap1,
1134 t->operand_types[0],
1135 t->operand_types[1]))
1136 {
1137 /* does not match either direction */
1138 continue;
1139 }
1140 /* found a reverse match here -- slip through */
1141 /* found_reverse_match holds which of D or FloatD we've found */
1142 found_reverse_match = t->opcode_modifier & COMES_IN_BOTH_DIRECTIONS;
1143 } /* endif: not forward match */
--- 16 unchanged lines hidden (view full) ---
1160 break; /* we've found a match; break out of loop */
1161 } /* for (t = ... */
1162 if (t == current_templates->end)
1163 { /* we found no match */
1164 as_bad ("operands given don't match any known 386 instruction");
1165 return;
1166 }
1167
1168 /* Copy the template we found (we may change it!). */
1169 i.tm = *t;
1170 t = &i.tm; /* alter new copy of template */
1171
1172 /* If the matched instruction specifies an explicit opcode suffix,
1173 use it - and make sure none has already been specified. */
1174 if (t->opcode_modifier & (Data16|Data32))
1175 {
1176 if (i.suffix)
1177 {
1178 as_bad ("extraneous opcode suffix given");
1179 return;
1180 }
1181 if (t->opcode_modifier & Data16)
1182 i.suffix = WORD_OPCODE_SUFFIX;
1183 else
1184 i.suffix = DWORD_OPCODE_SUFFIX;
1185 }
1186
1187 /* If there's no opcode suffix we try to invent one based on register
1188 operands. */
1189 if (!i.suffix && i.reg_operands)
--- 80 unchanged lines hidden (view full) ---
1270 i.reg_operands--;
1271 if (overlap1 & ImplicitRegister)
1272 i.reg_operands--;
1273 if (overlap2 & ImplicitRegister)
1274 i.reg_operands--;
1275 if (overlap0 & Imm1)
1276 i.imm_operands = 0; /* kludge for shift insns */
1277
1278 if (found_reverse_match)
1279 {
1280 unsigned int save;
1281 save = t->operand_types[0];
1282 t->operand_types[0] = t->operand_types[1];
1283 t->operand_types[1] = save;
1284 }
1285
1286 /* Finalize opcode. First, we change the opcode based on the operand
1287 size given by i.suffix: we never have to change things for byte insns,
1288 or when no opcode suffix is need to size the operands. */
1289
1290 if (!i.suffix && (t->opcode_modifier & W))
1291 {
1292 as_bad ("no opcode suffix given and no register operands; can't size instruction");
1293 return;
1294 }
1295
1296 if (i.suffix && i.suffix != BYTE_OPCODE_SUFFIX)
1297 {
1298 /* Select between byte and word/dword operations. */
1299 if (t->opcode_modifier & W)
1300 t->base_opcode |= W;
1301 /* Now select between word & dword operations via the
1302 operand size prefix. */
1303 if ((i.suffix == WORD_OPCODE_SUFFIX) ^ flag_16bit_code)
1304 {
1305 if (i.prefixes == MAX_PREFIXES)
1306 {
1307 as_bad ("%d prefixes given and 'w' opcode suffix gives too many prefixes",
1308 MAX_PREFIXES);
1309 return;
1310 }
1311 i.prefix[i.prefixes++] = WORD_PREFIX_OPCODE;
1312 }
1313 }
1314
1315 /* For insns with operands there are more diddles to do to the opcode. */
--- 10 unchanged lines hidden (view full) ---
1326
1327
1328 /* If we found a reverse match we must alter the opcode direction bit
1329 found_reverse_match holds bit to set (different for int &
1330 float insns). */
1331
1332 if (found_reverse_match)
1333 {
1334 t->base_opcode |= found_reverse_match;
1335 }
1336
1337 /* The imul $imm, %reg instruction is converted into
1338 imul $imm, %reg, %reg. */
1339 if (t->opcode_modifier & imulKludge)
1340 {
1341 /* Pretend we saw the 3 operand case. */
1342 i.regs[2] = i.regs[1];
1343 i.reg_operands = 2;
1344 }
1345
1346 /* The clr %reg instruction is converted into xor %reg, %reg. */
1347 if (t->opcode_modifier & iclrKludge)
1348 {
1349 i.regs[1] = i.regs[0];
1350 i.reg_operands = 2;
1351 }
1352
1353 /* Certain instructions expect the destination to be in the i.rm.reg
1354 field. This is by far the exceptional case. For these
1355 instructions, if the source operand is a register, we must reverse
1356 the i.rm.reg and i.rm.regmem fields. We accomplish this by faking
1357 that the two register operands were given in the reverse order. */
1358 if ((t->opcode_modifier & ReverseRegRegmem) && i.reg_operands == 2)
1359 {
1360 unsigned int first_reg_operand = (i.types[0] & Reg) ? 0 : 1;
1361 unsigned int second_reg_operand = first_reg_operand + 1;
1362 reg_entry *tmp = i.regs[first_reg_operand];
1363 i.regs[first_reg_operand] = i.regs[second_reg_operand];
1364 i.regs[second_reg_operand] = tmp;
1365 }
1366
1367 if (t->opcode_modifier & ShortForm)
1368 {
1369 /* The register or float register operand is in operand 0 or 1. */
1370 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
1371 /* Register goes in low 3 bits of opcode. */
1372 t->base_opcode |= i.regs[op]->reg_num;
1373 }
1374 else if (t->opcode_modifier & ShortFormW)
1375 {
1376 /* Short form with 0x8 width bit. Register is always dest. operand */
1377 t->base_opcode |= i.regs[1]->reg_num;
1378 if (i.suffix == WORD_OPCODE_SUFFIX ||
1379 i.suffix == DWORD_OPCODE_SUFFIX)
1380 t->base_opcode |= 0x8;
1381 }
1382 else if (t->opcode_modifier & Seg2ShortForm)
1383 {
1384 if (t->base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1)
1385 {
1386 as_bad ("you can't 'pop cs' on the 386.");
1387 return;
1388 }
1389 t->base_opcode |= (i.regs[0]->reg_num << 3);
1390 }
1391 else if (t->opcode_modifier & Seg3ShortForm)
1392 {
1393 /* 'push %fs' is 0x0fa0; 'pop %fs' is 0x0fa1.
1394 'push %gs' is 0x0fa8; 'pop %fs' is 0x0fa9.
1395 So, only if i.regs[0]->reg_num == 5 (%gs) do we need
1396 to change the opcode. */
1397 if (i.regs[0]->reg_num == 5)
1398 t->base_opcode |= 0x08;
1399 }
1400 else if ((t->base_opcode & ~DW) == MOV_AX_DISP32)
1401 {
1402 /* This is a special non-modrm instruction
1403 that addresses memory with a 32-bit displacement mode anyway,
1404 and thus requires an address-size prefix if in 16-bit mode. */
1405 uses_mem_addrmode = 1;
1406 default_seg = &ds;
1407 }
1408 else if (t->opcode_modifier & Modrm)
1409 {
1410 /* The opcode is completed (modulo t->extension_opcode which must
1411 be put into the modrm byte.
1412 Now, we make the modrm & index base bytes based on all the info
1413 we've collected. */
1414
1415 /* i.reg_operands MUST be the number of real register operands;
1416 implicit registers do not count. */
1417 if (i.reg_operands == 2)
1418 {
1419 unsigned int source, dest;
1420 source = ((i.types[0]
1421 & (Reg
--- 135 unchanged lines hidden (view full) ---
1557 {
1558 seg_index = (i.rm.mode << 3) | i.rm.regmem;
1559 default_seg = one_byte_segment_defaults[seg_index];
1560 }
1561 }
1562 }
1563
1564 /* Fill in i.rm.reg or i.rm.regmem field with register
1565 operand (if any) based on
1566 t->extension_opcode. Again, we must be careful to
1567 make sure that segment/control/debug/test/MMX
1568 registers are coded into the i.rm.reg field. */
1569 if (i.reg_operands)
1570 {
1571 unsigned int op =
1572 ((i.types[0]
1573 & (Reg | SReg2 | SReg3 | Control | Debug
1574 | Test | RegMMX))
1575 ? 0
1576 : ((i.types[1]
1577 & (Reg | SReg2 | SReg3 | Control | Debug
1578 | Test | RegMMX))
1579 ? 1
1580 : 2));
1581 /* If there is an extension opcode to put here, the
1582 register number must be put into the regmem field. */
1583 if (t->extension_opcode != None)
1584 i.rm.regmem = i.regs[op]->reg_num;
1585 else
1586 i.rm.reg = i.regs[op]->reg_num;
1587
1588 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
1589 we must set it to 3 to indicate this is a register
1590 operand int the regmem field */
1591 if (!i.mem_operands)
1592 i.rm.mode = 3;
1593 }
1594
1595 /* Fill in i.rm.reg field with extension opcode (if any). */
1596 if (t->extension_opcode != None)
1597 i.rm.reg = t->extension_opcode;
1598 }
1599
1600 if (i.rm.mode != 3)
1601 uses_mem_addrmode = 1;
1602 }
1603
1604 /* GAS currently doesn't support 16-bit memory addressing modes at all,
1605 so if we're writing 16-bit code and using a memory addressing mode,
--- 24 unchanged lines hidden (view full) ---
1630 return;
1631 }
1632 i.prefix[i.prefixes++] = i.seg->seg_prefix;
1633 }
1634 }
1635 }
1636
1637 /* Handle conversion of 'int $3' --> special int3 insn. */
1638 if (t->base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3)
1639 {
1640 t->base_opcode = INT3_OPCODE;
1641 i.imm_operands = 0;
1642 }
1643
1644 /* We are ready to output the insn. */
1645 {
1646 register char *p;
1647
1648 /* Output jumps. */
1649 if (t->opcode_modifier & Jump)
1650 {
1651 unsigned long n = i.disps[0]->X_add_number;
1652
1653 if (i.disps[0]->X_op == O_constant)
1654 {
1655 if (fits_in_signed_byte (n))
1656 {
1657 p = frag_more (2);
1658 insn_size += 2;
1659 p[0] = t->base_opcode;
1660 p[1] = n;
1661 }
1662 else
1663 { /* It's an absolute word/dword displacement. */
1664
1665 /* Use only 16-bit jumps for 16-bit code,
1666 because text segments are limited to 64K anyway;
1667 use only 32-bit jumps for 32-bit code,
1668 because they're faster. */
1669 int jmp_size = flag_16bit_code ? 2 : 4;
1670 if (flag_16bit_code && !fits_in_signed_word (n))
1671 {
1672 as_bad ("16-bit jump out of range");
1673 return;
1674 }
1675
1676 if (t->base_opcode == JUMP_PC_RELATIVE)
1677 { /* pace */
1678 /* unconditional jump */
1679 p = frag_more (1 + jmp_size);
1680 insn_size += 1 + jmp_size;
1681 p[0] = (char) 0xe9;
1682 md_number_to_chars (&p[1], (valueT) n, jmp_size);
1683 }
1684 else
1685 {
1686 /* conditional jump */
1687 p = frag_more (2 + jmp_size);
1688 insn_size += 2 + jmp_size;
1689 p[0] = TWO_BYTE_OPCODE_ESCAPE;
1690 p[1] = t->base_opcode + 0x10;
1691 md_number_to_chars (&p[2], (valueT) n, jmp_size);
1692 }
1693 }
1694 }
1695 else
1696 {
1697 if (flag_16bit_code)
1698 {
1699 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1700 insn_size += 1;
1701 }
1702
1703 /* It's a symbol; end frag & setup for relax.
1704 Make sure there are more than 6 chars left in the current frag;
1705 if not we'll have to start a new one. */
1706 frag_grow (7);
1707 p = frag_more (1);
1708 insn_size += 1;
1709 p[0] = t->base_opcode;
1710 frag_var (rs_machine_dependent,
1711 6, /* 2 opcode/prefix + 4 displacement */
1712 1,
1713 ((unsigned char) *p == JUMP_PC_RELATIVE
1714 ? ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE)
1715 : ENCODE_RELAX_STATE (COND_JUMP, BYTE)),
1716 i.disps[0]->X_add_symbol,
1717 (offsetT) n, p);
1718 }
1719 }
1720 else if (t->opcode_modifier & (JumpByte | JumpDword))
1721 {
1722 int size = (t->opcode_modifier & JumpByte) ? 1 : 4;
1723 unsigned long n = i.disps[0]->X_add_number;
1724 unsigned char *q;
1725
1726 /* The jcx/jecx instruction might need a data size prefix. */
1727 for (q = i.prefix; q < i.prefix + i.prefixes; q++)
1728 {
1729 if (*q == WORD_PREFIX_OPCODE)
1730 {
1731 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1732 insn_size += 1;
1733 break;
1734 }
1735 }
1736
1737 if ((size == 4) && (flag_16bit_code))
1738 {
1739 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1740 insn_size += 1;
1741 }
1742
1743 if (fits_in_unsigned_byte (t->base_opcode))
1744 {
1745 FRAG_APPEND_1_CHAR (t->base_opcode);
1746 insn_size += 1;
1747 }
1748 else
1749 {
1750 p = frag_more (2); /* opcode can be at most two bytes */
1751 insn_size += 2;
1752 /* put out high byte first: can't use md_number_to_chars! */
1753 *p++ = (t->base_opcode >> 8) & 0xff;
1754 *p = t->base_opcode & 0xff;
1755 }
1756
1757 p = frag_more (size);
1758 insn_size += size;
1759 if (i.disps[0]->X_op == O_constant)
1760 {
1761 md_number_to_chars (p, (valueT) n, size);
1762 if (size == 1 && !fits_in_signed_byte (n))
--- 4 unchanged lines hidden (view full) ---
1767 }
1768 else
1769 {
1770 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
1771 i.disps[0], 1, reloc (size, 1, i.disp_reloc[0]));
1772
1773 }
1774 }
1775 else if (t->opcode_modifier & JumpInterSegment)
1776 {
1777 if (flag_16bit_code)
1778 {
1779 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1780 insn_size += 1;
1781 }
1782
1783 p = frag_more (1 + 2 + 4); /* 1 opcode; 2 segment; 4 offset */
1784 insn_size += 1 + 2 + 4;
1785 p[0] = t->base_opcode;
1786 if (i.imms[1]->X_op == O_constant)
1787 md_number_to_chars (p + 1, (valueT) i.imms[1]->X_add_number, 4);
1788 else
1789 fix_new_exp (frag_now, p + 1 - frag_now->fr_literal, 4,
1790 i.imms[1], 0, BFD_RELOC_32);
1791 if (i.imms[0]->X_op != O_constant)
1792 as_bad ("can't handle non absolute segment in long call/jmp");
1793 md_number_to_chars (p + 5, (valueT) i.imms[0]->X_add_number, 2);
1794 }
1795 else
1796 {
1797 /* Output normal instructions here. */
1798 unsigned char *q;
1799
1800 /* First the prefix bytes. */
1801 for (q = i.prefix; q < i.prefix + i.prefixes; q++)
1802 {
1803 p = frag_more (1);
1804 insn_size += 1;
1805 md_number_to_chars (p, (valueT) *q, 1);
1806 }
1807
1808 /* Now the opcode; be careful about word order here! */
1809 if (fits_in_unsigned_byte (t->base_opcode))
1810 {
1811 FRAG_APPEND_1_CHAR (t->base_opcode);
1812 insn_size += 1;
1813 }
1814 else if (fits_in_unsigned_word (t->base_opcode))
1815 {
1816 p = frag_more (2);
1817 insn_size += 2;
1818 /* put out high byte first: can't use md_number_to_chars! */
1819 *p++ = (t->base_opcode >> 8) & 0xff;
1820 *p = t->base_opcode & 0xff;
1821 }
1822 else
1823 { /* opcode is either 3 or 4 bytes */
1824 if (t->base_opcode & 0xff000000)
1825 {
1826 p = frag_more (4);
1827 insn_size += 4;
1828 *p++ = (t->base_opcode >> 24) & 0xff;
1829 }
1830 else
1831 {
1832 p = frag_more (3);
1833 insn_size += 3;
1834 }
1835 *p++ = (t->base_opcode >> 16) & 0xff;
1836 *p++ = (t->base_opcode >> 8) & 0xff;
1837 *p = (t->base_opcode) & 0xff;
1838 }
1839
1840 /* Now the modrm byte and base index byte (if present). */
1841 if (t->opcode_modifier & Modrm)
1842 {
1843 p = frag_more (1);
1844 insn_size += 1;
1845 /* md_number_to_chars (p, i.rm, 1); */
1846 md_number_to_chars (p,
1847 (valueT) (i.rm.regmem << 0
1848 | i.rm.reg << 3
1849 | i.rm.mode << 6),
--- 235 unchanged lines hidden (view full) ---
2085 }
2086
2087 exp = &im_expressions[i.imm_operands++];
2088 i.imms[this_operand] = exp;
2089 save_input_line_pointer = input_line_pointer;
2090 input_line_pointer = ++op_string; /* must advance op_string! */
2091 SKIP_WHITESPACE ();
2092 exp_seg = expression (exp);
2093 input_line_pointer = save_input_line_pointer;
2094
2095 if (exp->X_op == O_absent)
2096 {
2097 /* missing or bad expr becomes absolute 0 */
2098 as_bad ("missing or invalid immediate expression '%s' taken as 0",
2099 operand_string);
2100 exp->X_op = O_constant;
--- 53 unchanged lines hidden (view full) ---
2154 if (i.mem_operands == MAX_MEMORY_OPERANDS)
2155 {
2156 as_bad ("more than 1 memory reference in instruction");
2157 return 0;
2158 }
2159 i.mem_operands++;
2160
2161 /* Determine type of memory operand from opcode_suffix;
2162 no opcode suffix implies general memory references. */
2163 switch (i.suffix)
2164 {
2165 case BYTE_OPCODE_SUFFIX:
2166 i.types[this_operand] |= Mem8;
2167 break;
2168 case WORD_OPCODE_SUFFIX:
2169 i.types[this_operand] |= Mem16;
2170 break;
--- 154 unchanged lines hidden (view full) ---
2325 char *save_input_line_pointer;
2326 exp = &disp_expressions[i.disp_operands];
2327 i.disps[this_operand] = exp;
2328 i.disp_reloc[this_operand] = NO_RELOC;
2329 i.disp_operands++;
2330 save_input_line_pointer = input_line_pointer;
2331 input_line_pointer = displacement_string_start;
2332 END_STRING_AND_SAVE (displacement_string_end);
2333#ifndef LEX_AT
2334 {
2335 /*
2336 * We can have operands of the form
2337 * <symbol>@GOTOFF+<nnn>
2338 * Take the easy way out here and copy everything
2339 * into a temporary buffer...
2340 */
2341 register char *cp;
2342 if ((cp = strchr (input_line_pointer,'@')) != NULL) {
2343 char tmpbuf[BUFSIZ];
2344
2345 if(!GOT_symbol)
2346 GOT_symbol = symbol_find_or_make(GLOBAL_OFFSET_TABLE_NAME);
2347
2348 if (strncmp(cp+1, "PLT", 3) == 0) {
2349 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
2350 *cp = '\0';
2351 strcpy(tmpbuf, input_line_pointer);
2352 strcat(tmpbuf, cp+1+3);
2353 *cp = '@';
2354 } else if (strncmp(cp+1, "GOTOFF", 6) == 0) {
2355 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
2356 *cp = '\0';
2357 strcpy(tmpbuf, input_line_pointer);
2358 strcat(tmpbuf, cp+1+6);
2359 *cp = '@';
2360 } else if (strncmp(cp+1, "GOT", 3) == 0) {
2361 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
2362 *cp = '\0';
2363 strcpy(tmpbuf, input_line_pointer);
2364 strcat(tmpbuf, cp+1+3);
2365 *cp = '@';
2366 } else
2367 as_bad("Bad reloc specifier '%s' in expression", cp+1);
2368 input_line_pointer = tmpbuf;
2369 }
2370 }
2371#endif
2372 exp_seg = expression (exp);
2373
2374#ifdef BFD_ASSEMBLER
2375 /* We do this to make sure that the section symbol is in
2376 the symbol table. We will ultimately change the relocation
2377 to be relative to the beginning of the section */
2378 if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF)
2379 {
--- 298 unchanged lines hidden (view full) ---
2678md_apply_fix3 (fixP, valp, seg)
2679 fixS *fixP; /* The fix we're to put in. */
2680 valueT *valp; /* Pointer to the value of the bits. */
2681 segT seg; /* Segment fix is from. */
2682{
2683 register char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
2684 valueT value = *valp;
2685
2686#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
2687 /*
2688 * This is a hack. There should be a better way to
2689 * handle this.
2690 */
2691 if (fixP->fx_r_type == BFD_RELOC_32_PCREL && fixP->fx_addsy)
2692 {
2693#ifndef OBJ_AOUT
2694 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
2695 value += fixP->fx_where + fixP->fx_frag->fr_address;
2696#endif
2697#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2698 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2699 && (S_GET_SEGMENT (fixP->fx_addsy) == seg
2700 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0))
2701 {
2702 /* Yes, we add the values in twice. This is because
2703 bfd_perform_relocation subtracts them out again. I think
2704 bfd_perform_relocation is broken, but I don't dare change
2705 it. FIXME. */
2706 value += fixP->fx_where + fixP->fx_frag->fr_address;
2707 }
2708#endif
2709 }
2710
2711 /* Fix a few things - the dynamic linker expects certain values here,
2712 and we must not dissappoint it. */
2713#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2714 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2715 && fixP->fx_addsy)
2716 switch(fixP->fx_r_type) {
--- 333 unchanged lines hidden (view full) ---
3050 bfd_reloc_code_real_type code;
3051
3052 switch(fixp->fx_r_type)
3053 {
3054 case BFD_RELOC_386_PLT32:
3055 case BFD_RELOC_386_GOT32:
3056 case BFD_RELOC_386_GOTOFF:
3057 case BFD_RELOC_386_GOTPC:
3058 code = fixp->fx_r_type;
3059 break;
3060 default:
3061 switch (F (fixp->fx_size, fixp->fx_pcrel))
3062 {
3063 MAP (1, 0, BFD_RELOC_8);
3064 MAP (2, 0, BFD_RELOC_16);
3065 MAP (4, 0, BFD_RELOC_32);
--- 109 unchanged lines hidden ---