1/* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 1998
3 Free Software Foundation.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
--- 89 unchanged lines hidden (view full) ---
101 const seg_entry *seg; /* segment for memory operands (if given) */
102
103 /* PREFIX holds all the given prefix opcodes (usually null).
104 PREFIXES is the size of PREFIX. */
105 /* richfix: really unsigned? */
106 unsigned char prefix[MAX_PREFIXES];
107 unsigned int prefixes;
108
109 /* RM and BI are the modrm byte and the base index byte where the
110 addressing modes of this insn are encoded. */
111
112 modrm_byte rm;
113 base_index_byte bi;
114 };
115
116typedef struct _i386_insn i386_insn;
117
--- 180 unchanged lines hidden (view full) ---
298 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
299 static const char f32_14[] =
300 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
301 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
302 static const char f32_15[] =
303 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
304 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
305 static const char f16_4[] =
306 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
307 static const char f16_5[] =
308 {0x90, /* nop */
309 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
310 static const char f16_6[] =
311 {0x89,0xf6, /* mov %si,%si */
312 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
313 static const char f16_7[] =
314 {0x8d,0x74,0x00, /* lea 0(%si),%si */
315 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
316 static const char f16_8[] =
317 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
318 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
319 static const char *const f32_patt[] = {
320 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
321 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
322 };
323 static const char *const f16_patt[] = {
324 f32_1, f32_2, f32_3, f16_4, f16_5, f16_6, f16_7, f16_8,
325 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
--- 103 unchanged lines hidden (view full) ---
429 flag_16bit_code = new_16bit_code_flag;
430}
431
432const pseudo_typeS md_pseudo_table[] =
433{
434#ifndef I386COFF
435 {"bss", s_bss, 0},
436#endif
437#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
438 {"align", s_align_bytes, 0},
439#else
440 {"align", s_align_ptwo, 0},
441#endif
442 {"ffloat", float_cons, 'f'},
443 {"dfloat", float_cons, 'd'},
444 {"tfloat", float_cons, 'x'},
445 {"value", cons, 2},
--- 352 unchanged lines hidden (view full) ---
798 * the beginning of the section instead of the symbol. Basically we need
799 * to make sure that the dynamic relocations are done correctly, so in
800 * some cases we force the original symbol to be used.
801 */
802int
803tc_i386_fix_adjustable(fixP)
804 fixS * fixP;
805{
806#ifdef OBJ_ELF
807 /* Prevent all adjustments to global symbols. */
808 if (S_IS_EXTERN (fixP->fx_addsy))
809 return 0;
810 if (S_IS_WEAK (fixP->fx_addsy))
811 return 0;
812#endif /* ! defined (OBJ_AOUT) */
813 /* adjust_reloc_syms doesn't know about the GOT */
814 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
--- 14 unchanged lines hidden (view full) ---
829/* This is the guts of the machine-dependent assembler. LINE points to a
830 machine dependent instruction. This function is supposed to emit
831 the frags/bytes it assembles to. */
832
833void
834md_assemble (line)
835 char *line;
836{
837 /* Points to template once we've found it. */
838 const template *t;
839
840 /* Count the size of the instruction generated. */
841 int insn_size = 0;
842
843 /* Possible templates for current insn */
844 templates *current_templates = (templates *) 0;
845
846 int j;
847
848 /* Wait prefix needs to come before any other prefixes, so handle it
849 specially. wait_prefix will hold the opcode modifier flag FWait
850 if a wait prefix is given. */
851 int wait_prefix = 0;
852
853 /* Initialize globals. */
854 memset (&i, '\0', sizeof (i));
855 for (j = 0; j < MAX_OPERANDS; j++)
856 i.disp_reloc[j] = NO_RELOC;
857 memset (disp_expressions, '\0', sizeof (disp_expressions));
858 memset (im_expressions, '\0', sizeof (im_expressions));
859 save_stack_p = save_stack; /* reset stack pointer */
860
861 /* First parse an opcode & call i386_operand for the operands.
862 We assume that the scrubber has arranged it so that line[0] is the valid
863 start of a (possibly prefixed) opcode. */
864 {
865 char *l = line;
866
867 /* 1 if operand is pending after ','. */
868 unsigned int expecting_operand = 0;
869 /* 1 if we found a prefix only acceptable with string insns. */
--- 35 unchanged lines hidden (view full) ---
905 RESTORE_END_STRING (l);
906 /* check for repeated prefix */
907 for (q = 0; q < i.prefixes; q++)
908 if (i.prefix[q] == prefix->prefix_code)
909 {
910 as_bad ("same prefix used twice; you don't really want this!");
911 return;
912 }
913 if (prefix->prefix_code == FWAIT_OPCODE)
914 {
915 if (wait_prefix != 0)
916 {
917 as_bad ("same prefix used twice; you don't really want this!");
918 return;
919 }
920 wait_prefix = FWait;
921 }
922 else
923 {
924 if (i.prefixes == MAX_PREFIXES)
925 {
926 as_bad ("too many opcode prefixes");
927 return;
928 }
929 i.prefix[i.prefixes++] = prefix->prefix_code;
930 if (prefix->prefix_code == REPE
931 || prefix->prefix_code == REPNE)
932 expecting_string_instruction = 1;
933 }
934 /* skip past PREFIX_SEPERATOR and reset token_start */
935 token_start = ++l;
936 }
937 }
938 END_STRING_AND_SAVE (l);
939 if (token_start == l)
940 {
941 as_bad ("expecting opcode; got nothing");
--- 203 unchanged lines hidden (view full) ---
1145 continue;
1146
1147 /* try reversing direction of operands */
1148 overlap0 = i.types[0] & t->operand_types[1];
1149 overlap1 = i.types[1] & t->operand_types[0];
1150 if (!MATCH (overlap0, i.types[0]) ||
1151 !MATCH (overlap1, i.types[1]) ||
1152 !CONSISTENT_REGISTER_MATCH (overlap0, overlap1,
1153 t->operand_types[1],
1154 t->operand_types[0]))
1155 {
1156 /* does not match either direction */
1157 continue;
1158 }
1159 /* found a reverse match here -- slip through */
1160 /* found_reverse_match holds which of D or FloatD we've found */
1161 found_reverse_match = t->opcode_modifier & COMES_IN_BOTH_DIRECTIONS;
1162 } /* endif: not forward match */
--- 16 unchanged lines hidden (view full) ---
1179 break; /* we've found a match; break out of loop */
1180 } /* for (t = ... */
1181 if (t == current_templates->end)
1182 { /* we found no match */
1183 as_bad ("operands given don't match any known 386 instruction");
1184 return;
1185 }
1186
1187 /* Copy the template we found. */
1188 i.tm = *t;
1189 i.tm.opcode_modifier |= wait_prefix;
1190
1191 if (found_reverse_match)
1192 {
1193 i.tm.operand_types[0] = t->operand_types[1];
1194 i.tm.operand_types[1] = t->operand_types[0];
1195 }
1196
1197 /* If the matched instruction specifies an explicit opcode suffix,
1198 use it - and make sure none has already been specified. */
1199 if (i.tm.opcode_modifier & (Data16|Data32))
1200 {
1201 if (i.suffix)
1202 {
1203 as_bad ("extraneous opcode suffix given");
1204 return;
1205 }
1206 if (i.tm.opcode_modifier & Data16)
1207 i.suffix = WORD_OPCODE_SUFFIX;
1208 else
1209 i.suffix = DWORD_OPCODE_SUFFIX;
1210 }
1211
1212 /* If there's no opcode suffix we try to invent one based on register
1213 operands. */
1214 if (!i.suffix && i.reg_operands)
--- 80 unchanged lines hidden (view full) ---
1295 i.reg_operands--;
1296 if (overlap1 & ImplicitRegister)
1297 i.reg_operands--;
1298 if (overlap2 & ImplicitRegister)
1299 i.reg_operands--;
1300 if (overlap0 & Imm1)
1301 i.imm_operands = 0; /* kludge for shift insns */
1302
1303 /* Finalize opcode. First, we change the opcode based on the operand
1304 size given by i.suffix: we never have to change things for byte insns,
1305 or when no opcode suffix is need to size the operands. */
1306
1307 if (!i.suffix && (i.tm.opcode_modifier & W))
1308 {
1309 as_bad ("no opcode suffix given and no register operands; can't size instruction");
1310 return;
1311 }
1312
1313 if (i.suffix && i.suffix != BYTE_OPCODE_SUFFIX)
1314 {
1315 /* Select between byte and word/dword operations. */
1316 if (i.tm.opcode_modifier & W)
1317 i.tm.base_opcode |= W;
1318 /* Now select between word & dword operations via the
1319 operand size prefix. */
1320 if ((i.suffix == WORD_OPCODE_SUFFIX) ^ flag_16bit_code)
1321 {
1322 if (i.prefixes == MAX_PREFIXES)
1323 {
1324 as_bad ("%d prefixes given and data size prefix gives too many prefixes",
1325 MAX_PREFIXES);
1326 return;
1327 }
1328 i.prefix[i.prefixes++] = WORD_PREFIX_OPCODE;
1329 }
1330 }
1331
1332 /* For insns with operands there are more diddles to do to the opcode. */
--- 10 unchanged lines hidden (view full) ---
1343
1344
1345 /* If we found a reverse match we must alter the opcode direction bit
1346 found_reverse_match holds bit to set (different for int &
1347 float insns). */
1348
1349 if (found_reverse_match)
1350 {
1351 i.tm.base_opcode |= found_reverse_match;
1352 }
1353
1354 /* The imul $imm, %reg instruction is converted into
1355 imul $imm, %reg, %reg. */
1356 if (i.tm.opcode_modifier & imulKludge)
1357 {
1358 /* Pretend we saw the 3 operand case. */
1359 i.regs[2] = i.regs[1];
1360 i.reg_operands = 2;
1361 }
1362
1363 /* The clr %reg instruction is converted into xor %reg, %reg. */
1364 if (i.tm.opcode_modifier & iclrKludge)
1365 {
1366 i.regs[1] = i.regs[0];
1367 i.reg_operands = 2;
1368 }
1369
1370 /* Certain instructions expect the destination to be in the i.rm.reg
1371 field. This is by far the exceptional case. For these
1372 instructions, if the source operand is a register, we must reverse
1373 the i.rm.reg and i.rm.regmem fields. We accomplish this by faking
1374 that the two register operands were given in the reverse order. */
1375 if ((i.tm.opcode_modifier & ReverseRegRegmem) && i.reg_operands == 2)
1376 {
1377 unsigned int first_reg_operand = (i.types[0] & Reg) ? 0 : 1;
1378 unsigned int second_reg_operand = first_reg_operand + 1;
1379 reg_entry *tmp = i.regs[first_reg_operand];
1380 i.regs[first_reg_operand] = i.regs[second_reg_operand];
1381 i.regs[second_reg_operand] = tmp;
1382 }
1383
1384 if (i.tm.opcode_modifier & ShortForm)
1385 {
1386 /* The register or float register operand is in operand 0 or 1. */
1387 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
1388 /* Register goes in low 3 bits of opcode. */
1389 i.tm.base_opcode |= i.regs[op]->reg_num;
1390 }
1391 else if (i.tm.opcode_modifier & ShortFormW)
1392 {
1393 /* Short form with 0x8 width bit. Register is always dest. operand */
1394 i.tm.base_opcode |= i.regs[1]->reg_num;
1395 if (i.suffix == WORD_OPCODE_SUFFIX ||
1396 i.suffix == DWORD_OPCODE_SUFFIX)
1397 i.tm.base_opcode |= 0x8;
1398 }
1399 else if (i.tm.opcode_modifier & Seg2ShortForm)
1400 {
1401 if (i.tm.base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1)
1402 {
1403 as_bad ("you can't 'pop cs' on the 386.");
1404 return;
1405 }
1406 i.tm.base_opcode |= (i.regs[0]->reg_num << 3);
1407 }
1408 else if (i.tm.opcode_modifier & Seg3ShortForm)
1409 {
1410 /* 'push %fs' is 0x0fa0; 'pop %fs' is 0x0fa1.
1411 'push %gs' is 0x0fa8; 'pop %fs' is 0x0fa9.
1412 So, only if i.regs[0]->reg_num == 5 (%gs) do we need
1413 to change the opcode. */
1414 if (i.regs[0]->reg_num == 5)
1415 i.tm.base_opcode |= 0x08;
1416 }
1417 else if ((i.tm.base_opcode & ~DW) == MOV_AX_DISP32)
1418 {
1419 /* This is a special non-modrm instruction
1420 that addresses memory with a 32-bit displacement mode anyway,
1421 and thus requires an address-size prefix if in 16-bit mode. */
1422 uses_mem_addrmode = 1;
1423 default_seg = &ds;
1424 }
1425 else if (i.tm.opcode_modifier & Modrm)
1426 {
1427 /* The opcode is completed (modulo i.tm.extension_opcode which
1428 must be put into the modrm byte).
1429 Now, we make the modrm & index base bytes based on all the
1430 info we've collected. */
1431
1432 /* i.reg_operands MUST be the number of real register operands;
1433 implicit registers do not count. */
1434 if (i.reg_operands == 2)
1435 {
1436 unsigned int source, dest;
1437 source = ((i.types[0]
1438 & (Reg
--- 135 unchanged lines hidden (view full) ---
1574 {
1575 seg_index = (i.rm.mode << 3) | i.rm.regmem;
1576 default_seg = one_byte_segment_defaults[seg_index];
1577 }
1578 }
1579 }
1580
1581 /* Fill in i.rm.reg or i.rm.regmem field with register
1582 operand (if any) based on i.tm.extension_opcode.
1583 Again, we must be careful to make sure that
1584 segment/control/debug/test/MMX registers are coded
1585 into the i.rm.reg field. */
1586 if (i.reg_operands)
1587 {
1588 unsigned int op =
1589 ((i.types[0]
1590 & (Reg | SReg2 | SReg3 | Control | Debug
1591 | Test | RegMMX))
1592 ? 0
1593 : ((i.types[1]
1594 & (Reg | SReg2 | SReg3 | Control | Debug
1595 | Test | RegMMX))
1596 ? 1
1597 : 2));
1598 /* If there is an extension opcode to put here, the
1599 register number must be put into the regmem field. */
1600 if (i.tm.extension_opcode != None)
1601 i.rm.regmem = i.regs[op]->reg_num;
1602 else
1603 i.rm.reg = i.regs[op]->reg_num;
1604
1605 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
1606 we must set it to 3 to indicate this is a register
1607 operand int the regmem field */
1608 if (!i.mem_operands)
1609 i.rm.mode = 3;
1610 }
1611
1612 /* Fill in i.rm.reg field with extension opcode (if any). */
1613 if (i.tm.extension_opcode != None)
1614 i.rm.reg = i.tm.extension_opcode;
1615 }
1616
1617 if (i.rm.mode != 3)
1618 uses_mem_addrmode = 1;
1619 }
1620
1621 /* GAS currently doesn't support 16-bit memory addressing modes at all,
1622 so if we're writing 16-bit code and using a memory addressing mode,
--- 24 unchanged lines hidden (view full) ---
1647 return;
1648 }
1649 i.prefix[i.prefixes++] = i.seg->seg_prefix;
1650 }
1651 }
1652 }
1653
1654 /* Handle conversion of 'int $3' --> special int3 insn. */
1655 if (i.tm.base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3)
1656 {
1657 i.tm.base_opcode = INT3_OPCODE;
1658 i.imm_operands = 0;
1659 }
1660
1661 /* We are ready to output the insn. */
1662 {
1663 register char *p;
1664
1665 /* Output jumps. */
1666 if (i.tm.opcode_modifier & Jump)
1667 {
1668 unsigned long n = i.disps[0]->X_add_number;
1669
1670 if (i.disps[0]->X_op == O_constant)
1671 {
1672 if (fits_in_signed_byte (n))
1673 {
1674 p = frag_more (2);
1675 insn_size += 2;
1676 p[0] = i.tm.base_opcode;
1677 p[1] = n;
1678 }
1679 else
1680 { /* It's an absolute word/dword displacement. */
1681
1682 /* Use only 16-bit jumps for 16-bit code,
1683 because text segments are limited to 64K anyway;
1684 use only 32-bit jumps for 32-bit code,
1685 because they're faster. */
1686 int jmp_size = flag_16bit_code ? 2 : 4;
1687 if (flag_16bit_code && !fits_in_signed_word (n))
1688 {
1689 as_bad ("16-bit jump out of range");
1690 return;
1691 }
1692
1693 if (i.tm.base_opcode == JUMP_PC_RELATIVE)
1694 { /* pace */
1695 /* unconditional jump */
1696 p = frag_more (1 + jmp_size);
1697 insn_size += 1 + jmp_size;
1698 p[0] = (char) 0xe9;
1699 md_number_to_chars (&p[1], (valueT) n, jmp_size);
1700 }
1701 else
1702 {
1703 /* conditional jump */
1704 p = frag_more (2 + jmp_size);
1705 insn_size += 2 + jmp_size;
1706 p[0] = TWO_BYTE_OPCODE_ESCAPE;
1707 p[1] = i.tm.base_opcode + 0x10;
1708 md_number_to_chars (&p[2], (valueT) n, jmp_size);
1709 }
1710 }
1711 }
1712 else
1713 {
1714 if (flag_16bit_code)
1715 {
1716 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1717 insn_size += 1;
1718 }
1719
1720 /* It's a symbol; end frag & setup for relax.
1721 Make sure there are more than 6 chars left in the current frag;
1722 if not we'll have to start a new one. */
1723 frag_grow (7);
1724 p = frag_more (1);
1725 insn_size += 1;
1726 p[0] = i.tm.base_opcode;
1727 frag_var (rs_machine_dependent,
1728 6, /* 2 opcode/prefix + 4 displacement */
1729 1,
1730 ((unsigned char) *p == JUMP_PC_RELATIVE
1731 ? ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE)
1732 : ENCODE_RELAX_STATE (COND_JUMP, BYTE)),
1733 i.disps[0]->X_add_symbol,
1734 (offsetT) n, p);
1735 }
1736 }
1737 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
1738 {
1739 int size = (i.tm.opcode_modifier & JumpByte) ? 1 : 4;
1740 unsigned long n = i.disps[0]->X_add_number;
1741 unsigned char *q;
1742
1743 /* The jcx/jecx instruction might need a data size prefix. */
1744 for (q = i.prefix; q < i.prefix + i.prefixes; q++)
1745 {
1746 if (*q == WORD_PREFIX_OPCODE)
1747 {
1748 /* The jcxz/jecxz instructions are marked with Data16
1749 and Data32, which means that they may get
1750 WORD_PREFIX_OPCODE added to the list of prefixes.
1751 However, the are correctly distinguished using
1752 ADDR_PREFIX_OPCODE. Here we look for
1753 WORD_PREFIX_OPCODE, and actually emit
1754 ADDR_PREFIX_OPCODE. This is a hack, but, then, so
1755 is the instruction itself.
1756
1757 If an explicit suffix is used for the loop
1758 instruction, that actually controls whether we use
1759 cx vs. ecx. This is also controlled by
1760 ADDR_PREFIX_OPCODE.
1761
1762 I don't know if there is any valid case in which we
1763 want to emit WORD_PREFIX_OPCODE, but I am keeping
1764 the old behaviour for safety. */
1765
1766 if (IS_JUMP_ON_CX_ZERO (i.tm.base_opcode)
1767 || IS_LOOP_ECX_TIMES (i.tm.base_opcode))
1768 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
1769 else
1770 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1771 insn_size += 1;
1772 break;
1773 }
1774 }
1775
1776 if ((size == 4) && (flag_16bit_code))
1777 {
1778 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1779 insn_size += 1;
1780 }
1781
1782 if (fits_in_unsigned_byte (i.tm.base_opcode))
1783 {
1784 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
1785 insn_size += 1;
1786 }
1787 else
1788 {
1789 p = frag_more (2); /* opcode can be at most two bytes */
1790 insn_size += 2;
1791 /* put out high byte first: can't use md_number_to_chars! */
1792 *p++ = (i.tm.base_opcode >> 8) & 0xff;
1793 *p = i.tm.base_opcode & 0xff;
1794 }
1795
1796 p = frag_more (size);
1797 insn_size += size;
1798 if (i.disps[0]->X_op == O_constant)
1799 {
1800 md_number_to_chars (p, (valueT) n, size);
1801 if (size == 1 && !fits_in_signed_byte (n))
--- 4 unchanged lines hidden (view full) ---
1806 }
1807 else
1808 {
1809 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
1810 i.disps[0], 1, reloc (size, 1, i.disp_reloc[0]));
1811
1812 }
1813 }
1814 else if (i.tm.opcode_modifier & JumpInterSegment)
1815 {
1816 if (flag_16bit_code)
1817 {
1818 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1819 insn_size += 1;
1820 }
1821
1822 p = frag_more (1 + 2 + 4); /* 1 opcode; 2 segment; 4 offset */
1823 insn_size += 1 + 2 + 4;
1824 p[0] = i.tm.base_opcode;
1825 if (i.imms[1]->X_op == O_constant)
1826 md_number_to_chars (p + 1, (valueT) i.imms[1]->X_add_number, 4);
1827 else
1828 fix_new_exp (frag_now, p + 1 - frag_now->fr_literal, 4,
1829 i.imms[1], 0, BFD_RELOC_32);
1830 if (i.imms[0]->X_op != O_constant)
1831 as_bad ("can't handle non absolute segment in long call/jmp");
1832 md_number_to_chars (p + 5, (valueT) i.imms[0]->X_add_number, 2);
1833 }
1834 else
1835 {
1836 /* Output normal instructions here. */
1837 unsigned char *q;
1838
1839 /* Hack for fwait. It must come before any prefixes, as it
1840 really is an instruction rather than a prefix. */
1841 if ((i.tm.opcode_modifier & FWait) != 0)
1842 {
1843 p = frag_more (1);
1844 insn_size += 1;
1845 md_number_to_chars (p, (valueT) FWAIT_OPCODE, 1);
1846 }
1847
1848 /* The prefix bytes. */
1849 for (q = i.prefix; q < i.prefix + i.prefixes; q++)
1850 {
1851 p = frag_more (1);
1852 insn_size += 1;
1853 md_number_to_chars (p, (valueT) *q, 1);
1854 }
1855
1856 /* Now the opcode; be careful about word order here! */
1857 if (fits_in_unsigned_byte (i.tm.base_opcode))
1858 {
1859 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
1860 insn_size += 1;
1861 }
1862 else if (fits_in_unsigned_word (i.tm.base_opcode))
1863 {
1864 p = frag_more (2);
1865 insn_size += 2;
1866 /* put out high byte first: can't use md_number_to_chars! */
1867 *p++ = (i.tm.base_opcode >> 8) & 0xff;
1868 *p = i.tm.base_opcode & 0xff;
1869 }
1870 else
1871 { /* opcode is either 3 or 4 bytes */
1872 if (i.tm.base_opcode & 0xff000000)
1873 {
1874 p = frag_more (4);
1875 insn_size += 4;
1876 *p++ = (i.tm.base_opcode >> 24) & 0xff;
1877 }
1878 else
1879 {
1880 p = frag_more (3);
1881 insn_size += 3;
1882 }
1883 *p++ = (i.tm.base_opcode >> 16) & 0xff;
1884 *p++ = (i.tm.base_opcode >> 8) & 0xff;
1885 *p = (i.tm.base_opcode) & 0xff;
1886 }
1887
1888 /* Now the modrm byte and base index byte (if present). */
1889 if (i.tm.opcode_modifier & Modrm)
1890 {
1891 p = frag_more (1);
1892 insn_size += 1;
1893 /* md_number_to_chars (p, i.rm, 1); */
1894 md_number_to_chars (p,
1895 (valueT) (i.rm.regmem << 0
1896 | i.rm.reg << 3
1897 | i.rm.mode << 6),
--- 235 unchanged lines hidden (view full) ---
2133 }
2134
2135 exp = &im_expressions[i.imm_operands++];
2136 i.imms[this_operand] = exp;
2137 save_input_line_pointer = input_line_pointer;
2138 input_line_pointer = ++op_string; /* must advance op_string! */
2139 SKIP_WHITESPACE ();
2140 exp_seg = expression (exp);
2141 if (*input_line_pointer != '\0')
2142 {
2143 /* This should be as_bad, but some versions of gcc, up to
2144 about 2.8 and egcs 1.01, generate a bogus @GOTOFF(%ebx)
2145 in certain cases. Oddly, the code in question turns out
2146 to work correctly anyhow, so we make this just a warning
2147 until those versions of gcc are obsolete. */
2148 as_warn ("warning: unrecognized characters `%s' in expression",
2149 input_line_pointer);
2150 }
2151 input_line_pointer = save_input_line_pointer;
2152
2153 if (exp->X_op == O_absent)
2154 {
2155 /* missing or bad expr becomes absolute 0 */
2156 as_bad ("missing or invalid immediate expression '%s' taken as 0",
2157 operand_string);
2158 exp->X_op = O_constant;
--- 53 unchanged lines hidden (view full) ---
2212 if (i.mem_operands == MAX_MEMORY_OPERANDS)
2213 {
2214 as_bad ("more than 1 memory reference in instruction");
2215 return 0;
2216 }
2217 i.mem_operands++;
2218
2219 /* Determine type of memory operand from opcode_suffix;
2220 no opcode suffix implies general memory references. */
2221 switch (i.suffix)
2222 {
2223 case BYTE_OPCODE_SUFFIX:
2224 i.types[this_operand] |= Mem8;
2225 break;
2226 case WORD_OPCODE_SUFFIX:
2227 i.types[this_operand] |= Mem16;
2228 break;
--- 154 unchanged lines hidden (view full) ---
2383 char *save_input_line_pointer;
2384 exp = &disp_expressions[i.disp_operands];
2385 i.disps[this_operand] = exp;
2386 i.disp_reloc[this_operand] = NO_RELOC;
2387 i.disp_operands++;
2388 save_input_line_pointer = input_line_pointer;
2389 input_line_pointer = displacement_string_start;
2390 END_STRING_AND_SAVE (displacement_string_end);
2391
2392#ifndef LEX_AT
2393 {
2394 /*
2395 * We can have operands of the form
2396 * <symbol>@GOTOFF+<nnn>
2397 * Take the easy way out here and copy everything
2398 * into a temporary buffer...
2399 */
2400 register char *cp;
2401
2402 cp = strchr (input_line_pointer, '@');
2403 if (cp != NULL)
2404 {
2405 char *tmpbuf;
2406
2407 if (GOT_symbol == NULL)
2408 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
2409
2410 tmpbuf = (char *) alloca ((cp - input_line_pointer) + 20);
2411
2412 if (strncmp (cp + 1, "PLT", 3) == 0)
2413 {
2414 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
2415 *cp = '\0';
2416 strcpy (tmpbuf, input_line_pointer);
2417 strcat (tmpbuf, cp + 1 + 3);
2418 *cp = '@';
2419 }
2420 else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
2421 {
2422 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
2423 *cp = '\0';
2424 strcpy (tmpbuf, input_line_pointer);
2425 strcat (tmpbuf, cp + 1 + 6);
2426 *cp = '@';
2427 }
2428 else if (strncmp (cp + 1, "GOT", 3) == 0)
2429 {
2430 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
2431 *cp = '\0';
2432 strcpy (tmpbuf, input_line_pointer);
2433 strcat (tmpbuf, cp + 1 + 3);
2434 *cp = '@';
2435 }
2436 else
2437 as_bad ("Bad reloc specifier '%s' in expression", cp + 1);
2438
2439 input_line_pointer = tmpbuf;
2440 }
2441 }
2442#endif
2443
2444 exp_seg = expression (exp);
2445
2446#ifdef BFD_ASSEMBLER
2447 /* We do this to make sure that the section symbol is in
2448 the symbol table. We will ultimately change the relocation
2449 to be relative to the beginning of the section */
2450 if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF)
2451 {
--- 298 unchanged lines hidden (view full) ---
2750md_apply_fix3 (fixP, valp, seg)
2751 fixS *fixP; /* The fix we're to put in. */
2752 valueT *valp; /* Pointer to the value of the bits. */
2753 segT seg; /* Segment fix is from. */
2754{
2755 register char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
2756 valueT value = *valp;
2757
2758 if (fixP->fx_r_type == BFD_RELOC_32 && fixP->fx_pcrel)
2759 fixP->fx_r_type = BFD_RELOC_32_PCREL;
2760
2761#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
2762 /*
2763 * This is a hack. There should be a better way to
2764 * handle this.
2765 */
2766 if (fixP->fx_r_type == BFD_RELOC_32_PCREL && fixP->fx_addsy)
2767 {
2768#ifndef OBJ_AOUT
2769 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2770 || OUTPUT_FLAVOR == bfd_target_coff_flavour)
2771 value += fixP->fx_where + fixP->fx_frag->fr_address;
2772#endif
2773#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2774 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2775 && (S_GET_SEGMENT (fixP->fx_addsy) == seg
2776 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0))
2777 {
2778 /* Yes, we add the values in twice. This is because
2779 bfd_perform_relocation subtracts them out again. I think
2780 bfd_perform_relocation is broken, but I don't dare change
2781 it. FIXME. */
2782 value += fixP->fx_where + fixP->fx_frag->fr_address;
2783 }
2784#endif
2785#if defined (OBJ_COFF) && defined (TE_PE)
2786 /* For some reason, the PE format does not store a section
2787 address offset for a PC relative symbol. */
2788 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
2789 value += md_pcrel_from (fixP);
2790#endif
2791 }
2792
2793 /* Fix a few things - the dynamic linker expects certain values here,
2794 and we must not dissappoint it. */
2795#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2796 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2797 && fixP->fx_addsy)
2798 switch(fixP->fx_r_type) {
--- 333 unchanged lines hidden (view full) ---
3132 bfd_reloc_code_real_type code;
3133
3134 switch(fixp->fx_r_type)
3135 {
3136 case BFD_RELOC_386_PLT32:
3137 case BFD_RELOC_386_GOT32:
3138 case BFD_RELOC_386_GOTOFF:
3139 case BFD_RELOC_386_GOTPC:
3140 case BFD_RELOC_RVA:
3141 code = fixp->fx_r_type;
3142 break;
3143 default:
3144 switch (F (fixp->fx_size, fixp->fx_pcrel))
3145 {
3146 MAP (1, 0, BFD_RELOC_8);
3147 MAP (2, 0, BFD_RELOC_16);
3148 MAP (4, 0, BFD_RELOC_32);
--- 109 unchanged lines hidden ---
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 1998
3 Free Software Foundation.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
--- 89 unchanged lines hidden (view full) ---
101 const seg_entry *seg; /* segment for memory operands (if given) */
102
103 /* PREFIX holds all the given prefix opcodes (usually null).
104 PREFIXES is the size of PREFIX. */
105 /* richfix: really unsigned? */
106 unsigned char prefix[MAX_PREFIXES];
107 unsigned int prefixes;
108
109 /* RM and BI are the modrm byte and the base index byte where the
110 addressing modes of this insn are encoded. */
111
112 modrm_byte rm;
113 base_index_byte bi;
114 };
115
116typedef struct _i386_insn i386_insn;
117
--- 180 unchanged lines hidden (view full) ---
298 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
299 static const char f32_14[] =
300 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
301 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
302 static const char f32_15[] =
303 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
304 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
305 static const char f16_4[] =
306 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
307 static const char f16_5[] =
308 {0x90, /* nop */
309 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
310 static const char f16_6[] =
311 {0x89,0xf6, /* mov %si,%si */
312 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
313 static const char f16_7[] =
314 {0x8d,0x74,0x00, /* lea 0(%si),%si */
315 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
316 static const char f16_8[] =
317 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
318 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
319 static const char *const f32_patt[] = {
320 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
321 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
322 };
323 static const char *const f16_patt[] = {
324 f32_1, f32_2, f32_3, f16_4, f16_5, f16_6, f16_7, f16_8,
325 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
--- 103 unchanged lines hidden (view full) ---
429 flag_16bit_code = new_16bit_code_flag;
430}
431
432const pseudo_typeS md_pseudo_table[] =
433{
434#ifndef I386COFF
435 {"bss", s_bss, 0},
436#endif
437#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
438 {"align", s_align_bytes, 0},
439#else
440 {"align", s_align_ptwo, 0},
441#endif
442 {"ffloat", float_cons, 'f'},
443 {"dfloat", float_cons, 'd'},
444 {"tfloat", float_cons, 'x'},
445 {"value", cons, 2},
--- 352 unchanged lines hidden (view full) ---
798 * the beginning of the section instead of the symbol. Basically we need
799 * to make sure that the dynamic relocations are done correctly, so in
800 * some cases we force the original symbol to be used.
801 */
802int
803tc_i386_fix_adjustable(fixP)
804 fixS * fixP;
805{
806#ifdef OBJ_ELF
807 /* Prevent all adjustments to global symbols. */
808 if (S_IS_EXTERN (fixP->fx_addsy))
809 return 0;
810 if (S_IS_WEAK (fixP->fx_addsy))
811 return 0;
812#endif /* ! defined (OBJ_AOUT) */
813 /* adjust_reloc_syms doesn't know about the GOT */
814 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
--- 14 unchanged lines hidden (view full) ---
829/* This is the guts of the machine-dependent assembler. LINE points to a
830 machine dependent instruction. This function is supposed to emit
831 the frags/bytes it assembles to. */
832
833void
834md_assemble (line)
835 char *line;
836{
837 /* Points to template once we've found it. */
838 const template *t;
839
840 /* Count the size of the instruction generated. */
841 int insn_size = 0;
842
843 /* Possible templates for current insn */
844 templates *current_templates = (templates *) 0;
845
846 int j;
847
848 /* Wait prefix needs to come before any other prefixes, so handle it
849 specially. wait_prefix will hold the opcode modifier flag FWait
850 if a wait prefix is given. */
851 int wait_prefix = 0;
852
853 /* Initialize globals. */
854 memset (&i, '\0', sizeof (i));
855 for (j = 0; j < MAX_OPERANDS; j++)
856 i.disp_reloc[j] = NO_RELOC;
857 memset (disp_expressions, '\0', sizeof (disp_expressions));
858 memset (im_expressions, '\0', sizeof (im_expressions));
859 save_stack_p = save_stack; /* reset stack pointer */
860
861 /* First parse an opcode & call i386_operand for the operands.
862 We assume that the scrubber has arranged it so that line[0] is the valid
863 start of a (possibly prefixed) opcode. */
864 {
865 char *l = line;
866
867 /* 1 if operand is pending after ','. */
868 unsigned int expecting_operand = 0;
869 /* 1 if we found a prefix only acceptable with string insns. */
--- 35 unchanged lines hidden (view full) ---
905 RESTORE_END_STRING (l);
906 /* check for repeated prefix */
907 for (q = 0; q < i.prefixes; q++)
908 if (i.prefix[q] == prefix->prefix_code)
909 {
910 as_bad ("same prefix used twice; you don't really want this!");
911 return;
912 }
913 if (prefix->prefix_code == FWAIT_OPCODE)
914 {
915 if (wait_prefix != 0)
916 {
917 as_bad ("same prefix used twice; you don't really want this!");
918 return;
919 }
920 wait_prefix = FWait;
921 }
922 else
923 {
924 if (i.prefixes == MAX_PREFIXES)
925 {
926 as_bad ("too many opcode prefixes");
927 return;
928 }
929 i.prefix[i.prefixes++] = prefix->prefix_code;
930 if (prefix->prefix_code == REPE
931 || prefix->prefix_code == REPNE)
932 expecting_string_instruction = 1;
933 }
934 /* skip past PREFIX_SEPERATOR and reset token_start */
935 token_start = ++l;
936 }
937 }
938 END_STRING_AND_SAVE (l);
939 if (token_start == l)
940 {
941 as_bad ("expecting opcode; got nothing");
--- 203 unchanged lines hidden (view full) ---
1145 continue;
1146
1147 /* try reversing direction of operands */
1148 overlap0 = i.types[0] & t->operand_types[1];
1149 overlap1 = i.types[1] & t->operand_types[0];
1150 if (!MATCH (overlap0, i.types[0]) ||
1151 !MATCH (overlap1, i.types[1]) ||
1152 !CONSISTENT_REGISTER_MATCH (overlap0, overlap1,
1153 t->operand_types[1],
1154 t->operand_types[0]))
1155 {
1156 /* does not match either direction */
1157 continue;
1158 }
1159 /* found a reverse match here -- slip through */
1160 /* found_reverse_match holds which of D or FloatD we've found */
1161 found_reverse_match = t->opcode_modifier & COMES_IN_BOTH_DIRECTIONS;
1162 } /* endif: not forward match */
--- 16 unchanged lines hidden (view full) ---
1179 break; /* we've found a match; break out of loop */
1180 } /* for (t = ... */
1181 if (t == current_templates->end)
1182 { /* we found no match */
1183 as_bad ("operands given don't match any known 386 instruction");
1184 return;
1185 }
1186
1187 /* Copy the template we found. */
1188 i.tm = *t;
1189 i.tm.opcode_modifier |= wait_prefix;
1190
1191 if (found_reverse_match)
1192 {
1193 i.tm.operand_types[0] = t->operand_types[1];
1194 i.tm.operand_types[1] = t->operand_types[0];
1195 }
1196
1197 /* If the matched instruction specifies an explicit opcode suffix,
1198 use it - and make sure none has already been specified. */
1199 if (i.tm.opcode_modifier & (Data16|Data32))
1200 {
1201 if (i.suffix)
1202 {
1203 as_bad ("extraneous opcode suffix given");
1204 return;
1205 }
1206 if (i.tm.opcode_modifier & Data16)
1207 i.suffix = WORD_OPCODE_SUFFIX;
1208 else
1209 i.suffix = DWORD_OPCODE_SUFFIX;
1210 }
1211
1212 /* If there's no opcode suffix we try to invent one based on register
1213 operands. */
1214 if (!i.suffix && i.reg_operands)
--- 80 unchanged lines hidden (view full) ---
1295 i.reg_operands--;
1296 if (overlap1 & ImplicitRegister)
1297 i.reg_operands--;
1298 if (overlap2 & ImplicitRegister)
1299 i.reg_operands--;
1300 if (overlap0 & Imm1)
1301 i.imm_operands = 0; /* kludge for shift insns */
1302
1303 /* Finalize opcode. First, we change the opcode based on the operand
1304 size given by i.suffix: we never have to change things for byte insns,
1305 or when no opcode suffix is need to size the operands. */
1306
1307 if (!i.suffix && (i.tm.opcode_modifier & W))
1308 {
1309 as_bad ("no opcode suffix given and no register operands; can't size instruction");
1310 return;
1311 }
1312
1313 if (i.suffix && i.suffix != BYTE_OPCODE_SUFFIX)
1314 {
1315 /* Select between byte and word/dword operations. */
1316 if (i.tm.opcode_modifier & W)
1317 i.tm.base_opcode |= W;
1318 /* Now select between word & dword operations via the
1319 operand size prefix. */
1320 if ((i.suffix == WORD_OPCODE_SUFFIX) ^ flag_16bit_code)
1321 {
1322 if (i.prefixes == MAX_PREFIXES)
1323 {
1324 as_bad ("%d prefixes given and data size prefix gives too many prefixes",
1325 MAX_PREFIXES);
1326 return;
1327 }
1328 i.prefix[i.prefixes++] = WORD_PREFIX_OPCODE;
1329 }
1330 }
1331
1332 /* For insns with operands there are more diddles to do to the opcode. */
--- 10 unchanged lines hidden (view full) ---
1343
1344
1345 /* If we found a reverse match we must alter the opcode direction bit
1346 found_reverse_match holds bit to set (different for int &
1347 float insns). */
1348
1349 if (found_reverse_match)
1350 {
1351 i.tm.base_opcode |= found_reverse_match;
1352 }
1353
1354 /* The imul $imm, %reg instruction is converted into
1355 imul $imm, %reg, %reg. */
1356 if (i.tm.opcode_modifier & imulKludge)
1357 {
1358 /* Pretend we saw the 3 operand case. */
1359 i.regs[2] = i.regs[1];
1360 i.reg_operands = 2;
1361 }
1362
1363 /* The clr %reg instruction is converted into xor %reg, %reg. */
1364 if (i.tm.opcode_modifier & iclrKludge)
1365 {
1366 i.regs[1] = i.regs[0];
1367 i.reg_operands = 2;
1368 }
1369
1370 /* Certain instructions expect the destination to be in the i.rm.reg
1371 field. This is by far the exceptional case. For these
1372 instructions, if the source operand is a register, we must reverse
1373 the i.rm.reg and i.rm.regmem fields. We accomplish this by faking
1374 that the two register operands were given in the reverse order. */
1375 if ((i.tm.opcode_modifier & ReverseRegRegmem) && i.reg_operands == 2)
1376 {
1377 unsigned int first_reg_operand = (i.types[0] & Reg) ? 0 : 1;
1378 unsigned int second_reg_operand = first_reg_operand + 1;
1379 reg_entry *tmp = i.regs[first_reg_operand];
1380 i.regs[first_reg_operand] = i.regs[second_reg_operand];
1381 i.regs[second_reg_operand] = tmp;
1382 }
1383
1384 if (i.tm.opcode_modifier & ShortForm)
1385 {
1386 /* The register or float register operand is in operand 0 or 1. */
1387 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
1388 /* Register goes in low 3 bits of opcode. */
1389 i.tm.base_opcode |= i.regs[op]->reg_num;
1390 }
1391 else if (i.tm.opcode_modifier & ShortFormW)
1392 {
1393 /* Short form with 0x8 width bit. Register is always dest. operand */
1394 i.tm.base_opcode |= i.regs[1]->reg_num;
1395 if (i.suffix == WORD_OPCODE_SUFFIX ||
1396 i.suffix == DWORD_OPCODE_SUFFIX)
1397 i.tm.base_opcode |= 0x8;
1398 }
1399 else if (i.tm.opcode_modifier & Seg2ShortForm)
1400 {
1401 if (i.tm.base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1)
1402 {
1403 as_bad ("you can't 'pop cs' on the 386.");
1404 return;
1405 }
1406 i.tm.base_opcode |= (i.regs[0]->reg_num << 3);
1407 }
1408 else if (i.tm.opcode_modifier & Seg3ShortForm)
1409 {
1410 /* 'push %fs' is 0x0fa0; 'pop %fs' is 0x0fa1.
1411 'push %gs' is 0x0fa8; 'pop %fs' is 0x0fa9.
1412 So, only if i.regs[0]->reg_num == 5 (%gs) do we need
1413 to change the opcode. */
1414 if (i.regs[0]->reg_num == 5)
1415 i.tm.base_opcode |= 0x08;
1416 }
1417 else if ((i.tm.base_opcode & ~DW) == MOV_AX_DISP32)
1418 {
1419 /* This is a special non-modrm instruction
1420 that addresses memory with a 32-bit displacement mode anyway,
1421 and thus requires an address-size prefix if in 16-bit mode. */
1422 uses_mem_addrmode = 1;
1423 default_seg = &ds;
1424 }
1425 else if (i.tm.opcode_modifier & Modrm)
1426 {
1427 /* The opcode is completed (modulo i.tm.extension_opcode which
1428 must be put into the modrm byte).
1429 Now, we make the modrm & index base bytes based on all the
1430 info we've collected. */
1431
1432 /* i.reg_operands MUST be the number of real register operands;
1433 implicit registers do not count. */
1434 if (i.reg_operands == 2)
1435 {
1436 unsigned int source, dest;
1437 source = ((i.types[0]
1438 & (Reg
--- 135 unchanged lines hidden (view full) ---
1574 {
1575 seg_index = (i.rm.mode << 3) | i.rm.regmem;
1576 default_seg = one_byte_segment_defaults[seg_index];
1577 }
1578 }
1579 }
1580
1581 /* Fill in i.rm.reg or i.rm.regmem field with register
1582 operand (if any) based on i.tm.extension_opcode.
1583 Again, we must be careful to make sure that
1584 segment/control/debug/test/MMX registers are coded
1585 into the i.rm.reg field. */
1586 if (i.reg_operands)
1587 {
1588 unsigned int op =
1589 ((i.types[0]
1590 & (Reg | SReg2 | SReg3 | Control | Debug
1591 | Test | RegMMX))
1592 ? 0
1593 : ((i.types[1]
1594 & (Reg | SReg2 | SReg3 | Control | Debug
1595 | Test | RegMMX))
1596 ? 1
1597 : 2));
1598 /* If there is an extension opcode to put here, the
1599 register number must be put into the regmem field. */
1600 if (i.tm.extension_opcode != None)
1601 i.rm.regmem = i.regs[op]->reg_num;
1602 else
1603 i.rm.reg = i.regs[op]->reg_num;
1604
1605 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
1606 we must set it to 3 to indicate this is a register
1607 operand int the regmem field */
1608 if (!i.mem_operands)
1609 i.rm.mode = 3;
1610 }
1611
1612 /* Fill in i.rm.reg field with extension opcode (if any). */
1613 if (i.tm.extension_opcode != None)
1614 i.rm.reg = i.tm.extension_opcode;
1615 }
1616
1617 if (i.rm.mode != 3)
1618 uses_mem_addrmode = 1;
1619 }
1620
1621 /* GAS currently doesn't support 16-bit memory addressing modes at all,
1622 so if we're writing 16-bit code and using a memory addressing mode,
--- 24 unchanged lines hidden (view full) ---
1647 return;
1648 }
1649 i.prefix[i.prefixes++] = i.seg->seg_prefix;
1650 }
1651 }
1652 }
1653
1654 /* Handle conversion of 'int $3' --> special int3 insn. */
1655 if (i.tm.base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3)
1656 {
1657 i.tm.base_opcode = INT3_OPCODE;
1658 i.imm_operands = 0;
1659 }
1660
1661 /* We are ready to output the insn. */
1662 {
1663 register char *p;
1664
1665 /* Output jumps. */
1666 if (i.tm.opcode_modifier & Jump)
1667 {
1668 unsigned long n = i.disps[0]->X_add_number;
1669
1670 if (i.disps[0]->X_op == O_constant)
1671 {
1672 if (fits_in_signed_byte (n))
1673 {
1674 p = frag_more (2);
1675 insn_size += 2;
1676 p[0] = i.tm.base_opcode;
1677 p[1] = n;
1678 }
1679 else
1680 { /* It's an absolute word/dword displacement. */
1681
1682 /* Use only 16-bit jumps for 16-bit code,
1683 because text segments are limited to 64K anyway;
1684 use only 32-bit jumps for 32-bit code,
1685 because they're faster. */
1686 int jmp_size = flag_16bit_code ? 2 : 4;
1687 if (flag_16bit_code && !fits_in_signed_word (n))
1688 {
1689 as_bad ("16-bit jump out of range");
1690 return;
1691 }
1692
1693 if (i.tm.base_opcode == JUMP_PC_RELATIVE)
1694 { /* pace */
1695 /* unconditional jump */
1696 p = frag_more (1 + jmp_size);
1697 insn_size += 1 + jmp_size;
1698 p[0] = (char) 0xe9;
1699 md_number_to_chars (&p[1], (valueT) n, jmp_size);
1700 }
1701 else
1702 {
1703 /* conditional jump */
1704 p = frag_more (2 + jmp_size);
1705 insn_size += 2 + jmp_size;
1706 p[0] = TWO_BYTE_OPCODE_ESCAPE;
1707 p[1] = i.tm.base_opcode + 0x10;
1708 md_number_to_chars (&p[2], (valueT) n, jmp_size);
1709 }
1710 }
1711 }
1712 else
1713 {
1714 if (flag_16bit_code)
1715 {
1716 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1717 insn_size += 1;
1718 }
1719
1720 /* It's a symbol; end frag & setup for relax.
1721 Make sure there are more than 6 chars left in the current frag;
1722 if not we'll have to start a new one. */
1723 frag_grow (7);
1724 p = frag_more (1);
1725 insn_size += 1;
1726 p[0] = i.tm.base_opcode;
1727 frag_var (rs_machine_dependent,
1728 6, /* 2 opcode/prefix + 4 displacement */
1729 1,
1730 ((unsigned char) *p == JUMP_PC_RELATIVE
1731 ? ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE)
1732 : ENCODE_RELAX_STATE (COND_JUMP, BYTE)),
1733 i.disps[0]->X_add_symbol,
1734 (offsetT) n, p);
1735 }
1736 }
1737 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
1738 {
1739 int size = (i.tm.opcode_modifier & JumpByte) ? 1 : 4;
1740 unsigned long n = i.disps[0]->X_add_number;
1741 unsigned char *q;
1742
1743 /* The jcx/jecx instruction might need a data size prefix. */
1744 for (q = i.prefix; q < i.prefix + i.prefixes; q++)
1745 {
1746 if (*q == WORD_PREFIX_OPCODE)
1747 {
1748 /* The jcxz/jecxz instructions are marked with Data16
1749 and Data32, which means that they may get
1750 WORD_PREFIX_OPCODE added to the list of prefixes.
1751 However, the are correctly distinguished using
1752 ADDR_PREFIX_OPCODE. Here we look for
1753 WORD_PREFIX_OPCODE, and actually emit
1754 ADDR_PREFIX_OPCODE. This is a hack, but, then, so
1755 is the instruction itself.
1756
1757 If an explicit suffix is used for the loop
1758 instruction, that actually controls whether we use
1759 cx vs. ecx. This is also controlled by
1760 ADDR_PREFIX_OPCODE.
1761
1762 I don't know if there is any valid case in which we
1763 want to emit WORD_PREFIX_OPCODE, but I am keeping
1764 the old behaviour for safety. */
1765
1766 if (IS_JUMP_ON_CX_ZERO (i.tm.base_opcode)
1767 || IS_LOOP_ECX_TIMES (i.tm.base_opcode))
1768 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
1769 else
1770 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1771 insn_size += 1;
1772 break;
1773 }
1774 }
1775
1776 if ((size == 4) && (flag_16bit_code))
1777 {
1778 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1779 insn_size += 1;
1780 }
1781
1782 if (fits_in_unsigned_byte (i.tm.base_opcode))
1783 {
1784 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
1785 insn_size += 1;
1786 }
1787 else
1788 {
1789 p = frag_more (2); /* opcode can be at most two bytes */
1790 insn_size += 2;
1791 /* put out high byte first: can't use md_number_to_chars! */
1792 *p++ = (i.tm.base_opcode >> 8) & 0xff;
1793 *p = i.tm.base_opcode & 0xff;
1794 }
1795
1796 p = frag_more (size);
1797 insn_size += size;
1798 if (i.disps[0]->X_op == O_constant)
1799 {
1800 md_number_to_chars (p, (valueT) n, size);
1801 if (size == 1 && !fits_in_signed_byte (n))
--- 4 unchanged lines hidden (view full) ---
1806 }
1807 else
1808 {
1809 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
1810 i.disps[0], 1, reloc (size, 1, i.disp_reloc[0]));
1811
1812 }
1813 }
1814 else if (i.tm.opcode_modifier & JumpInterSegment)
1815 {
1816 if (flag_16bit_code)
1817 {
1818 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1819 insn_size += 1;
1820 }
1821
1822 p = frag_more (1 + 2 + 4); /* 1 opcode; 2 segment; 4 offset */
1823 insn_size += 1 + 2 + 4;
1824 p[0] = i.tm.base_opcode;
1825 if (i.imms[1]->X_op == O_constant)
1826 md_number_to_chars (p + 1, (valueT) i.imms[1]->X_add_number, 4);
1827 else
1828 fix_new_exp (frag_now, p + 1 - frag_now->fr_literal, 4,
1829 i.imms[1], 0, BFD_RELOC_32);
1830 if (i.imms[0]->X_op != O_constant)
1831 as_bad ("can't handle non absolute segment in long call/jmp");
1832 md_number_to_chars (p + 5, (valueT) i.imms[0]->X_add_number, 2);
1833 }
1834 else
1835 {
1836 /* Output normal instructions here. */
1837 unsigned char *q;
1838
1839 /* Hack for fwait. It must come before any prefixes, as it
1840 really is an instruction rather than a prefix. */
1841 if ((i.tm.opcode_modifier & FWait) != 0)
1842 {
1843 p = frag_more (1);
1844 insn_size += 1;
1845 md_number_to_chars (p, (valueT) FWAIT_OPCODE, 1);
1846 }
1847
1848 /* The prefix bytes. */
1849 for (q = i.prefix; q < i.prefix + i.prefixes; q++)
1850 {
1851 p = frag_more (1);
1852 insn_size += 1;
1853 md_number_to_chars (p, (valueT) *q, 1);
1854 }
1855
1856 /* Now the opcode; be careful about word order here! */
1857 if (fits_in_unsigned_byte (i.tm.base_opcode))
1858 {
1859 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
1860 insn_size += 1;
1861 }
1862 else if (fits_in_unsigned_word (i.tm.base_opcode))
1863 {
1864 p = frag_more (2);
1865 insn_size += 2;
1866 /* put out high byte first: can't use md_number_to_chars! */
1867 *p++ = (i.tm.base_opcode >> 8) & 0xff;
1868 *p = i.tm.base_opcode & 0xff;
1869 }
1870 else
1871 { /* opcode is either 3 or 4 bytes */
1872 if (i.tm.base_opcode & 0xff000000)
1873 {
1874 p = frag_more (4);
1875 insn_size += 4;
1876 *p++ = (i.tm.base_opcode >> 24) & 0xff;
1877 }
1878 else
1879 {
1880 p = frag_more (3);
1881 insn_size += 3;
1882 }
1883 *p++ = (i.tm.base_opcode >> 16) & 0xff;
1884 *p++ = (i.tm.base_opcode >> 8) & 0xff;
1885 *p = (i.tm.base_opcode) & 0xff;
1886 }
1887
1888 /* Now the modrm byte and base index byte (if present). */
1889 if (i.tm.opcode_modifier & Modrm)
1890 {
1891 p = frag_more (1);
1892 insn_size += 1;
1893 /* md_number_to_chars (p, i.rm, 1); */
1894 md_number_to_chars (p,
1895 (valueT) (i.rm.regmem << 0
1896 | i.rm.reg << 3
1897 | i.rm.mode << 6),
--- 235 unchanged lines hidden (view full) ---
2133 }
2134
2135 exp = &im_expressions[i.imm_operands++];
2136 i.imms[this_operand] = exp;
2137 save_input_line_pointer = input_line_pointer;
2138 input_line_pointer = ++op_string; /* must advance op_string! */
2139 SKIP_WHITESPACE ();
2140 exp_seg = expression (exp);
2141 if (*input_line_pointer != '\0')
2142 {
2143 /* This should be as_bad, but some versions of gcc, up to
2144 about 2.8 and egcs 1.01, generate a bogus @GOTOFF(%ebx)
2145 in certain cases. Oddly, the code in question turns out
2146 to work correctly anyhow, so we make this just a warning
2147 until those versions of gcc are obsolete. */
2148 as_warn ("warning: unrecognized characters `%s' in expression",
2149 input_line_pointer);
2150 }
2151 input_line_pointer = save_input_line_pointer;
2152
2153 if (exp->X_op == O_absent)
2154 {
2155 /* missing or bad expr becomes absolute 0 */
2156 as_bad ("missing or invalid immediate expression '%s' taken as 0",
2157 operand_string);
2158 exp->X_op = O_constant;
--- 53 unchanged lines hidden (view full) ---
2212 if (i.mem_operands == MAX_MEMORY_OPERANDS)
2213 {
2214 as_bad ("more than 1 memory reference in instruction");
2215 return 0;
2216 }
2217 i.mem_operands++;
2218
2219 /* Determine type of memory operand from opcode_suffix;
2220 no opcode suffix implies general memory references. */
2221 switch (i.suffix)
2222 {
2223 case BYTE_OPCODE_SUFFIX:
2224 i.types[this_operand] |= Mem8;
2225 break;
2226 case WORD_OPCODE_SUFFIX:
2227 i.types[this_operand] |= Mem16;
2228 break;
--- 154 unchanged lines hidden (view full) ---
2383 char *save_input_line_pointer;
2384 exp = &disp_expressions[i.disp_operands];
2385 i.disps[this_operand] = exp;
2386 i.disp_reloc[this_operand] = NO_RELOC;
2387 i.disp_operands++;
2388 save_input_line_pointer = input_line_pointer;
2389 input_line_pointer = displacement_string_start;
2390 END_STRING_AND_SAVE (displacement_string_end);
2391
2392#ifndef LEX_AT
2393 {
2394 /*
2395 * We can have operands of the form
2396 * <symbol>@GOTOFF+<nnn>
2397 * Take the easy way out here and copy everything
2398 * into a temporary buffer...
2399 */
2400 register char *cp;
2401
2402 cp = strchr (input_line_pointer, '@');
2403 if (cp != NULL)
2404 {
2405 char *tmpbuf;
2406
2407 if (GOT_symbol == NULL)
2408 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
2409
2410 tmpbuf = (char *) alloca ((cp - input_line_pointer) + 20);
2411
2412 if (strncmp (cp + 1, "PLT", 3) == 0)
2413 {
2414 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
2415 *cp = '\0';
2416 strcpy (tmpbuf, input_line_pointer);
2417 strcat (tmpbuf, cp + 1 + 3);
2418 *cp = '@';
2419 }
2420 else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
2421 {
2422 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
2423 *cp = '\0';
2424 strcpy (tmpbuf, input_line_pointer);
2425 strcat (tmpbuf, cp + 1 + 6);
2426 *cp = '@';
2427 }
2428 else if (strncmp (cp + 1, "GOT", 3) == 0)
2429 {
2430 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
2431 *cp = '\0';
2432 strcpy (tmpbuf, input_line_pointer);
2433 strcat (tmpbuf, cp + 1 + 3);
2434 *cp = '@';
2435 }
2436 else
2437 as_bad ("Bad reloc specifier '%s' in expression", cp + 1);
2438
2439 input_line_pointer = tmpbuf;
2440 }
2441 }
2442#endif
2443
2444 exp_seg = expression (exp);
2445
2446#ifdef BFD_ASSEMBLER
2447 /* We do this to make sure that the section symbol is in
2448 the symbol table. We will ultimately change the relocation
2449 to be relative to the beginning of the section */
2450 if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF)
2451 {
--- 298 unchanged lines hidden (view full) ---
2750md_apply_fix3 (fixP, valp, seg)
2751 fixS *fixP; /* The fix we're to put in. */
2752 valueT *valp; /* Pointer to the value of the bits. */
2753 segT seg; /* Segment fix is from. */
2754{
2755 register char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
2756 valueT value = *valp;
2757
2758 if (fixP->fx_r_type == BFD_RELOC_32 && fixP->fx_pcrel)
2759 fixP->fx_r_type = BFD_RELOC_32_PCREL;
2760
2761#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
2762 /*
2763 * This is a hack. There should be a better way to
2764 * handle this.
2765 */
2766 if (fixP->fx_r_type == BFD_RELOC_32_PCREL && fixP->fx_addsy)
2767 {
2768#ifndef OBJ_AOUT
2769 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2770 || OUTPUT_FLAVOR == bfd_target_coff_flavour)
2771 value += fixP->fx_where + fixP->fx_frag->fr_address;
2772#endif
2773#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2774 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2775 && (S_GET_SEGMENT (fixP->fx_addsy) == seg
2776 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0))
2777 {
2778 /* Yes, we add the values in twice. This is because
2779 bfd_perform_relocation subtracts them out again. I think
2780 bfd_perform_relocation is broken, but I don't dare change
2781 it. FIXME. */
2782 value += fixP->fx_where + fixP->fx_frag->fr_address;
2783 }
2784#endif
2785#if defined (OBJ_COFF) && defined (TE_PE)
2786 /* For some reason, the PE format does not store a section
2787 address offset for a PC relative symbol. */
2788 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
2789 value += md_pcrel_from (fixP);
2790#endif
2791 }
2792
2793 /* Fix a few things - the dynamic linker expects certain values here,
2794 and we must not dissappoint it. */
2795#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2796 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2797 && fixP->fx_addsy)
2798 switch(fixP->fx_r_type) {
--- 333 unchanged lines hidden (view full) ---
3132 bfd_reloc_code_real_type code;
3133
3134 switch(fixp->fx_r_type)
3135 {
3136 case BFD_RELOC_386_PLT32:
3137 case BFD_RELOC_386_GOT32:
3138 case BFD_RELOC_386_GOTOFF:
3139 case BFD_RELOC_386_GOTPC:
3140 case BFD_RELOC_RVA:
3141 code = fixp->fx_r_type;
3142 break;
3143 default:
3144 switch (F (fixp->fx_size, fixp->fx_pcrel))
3145 {
3146 MAP (1, 0, BFD_RELOC_8);
3147 MAP (2, 0, BFD_RELOC_16);
3148 MAP (4, 0, BFD_RELOC_32);
--- 109 unchanged lines hidden ---