| pci_emul.c (221942) | pci_emul.c (234761) |
|---|---|
| 1/*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 31 unchanged lines hidden (view full) --- 40#include <assert.h> 41 42#include <machine/vmm.h> 43#include <vmmapi.h> 44 45#include "fbsdrun.h" 46#include "inout.h" 47#include "pci_emul.h" | 1/*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 31 unchanged lines hidden (view full) --- 40#include <assert.h> 41 42#include <machine/vmm.h> 43#include <vmmapi.h> 44 45#include "fbsdrun.h" 46#include "inout.h" 47#include "pci_emul.h" |
| 48#include "instruction_emul.h" |
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| 48 49#define CONF1_ADDR_PORT 0x0cf8 50#define CONF1_DATA_PORT 0x0cfc 51 52#define CFGWRITE(pi,off,val,b) \ 53do { \ 54 if ((b) == 1) { \ 55 pci_set_cfgdata8((pi),(off),(val)); \ --- 511 unchanged lines hidden (view full) --- 567 struct msicap msicap; 568 569 pci_populate_msicap(&msicap, msgnum, 0); 570 571 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 572} 573 574void | 49 50#define CONF1_ADDR_PORT 0x0cf8 51#define CONF1_DATA_PORT 0x0cfc 52 53#define CFGWRITE(pi,off,val,b) \ 54do { \ 55 if ((b) == 1) { \ 56 pci_set_cfgdata8((pi),(off),(val)); \ --- 511 unchanged lines hidden (view full) --- 568 struct msicap msicap; 569 570 pci_populate_msicap(&msicap, msgnum, 0); 571 572 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 573} 574 575void |
| 576msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 577 int bytes, uint32_t val) 578{ 579 uint16_t msgctrl, rwmask; 580 int off, table_bar; 581 582 off = offset - capoff; 583 table_bar = pi->pi_msix.table_bar; 584 /* Message Control Register */ 585 if (off == 2 && bytes == 2) { 586 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 587 msgctrl = pci_get_cfgdata16(pi, offset); 588 msgctrl &= ~rwmask; 589 msgctrl |= val & rwmask; 590 val = msgctrl; 591 592 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 593 } 594 595 CFGWRITE(pi, offset, val, bytes); 596} 597 598void |
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| 575msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 576 int bytes, uint32_t val) 577{ 578 uint16_t msgctrl, rwmask, msgdata, mme; 579 uint32_t addrlo; 580 581 /* 582 * If guest is writing to the message control register make sure --- 259 unchanged lines hidden (view full) --- 842 mask &= PCIM_BAR_MEM_BASE; 843 bar = ((uint64_t)*eax << 32) & mask; 844 bar = bar >> 32; 845 break; 846 default: 847 assert(0); 848 } 849 pci_set_cfgdata32(pi, coff, bar); | 599msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 600 int bytes, uint32_t val) 601{ 602 uint16_t msgctrl, rwmask, msgdata, mme; 603 uint32_t addrlo; 604 605 /* 606 * If guest is writing to the message control register make sure --- 259 unchanged lines hidden (view full) --- 866 mask &= PCIM_BAR_MEM_BASE; 867 bar = ((uint64_t)*eax << 32) & mask; 868 bar = bar >> 32; 869 break; 870 default: 871 assert(0); 872 } 873 pci_set_cfgdata32(pi, coff, bar); |
| 874 875 if (pi->pi_bar[idx].handler) { 876 pi->pi_bar[idx].handler(pi, idx, bar); 877 } 878 |
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| 850 } else if (pci_emul_iscap(pi, coff)) { 851 pci_emul_capwrite(pi, coff, bytes, *eax); 852 } else { 853 CFGWRITE(pi, coff, *eax, bytes); 854 } 855 } 856 857 return (0); --- 119 unchanged lines hidden --- | 879 } else if (pci_emul_iscap(pi, coff)) { 880 pci_emul_capwrite(pi, coff, bytes, *eax); 881 } else { 882 CFGWRITE(pi, coff, *eax, bytes); 883 } 884 } 885 886 return (0); --- 119 unchanged lines hidden --- |