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pci_e82545.c (323425) pci_e82545.c (336161)
1/*
2 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org>
3 * Copyright (c) 2015 Peter Grehan <grehan@freebsd.org>
4 * Copyright (c) 2013 Jeremiah Lott, Avere Systems
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <sys/cdefs.h>
1/*
2 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org>
3 * Copyright (c) 2015 Peter Grehan <grehan@freebsd.org>
4 * Copyright (c) 2013 Jeremiah Lott, Avere Systems
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 14 unchanged lines hidden (view full) ---

23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: stable/11/usr.sbin/bhyve/pci_e82545.c 323425 2017-09-11 07:21:34Z rlibby $");
31__FBSDID("$FreeBSD: stable/11/usr.sbin/bhyve/pci_e82545.c 336161 2018-07-10 04:26:32Z araujo $");
32
33#include <sys/types.h>
34#ifndef WITHOUT_CAPSICUM
35#include <sys/capsicum.h>
36#endif
37#include <sys/limits.h>
38#include <sys/ioctl.h>
39#include <sys/uio.h>

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337 uint64_t good_octets_tx;
338 uint64_t missed_octets; /* counts missed and oversized */
339
340 uint8_t nvm_bits:6; /* number of bits remaining in/out */
341 uint8_t nvm_mode:2;
342#define E82545_NVM_MODE_OPADDR 0x0
343#define E82545_NVM_MODE_DATAIN 0x1
344#define E82545_NVM_MODE_DATAOUT 0x2
32
33#include <sys/types.h>
34#ifndef WITHOUT_CAPSICUM
35#include <sys/capsicum.h>
36#endif
37#include <sys/limits.h>
38#include <sys/ioctl.h>
39#include <sys/uio.h>

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337 uint64_t good_octets_tx;
338 uint64_t missed_octets; /* counts missed and oversized */
339
340 uint8_t nvm_bits:6; /* number of bits remaining in/out */
341 uint8_t nvm_mode:2;
342#define E82545_NVM_MODE_OPADDR 0x0
343#define E82545_NVM_MODE_DATAIN 0x1
344#define E82545_NVM_MODE_DATAOUT 0x2
345 /* EEPROM data */
346 uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE];
345 /* EEPROM data */
346 uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE];
347};
348
349static void e82545_reset(struct e82545_softc *sc, int dev);
350static void e82545_rx_enable(struct e82545_softc *sc);
351static void e82545_rx_disable(struct e82545_softc *sc);
352static void e82545_tap_callback(int fd, enum ev_type type, void *param);
353static void e82545_tx_start(struct e82545_softc *sc);
354static void e82545_tx_enable(struct e82545_softc *sc);

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1465 sc->esc_rx_enabled = 0;
1466 while (sc->esc_rx_active)
1467 pthread_cond_wait(&sc->esc_rx_cond, &sc->esc_mtx);
1468}
1469
1470static void
1471e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval)
1472{
347};
348
349static void e82545_reset(struct e82545_softc *sc, int dev);
350static void e82545_rx_enable(struct e82545_softc *sc);
351static void e82545_rx_disable(struct e82545_softc *sc);
352static void e82545_tap_callback(int fd, enum ev_type type, void *param);
353static void e82545_tx_start(struct e82545_softc *sc);
354static void e82545_tx_enable(struct e82545_softc *sc);

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1465 sc->esc_rx_enabled = 0;
1466 while (sc->esc_rx_active)
1467 pthread_cond_wait(&sc->esc_rx_cond, &sc->esc_mtx);
1468}
1469
1470static void
1471e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval)
1472{
1473 struct eth_uni *eu;
1473 struct eth_uni *eu;
1474 int idx;
1475
1476 idx = reg >> 1;
1477 assert(idx < 15);
1478
1479 eu = &sc->esc_uni[idx];
1480
1481 if (reg & 0x1) {

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1491 eu->eu_eth.octet[1] = wval >> 8;
1492 eu->eu_eth.octet[0] = wval;
1493 }
1494}
1495
1496static uint32_t
1497e82545_read_ra(struct e82545_softc *sc, int reg)
1498{
1474 int idx;
1475
1476 idx = reg >> 1;
1477 assert(idx < 15);
1478
1479 eu = &sc->esc_uni[idx];
1480
1481 if (reg & 0x1) {

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1491 eu->eu_eth.octet[1] = wval >> 8;
1492 eu->eu_eth.octet[0] = wval;
1493 }
1494}
1495
1496static uint32_t
1497e82545_read_ra(struct e82545_softc *sc, int reg)
1498{
1499 struct eth_uni *eu;
1499 struct eth_uni *eu;
1500 uint32_t retval;
1501 int idx;
1502
1503 idx = reg >> 1;
1504 assert(idx < 15);
1505
1506 eu = &sc->esc_uni[idx];
1507

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1735 }
1736}
1737
1738static uint32_t
1739e82545_read_register(struct e82545_softc *sc, uint32_t offset)
1740{
1741 uint32_t retval;
1742 int ridx;
1500 uint32_t retval;
1501 int idx;
1502
1503 idx = reg >> 1;
1504 assert(idx < 15);
1505
1506 eu = &sc->esc_uni[idx];
1507

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1735 }
1736}
1737
1738static uint32_t
1739e82545_read_register(struct e82545_softc *sc, uint32_t offset)
1740{
1741 uint32_t retval;
1742 int ridx;
1743
1743
1744 if (offset & 0x3) {
1745 DPRINTF("Unaligned register read offset:0x%x\r\n", offset);
1746 return 0;
1747 }
1744 if (offset & 0x3) {
1745 DPRINTF("Unaligned register read offset:0x%x\r\n", offset);
1746 return 0;
1747 }
1748
1748
1749 DPRINTF("Register read: 0x%x\r\n", offset);
1750
1751 switch (offset) {
1752 case E1000_CTRL:
1753 retval = sc->esc_CTRL;
1754 break;
1755 case E1000_STATUS:
1756 retval = E1000_STATUS_FD | E1000_STATUS_LU |

--- 630 unchanged lines hidden --- 		1749 DPRINTF("Register read: 0x%x\r\n", offset);
1750
1751 switch (offset) {
1752 case E1000_CTRL:
1753 retval = sc->esc_CTRL;
1754 break;
1755 case E1000_STATUS:
1756 retval = E1000_STATUS_FD | E1000_STATUS_LU |

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