| intel_utils.c (278605) | intel_utils.c (280260) |
|---|---|
| 1/*- 2 * Copyright (c) 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 14 unchanged lines hidden (view full) --- 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 14 unchanged lines hidden (view full) --- 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> |
| 31__FBSDID("$FreeBSD: head/sys/x86/iommu/intel_utils.c 278605 2015-02-11 23:28:28Z kib $"); | 31__FBSDID("$FreeBSD: head/sys/x86/iommu/intel_utils.c 280260 2015-03-19 13:57:47Z kib $"); |
| 32 33#include <sys/param.h> 34#include <sys/bus.h> 35#include <sys/kernel.h> 36#include <sys/lock.h> 37#include <sys/malloc.h> 38#include <sys/memdesc.h> 39#include <sys/mutex.h> 40#include <sys/proc.h> 41#include <sys/queue.h> 42#include <sys/rman.h> 43#include <sys/rwlock.h> 44#include <sys/sched.h> 45#include <sys/sf_buf.h> 46#include <sys/sysctl.h> 47#include <sys/systm.h> 48#include <sys/taskqueue.h> 49#include <sys/tree.h> | 32 33#include <sys/param.h> 34#include <sys/bus.h> 35#include <sys/kernel.h> 36#include <sys/lock.h> 37#include <sys/malloc.h> 38#include <sys/memdesc.h> 39#include <sys/mutex.h> 40#include <sys/proc.h> 41#include <sys/queue.h> 42#include <sys/rman.h> 43#include <sys/rwlock.h> 44#include <sys/sched.h> 45#include <sys/sf_buf.h> 46#include <sys/sysctl.h> 47#include <sys/systm.h> 48#include <sys/taskqueue.h> 49#include <sys/tree.h> |
| 50#include <sys/vmem.h> |
|
| 50#include <dev/pci/pcivar.h> 51#include <vm/vm.h> 52#include <vm/vm_extern.h> 53#include <vm/vm_kern.h> 54#include <vm/vm_object.h> 55#include <vm/vm_page.h> 56#include <vm/vm_map.h> 57#include <vm/vm_pageout.h> 58#include <machine/bus.h> 59#include <machine/cpu.h> | 51#include <dev/pci/pcivar.h> 52#include <vm/vm.h> 53#include <vm/vm_extern.h> 54#include <vm/vm_kern.h> 55#include <vm/vm_object.h> 56#include <vm/vm_page.h> 57#include <vm/vm_map.h> 58#include <vm/vm_pageout.h> 59#include <machine/bus.h> 60#include <machine/cpu.h> |
| 61#include <machine/intr_machdep.h> 62#include <x86/include/apicvar.h> |
|
| 60#include <x86/include/busdma_impl.h> 61#include <x86/iommu/intel_reg.h> 62#include <x86/iommu/busdma_dmar.h> 63#include <x86/iommu/intel_dmar.h> 64 65u_int 66dmar_nd2mask(u_int nd) 67{ --- 448 unchanged lines hidden (view full) --- 516 unit->hw_gcmd &= ~DMAR_GCMD_TE; 517 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 518 /* XXXKIB should have a timeout */ 519 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) != 0) 520 cpu_spinwait(); 521 return (0); 522} 523 | 63#include <x86/include/busdma_impl.h> 64#include <x86/iommu/intel_reg.h> 65#include <x86/iommu/busdma_dmar.h> 66#include <x86/iommu/intel_dmar.h> 67 68u_int 69dmar_nd2mask(u_int nd) 70{ --- 448 unchanged lines hidden (view full) --- 519 unit->hw_gcmd &= ~DMAR_GCMD_TE; 520 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 521 /* XXXKIB should have a timeout */ 522 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) != 0) 523 cpu_spinwait(); 524 return (0); 525} 526 |
| 527int 528dmar_load_irt_ptr(struct dmar_unit *unit) 529{ 530 uint64_t irta, s; 531 532 DMAR_ASSERT_LOCKED(unit); 533 irta = unit->irt_phys; 534 if (DMAR_X2APIC(unit)) 535 irta |= DMAR_IRTA_EIME; 536 s = fls(unit->irte_cnt) - 2; 537 KASSERT(unit->irte_cnt >= 2 && s <= DMAR_IRTA_S_MASK && 538 powerof2(unit->irte_cnt), 539 ("IRTA_REG_S overflow %x", unit->irte_cnt)); 540 irta |= s; 541 dmar_write8(unit, DMAR_IRTA_REG, irta); 542 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SIRTP); 543 /* XXXKIB should have a timeout */ 544 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRTPS) == 0) 545 cpu_spinwait(); 546 return (0); 547} 548 549int 550dmar_enable_ir(struct dmar_unit *unit) 551{ 552 553 DMAR_ASSERT_LOCKED(unit); 554 unit->hw_gcmd |= DMAR_GCMD_IRE; 555 unit->hw_gcmd &= ~DMAR_GCMD_CFI; 556 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 557 /* XXXKIB should have a timeout */ 558 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES) == 0) 559 cpu_spinwait(); 560 return (0); 561} 562 563int 564dmar_disable_ir(struct dmar_unit *unit) 565{ 566 567 DMAR_ASSERT_LOCKED(unit); 568 unit->hw_gcmd &= ~DMAR_GCMD_IRE; 569 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 570 /* XXXKIB should have a timeout */ 571 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES) != 0) 572 cpu_spinwait(); 573 return (0); 574} 575 |
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| 524#define BARRIER_F \ 525 u_int f_done, f_inproc, f_wakeup; \ 526 \ 527 f_done = 1 << (barrier_id * 3); \ 528 f_inproc = 1 << (barrier_id * 3 + 1); \ 529 f_wakeup = 1 << (barrier_id * 3 + 2) 530 531bool --- 58 unchanged lines hidden --- | 576#define BARRIER_F \ 577 u_int f_done, f_inproc, f_wakeup; \ 578 \ 579 f_done = 1 << (barrier_id * 3); \ 580 f_inproc = 1 << (barrier_id * 3 + 1); \ 581 f_wakeup = 1 << (barrier_id * 3 + 2) 582 583bool --- 58 unchanged lines hidden --- |