1/*-
2 * Copyright (c) 1995 Bruce D. Evans.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
| 1/*-
2 * Copyright (c) 1995 Bruce D. Evans.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
|
29 * $FreeBSD: stable/11/sys/x86/include/x86_var.h 361561 2020-05-27 18:55:24Z kib $
| 29 * $FreeBSD: stable/11/sys/x86/include/x86_var.h 362383 2020-06-19 13:48:23Z kib $
|
30 */
31
32#ifndef _X86_X86_VAR_H_
33#define _X86_X86_VAR_H_
34
35/*
36 * Miscellaneous machine-dependent declarations.
37 */
38
39extern long Maxmem;
40extern u_int basemem;
41extern int busdma_swi_pending;
42extern u_int cpu_exthigh;
43extern u_int cpu_feature;
44extern u_int cpu_feature2;
45extern u_int amd_feature;
46extern u_int amd_feature2;
47extern u_int amd_pminfo;
48extern u_int amd_extended_feature_extensions;
49extern u_int via_feature_rng;
50extern u_int via_feature_xcrypt;
51extern u_int cpu_clflush_line_size;
52extern u_int cpu_stdext_feature;
53extern u_int cpu_stdext_feature2;
54extern u_int cpu_stdext_feature3;
55extern uint64_t cpu_ia32_arch_caps;
56extern u_int cpu_fxsr;
57extern u_int cpu_high;
58extern u_int cpu_id;
59extern u_int cpu_max_ext_state_size;
60extern u_int cpu_mxcsr_mask;
61extern u_int cpu_procinfo;
62extern u_int cpu_procinfo2;
63extern char cpu_vendor[];
64extern u_int cpu_vendor_id;
65extern u_int cpu_mon_mwait_flags;
66extern u_int cpu_mon_min_size;
67extern u_int cpu_mon_max_size;
68extern u_int cpu_maxphyaddr;
69extern char ctx_switch_xsave[];
70extern u_int hv_high;
71extern char hv_vendor[];
72extern char kstack[];
73extern char sigcode[];
74extern int szsigcode;
75extern int vm_page_dump_size;
76extern int workaround_erratum383;
77extern int _udatasel;
78extern int _ucodesel;
79extern int _ucode32sel;
80extern int _ufssel;
81extern int _ugssel;
82extern int use_xsave;
83extern uint64_t xsave_mask;
84extern int pti;
85extern int hw_ibrs_ibpb_active;
86extern int hw_mds_disable;
87extern int hw_ssb_active;
88extern int x86_taa_enable;
89extern int cpu_flush_rsb_ctxsw;
| 30 */
31
32#ifndef _X86_X86_VAR_H_
33#define _X86_X86_VAR_H_
34
35/*
36 * Miscellaneous machine-dependent declarations.
37 */
38
39extern long Maxmem;
40extern u_int basemem;
41extern int busdma_swi_pending;
42extern u_int cpu_exthigh;
43extern u_int cpu_feature;
44extern u_int cpu_feature2;
45extern u_int amd_feature;
46extern u_int amd_feature2;
47extern u_int amd_pminfo;
48extern u_int amd_extended_feature_extensions;
49extern u_int via_feature_rng;
50extern u_int via_feature_xcrypt;
51extern u_int cpu_clflush_line_size;
52extern u_int cpu_stdext_feature;
53extern u_int cpu_stdext_feature2;
54extern u_int cpu_stdext_feature3;
55extern uint64_t cpu_ia32_arch_caps;
56extern u_int cpu_fxsr;
57extern u_int cpu_high;
58extern u_int cpu_id;
59extern u_int cpu_max_ext_state_size;
60extern u_int cpu_mxcsr_mask;
61extern u_int cpu_procinfo;
62extern u_int cpu_procinfo2;
63extern char cpu_vendor[];
64extern u_int cpu_vendor_id;
65extern u_int cpu_mon_mwait_flags;
66extern u_int cpu_mon_min_size;
67extern u_int cpu_mon_max_size;
68extern u_int cpu_maxphyaddr;
69extern char ctx_switch_xsave[];
70extern u_int hv_high;
71extern char hv_vendor[];
72extern char kstack[];
73extern char sigcode[];
74extern int szsigcode;
75extern int vm_page_dump_size;
76extern int workaround_erratum383;
77extern int _udatasel;
78extern int _ucodesel;
79extern int _ucode32sel;
80extern int _ufssel;
81extern int _ugssel;
82extern int use_xsave;
83extern uint64_t xsave_mask;
84extern int pti;
85extern int hw_ibrs_ibpb_active;
86extern int hw_mds_disable;
87extern int hw_ssb_active;
88extern int x86_taa_enable;
89extern int cpu_flush_rsb_ctxsw;
|
| 90extern int x86_rngds_mitg_enable;
|
90
91struct pcb;
92struct thread;
93struct reg;
94struct fpreg;
95struct dbreg;
96struct dumperinfo;
97struct trapframe;
98
99/*
100 * The interface type of the interrupt handler entry point cannot be
101 * expressed in C. Use simplest non-variadic function type as an
102 * approximation.
103 */
104typedef void alias_for_inthand_t(void);
105
106/*
107 * Returns the maximum physical address that can be used with the
108 * current system.
109 */
110static __inline vm_paddr_t
111cpu_getmaxphyaddr(void)
112{
113#if defined(__i386__) && !defined(PAE)
114 return (0xffffffff);
115#else
116 return ((1ULL << cpu_maxphyaddr) - 1);
117#endif
118}
119
120void *alloc_fpusave(int flags);
121void busdma_swi(void);
122bool cpu_mwait_usable(void);
123void cpu_probe_amdc1e(void);
124void cpu_setregs(void);
125void dump_add_page(vm_paddr_t);
126void dump_drop_page(vm_paddr_t);
127void finishidentcpu(void);
128void identify_cpu1(void);
129void identify_cpu2(void);
130void identify_hypervisor(void);
131void initializecpu(void);
132void initializecpucache(void);
133bool fix_cpuid(void);
134void fillw(int /*u_short*/ pat, void *base, size_t cnt);
135int is_physical_memory(vm_paddr_t addr);
136int isa_nmi(int cd);
137void handle_ibrs_entry(void);
138void handle_ibrs_exit(void);
139void hw_ibrs_recalculate(bool all_cpus);
140void hw_mds_recalculate(void);
141void hw_ssb_recalculate(bool all_cpus);
142void x86_taa_recalculate(void);
| 91
92struct pcb;
93struct thread;
94struct reg;
95struct fpreg;
96struct dbreg;
97struct dumperinfo;
98struct trapframe;
99
100/*
101 * The interface type of the interrupt handler entry point cannot be
102 * expressed in C. Use simplest non-variadic function type as an
103 * approximation.
104 */
105typedef void alias_for_inthand_t(void);
106
107/*
108 * Returns the maximum physical address that can be used with the
109 * current system.
110 */
111static __inline vm_paddr_t
112cpu_getmaxphyaddr(void)
113{
114#if defined(__i386__) && !defined(PAE)
115 return (0xffffffff);
116#else
117 return ((1ULL << cpu_maxphyaddr) - 1);
118#endif
119}
120
121void *alloc_fpusave(int flags);
122void busdma_swi(void);
123bool cpu_mwait_usable(void);
124void cpu_probe_amdc1e(void);
125void cpu_setregs(void);
126void dump_add_page(vm_paddr_t);
127void dump_drop_page(vm_paddr_t);
128void finishidentcpu(void);
129void identify_cpu1(void);
130void identify_cpu2(void);
131void identify_hypervisor(void);
132void initializecpu(void);
133void initializecpucache(void);
134bool fix_cpuid(void);
135void fillw(int /*u_short*/ pat, void *base, size_t cnt);
136int is_physical_memory(vm_paddr_t addr);
137int isa_nmi(int cd);
138void handle_ibrs_entry(void);
139void handle_ibrs_exit(void);
140void hw_ibrs_recalculate(bool all_cpus);
141void hw_mds_recalculate(void);
142void hw_ssb_recalculate(bool all_cpus);
143void x86_taa_recalculate(void);
|
| 144void x86_rngds_mitg_recalculate(bool all_cpus);
|
143void nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame);
144void nmi_call_kdb_smp(u_int type, struct trapframe *frame);
145void nmi_handle_intr(u_int type, struct trapframe *frame);
146void pagecopy(void *from, void *to);
147void printcpuinfo(void);
148int pti_get_default(void);
149int user_dbreg_trap(register_t dr6);
150int minidumpsys(struct dumperinfo *);
151struct pcb *get_pcb_td(struct thread *td);
152
153#define MSR_OP_ANDNOT 0x00000001
154#define MSR_OP_OR 0x00000002
155#define MSR_OP_WRITE 0x00000003
156#define MSR_OP_LOCAL 0x10000000
157#define MSR_OP_SCHED 0x20000000
158#define MSR_OP_RENDEZVOUS 0x30000000
159void x86_msr_op(u_int msr, u_int op, uint64_t arg1);
160
161#endif
| 145void nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame);
146void nmi_call_kdb_smp(u_int type, struct trapframe *frame);
147void nmi_handle_intr(u_int type, struct trapframe *frame);
148void pagecopy(void *from, void *to);
149void printcpuinfo(void);
150int pti_get_default(void);
151int user_dbreg_trap(register_t dr6);
152int minidumpsys(struct dumperinfo *);
153struct pcb *get_pcb_td(struct thread *td);
154
155#define MSR_OP_ANDNOT 0x00000001
156#define MSR_OP_OR 0x00000002
157#define MSR_OP_WRITE 0x00000003
158#define MSR_OP_LOCAL 0x10000000
159#define MSR_OP_SCHED 0x20000000
160#define MSR_OP_RENDEZVOUS 0x30000000
161void x86_msr_op(u_int msr, u_int op, uint64_t arg1);
162
163#endif
|