| specialreg.h (8876) | specialreg.h (13765) |
|---|---|
| 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 | 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 |
| 34 * $Id: specialreg.h,v 1.6 1995/01/14 10:44:55 bde Exp $ | 34 * $Id: specialreg.h,v 1.7 1995/05/30 08:00:54 rgrimes Exp $ |
| 35 */ 36 37#ifndef _MACHINE_SPECIALREG_H_ 38#define _MACHINE_SPECIALREG_H_ 39 40/* 41 * Bits in 386 special registers: 42 */ --- 11 unchanged lines hidden (view full) --- 54/* 55 * Bits in 486 special registers: 56 */ 57#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 58#define CR0_WP 0x00010000 /* Write Protect (honor page protect in all modes) */ 59#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 60 61/* | 35 */ 36 37#ifndef _MACHINE_SPECIALREG_H_ 38#define _MACHINE_SPECIALREG_H_ 39 40/* 41 * Bits in 386 special registers: 42 */ --- 11 unchanged lines hidden (view full) --- 54/* 55 * Bits in 486 special registers: 56 */ 57#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 58#define CR0_WP 0x00010000 /* Write Protect (honor page protect in all modes) */ 59#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 60 61/* |
| 62 * Cyrix 486 DLC special registers, accessable as IO ports. | 62 * Cyrix 486 DLC special registers, accessible as IO ports. |
| 63 */ 64#define CCR0 0xc0 /* configuration control register 0 */ 65#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is 66 non-cacheable */ 67#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 68#define CCR0_A20M 0x04 /* enables A20M# input pin */ 69#define CCR0_KEN 0x08 /* enables KEN# input pin */ 70#define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 71#define CCR0_BARB 0x20 /* flushes internal cache when entering hold 72 state */ 73#define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 74#define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 75 76#define CCR1 0xc1 /* configuration control register 1 */ 77#define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 78/* the remaining 7 bits of this register are reserved */ 79 80/* 81 * the following four 3-byte registers control the non-cacheable regions. | 63 */ 64#define CCR0 0xc0 /* configuration control register 0 */ 65#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is 66 non-cacheable */ 67#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 68#define CCR0_A20M 0x04 /* enables A20M# input pin */ 69#define CCR0_KEN 0x08 /* enables KEN# input pin */ 70#define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 71#define CCR0_BARB 0x20 /* flushes internal cache when entering hold 72 state */ 73#define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 74#define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 75 76#define CCR1 0xc1 /* configuration control register 1 */ 77#define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 78/* the remaining 7 bits of this register are reserved */ 79 80/* 81 * the following four 3-byte registers control the non-cacheable regions. |
| 82 * These registers must be written as three seperate bytes. | 82 * These registers must be written as three separate bytes. |
| 83 * 84 * NCRx+0: A31-A24 of starting address 85 * NCRx+1: A23-A16 of starting address 86 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 87 * 88 * The non-cacheable region's starting address must be aligned to the 89 * size indicated by the NCR_SIZE_xx field. 90 */ --- 23 unchanged lines hidden --- | 83 * 84 * NCRx+0: A31-A24 of starting address 85 * NCRx+1: A23-A16 of starting address 86 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 87 * 88 * The non-cacheable region's starting address must be aligned to the 89 * size indicated by the NCR_SIZE_xx field. 90 */ --- 23 unchanged lines hidden --- |