1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 4. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
| 1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 4. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
|
30 * $FreeBSD: stable/11/sys/x86/include/specialreg.h 345261 2019-03-18 10:28:40Z kib $
| 30 * $FreeBSD: stable/11/sys/x86/include/specialreg.h 347568 2019-05-14 17:05:02Z kib $
|
31 */
32
33#ifndef _MACHINE_SPECIALREG_H_
34#define _MACHINE_SPECIALREG_H_
35
36/*
37 * Bits in 386 special registers:
38 */
39#define CR0_PE 0x00000001 /* Protected mode Enable */
40#define CR0_MP 0x00000002 /* "Math" (fpu) Present */
41#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
42#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
43#define CR0_PG 0x80000000 /* PaGing enable */
44
45/*
46 * Bits in 486 special registers:
47 */
48#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
49#define CR0_WP 0x00010000 /* Write Protect (honor page protect in
50 all modes) */
51#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
52#define CR0_NW 0x20000000 /* Not Write-through */
53#define CR0_CD 0x40000000 /* Cache Disable */
54
55#define CR3_PCID_SAVE 0x8000000000000000
56#define CR3_PCID_MASK 0xfff
57
58/*
59 * Bits in PPro special registers
60 */
61#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
62#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
63#define CR4_TSD 0x00000004 /* Time stamp disable */
64#define CR4_DE 0x00000008 /* Debugging extensions */
65#define CR4_PSE 0x00000010 /* Page size extensions */
66#define CR4_PAE 0x00000020 /* Physical address extension */
67#define CR4_MCE 0x00000040 /* Machine check enable */
68#define CR4_PGE 0x00000080 /* Page global enable */
69#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
70#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
71#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
72#define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */
73#define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */
74#define CR4_PCIDE 0x00020000 /* Enable Context ID */
75#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */
76#define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */
77#define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Prevention */
78
79/*
80 * Bits in AMD64 special registers. EFER is 64 bits wide.
81 */
82#define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
83#define EFER_LME 0x000000100 /* Long mode enable (R/W) */
84#define EFER_LMA 0x000000400 /* Long mode active (R) */
85#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
86#define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */
87#define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */
88#define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */
89#define EFER_TCE 0x000008000 /* Translation Cache Extension */
90
91/*
92 * Intel Extended Features registers
93 */
94#define XCR0 0 /* XFEATURE_ENABLED_MASK register */
95
96#define XFEATURE_ENABLED_X87 0x00000001
97#define XFEATURE_ENABLED_SSE 0x00000002
98#define XFEATURE_ENABLED_YMM_HI128 0x00000004
99#define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128
100#define XFEATURE_ENABLED_BNDREGS 0x00000008
101#define XFEATURE_ENABLED_BNDCSR 0x00000010
102#define XFEATURE_ENABLED_OPMASK 0x00000020
103#define XFEATURE_ENABLED_ZMM_HI256 0x00000040
104#define XFEATURE_ENABLED_HI16_ZMM 0x00000080
105
106#define XFEATURE_AVX \
107 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX)
108#define XFEATURE_AVX512 \
109 (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \
110 XFEATURE_ENABLED_HI16_ZMM)
111#define XFEATURE_MPX \
112 (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR)
113
114/*
115 * CPUID instruction features register
116 */
117#define CPUID_FPU 0x00000001
118#define CPUID_VME 0x00000002
119#define CPUID_DE 0x00000004
120#define CPUID_PSE 0x00000008
121#define CPUID_TSC 0x00000010
122#define CPUID_MSR 0x00000020
123#define CPUID_PAE 0x00000040
124#define CPUID_MCE 0x00000080
125#define CPUID_CX8 0x00000100
126#define CPUID_APIC 0x00000200
127#define CPUID_B10 0x00000400
128#define CPUID_SEP 0x00000800
129#define CPUID_MTRR 0x00001000
130#define CPUID_PGE 0x00002000
131#define CPUID_MCA 0x00004000
132#define CPUID_CMOV 0x00008000
133#define CPUID_PAT 0x00010000
134#define CPUID_PSE36 0x00020000
135#define CPUID_PSN 0x00040000
136#define CPUID_CLFSH 0x00080000
137#define CPUID_B20 0x00100000
138#define CPUID_DS 0x00200000
139#define CPUID_ACPI 0x00400000
140#define CPUID_MMX 0x00800000
141#define CPUID_FXSR 0x01000000
142#define CPUID_SSE 0x02000000
143#define CPUID_XMM 0x02000000
144#define CPUID_SSE2 0x04000000
145#define CPUID_SS 0x08000000
146#define CPUID_HTT 0x10000000
147#define CPUID_TM 0x20000000
148#define CPUID_IA64 0x40000000
149#define CPUID_PBE 0x80000000
150
151#define CPUID2_SSE3 0x00000001
152#define CPUID2_PCLMULQDQ 0x00000002
153#define CPUID2_DTES64 0x00000004
154#define CPUID2_MON 0x00000008
155#define CPUID2_DS_CPL 0x00000010
156#define CPUID2_VMX 0x00000020
157#define CPUID2_SMX 0x00000040
158#define CPUID2_EST 0x00000080
159#define CPUID2_TM2 0x00000100
160#define CPUID2_SSSE3 0x00000200
161#define CPUID2_CNXTID 0x00000400
162#define CPUID2_SDBG 0x00000800
163#define CPUID2_FMA 0x00001000
164#define CPUID2_CX16 0x00002000
165#define CPUID2_XTPR 0x00004000
166#define CPUID2_PDCM 0x00008000
167#define CPUID2_PCID 0x00020000
168#define CPUID2_DCA 0x00040000
169#define CPUID2_SSE41 0x00080000
170#define CPUID2_SSE42 0x00100000
171#define CPUID2_X2APIC 0x00200000
172#define CPUID2_MOVBE 0x00400000
173#define CPUID2_POPCNT 0x00800000
174#define CPUID2_TSCDLT 0x01000000
175#define CPUID2_AESNI 0x02000000
176#define CPUID2_XSAVE 0x04000000
177#define CPUID2_OSXSAVE 0x08000000
178#define CPUID2_AVX 0x10000000
179#define CPUID2_F16C 0x20000000
180#define CPUID2_RDRAND 0x40000000
181#define CPUID2_HV 0x80000000
182
183/*
184 * Important bits in the Thermal and Power Management flags
185 * CPUID.6 EAX and ECX.
186 */
187#define CPUTPM1_SENSOR 0x00000001
188#define CPUTPM1_TURBO 0x00000002
189#define CPUTPM1_ARAT 0x00000004
190#define CPUTPM2_EFFREQ 0x00000001
191
192/*
193 * Important bits in the AMD extended cpuid flags
194 */
195#define AMDID_SYSCALL 0x00000800
196#define AMDID_MP 0x00080000
197#define AMDID_NX 0x00100000
198#define AMDID_EXT_MMX 0x00400000
199#define AMDID_FFXSR 0x02000000
200#define AMDID_PAGE1GB 0x04000000
201#define AMDID_RDTSCP 0x08000000
202#define AMDID_LM 0x20000000
203#define AMDID_EXT_3DNOW 0x40000000
204#define AMDID_3DNOW 0x80000000
205
206#define AMDID2_LAHF 0x00000001
207#define AMDID2_CMP 0x00000002
208#define AMDID2_SVM 0x00000004
209#define AMDID2_EXT_APIC 0x00000008
210#define AMDID2_CR8 0x00000010
211#define AMDID2_ABM 0x00000020
212#define AMDID2_SSE4A 0x00000040
213#define AMDID2_MAS 0x00000080
214#define AMDID2_PREFETCH 0x00000100
215#define AMDID2_OSVW 0x00000200
216#define AMDID2_IBS 0x00000400
217#define AMDID2_XOP 0x00000800
218#define AMDID2_SKINIT 0x00001000
219#define AMDID2_WDT 0x00002000
220#define AMDID2_LWP 0x00008000
221#define AMDID2_FMA4 0x00010000
222#define AMDID2_TCE 0x00020000
223#define AMDID2_NODE_ID 0x00080000
224#define AMDID2_TBM 0x00200000
225#define AMDID2_TOPOLOGY 0x00400000
226#define AMDID2_PCXC 0x00800000
227#define AMDID2_PNXC 0x01000000
228#define AMDID2_DBE 0x04000000
229#define AMDID2_PTSC 0x08000000
230#define AMDID2_PTSCEL2I 0x10000000
231#define AMDID2_MWAITX 0x20000000
232
233/*
234 * CPUID instruction 1 eax info
235 */
236#define CPUID_STEPPING 0x0000000f
237#define CPUID_MODEL 0x000000f0
238#define CPUID_FAMILY 0x00000f00
239#define CPUID_EXT_MODEL 0x000f0000
240#define CPUID_EXT_FAMILY 0x0ff00000
241#ifdef __i386__
242#define CPUID_TO_MODEL(id) \
243 ((((id) & CPUID_MODEL) >> 4) | \
244 ((((id) & CPUID_FAMILY) >= 0x600) ? \
245 (((id) & CPUID_EXT_MODEL) >> 12) : 0))
246#define CPUID_TO_FAMILY(id) \
247 ((((id) & CPUID_FAMILY) >> 8) + \
248 ((((id) & CPUID_FAMILY) == 0xf00) ? \
249 (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
250#else
251#define CPUID_TO_MODEL(id) \
252 ((((id) & CPUID_MODEL) >> 4) | \
253 (((id) & CPUID_EXT_MODEL) >> 12))
254#define CPUID_TO_FAMILY(id) \
255 ((((id) & CPUID_FAMILY) >> 8) + \
256 (((id) & CPUID_EXT_FAMILY) >> 20))
257#endif
258
259/*
260 * CPUID instruction 1 ebx info
261 */
262#define CPUID_BRAND_INDEX 0x000000ff
263#define CPUID_CLFUSH_SIZE 0x0000ff00
264#define CPUID_HTT_CORES 0x00ff0000
265#define CPUID_LOCAL_APIC_ID 0xff000000
266
267/*
268 * CPUID instruction 5 info
269 */
270#define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */
271#define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */
272#define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */
273#define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */
274
275/*
276 * MWAIT cpu power states. Lower 4 bits are sub-states.
277 */
278#define MWAIT_C0 0xf0
279#define MWAIT_C1 0x00
280#define MWAIT_C2 0x10
281#define MWAIT_C3 0x20
282#define MWAIT_C4 0x30
283
284/*
285 * MWAIT extensions.
286 */
287/* Interrupt breaks MWAIT even when masked. */
288#define MWAIT_INTRBREAK 0x00000001
289
290/*
291 * CPUID instruction 6 ecx info
292 */
293#define CPUID_PERF_STAT 0x00000001
294#define CPUID_PERF_BIAS 0x00000008
295
296/*
297 * CPUID instruction 0xb ebx info.
298 */
299#define CPUID_TYPE_INVAL 0
300#define CPUID_TYPE_SMT 1
301#define CPUID_TYPE_CORE 2
302
303/*
304 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
305 */
306#define CPUID_EXTSTATE_XSAVEOPT 0x00000001
307#define CPUID_EXTSTATE_XSAVEC 0x00000002
308#define CPUID_EXTSTATE_XINUSE 0x00000004
309#define CPUID_EXTSTATE_XSAVES 0x00000008
310
311/*
312 * AMD extended function 8000_0007h edx info
313 */
314#define AMDPM_TS 0x00000001
315#define AMDPM_FID 0x00000002
316#define AMDPM_VID 0x00000004
317#define AMDPM_TTP 0x00000008
318#define AMDPM_TM 0x00000010
319#define AMDPM_STC 0x00000020
320#define AMDPM_100MHZ_STEPS 0x00000040
321#define AMDPM_HW_PSTATE 0x00000080
322#define AMDPM_TSC_INVARIANT 0x00000100
323#define AMDPM_CPB 0x00000200
324
325/*
326 * AMD extended function 8000_0008h ebx info (amd_extended_feature_extensions)
327 */
328#define AMDFEID_CLZERO 0x00000001
329#define AMDFEID_IRPERF 0x00000002
330#define AMDFEID_XSAVEERPTR 0x00000004
331
332/*
333 * AMD extended function 8000_0008h ecx info
334 */
335#define AMDID_CMP_CORES 0x000000ff
336#define AMDID_COREID_SIZE 0x0000f000
337#define AMDID_COREID_SIZE_SHIFT 12
338
339/*
340 * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
341 */
342#define CPUID_STDEXT_FSGSBASE 0x00000001
343#define CPUID_STDEXT_TSC_ADJUST 0x00000002
344#define CPUID_STDEXT_SGX 0x00000004
345#define CPUID_STDEXT_BMI1 0x00000008
346#define CPUID_STDEXT_HLE 0x00000010
347#define CPUID_STDEXT_AVX2 0x00000020
348#define CPUID_STDEXT_FDP_EXC 0x00000040
349#define CPUID_STDEXT_SMEP 0x00000080
350#define CPUID_STDEXT_BMI2 0x00000100
351#define CPUID_STDEXT_ERMS 0x00000200
352#define CPUID_STDEXT_INVPCID 0x00000400
353#define CPUID_STDEXT_RTM 0x00000800
354#define CPUID_STDEXT_PQM 0x00001000
355#define CPUID_STDEXT_NFPUSG 0x00002000
356#define CPUID_STDEXT_MPX 0x00004000
357#define CPUID_STDEXT_PQE 0x00008000
358#define CPUID_STDEXT_AVX512F 0x00010000
359#define CPUID_STDEXT_AVX512DQ 0x00020000
360#define CPUID_STDEXT_RDSEED 0x00040000
361#define CPUID_STDEXT_ADX 0x00080000
362#define CPUID_STDEXT_SMAP 0x00100000
363#define CPUID_STDEXT_AVX512IFMA 0x00200000
364#define CPUID_STDEXT_PCOMMIT 0x00400000
365#define CPUID_STDEXT_CLFLUSHOPT 0x00800000
366#define CPUID_STDEXT_CLWB 0x01000000
367#define CPUID_STDEXT_PROCTRACE 0x02000000
368#define CPUID_STDEXT_AVX512PF 0x04000000
369#define CPUID_STDEXT_AVX512ER 0x08000000
370#define CPUID_STDEXT_AVX512CD 0x10000000
371#define CPUID_STDEXT_SHA 0x20000000
372#define CPUID_STDEXT_AVX512BW 0x40000000
373#define CPUID_STDEXT_AVX512VL 0x80000000
374
375/*
376 * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info
377 */
378#define CPUID_STDEXT2_PREFETCHWT1 0x00000001
379#define CPUID_STDEXT2_UMIP 0x00000004
380#define CPUID_STDEXT2_PKU 0x00000008
381#define CPUID_STDEXT2_OSPKE 0x00000010
382#define CPUID_STDEXT2_WAITPKG 0x00000020
383#define CPUID_STDEXT2_GFNI 0x00000100
384#define CPUID_STDEXT2_RDPID 0x00400000
385#define CPUID_STDEXT2_CLDEMOTE 0x02000000
386#define CPUID_STDEXT2_MOVDIRI 0x08000000
387#define CPUID_STDEXT2_MOVDIRI64B 0x10000000
388#define CPUID_STDEXT2_SGXLC 0x40000000
389
390/*
391 * CPUID instruction 7 Structured Extended Features, leaf 0 edx info
392 */
| 31 */
32
33#ifndef _MACHINE_SPECIALREG_H_
34#define _MACHINE_SPECIALREG_H_
35
36/*
37 * Bits in 386 special registers:
38 */
39#define CR0_PE 0x00000001 /* Protected mode Enable */
40#define CR0_MP 0x00000002 /* "Math" (fpu) Present */
41#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
42#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
43#define CR0_PG 0x80000000 /* PaGing enable */
44
45/*
46 * Bits in 486 special registers:
47 */
48#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
49#define CR0_WP 0x00010000 /* Write Protect (honor page protect in
50 all modes) */
51#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
52#define CR0_NW 0x20000000 /* Not Write-through */
53#define CR0_CD 0x40000000 /* Cache Disable */
54
55#define CR3_PCID_SAVE 0x8000000000000000
56#define CR3_PCID_MASK 0xfff
57
58/*
59 * Bits in PPro special registers
60 */
61#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
62#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
63#define CR4_TSD 0x00000004 /* Time stamp disable */
64#define CR4_DE 0x00000008 /* Debugging extensions */
65#define CR4_PSE 0x00000010 /* Page size extensions */
66#define CR4_PAE 0x00000020 /* Physical address extension */
67#define CR4_MCE 0x00000040 /* Machine check enable */
68#define CR4_PGE 0x00000080 /* Page global enable */
69#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
70#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
71#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
72#define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */
73#define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */
74#define CR4_PCIDE 0x00020000 /* Enable Context ID */
75#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */
76#define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */
77#define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Prevention */
78
79/*
80 * Bits in AMD64 special registers. EFER is 64 bits wide.
81 */
82#define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
83#define EFER_LME 0x000000100 /* Long mode enable (R/W) */
84#define EFER_LMA 0x000000400 /* Long mode active (R) */
85#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
86#define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */
87#define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */
88#define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */
89#define EFER_TCE 0x000008000 /* Translation Cache Extension */
90
91/*
92 * Intel Extended Features registers
93 */
94#define XCR0 0 /* XFEATURE_ENABLED_MASK register */
95
96#define XFEATURE_ENABLED_X87 0x00000001
97#define XFEATURE_ENABLED_SSE 0x00000002
98#define XFEATURE_ENABLED_YMM_HI128 0x00000004
99#define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128
100#define XFEATURE_ENABLED_BNDREGS 0x00000008
101#define XFEATURE_ENABLED_BNDCSR 0x00000010
102#define XFEATURE_ENABLED_OPMASK 0x00000020
103#define XFEATURE_ENABLED_ZMM_HI256 0x00000040
104#define XFEATURE_ENABLED_HI16_ZMM 0x00000080
105
106#define XFEATURE_AVX \
107 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX)
108#define XFEATURE_AVX512 \
109 (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \
110 XFEATURE_ENABLED_HI16_ZMM)
111#define XFEATURE_MPX \
112 (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR)
113
114/*
115 * CPUID instruction features register
116 */
117#define CPUID_FPU 0x00000001
118#define CPUID_VME 0x00000002
119#define CPUID_DE 0x00000004
120#define CPUID_PSE 0x00000008
121#define CPUID_TSC 0x00000010
122#define CPUID_MSR 0x00000020
123#define CPUID_PAE 0x00000040
124#define CPUID_MCE 0x00000080
125#define CPUID_CX8 0x00000100
126#define CPUID_APIC 0x00000200
127#define CPUID_B10 0x00000400
128#define CPUID_SEP 0x00000800
129#define CPUID_MTRR 0x00001000
130#define CPUID_PGE 0x00002000
131#define CPUID_MCA 0x00004000
132#define CPUID_CMOV 0x00008000
133#define CPUID_PAT 0x00010000
134#define CPUID_PSE36 0x00020000
135#define CPUID_PSN 0x00040000
136#define CPUID_CLFSH 0x00080000
137#define CPUID_B20 0x00100000
138#define CPUID_DS 0x00200000
139#define CPUID_ACPI 0x00400000
140#define CPUID_MMX 0x00800000
141#define CPUID_FXSR 0x01000000
142#define CPUID_SSE 0x02000000
143#define CPUID_XMM 0x02000000
144#define CPUID_SSE2 0x04000000
145#define CPUID_SS 0x08000000
146#define CPUID_HTT 0x10000000
147#define CPUID_TM 0x20000000
148#define CPUID_IA64 0x40000000
149#define CPUID_PBE 0x80000000
150
151#define CPUID2_SSE3 0x00000001
152#define CPUID2_PCLMULQDQ 0x00000002
153#define CPUID2_DTES64 0x00000004
154#define CPUID2_MON 0x00000008
155#define CPUID2_DS_CPL 0x00000010
156#define CPUID2_VMX 0x00000020
157#define CPUID2_SMX 0x00000040
158#define CPUID2_EST 0x00000080
159#define CPUID2_TM2 0x00000100
160#define CPUID2_SSSE3 0x00000200
161#define CPUID2_CNXTID 0x00000400
162#define CPUID2_SDBG 0x00000800
163#define CPUID2_FMA 0x00001000
164#define CPUID2_CX16 0x00002000
165#define CPUID2_XTPR 0x00004000
166#define CPUID2_PDCM 0x00008000
167#define CPUID2_PCID 0x00020000
168#define CPUID2_DCA 0x00040000
169#define CPUID2_SSE41 0x00080000
170#define CPUID2_SSE42 0x00100000
171#define CPUID2_X2APIC 0x00200000
172#define CPUID2_MOVBE 0x00400000
173#define CPUID2_POPCNT 0x00800000
174#define CPUID2_TSCDLT 0x01000000
175#define CPUID2_AESNI 0x02000000
176#define CPUID2_XSAVE 0x04000000
177#define CPUID2_OSXSAVE 0x08000000
178#define CPUID2_AVX 0x10000000
179#define CPUID2_F16C 0x20000000
180#define CPUID2_RDRAND 0x40000000
181#define CPUID2_HV 0x80000000
182
183/*
184 * Important bits in the Thermal and Power Management flags
185 * CPUID.6 EAX and ECX.
186 */
187#define CPUTPM1_SENSOR 0x00000001
188#define CPUTPM1_TURBO 0x00000002
189#define CPUTPM1_ARAT 0x00000004
190#define CPUTPM2_EFFREQ 0x00000001
191
192/*
193 * Important bits in the AMD extended cpuid flags
194 */
195#define AMDID_SYSCALL 0x00000800
196#define AMDID_MP 0x00080000
197#define AMDID_NX 0x00100000
198#define AMDID_EXT_MMX 0x00400000
199#define AMDID_FFXSR 0x02000000
200#define AMDID_PAGE1GB 0x04000000
201#define AMDID_RDTSCP 0x08000000
202#define AMDID_LM 0x20000000
203#define AMDID_EXT_3DNOW 0x40000000
204#define AMDID_3DNOW 0x80000000
205
206#define AMDID2_LAHF 0x00000001
207#define AMDID2_CMP 0x00000002
208#define AMDID2_SVM 0x00000004
209#define AMDID2_EXT_APIC 0x00000008
210#define AMDID2_CR8 0x00000010
211#define AMDID2_ABM 0x00000020
212#define AMDID2_SSE4A 0x00000040
213#define AMDID2_MAS 0x00000080
214#define AMDID2_PREFETCH 0x00000100
215#define AMDID2_OSVW 0x00000200
216#define AMDID2_IBS 0x00000400
217#define AMDID2_XOP 0x00000800
218#define AMDID2_SKINIT 0x00001000
219#define AMDID2_WDT 0x00002000
220#define AMDID2_LWP 0x00008000
221#define AMDID2_FMA4 0x00010000
222#define AMDID2_TCE 0x00020000
223#define AMDID2_NODE_ID 0x00080000
224#define AMDID2_TBM 0x00200000
225#define AMDID2_TOPOLOGY 0x00400000
226#define AMDID2_PCXC 0x00800000
227#define AMDID2_PNXC 0x01000000
228#define AMDID2_DBE 0x04000000
229#define AMDID2_PTSC 0x08000000
230#define AMDID2_PTSCEL2I 0x10000000
231#define AMDID2_MWAITX 0x20000000
232
233/*
234 * CPUID instruction 1 eax info
235 */
236#define CPUID_STEPPING 0x0000000f
237#define CPUID_MODEL 0x000000f0
238#define CPUID_FAMILY 0x00000f00
239#define CPUID_EXT_MODEL 0x000f0000
240#define CPUID_EXT_FAMILY 0x0ff00000
241#ifdef __i386__
242#define CPUID_TO_MODEL(id) \
243 ((((id) & CPUID_MODEL) >> 4) | \
244 ((((id) & CPUID_FAMILY) >= 0x600) ? \
245 (((id) & CPUID_EXT_MODEL) >> 12) : 0))
246#define CPUID_TO_FAMILY(id) \
247 ((((id) & CPUID_FAMILY) >> 8) + \
248 ((((id) & CPUID_FAMILY) == 0xf00) ? \
249 (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
250#else
251#define CPUID_TO_MODEL(id) \
252 ((((id) & CPUID_MODEL) >> 4) | \
253 (((id) & CPUID_EXT_MODEL) >> 12))
254#define CPUID_TO_FAMILY(id) \
255 ((((id) & CPUID_FAMILY) >> 8) + \
256 (((id) & CPUID_EXT_FAMILY) >> 20))
257#endif
258
259/*
260 * CPUID instruction 1 ebx info
261 */
262#define CPUID_BRAND_INDEX 0x000000ff
263#define CPUID_CLFUSH_SIZE 0x0000ff00
264#define CPUID_HTT_CORES 0x00ff0000
265#define CPUID_LOCAL_APIC_ID 0xff000000
266
267/*
268 * CPUID instruction 5 info
269 */
270#define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */
271#define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */
272#define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */
273#define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */
274
275/*
276 * MWAIT cpu power states. Lower 4 bits are sub-states.
277 */
278#define MWAIT_C0 0xf0
279#define MWAIT_C1 0x00
280#define MWAIT_C2 0x10
281#define MWAIT_C3 0x20
282#define MWAIT_C4 0x30
283
284/*
285 * MWAIT extensions.
286 */
287/* Interrupt breaks MWAIT even when masked. */
288#define MWAIT_INTRBREAK 0x00000001
289
290/*
291 * CPUID instruction 6 ecx info
292 */
293#define CPUID_PERF_STAT 0x00000001
294#define CPUID_PERF_BIAS 0x00000008
295
296/*
297 * CPUID instruction 0xb ebx info.
298 */
299#define CPUID_TYPE_INVAL 0
300#define CPUID_TYPE_SMT 1
301#define CPUID_TYPE_CORE 2
302
303/*
304 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
305 */
306#define CPUID_EXTSTATE_XSAVEOPT 0x00000001
307#define CPUID_EXTSTATE_XSAVEC 0x00000002
308#define CPUID_EXTSTATE_XINUSE 0x00000004
309#define CPUID_EXTSTATE_XSAVES 0x00000008
310
311/*
312 * AMD extended function 8000_0007h edx info
313 */
314#define AMDPM_TS 0x00000001
315#define AMDPM_FID 0x00000002
316#define AMDPM_VID 0x00000004
317#define AMDPM_TTP 0x00000008
318#define AMDPM_TM 0x00000010
319#define AMDPM_STC 0x00000020
320#define AMDPM_100MHZ_STEPS 0x00000040
321#define AMDPM_HW_PSTATE 0x00000080
322#define AMDPM_TSC_INVARIANT 0x00000100
323#define AMDPM_CPB 0x00000200
324
325/*
326 * AMD extended function 8000_0008h ebx info (amd_extended_feature_extensions)
327 */
328#define AMDFEID_CLZERO 0x00000001
329#define AMDFEID_IRPERF 0x00000002
330#define AMDFEID_XSAVEERPTR 0x00000004
331
332/*
333 * AMD extended function 8000_0008h ecx info
334 */
335#define AMDID_CMP_CORES 0x000000ff
336#define AMDID_COREID_SIZE 0x0000f000
337#define AMDID_COREID_SIZE_SHIFT 12
338
339/*
340 * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
341 */
342#define CPUID_STDEXT_FSGSBASE 0x00000001
343#define CPUID_STDEXT_TSC_ADJUST 0x00000002
344#define CPUID_STDEXT_SGX 0x00000004
345#define CPUID_STDEXT_BMI1 0x00000008
346#define CPUID_STDEXT_HLE 0x00000010
347#define CPUID_STDEXT_AVX2 0x00000020
348#define CPUID_STDEXT_FDP_EXC 0x00000040
349#define CPUID_STDEXT_SMEP 0x00000080
350#define CPUID_STDEXT_BMI2 0x00000100
351#define CPUID_STDEXT_ERMS 0x00000200
352#define CPUID_STDEXT_INVPCID 0x00000400
353#define CPUID_STDEXT_RTM 0x00000800
354#define CPUID_STDEXT_PQM 0x00001000
355#define CPUID_STDEXT_NFPUSG 0x00002000
356#define CPUID_STDEXT_MPX 0x00004000
357#define CPUID_STDEXT_PQE 0x00008000
358#define CPUID_STDEXT_AVX512F 0x00010000
359#define CPUID_STDEXT_AVX512DQ 0x00020000
360#define CPUID_STDEXT_RDSEED 0x00040000
361#define CPUID_STDEXT_ADX 0x00080000
362#define CPUID_STDEXT_SMAP 0x00100000
363#define CPUID_STDEXT_AVX512IFMA 0x00200000
364#define CPUID_STDEXT_PCOMMIT 0x00400000
365#define CPUID_STDEXT_CLFLUSHOPT 0x00800000
366#define CPUID_STDEXT_CLWB 0x01000000
367#define CPUID_STDEXT_PROCTRACE 0x02000000
368#define CPUID_STDEXT_AVX512PF 0x04000000
369#define CPUID_STDEXT_AVX512ER 0x08000000
370#define CPUID_STDEXT_AVX512CD 0x10000000
371#define CPUID_STDEXT_SHA 0x20000000
372#define CPUID_STDEXT_AVX512BW 0x40000000
373#define CPUID_STDEXT_AVX512VL 0x80000000
374
375/*
376 * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info
377 */
378#define CPUID_STDEXT2_PREFETCHWT1 0x00000001
379#define CPUID_STDEXT2_UMIP 0x00000004
380#define CPUID_STDEXT2_PKU 0x00000008
381#define CPUID_STDEXT2_OSPKE 0x00000010
382#define CPUID_STDEXT2_WAITPKG 0x00000020
383#define CPUID_STDEXT2_GFNI 0x00000100
384#define CPUID_STDEXT2_RDPID 0x00400000
385#define CPUID_STDEXT2_CLDEMOTE 0x02000000
386#define CPUID_STDEXT2_MOVDIRI 0x08000000
387#define CPUID_STDEXT2_MOVDIRI64B 0x10000000
388#define CPUID_STDEXT2_SGXLC 0x40000000
389
390/*
391 * CPUID instruction 7 Structured Extended Features, leaf 0 edx info
392 */
|
| 393#define CPUID_STDEXT3_MD_CLEAR 0x00000400
|
393#define CPUID_STDEXT3_TSXFA 0x00002000
394#define CPUID_STDEXT3_IBPB 0x04000000
395#define CPUID_STDEXT3_STIBP 0x08000000
396#define CPUID_STDEXT3_L1D_FLUSH 0x10000000
397#define CPUID_STDEXT3_ARCH_CAP 0x20000000
398#define CPUID_STDEXT3_CORE_CAP 0x40000000
399#define CPUID_STDEXT3_SSBD 0x80000000
400
401/* MSR IA32_ARCH_CAP(ABILITIES) bits */
402#define IA32_ARCH_CAP_RDCL_NO 0x00000001
403#define IA32_ARCH_CAP_IBRS_ALL 0x00000002
404#define IA32_ARCH_CAP_RSBA 0x00000004
405#define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008
406#define IA32_ARCH_CAP_SSB_NO 0x00000010
| 394#define CPUID_STDEXT3_TSXFA 0x00002000
395#define CPUID_STDEXT3_IBPB 0x04000000
396#define CPUID_STDEXT3_STIBP 0x08000000
397#define CPUID_STDEXT3_L1D_FLUSH 0x10000000
398#define CPUID_STDEXT3_ARCH_CAP 0x20000000
399#define CPUID_STDEXT3_CORE_CAP 0x40000000
400#define CPUID_STDEXT3_SSBD 0x80000000
401
402/* MSR IA32_ARCH_CAP(ABILITIES) bits */
403#define IA32_ARCH_CAP_RDCL_NO 0x00000001
404#define IA32_ARCH_CAP_IBRS_ALL 0x00000002
405#define IA32_ARCH_CAP_RSBA 0x00000004
406#define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008
407#define IA32_ARCH_CAP_SSB_NO 0x00000010
|
| 408#define IA32_ARCH_CAP_MDS_NO 0x00000020
|
407
408/*
409 * CPUID manufacturers identifiers
410 */
411#define AMD_VENDOR_ID "AuthenticAMD"
412#define CENTAUR_VENDOR_ID "CentaurHauls"
413#define CYRIX_VENDOR_ID "CyrixInstead"
414#define INTEL_VENDOR_ID "GenuineIntel"
415#define NEXGEN_VENDOR_ID "NexGenDriven"
416#define NSC_VENDOR_ID "Geode by NSC"
417#define RISE_VENDOR_ID "RiseRiseRise"
418#define SIS_VENDOR_ID "SiS SiS SiS "
419#define TRANSMETA_VENDOR_ID "GenuineTMx86"
420#define UMC_VENDOR_ID "UMC UMC UMC "
421
422/*
423 * Model-specific registers for the i386 family
424 */
425#define MSR_P5_MC_ADDR 0x000
426#define MSR_P5_MC_TYPE 0x001
427#define MSR_TSC 0x010
428#define MSR_P5_CESR 0x011
429#define MSR_P5_CTR0 0x012
430#define MSR_P5_CTR1 0x013
431#define MSR_IA32_PLATFORM_ID 0x017
432#define MSR_APICBASE 0x01b
433#define MSR_EBL_CR_POWERON 0x02a
434#define MSR_TEST_CTL 0x033
435#define MSR_IA32_FEATURE_CONTROL 0x03a
436#define MSR_IA32_SPEC_CTRL 0x048
437#define MSR_IA32_PRED_CMD 0x049
438#define MSR_BIOS_UPDT_TRIG 0x079
439#define MSR_BBL_CR_D0 0x088
440#define MSR_BBL_CR_D1 0x089
441#define MSR_BBL_CR_D2 0x08a
442#define MSR_BIOS_SIGN 0x08b
443#define MSR_PERFCTR0 0x0c1
444#define MSR_PERFCTR1 0x0c2
445#define MSR_PLATFORM_INFO 0x0ce
446#define MSR_MPERF 0x0e7
447#define MSR_APERF 0x0e8
448#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
449#define MSR_MTRRcap 0x0fe
450#define MSR_IA32_ARCH_CAP 0x10a
451#define MSR_IA32_FLUSH_CMD 0x10b
452#define MSR_TSX_FORCE_ABORT 0x10f
453#define MSR_BBL_CR_ADDR 0x116
454#define MSR_BBL_CR_DECC 0x118
455#define MSR_BBL_CR_CTL 0x119
456#define MSR_BBL_CR_TRIG 0x11a
457#define MSR_BBL_CR_BUSY 0x11b
458#define MSR_BBL_CR_CTL3 0x11e
459#define MSR_SYSENTER_CS_MSR 0x174
460#define MSR_SYSENTER_ESP_MSR 0x175
461#define MSR_SYSENTER_EIP_MSR 0x176
462#define MSR_MCG_CAP 0x179
463#define MSR_MCG_STATUS 0x17a
464#define MSR_MCG_CTL 0x17b
465#define MSR_EVNTSEL0 0x186
466#define MSR_EVNTSEL1 0x187
467#define MSR_THERM_CONTROL 0x19a
468#define MSR_THERM_INTERRUPT 0x19b
469#define MSR_THERM_STATUS 0x19c
470#define MSR_IA32_MISC_ENABLE 0x1a0
471#define MSR_IA32_TEMPERATURE_TARGET 0x1a2
472#define MSR_TURBO_RATIO_LIMIT 0x1ad
473#define MSR_TURBO_RATIO_LIMIT1 0x1ae
474#define MSR_DEBUGCTLMSR 0x1d9
475#define MSR_LASTBRANCHFROMIP 0x1db
476#define MSR_LASTBRANCHTOIP 0x1dc
477#define MSR_LASTINTFROMIP 0x1dd
478#define MSR_LASTINTTOIP 0x1de
479#define MSR_ROB_CR_BKUPTMPDR6 0x1e0
480#define MSR_MTRRVarBase 0x200
481#define MSR_MTRR64kBase 0x250
482#define MSR_MTRR16kBase 0x258
483#define MSR_MTRR4kBase 0x268
484#define MSR_PAT 0x277
485#define MSR_MC0_CTL2 0x280
486#define MSR_MTRRdefType 0x2ff
487#define MSR_MC0_CTL 0x400
488#define MSR_MC0_STATUS 0x401
489#define MSR_MC0_ADDR 0x402
490#define MSR_MC0_MISC 0x403
491#define MSR_MC1_CTL 0x404
492#define MSR_MC1_STATUS 0x405
493#define MSR_MC1_ADDR 0x406
494#define MSR_MC1_MISC 0x407
495#define MSR_MC2_CTL 0x408
496#define MSR_MC2_STATUS 0x409
497#define MSR_MC2_ADDR 0x40a
498#define MSR_MC2_MISC 0x40b
499#define MSR_MC3_CTL 0x40c
500#define MSR_MC3_STATUS 0x40d
501#define MSR_MC3_ADDR 0x40e
502#define MSR_MC3_MISC 0x40f
503#define MSR_MC4_CTL 0x410
504#define MSR_MC4_STATUS 0x411
505#define MSR_MC4_ADDR 0x412
506#define MSR_MC4_MISC 0x413
507#define MSR_RAPL_POWER_UNIT 0x606
508#define MSR_PKG_ENERGY_STATUS 0x611
509#define MSR_DRAM_ENERGY_STATUS 0x619
510#define MSR_PP0_ENERGY_STATUS 0x639
511#define MSR_PP1_ENERGY_STATUS 0x641
512#define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */
513
514/*
515 * VMX MSRs
516 */
517#define MSR_VMX_BASIC 0x480
518#define MSR_VMX_PINBASED_CTLS 0x481
519#define MSR_VMX_PROCBASED_CTLS 0x482
520#define MSR_VMX_EXIT_CTLS 0x483
521#define MSR_VMX_ENTRY_CTLS 0x484
522#define MSR_VMX_CR0_FIXED0 0x486
523#define MSR_VMX_CR0_FIXED1 0x487
524#define MSR_VMX_CR4_FIXED0 0x488
525#define MSR_VMX_CR4_FIXED1 0x489
526#define MSR_VMX_PROCBASED_CTLS2 0x48b
527#define MSR_VMX_EPT_VPID_CAP 0x48c
528#define MSR_VMX_TRUE_PINBASED_CTLS 0x48d
529#define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e
530#define MSR_VMX_TRUE_EXIT_CTLS 0x48f
531#define MSR_VMX_TRUE_ENTRY_CTLS 0x490
532
533/*
534 * X2APIC MSRs.
535 * Writes are not serializing.
536 */
537#define MSR_APIC_000 0x800
538#define MSR_APIC_ID 0x802
539#define MSR_APIC_VERSION 0x803
540#define MSR_APIC_TPR 0x808
541#define MSR_APIC_EOI 0x80b
542#define MSR_APIC_LDR 0x80d
543#define MSR_APIC_SVR 0x80f
544#define MSR_APIC_ISR0 0x810
545#define MSR_APIC_ISR1 0x811
546#define MSR_APIC_ISR2 0x812
547#define MSR_APIC_ISR3 0x813
548#define MSR_APIC_ISR4 0x814
549#define MSR_APIC_ISR5 0x815
550#define MSR_APIC_ISR6 0x816
551#define MSR_APIC_ISR7 0x817
552#define MSR_APIC_TMR0 0x818
553#define MSR_APIC_IRR0 0x820
554#define MSR_APIC_ESR 0x828
555#define MSR_APIC_LVT_CMCI 0x82F
556#define MSR_APIC_ICR 0x830
557#define MSR_APIC_LVT_TIMER 0x832
558#define MSR_APIC_LVT_THERMAL 0x833
559#define MSR_APIC_LVT_PCINT 0x834
560#define MSR_APIC_LVT_LINT0 0x835
561#define MSR_APIC_LVT_LINT1 0x836
562#define MSR_APIC_LVT_ERROR 0x837
563#define MSR_APIC_ICR_TIMER 0x838
564#define MSR_APIC_CCR_TIMER 0x839
565#define MSR_APIC_DCR_TIMER 0x83e
566#define MSR_APIC_SELF_IPI 0x83f
567
568#define MSR_IA32_XSS 0xda0
569
570/*
571 * Constants related to MSR's.
572 */
573#define APICBASE_RESERVED 0x000002ff
574#define APICBASE_BSP 0x00000100
575#define APICBASE_X2APIC 0x00000400
576#define APICBASE_ENABLED 0x00000800
577#define APICBASE_ADDRESS 0xfffff000
578
579/* MSR_IA32_FEATURE_CONTROL related */
580#define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */
581#define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */
582#define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */
583
584/* MSR IA32_MISC_ENABLE */
585#define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL
586#define IA32_MISC_EN_ATCCE 0x0000000000000008ULL
587#define IA32_MISC_EN_PERFMON 0x0000000000000080ULL
588#define IA32_MISC_EN_PEBSU 0x0000000000001000ULL
589#define IA32_MISC_EN_ESSTE 0x0000000000010000ULL
590#define IA32_MISC_EN_MONE 0x0000000000040000ULL
591#define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL
592#define IA32_MISC_EN_xTPRD 0x0000000000800000ULL
593#define IA32_MISC_EN_XDD 0x0000000400000000ULL
594
595/*
596 * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel'
597 * document 336996-001 Speculative Execution Side Channel Mitigations.
598 */
599/* MSR IA32_SPEC_CTRL */
600#define IA32_SPEC_CTRL_IBRS 0x00000001
601#define IA32_SPEC_CTRL_STIBP 0x00000002
602#define IA32_SPEC_CTRL_SSBD 0x00000004
603
604/* MSR IA32_PRED_CMD */
605#define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL
606
607/* MSR IA32_FLUSH_CMD */
608#define IA32_FLUSH_CMD_L1D 0x00000001
609
610/*
611 * PAT modes.
612 */
613#define PAT_UNCACHEABLE 0x00
614#define PAT_WRITE_COMBINING 0x01
615#define PAT_WRITE_THROUGH 0x04
616#define PAT_WRITE_PROTECTED 0x05
617#define PAT_WRITE_BACK 0x06
618#define PAT_UNCACHED 0x07
619#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i)))
620#define PAT_MASK(i) PAT_VALUE(i, 0xff)
621
622/*
623 * Constants related to MTRRs
624 */
625#define MTRR_UNCACHEABLE 0x00
626#define MTRR_WRITE_COMBINING 0x01
627#define MTRR_WRITE_THROUGH 0x04
628#define MTRR_WRITE_PROTECTED 0x05
629#define MTRR_WRITE_BACK 0x06
630#define MTRR_N64K 8 /* numbers of fixed-size entries */
631#define MTRR_N16K 16
632#define MTRR_N4K 64
633#define MTRR_CAP_WC 0x0000000000000400
634#define MTRR_CAP_FIXED 0x0000000000000100
635#define MTRR_CAP_VCNT 0x00000000000000ff
636#define MTRR_DEF_ENABLE 0x0000000000000800
637#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
638#define MTRR_DEF_TYPE 0x00000000000000ff
639#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
640#define MTRR_PHYSBASE_TYPE 0x00000000000000ff
641#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
642#define MTRR_PHYSMASK_VALID 0x0000000000000800
643
644/*
645 * Cyrix configuration registers, accessible as IO ports.
646 */
647#define CCR0 0xc0 /* Configuration control register 0 */
648#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
649 non-cacheable */
650#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
651#define CCR0_A20M 0x04 /* Enables A20M# input pin */
652#define CCR0_KEN 0x08 /* Enables KEN# input pin */
653#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
654#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
655 state */
656#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
657 assoc */
658#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
659
660#define CCR1 0xc1 /* Configuration control register 1 */
661#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
662#define CCR1_SMI 0x02 /* Enables SMM pins */
663#define CCR1_SMAC 0x04 /* System management memory access */
664#define CCR1_MMAC 0x08 /* Main memory access */
665#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
666#define CCR1_SM3 0x80 /* SMM address space address region 3 */
667
668#define CCR2 0xc2
669#define CCR2_WB 0x02 /* Enables WB cache interface pins */
670#define CCR2_SADS 0x02 /* Slow ADS */
671#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
672#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
673#define CCR2_WT1 0x10 /* WT region 1 */
674#define CCR2_WPR1 0x10 /* Write-protect region 1 */
675#define CCR2_BARB 0x20 /* Flushes write-back cache when entering
676 hold state. */
677#define CCR2_BWRT 0x40 /* Enables burst write cycles */
678#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
679
680#define CCR3 0xc3
681#define CCR3_SMILOCK 0x01 /* SMM register lock */
682#define CCR3_NMI 0x02 /* Enables NMI during SMM */
683#define CCR3_LINBRST 0x04 /* Linear address burst cycles */
684#define CCR3_SMMMODE 0x08 /* SMM Mode */
685#define CCR3_MAPEN0 0x10 /* Enables Map0 */
686#define CCR3_MAPEN1 0x20 /* Enables Map1 */
687#define CCR3_MAPEN2 0x40 /* Enables Map2 */
688#define CCR3_MAPEN3 0x80 /* Enables Map3 */
689
690#define CCR4 0xe8
691#define CCR4_IOMASK 0x07
692#define CCR4_MEM 0x08 /* Enables momory bypassing */
693#define CCR4_DTE 0x10 /* Enables directory table entry cache */
694#define CCR4_FASTFPE 0x20 /* Fast FPU exception */
695#define CCR4_CPUID 0x80 /* Enables CPUID instruction */
696
697#define CCR5 0xe9
698#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
699#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
700#define CCR5_LBR1 0x10 /* Local bus region 1 */
701#define CCR5_ARREN 0x20 /* Enables ARR region */
702
703#define CCR6 0xea
704
705#define CCR7 0xeb
706
707/* Performance Control Register (5x86 only). */
708#define PCR0 0x20
709#define PCR0_RSTK 0x01 /* Enables return stack */
710#define PCR0_BTB 0x02 /* Enables branch target buffer */
711#define PCR0_LOOP 0x04 /* Enables loop */
712#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
713 serialize pipe. */
714#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
715#define PCR0_BTBRT 0x40 /* Enables BTB test register. */
716#define PCR0_LSSER 0x80 /* Disable reorder */
717
718/* Device Identification Registers */
719#define DIR0 0xfe
720#define DIR1 0xff
721
722/*
723 * Machine Check register constants.
724 */
725#define MCG_CAP_COUNT 0x000000ff
726#define MCG_CAP_CTL_P 0x00000100
727#define MCG_CAP_EXT_P 0x00000200
728#define MCG_CAP_CMCI_P 0x00000400
729#define MCG_CAP_TES_P 0x00000800
730#define MCG_CAP_EXT_CNT 0x00ff0000
731#define MCG_CAP_SER_P 0x01000000
732#define MCG_STATUS_RIPV 0x00000001
733#define MCG_STATUS_EIPV 0x00000002
734#define MCG_STATUS_MCIP 0x00000004
735#define MCG_CTL_ENABLE 0xffffffffffffffff
736#define MCG_CTL_DISABLE 0x0000000000000000
737#define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
738#define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
739#define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
740#define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
741#define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */
742#define MC_STATUS_MCA_ERROR 0x000000000000ffff
743#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
744#define MC_STATUS_OTHER_INFO 0x01ffffff00000000
745#define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */
746#define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
747#define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */
748#define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */
749#define MC_STATUS_PCC 0x0200000000000000
750#define MC_STATUS_ADDRV 0x0400000000000000
751#define MC_STATUS_MISCV 0x0800000000000000
752#define MC_STATUS_EN 0x1000000000000000
753#define MC_STATUS_UC 0x2000000000000000
754#define MC_STATUS_OVER 0x4000000000000000
755#define MC_STATUS_VAL 0x8000000000000000
756#define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
757#define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
758#define MC_CTL2_THRESHOLD 0x0000000000007fff
759#define MC_CTL2_CMCI_EN 0x0000000040000000
760#define MC_AMDNB_BANK 4
761#define MC_MISC_AMDNB_VAL 0x8000000000000000 /* Counter presence valid */
762#define MC_MISC_AMDNB_CNTP 0x4000000000000000 /* Counter present */
763#define MC_MISC_AMDNB_LOCK 0x2000000000000000 /* Register locked */
764#define MC_MISC_AMDNB_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */
765#define MC_MISC_AMDNB_LVT_SHIFT 52
766#define MC_MISC_AMDNB_CNTEN 0x0008000000000000 /* Counter enabled */
767#define MC_MISC_AMDNB_INT_MASK 0x0006000000000000 /* Interrupt type */
768#define MC_MISC_AMDNB_INT_LVT 0x0002000000000000 /* Interrupt via Extended LVT */
769#define MC_MISC_AMDNB_INT_SMI 0x0004000000000000 /* SMI */
770#define MC_MISC_AMDNB_OVERFLOW 0x0001000000000000 /* Counter overflow */
771#define MC_MISC_AMDNB_CNT_MASK 0x00000fff00000000 /* Counter value */
772#define MC_MISC_AMDNB_CNT_SHIFT 32
773#define MC_MISC_AMDNB_CNT_MAX 0xfff
774#define MC_MISC_AMDNB_PTR_MASK 0x00000000ff000000 /* Pointer to additional registers */
775#define MC_MISC_AMDNB_PTR_SHIFT 24
776
777/*
778 * The following four 3-byte registers control the non-cacheable regions.
779 * These registers must be written as three separate bytes.
780 *
781 * NCRx+0: A31-A24 of starting address
782 * NCRx+1: A23-A16 of starting address
783 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
784 *
785 * The non-cacheable region's starting address must be aligned to the
786 * size indicated by the NCR_SIZE_xx field.
787 */
788#define NCR1 0xc4
789#define NCR2 0xc7
790#define NCR3 0xca
791#define NCR4 0xcd
792
793#define NCR_SIZE_0K 0
794#define NCR_SIZE_4K 1
795#define NCR_SIZE_8K 2
796#define NCR_SIZE_16K 3
797#define NCR_SIZE_32K 4
798#define NCR_SIZE_64K 5
799#define NCR_SIZE_128K 6
800#define NCR_SIZE_256K 7
801#define NCR_SIZE_512K 8
802#define NCR_SIZE_1M 9
803#define NCR_SIZE_2M 10
804#define NCR_SIZE_4M 11
805#define NCR_SIZE_8M 12
806#define NCR_SIZE_16M 13
807#define NCR_SIZE_32M 14
808#define NCR_SIZE_4G 15
809
810/*
811 * The address region registers are used to specify the location and
812 * size for the eight address regions.
813 *
814 * ARRx + 0: A31-A24 of start address
815 * ARRx + 1: A23-A16 of start address
816 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
817 */
818#define ARR0 0xc4
819#define ARR1 0xc7
820#define ARR2 0xca
821#define ARR3 0xcd
822#define ARR4 0xd0
823#define ARR5 0xd3
824#define ARR6 0xd6
825#define ARR7 0xd9
826
827#define ARR_SIZE_0K 0
828#define ARR_SIZE_4K 1
829#define ARR_SIZE_8K 2
830#define ARR_SIZE_16K 3
831#define ARR_SIZE_32K 4
832#define ARR_SIZE_64K 5
833#define ARR_SIZE_128K 6
834#define ARR_SIZE_256K 7
835#define ARR_SIZE_512K 8
836#define ARR_SIZE_1M 9
837#define ARR_SIZE_2M 10
838#define ARR_SIZE_4M 11
839#define ARR_SIZE_8M 12
840#define ARR_SIZE_16M 13
841#define ARR_SIZE_32M 14
842#define ARR_SIZE_4G 15
843
844/*
845 * The region control registers specify the attributes associated with
846 * the ARRx addres regions.
847 */
848#define RCR0 0xdc
849#define RCR1 0xdd
850#define RCR2 0xde
851#define RCR3 0xdf
852#define RCR4 0xe0
853#define RCR5 0xe1
854#define RCR6 0xe2
855#define RCR7 0xe3
856
857#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
858#define RCR_RCE 0x01 /* Enables caching for ARR7. */
859#define RCR_WWO 0x02 /* Weak write ordering. */
860#define RCR_WL 0x04 /* Weak locking. */
861#define RCR_WG 0x08 /* Write gathering. */
862#define RCR_WT 0x10 /* Write-through. */
863#define RCR_NLB 0x20 /* LBA# pin is not asserted. */
864
865/* AMD Write Allocate Top-Of-Memory and Control Register */
866#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
867#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
868#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
869
870/* AMD64 MSR's */
871#define MSR_EFER 0xc0000080 /* extended features */
872#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
873#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
874#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
875#define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
876#define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
877#define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
878#define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
879#define MSR_TSC_AUX 0xc0000103
880#define MSR_PERFEVSEL0 0xc0010000
881#define MSR_PERFEVSEL1 0xc0010001
882#define MSR_PERFEVSEL2 0xc0010002
883#define MSR_PERFEVSEL3 0xc0010003
884#define MSR_K7_PERFCTR0 0xc0010004
885#define MSR_K7_PERFCTR1 0xc0010005
886#define MSR_K7_PERFCTR2 0xc0010006
887#define MSR_K7_PERFCTR3 0xc0010007
888#define MSR_SYSCFG 0xc0010010
889#define MSR_HWCR 0xc0010015
890#define MSR_IORRBASE0 0xc0010016
891#define MSR_IORRMASK0 0xc0010017
892#define MSR_IORRBASE1 0xc0010018
893#define MSR_IORRMASK1 0xc0010019
894#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
895#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
896#define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */
897#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
898#define MSR_MC0_CTL_MASK 0xc0010044
899#define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */
900#define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */
901#define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */
902#define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
903#define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */
904#define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */
905#define MSR_VM_CR 0xc0010114 /* SVM: feature control */
906#define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */
907#define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */
908#define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */
909#define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
910
911/* MSR_VM_CR related */
912#define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */
913
914/* VIA ACE crypto featureset: for via_feature_rng */
915#define VIA_HAS_RNG 1 /* cpu has RNG */
916
917/* VIA ACE crypto featureset: for via_feature_xcrypt */
918#define VIA_HAS_AES 1 /* cpu has AES */
919#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
920#define VIA_HAS_MM 4 /* cpu has RSA instructions */
921#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
922
923/* Centaur Extended Feature flags */
924#define VIA_CPUID_HAS_RNG 0x000004
925#define VIA_CPUID_DO_RNG 0x000008
926#define VIA_CPUID_HAS_ACE 0x000040
927#define VIA_CPUID_DO_ACE 0x000080
928#define VIA_CPUID_HAS_ACE2 0x000100
929#define VIA_CPUID_DO_ACE2 0x000200
930#define VIA_CPUID_HAS_PHE 0x000400
931#define VIA_CPUID_DO_PHE 0x000800
932#define VIA_CPUID_HAS_PMM 0x001000
933#define VIA_CPUID_DO_PMM 0x002000
934
935/* VIA ACE xcrypt-* instruction context control options */
936#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
937#define VIA_CRYPT_CWLO_ALG_M 0x00000070
938#define VIA_CRYPT_CWLO_ALG_AES 0x00000000
939#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
940#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
941#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
942#define VIA_CRYPT_CWLO_NORMAL 0x00000000
943#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
944#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
945#define VIA_CRYPT_CWLO_DECRYPT 0x00000200
946#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
947#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
948#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
949
950#endif /* !_MACHINE_SPECIALREG_H_ */
| 409
410/*
411 * CPUID manufacturers identifiers
412 */
413#define AMD_VENDOR_ID "AuthenticAMD"
414#define CENTAUR_VENDOR_ID "CentaurHauls"
415#define CYRIX_VENDOR_ID "CyrixInstead"
416#define INTEL_VENDOR_ID "GenuineIntel"
417#define NEXGEN_VENDOR_ID "NexGenDriven"
418#define NSC_VENDOR_ID "Geode by NSC"
419#define RISE_VENDOR_ID "RiseRiseRise"
420#define SIS_VENDOR_ID "SiS SiS SiS "
421#define TRANSMETA_VENDOR_ID "GenuineTMx86"
422#define UMC_VENDOR_ID "UMC UMC UMC "
423
424/*
425 * Model-specific registers for the i386 family
426 */
427#define MSR_P5_MC_ADDR 0x000
428#define MSR_P5_MC_TYPE 0x001
429#define MSR_TSC 0x010
430#define MSR_P5_CESR 0x011
431#define MSR_P5_CTR0 0x012
432#define MSR_P5_CTR1 0x013
433#define MSR_IA32_PLATFORM_ID 0x017
434#define MSR_APICBASE 0x01b
435#define MSR_EBL_CR_POWERON 0x02a
436#define MSR_TEST_CTL 0x033
437#define MSR_IA32_FEATURE_CONTROL 0x03a
438#define MSR_IA32_SPEC_CTRL 0x048
439#define MSR_IA32_PRED_CMD 0x049
440#define MSR_BIOS_UPDT_TRIG 0x079
441#define MSR_BBL_CR_D0 0x088
442#define MSR_BBL_CR_D1 0x089
443#define MSR_BBL_CR_D2 0x08a
444#define MSR_BIOS_SIGN 0x08b
445#define MSR_PERFCTR0 0x0c1
446#define MSR_PERFCTR1 0x0c2
447#define MSR_PLATFORM_INFO 0x0ce
448#define MSR_MPERF 0x0e7
449#define MSR_APERF 0x0e8
450#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
451#define MSR_MTRRcap 0x0fe
452#define MSR_IA32_ARCH_CAP 0x10a
453#define MSR_IA32_FLUSH_CMD 0x10b
454#define MSR_TSX_FORCE_ABORT 0x10f
455#define MSR_BBL_CR_ADDR 0x116
456#define MSR_BBL_CR_DECC 0x118
457#define MSR_BBL_CR_CTL 0x119
458#define MSR_BBL_CR_TRIG 0x11a
459#define MSR_BBL_CR_BUSY 0x11b
460#define MSR_BBL_CR_CTL3 0x11e
461#define MSR_SYSENTER_CS_MSR 0x174
462#define MSR_SYSENTER_ESP_MSR 0x175
463#define MSR_SYSENTER_EIP_MSR 0x176
464#define MSR_MCG_CAP 0x179
465#define MSR_MCG_STATUS 0x17a
466#define MSR_MCG_CTL 0x17b
467#define MSR_EVNTSEL0 0x186
468#define MSR_EVNTSEL1 0x187
469#define MSR_THERM_CONTROL 0x19a
470#define MSR_THERM_INTERRUPT 0x19b
471#define MSR_THERM_STATUS 0x19c
472#define MSR_IA32_MISC_ENABLE 0x1a0
473#define MSR_IA32_TEMPERATURE_TARGET 0x1a2
474#define MSR_TURBO_RATIO_LIMIT 0x1ad
475#define MSR_TURBO_RATIO_LIMIT1 0x1ae
476#define MSR_DEBUGCTLMSR 0x1d9
477#define MSR_LASTBRANCHFROMIP 0x1db
478#define MSR_LASTBRANCHTOIP 0x1dc
479#define MSR_LASTINTFROMIP 0x1dd
480#define MSR_LASTINTTOIP 0x1de
481#define MSR_ROB_CR_BKUPTMPDR6 0x1e0
482#define MSR_MTRRVarBase 0x200
483#define MSR_MTRR64kBase 0x250
484#define MSR_MTRR16kBase 0x258
485#define MSR_MTRR4kBase 0x268
486#define MSR_PAT 0x277
487#define MSR_MC0_CTL2 0x280
488#define MSR_MTRRdefType 0x2ff
489#define MSR_MC0_CTL 0x400
490#define MSR_MC0_STATUS 0x401
491#define MSR_MC0_ADDR 0x402
492#define MSR_MC0_MISC 0x403
493#define MSR_MC1_CTL 0x404
494#define MSR_MC1_STATUS 0x405
495#define MSR_MC1_ADDR 0x406
496#define MSR_MC1_MISC 0x407
497#define MSR_MC2_CTL 0x408
498#define MSR_MC2_STATUS 0x409
499#define MSR_MC2_ADDR 0x40a
500#define MSR_MC2_MISC 0x40b
501#define MSR_MC3_CTL 0x40c
502#define MSR_MC3_STATUS 0x40d
503#define MSR_MC3_ADDR 0x40e
504#define MSR_MC3_MISC 0x40f
505#define MSR_MC4_CTL 0x410
506#define MSR_MC4_STATUS 0x411
507#define MSR_MC4_ADDR 0x412
508#define MSR_MC4_MISC 0x413
509#define MSR_RAPL_POWER_UNIT 0x606
510#define MSR_PKG_ENERGY_STATUS 0x611
511#define MSR_DRAM_ENERGY_STATUS 0x619
512#define MSR_PP0_ENERGY_STATUS 0x639
513#define MSR_PP1_ENERGY_STATUS 0x641
514#define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */
515
516/*
517 * VMX MSRs
518 */
519#define MSR_VMX_BASIC 0x480
520#define MSR_VMX_PINBASED_CTLS 0x481
521#define MSR_VMX_PROCBASED_CTLS 0x482
522#define MSR_VMX_EXIT_CTLS 0x483
523#define MSR_VMX_ENTRY_CTLS 0x484
524#define MSR_VMX_CR0_FIXED0 0x486
525#define MSR_VMX_CR0_FIXED1 0x487
526#define MSR_VMX_CR4_FIXED0 0x488
527#define MSR_VMX_CR4_FIXED1 0x489
528#define MSR_VMX_PROCBASED_CTLS2 0x48b
529#define MSR_VMX_EPT_VPID_CAP 0x48c
530#define MSR_VMX_TRUE_PINBASED_CTLS 0x48d
531#define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e
532#define MSR_VMX_TRUE_EXIT_CTLS 0x48f
533#define MSR_VMX_TRUE_ENTRY_CTLS 0x490
534
535/*
536 * X2APIC MSRs.
537 * Writes are not serializing.
538 */
539#define MSR_APIC_000 0x800
540#define MSR_APIC_ID 0x802
541#define MSR_APIC_VERSION 0x803
542#define MSR_APIC_TPR 0x808
543#define MSR_APIC_EOI 0x80b
544#define MSR_APIC_LDR 0x80d
545#define MSR_APIC_SVR 0x80f
546#define MSR_APIC_ISR0 0x810
547#define MSR_APIC_ISR1 0x811
548#define MSR_APIC_ISR2 0x812
549#define MSR_APIC_ISR3 0x813
550#define MSR_APIC_ISR4 0x814
551#define MSR_APIC_ISR5 0x815
552#define MSR_APIC_ISR6 0x816
553#define MSR_APIC_ISR7 0x817
554#define MSR_APIC_TMR0 0x818
555#define MSR_APIC_IRR0 0x820
556#define MSR_APIC_ESR 0x828
557#define MSR_APIC_LVT_CMCI 0x82F
558#define MSR_APIC_ICR 0x830
559#define MSR_APIC_LVT_TIMER 0x832
560#define MSR_APIC_LVT_THERMAL 0x833
561#define MSR_APIC_LVT_PCINT 0x834
562#define MSR_APIC_LVT_LINT0 0x835
563#define MSR_APIC_LVT_LINT1 0x836
564#define MSR_APIC_LVT_ERROR 0x837
565#define MSR_APIC_ICR_TIMER 0x838
566#define MSR_APIC_CCR_TIMER 0x839
567#define MSR_APIC_DCR_TIMER 0x83e
568#define MSR_APIC_SELF_IPI 0x83f
569
570#define MSR_IA32_XSS 0xda0
571
572/*
573 * Constants related to MSR's.
574 */
575#define APICBASE_RESERVED 0x000002ff
576#define APICBASE_BSP 0x00000100
577#define APICBASE_X2APIC 0x00000400
578#define APICBASE_ENABLED 0x00000800
579#define APICBASE_ADDRESS 0xfffff000
580
581/* MSR_IA32_FEATURE_CONTROL related */
582#define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */
583#define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */
584#define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */
585
586/* MSR IA32_MISC_ENABLE */
587#define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL
588#define IA32_MISC_EN_ATCCE 0x0000000000000008ULL
589#define IA32_MISC_EN_PERFMON 0x0000000000000080ULL
590#define IA32_MISC_EN_PEBSU 0x0000000000001000ULL
591#define IA32_MISC_EN_ESSTE 0x0000000000010000ULL
592#define IA32_MISC_EN_MONE 0x0000000000040000ULL
593#define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL
594#define IA32_MISC_EN_xTPRD 0x0000000000800000ULL
595#define IA32_MISC_EN_XDD 0x0000000400000000ULL
596
597/*
598 * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel'
599 * document 336996-001 Speculative Execution Side Channel Mitigations.
600 */
601/* MSR IA32_SPEC_CTRL */
602#define IA32_SPEC_CTRL_IBRS 0x00000001
603#define IA32_SPEC_CTRL_STIBP 0x00000002
604#define IA32_SPEC_CTRL_SSBD 0x00000004
605
606/* MSR IA32_PRED_CMD */
607#define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL
608
609/* MSR IA32_FLUSH_CMD */
610#define IA32_FLUSH_CMD_L1D 0x00000001
611
612/*
613 * PAT modes.
614 */
615#define PAT_UNCACHEABLE 0x00
616#define PAT_WRITE_COMBINING 0x01
617#define PAT_WRITE_THROUGH 0x04
618#define PAT_WRITE_PROTECTED 0x05
619#define PAT_WRITE_BACK 0x06
620#define PAT_UNCACHED 0x07
621#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i)))
622#define PAT_MASK(i) PAT_VALUE(i, 0xff)
623
624/*
625 * Constants related to MTRRs
626 */
627#define MTRR_UNCACHEABLE 0x00
628#define MTRR_WRITE_COMBINING 0x01
629#define MTRR_WRITE_THROUGH 0x04
630#define MTRR_WRITE_PROTECTED 0x05
631#define MTRR_WRITE_BACK 0x06
632#define MTRR_N64K 8 /* numbers of fixed-size entries */
633#define MTRR_N16K 16
634#define MTRR_N4K 64
635#define MTRR_CAP_WC 0x0000000000000400
636#define MTRR_CAP_FIXED 0x0000000000000100
637#define MTRR_CAP_VCNT 0x00000000000000ff
638#define MTRR_DEF_ENABLE 0x0000000000000800
639#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
640#define MTRR_DEF_TYPE 0x00000000000000ff
641#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
642#define MTRR_PHYSBASE_TYPE 0x00000000000000ff
643#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
644#define MTRR_PHYSMASK_VALID 0x0000000000000800
645
646/*
647 * Cyrix configuration registers, accessible as IO ports.
648 */
649#define CCR0 0xc0 /* Configuration control register 0 */
650#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
651 non-cacheable */
652#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
653#define CCR0_A20M 0x04 /* Enables A20M# input pin */
654#define CCR0_KEN 0x08 /* Enables KEN# input pin */
655#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
656#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
657 state */
658#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
659 assoc */
660#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
661
662#define CCR1 0xc1 /* Configuration control register 1 */
663#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
664#define CCR1_SMI 0x02 /* Enables SMM pins */
665#define CCR1_SMAC 0x04 /* System management memory access */
666#define CCR1_MMAC 0x08 /* Main memory access */
667#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
668#define CCR1_SM3 0x80 /* SMM address space address region 3 */
669
670#define CCR2 0xc2
671#define CCR2_WB 0x02 /* Enables WB cache interface pins */
672#define CCR2_SADS 0x02 /* Slow ADS */
673#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
674#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
675#define CCR2_WT1 0x10 /* WT region 1 */
676#define CCR2_WPR1 0x10 /* Write-protect region 1 */
677#define CCR2_BARB 0x20 /* Flushes write-back cache when entering
678 hold state. */
679#define CCR2_BWRT 0x40 /* Enables burst write cycles */
680#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
681
682#define CCR3 0xc3
683#define CCR3_SMILOCK 0x01 /* SMM register lock */
684#define CCR3_NMI 0x02 /* Enables NMI during SMM */
685#define CCR3_LINBRST 0x04 /* Linear address burst cycles */
686#define CCR3_SMMMODE 0x08 /* SMM Mode */
687#define CCR3_MAPEN0 0x10 /* Enables Map0 */
688#define CCR3_MAPEN1 0x20 /* Enables Map1 */
689#define CCR3_MAPEN2 0x40 /* Enables Map2 */
690#define CCR3_MAPEN3 0x80 /* Enables Map3 */
691
692#define CCR4 0xe8
693#define CCR4_IOMASK 0x07
694#define CCR4_MEM 0x08 /* Enables momory bypassing */
695#define CCR4_DTE 0x10 /* Enables directory table entry cache */
696#define CCR4_FASTFPE 0x20 /* Fast FPU exception */
697#define CCR4_CPUID 0x80 /* Enables CPUID instruction */
698
699#define CCR5 0xe9
700#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
701#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
702#define CCR5_LBR1 0x10 /* Local bus region 1 */
703#define CCR5_ARREN 0x20 /* Enables ARR region */
704
705#define CCR6 0xea
706
707#define CCR7 0xeb
708
709/* Performance Control Register (5x86 only). */
710#define PCR0 0x20
711#define PCR0_RSTK 0x01 /* Enables return stack */
712#define PCR0_BTB 0x02 /* Enables branch target buffer */
713#define PCR0_LOOP 0x04 /* Enables loop */
714#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
715 serialize pipe. */
716#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
717#define PCR0_BTBRT 0x40 /* Enables BTB test register. */
718#define PCR0_LSSER 0x80 /* Disable reorder */
719
720/* Device Identification Registers */
721#define DIR0 0xfe
722#define DIR1 0xff
723
724/*
725 * Machine Check register constants.
726 */
727#define MCG_CAP_COUNT 0x000000ff
728#define MCG_CAP_CTL_P 0x00000100
729#define MCG_CAP_EXT_P 0x00000200
730#define MCG_CAP_CMCI_P 0x00000400
731#define MCG_CAP_TES_P 0x00000800
732#define MCG_CAP_EXT_CNT 0x00ff0000
733#define MCG_CAP_SER_P 0x01000000
734#define MCG_STATUS_RIPV 0x00000001
735#define MCG_STATUS_EIPV 0x00000002
736#define MCG_STATUS_MCIP 0x00000004
737#define MCG_CTL_ENABLE 0xffffffffffffffff
738#define MCG_CTL_DISABLE 0x0000000000000000
739#define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
740#define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
741#define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
742#define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
743#define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */
744#define MC_STATUS_MCA_ERROR 0x000000000000ffff
745#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
746#define MC_STATUS_OTHER_INFO 0x01ffffff00000000
747#define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */
748#define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
749#define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */
750#define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */
751#define MC_STATUS_PCC 0x0200000000000000
752#define MC_STATUS_ADDRV 0x0400000000000000
753#define MC_STATUS_MISCV 0x0800000000000000
754#define MC_STATUS_EN 0x1000000000000000
755#define MC_STATUS_UC 0x2000000000000000
756#define MC_STATUS_OVER 0x4000000000000000
757#define MC_STATUS_VAL 0x8000000000000000
758#define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
759#define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
760#define MC_CTL2_THRESHOLD 0x0000000000007fff
761#define MC_CTL2_CMCI_EN 0x0000000040000000
762#define MC_AMDNB_BANK 4
763#define MC_MISC_AMDNB_VAL 0x8000000000000000 /* Counter presence valid */
764#define MC_MISC_AMDNB_CNTP 0x4000000000000000 /* Counter present */
765#define MC_MISC_AMDNB_LOCK 0x2000000000000000 /* Register locked */
766#define MC_MISC_AMDNB_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */
767#define MC_MISC_AMDNB_LVT_SHIFT 52
768#define MC_MISC_AMDNB_CNTEN 0x0008000000000000 /* Counter enabled */
769#define MC_MISC_AMDNB_INT_MASK 0x0006000000000000 /* Interrupt type */
770#define MC_MISC_AMDNB_INT_LVT 0x0002000000000000 /* Interrupt via Extended LVT */
771#define MC_MISC_AMDNB_INT_SMI 0x0004000000000000 /* SMI */
772#define MC_MISC_AMDNB_OVERFLOW 0x0001000000000000 /* Counter overflow */
773#define MC_MISC_AMDNB_CNT_MASK 0x00000fff00000000 /* Counter value */
774#define MC_MISC_AMDNB_CNT_SHIFT 32
775#define MC_MISC_AMDNB_CNT_MAX 0xfff
776#define MC_MISC_AMDNB_PTR_MASK 0x00000000ff000000 /* Pointer to additional registers */
777#define MC_MISC_AMDNB_PTR_SHIFT 24
778
779/*
780 * The following four 3-byte registers control the non-cacheable regions.
781 * These registers must be written as three separate bytes.
782 *
783 * NCRx+0: A31-A24 of starting address
784 * NCRx+1: A23-A16 of starting address
785 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
786 *
787 * The non-cacheable region's starting address must be aligned to the
788 * size indicated by the NCR_SIZE_xx field.
789 */
790#define NCR1 0xc4
791#define NCR2 0xc7
792#define NCR3 0xca
793#define NCR4 0xcd
794
795#define NCR_SIZE_0K 0
796#define NCR_SIZE_4K 1
797#define NCR_SIZE_8K 2
798#define NCR_SIZE_16K 3
799#define NCR_SIZE_32K 4
800#define NCR_SIZE_64K 5
801#define NCR_SIZE_128K 6
802#define NCR_SIZE_256K 7
803#define NCR_SIZE_512K 8
804#define NCR_SIZE_1M 9
805#define NCR_SIZE_2M 10
806#define NCR_SIZE_4M 11
807#define NCR_SIZE_8M 12
808#define NCR_SIZE_16M 13
809#define NCR_SIZE_32M 14
810#define NCR_SIZE_4G 15
811
812/*
813 * The address region registers are used to specify the location and
814 * size for the eight address regions.
815 *
816 * ARRx + 0: A31-A24 of start address
817 * ARRx + 1: A23-A16 of start address
818 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
819 */
820#define ARR0 0xc4
821#define ARR1 0xc7
822#define ARR2 0xca
823#define ARR3 0xcd
824#define ARR4 0xd0
825#define ARR5 0xd3
826#define ARR6 0xd6
827#define ARR7 0xd9
828
829#define ARR_SIZE_0K 0
830#define ARR_SIZE_4K 1
831#define ARR_SIZE_8K 2
832#define ARR_SIZE_16K 3
833#define ARR_SIZE_32K 4
834#define ARR_SIZE_64K 5
835#define ARR_SIZE_128K 6
836#define ARR_SIZE_256K 7
837#define ARR_SIZE_512K 8
838#define ARR_SIZE_1M 9
839#define ARR_SIZE_2M 10
840#define ARR_SIZE_4M 11
841#define ARR_SIZE_8M 12
842#define ARR_SIZE_16M 13
843#define ARR_SIZE_32M 14
844#define ARR_SIZE_4G 15
845
846/*
847 * The region control registers specify the attributes associated with
848 * the ARRx addres regions.
849 */
850#define RCR0 0xdc
851#define RCR1 0xdd
852#define RCR2 0xde
853#define RCR3 0xdf
854#define RCR4 0xe0
855#define RCR5 0xe1
856#define RCR6 0xe2
857#define RCR7 0xe3
858
859#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
860#define RCR_RCE 0x01 /* Enables caching for ARR7. */
861#define RCR_WWO 0x02 /* Weak write ordering. */
862#define RCR_WL 0x04 /* Weak locking. */
863#define RCR_WG 0x08 /* Write gathering. */
864#define RCR_WT 0x10 /* Write-through. */
865#define RCR_NLB 0x20 /* LBA# pin is not asserted. */
866
867/* AMD Write Allocate Top-Of-Memory and Control Register */
868#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
869#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
870#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
871
872/* AMD64 MSR's */
873#define MSR_EFER 0xc0000080 /* extended features */
874#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
875#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
876#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
877#define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
878#define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
879#define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
880#define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
881#define MSR_TSC_AUX 0xc0000103
882#define MSR_PERFEVSEL0 0xc0010000
883#define MSR_PERFEVSEL1 0xc0010001
884#define MSR_PERFEVSEL2 0xc0010002
885#define MSR_PERFEVSEL3 0xc0010003
886#define MSR_K7_PERFCTR0 0xc0010004
887#define MSR_K7_PERFCTR1 0xc0010005
888#define MSR_K7_PERFCTR2 0xc0010006
889#define MSR_K7_PERFCTR3 0xc0010007
890#define MSR_SYSCFG 0xc0010010
891#define MSR_HWCR 0xc0010015
892#define MSR_IORRBASE0 0xc0010016
893#define MSR_IORRMASK0 0xc0010017
894#define MSR_IORRBASE1 0xc0010018
895#define MSR_IORRMASK1 0xc0010019
896#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
897#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
898#define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */
899#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
900#define MSR_MC0_CTL_MASK 0xc0010044
901#define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */
902#define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */
903#define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */
904#define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
905#define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */
906#define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */
907#define MSR_VM_CR 0xc0010114 /* SVM: feature control */
908#define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */
909#define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */
910#define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */
911#define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
912
913/* MSR_VM_CR related */
914#define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */
915
916/* VIA ACE crypto featureset: for via_feature_rng */
917#define VIA_HAS_RNG 1 /* cpu has RNG */
918
919/* VIA ACE crypto featureset: for via_feature_xcrypt */
920#define VIA_HAS_AES 1 /* cpu has AES */
921#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
922#define VIA_HAS_MM 4 /* cpu has RSA instructions */
923#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
924
925/* Centaur Extended Feature flags */
926#define VIA_CPUID_HAS_RNG 0x000004
927#define VIA_CPUID_DO_RNG 0x000008
928#define VIA_CPUID_HAS_ACE 0x000040
929#define VIA_CPUID_DO_ACE 0x000080
930#define VIA_CPUID_HAS_ACE2 0x000100
931#define VIA_CPUID_DO_ACE2 0x000200
932#define VIA_CPUID_HAS_PHE 0x000400
933#define VIA_CPUID_DO_PHE 0x000800
934#define VIA_CPUID_HAS_PMM 0x001000
935#define VIA_CPUID_DO_PMM 0x002000
936
937/* VIA ACE xcrypt-* instruction context control options */
938#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
939#define VIA_CRYPT_CWLO_ALG_M 0x00000070
940#define VIA_CRYPT_CWLO_ALG_AES 0x00000000
941#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
942#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
943#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
944#define VIA_CRYPT_CWLO_NORMAL 0x00000000
945#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
946#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
947#define VIA_CRYPT_CWLO_DECRYPT 0x00000200
948#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
949#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
950#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
951
952#endif /* !_MACHINE_SPECIALREG_H_ */
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