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pmc.h (226526) pmc.h (228869)
1/*-
2 * Copyright (c) 2003-2008, Joseph Koshy
3 * Copyright (c) 2007 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * Portions of this software were developed by A. Joseph Koshy under
7 * sponsorship from the FreeBSD Foundation and Google, Inc.
8 *

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22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
1/*-
2 * Copyright (c) 2003-2008, Joseph Koshy
3 * Copyright (c) 2007 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * Portions of this software were developed by A. Joseph Koshy under
7 * sponsorship from the FreeBSD Foundation and Google, Inc.
8 *

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22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD: head/sys/sys/pmc.h 226526 2011-10-19 07:16:57Z fabient $
30 * $FreeBSD: head/sys/sys/pmc.h 228869 2011-12-24 19:34:52Z jhibbits $
31 */
32
33#ifndef _SYS_PMC_H_
34#define _SYS_PMC_H_
35
36#include <dev/hwpmc/pmc_events.h>
37
38#include <machine/pmc_mdep.h>

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82 __PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \
83 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \
84 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \
85 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \
86 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \
87 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \
88 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \
89 __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \
31 */
32
33#ifndef _SYS_PMC_H_
34#define _SYS_PMC_H_
35
36#include <dev/hwpmc/pmc_events.h>
37
38#include <machine/pmc_mdep.h>

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82 __PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \
83 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \
84 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \
85 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \
86 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \
87 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \
88 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \
89 __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \
90 __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K")
90 __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \
91 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450")
91
92enum pmc_cputype {
93#undef __PMC_CPU
94#define __PMC_CPU(S,V,D) PMC_CPU_##S = V,
95 __PMC_CPUS()
96};
97
98#define PMC_CPU_FIRST PMC_CPU_AMD_K7
92
93enum pmc_cputype {
94#undef __PMC_CPU
95#define __PMC_CPU(S,V,D) PMC_CPU_##S = V,
96 __PMC_CPUS()
97};
98
99#define PMC_CPU_FIRST PMC_CPU_AMD_K7
99#define PMC_CPU_LAST PMC_CPU_MIPS_24K
100#define PMC_CPU_LAST PMC_CPU_PPC_7450
100
101/*
102 * Classes of PMCs
103 */
104
105#define __PMC_CLASSES() \
106 __PMC_CLASS(TSC) /* CPU Timestamp counter */ \
107 __PMC_CLASS(K7) /* AMD K7 performance counters */ \
108 __PMC_CLASS(K8) /* AMD K8 performance counters */ \
109 __PMC_CLASS(P5) /* Intel Pentium counters */ \
110 __PMC_CLASS(P6) /* Intel Pentium Pro counters */ \
111 __PMC_CLASS(P4) /* Intel Pentium-IV counters */ \
112 __PMC_CLASS(IAF) /* Intel Core2/Atom, fixed function */ \
113 __PMC_CLASS(IAP) /* Intel Core...Atom, programmable */ \
114 __PMC_CLASS(UCF) /* Intel Uncore fixed function */ \
115 __PMC_CLASS(UCP) /* Intel Uncore programmable */ \
116 __PMC_CLASS(XSCALE) /* Intel XScale counters */ \
101
102/*
103 * Classes of PMCs
104 */
105
106#define __PMC_CLASSES() \
107 __PMC_CLASS(TSC) /* CPU Timestamp counter */ \
108 __PMC_CLASS(K7) /* AMD K7 performance counters */ \
109 __PMC_CLASS(K8) /* AMD K8 performance counters */ \
110 __PMC_CLASS(P5) /* Intel Pentium counters */ \
111 __PMC_CLASS(P6) /* Intel Pentium Pro counters */ \
112 __PMC_CLASS(P4) /* Intel Pentium-IV counters */ \
113 __PMC_CLASS(IAF) /* Intel Core2/Atom, fixed function */ \
114 __PMC_CLASS(IAP) /* Intel Core...Atom, programmable */ \
115 __PMC_CLASS(UCF) /* Intel Uncore fixed function */ \
116 __PMC_CLASS(UCP) /* Intel Uncore programmable */ \
117 __PMC_CLASS(XSCALE) /* Intel XScale counters */ \
117 __PMC_CLASS(MIPS24K) /* MIPS 24K */
118 __PMC_CLASS(MIPS24K) /* MIPS 24K */ \
119 __PMC_CLASS(PPC7450) /* Motorola MPC7450 class */
118
119enum pmc_class {
120#undef __PMC_CLASS
121#define __PMC_CLASS(N) PMC_CLASS_##N ,
122 __PMC_CLASSES()
123};
124
125#define PMC_CLASS_FIRST PMC_CLASS_TSC
120
121enum pmc_class {
122#undef __PMC_CLASS
123#define __PMC_CLASS(N) PMC_CLASS_##N ,
124 __PMC_CLASSES()
125};
126
127#define PMC_CLASS_FIRST PMC_CLASS_TSC
126#define PMC_CLASS_LAST PMC_CLASS_MIPS24K
128#define PMC_CLASS_LAST PMC_CLASS_PPC7450
127
128/*
129 * A PMC can be in the following states:
130 *
131 * Hardware states:
132 * DISABLED -- administratively prohibited from being used.
133 * FREE -- HW available for use
134 * Software states:

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129
130/*
131 * A PMC can be in the following states:
132 *
133 * Hardware states:
134 * DISABLED -- administratively prohibited from being used.
135 * FREE -- HW available for use
136 * Software states:

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