1/*-
2 * Copyright (c) 2003-2008, Joseph Koshy
3 * Copyright (c) 2007 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * Portions of this software were developed by A. Joseph Koshy under
7 * sponsorship from the FreeBSD Foundation and Google, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD: head/sys/sys/pmc.h 261342 2014-02-01 02:03:50Z jhibbits $
31 */
32
33#ifndef _SYS_PMC_H_
34#define _SYS_PMC_H_
35
36#include <dev/hwpmc/pmc_events.h>
37
38#include <machine/pmc_mdep.h>
39#include <machine/profile.h>
40
41#define PMC_MODULE_NAME "hwpmc"
42#define PMC_NAME_MAX 64 /* HW counter name size */
43#define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */
44
45/*
46 * Kernel<->userland API version number [MMmmpppp]
47 *
48 * Major numbers are to be incremented when an incompatible change to
49 * the ABI occurs that older clients will not be able to handle.
50 *
51 * Minor numbers are incremented when a backwards compatible change
52 * occurs that allows older correct programs to run unchanged. For
53 * example, when support for a new PMC type is added.
54 *
55 * The patch version is incremented for every bug fix.
56 */
57#define PMC_VERSION_MAJOR 0x03
58#define PMC_VERSION_MINOR 0x01
59#define PMC_VERSION_PATCH 0x0000
60
61#define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \
62 PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH)
63
64/*
65 * Kinds of CPUs known.
66 *
67 * We keep track of CPU variants that need to be distinguished in
68 * some way for PMC operations. CPU names are grouped by manufacturer
69 * and numbered sparsely in order to minimize changes to the ABI involved
70 * when new CPUs are added.
71 */
72
73#define __PMC_CPUS() \
74 __PMC_CPU(AMD_K7, 0x00, "AMD K7") \
75 __PMC_CPU(AMD_K8, 0x01, "AMD K8") \
76 __PMC_CPU(INTEL_P5, 0x80, "Intel Pentium") \
77 __PMC_CPU(INTEL_P6, 0x81, "Intel Pentium Pro") \
78 __PMC_CPU(INTEL_CL, 0x82, "Intel Celeron") \
79 __PMC_CPU(INTEL_PII, 0x83, "Intel Pentium II") \
80 __PMC_CPU(INTEL_PIII, 0x84, "Intel Pentium III") \
81 __PMC_CPU(INTEL_PM, 0x85, "Intel Pentium M") \
82 __PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \
83 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \
84 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \
85 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \
86 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \
87 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \
88 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \
89 __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \
90 __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \
91 __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \
92 __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \
93 __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \
94 __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \
95 __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \
96 __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \
97 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \
98 __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \
99 __PMC_CPU(GENERIC, 0x400, "Generic")
100
101enum pmc_cputype {
102#undef __PMC_CPU
103#define __PMC_CPU(S,V,D) PMC_CPU_##S = V,
104 __PMC_CPUS()
105};
106
107#define PMC_CPU_FIRST PMC_CPU_AMD_K7
108#define PMC_CPU_LAST PMC_CPU_GENERIC
109
110/*
111 * Classes of PMCs
112 */
113
114#define __PMC_CLASSES() \
115 __PMC_CLASS(TSC) /* CPU Timestamp counter */ \
116 __PMC_CLASS(K7) /* AMD K7 performance counters */ \
117 __PMC_CLASS(K8) /* AMD K8 performance counters */ \
118 __PMC_CLASS(P5) /* Intel Pentium counters */ \
119 __PMC_CLASS(P6) /* Intel Pentium Pro counters */ \
120 __PMC_CLASS(P4) /* Intel Pentium-IV counters */ \
121 __PMC_CLASS(IAF) /* Intel Core2/Atom, fixed function */ \
122 __PMC_CLASS(IAP) /* Intel Core...Atom, programmable */ \
123 __PMC_CLASS(UCF) /* Intel Uncore fixed function */ \
124 __PMC_CLASS(UCP) /* Intel Uncore programmable */ \
125 __PMC_CLASS(XSCALE) /* Intel XScale counters */ \
126 __PMC_CLASS(MIPS24K) /* MIPS 24K */ \
127 __PMC_CLASS(OCTEON) /* Cavium Octeon */ \
128 __PMC_CLASS(PPC7450) /* Motorola MPC7450 class */ \
129 __PMC_CLASS(PPC970) /* IBM PowerPC 970 class */ \
130 __PMC_CLASS(SOFT) /* Software events */
131
132enum pmc_class {
133#undef __PMC_CLASS
134#define __PMC_CLASS(N) PMC_CLASS_##N ,
135 __PMC_CLASSES()
136};
137
138#define PMC_CLASS_FIRST PMC_CLASS_TSC
139#define PMC_CLASS_LAST PMC_CLASS_SOFT
140
141/*
142 * A PMC can be in the following states:
143 *
144 * Hardware states:
145 * DISABLED -- administratively prohibited from being used.
146 * FREE -- HW available for use
147 * Software states:
148 * ALLOCATED -- allocated
149 * STOPPED -- allocated, but not counting events
150 * RUNNING -- allocated, and in operation; 'pm_runcount'
151 * holds the number of CPUs using this PMC at
152 * a given instant
153 * DELETED -- being destroyed
154 */
155
156#define __PMC_HWSTATES() \
157 __PMC_STATE(DISABLED) \
158 __PMC_STATE(FREE)
159
160#define __PMC_SWSTATES() \
161 __PMC_STATE(ALLOCATED) \
162 __PMC_STATE(STOPPED) \
163 __PMC_STATE(RUNNING) \
164 __PMC_STATE(DELETED)
165
166#define __PMC_STATES() \
167 __PMC_HWSTATES() \
168 __PMC_SWSTATES()
169
170enum pmc_state {
171#undef __PMC_STATE
172#define __PMC_STATE(S) PMC_STATE_##S,
173 __PMC_STATES()
174 __PMC_STATE(MAX)
175};
176
177#define PMC_STATE_FIRST PMC_STATE_DISABLED
178#define PMC_STATE_LAST PMC_STATE_DELETED
179
180/*
181 * An allocated PMC may used as a 'global' counter or as a
182 * 'thread-private' one. Each such mode of use can be in either
183 * statistical sampling mode or in counting mode. Thus a PMC in use
184 *
185 * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling
186 * SC i.e., SYSTEM COUNTER -- system-wide counting mode
187 * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling
188 * TC i.e., THREAD COUNTER -- thread virtual, counting mode
189 *
190 * Statistical profiling modes rely on the PMC periodically delivering
191 * a interrupt to the CPU (when the configured number of events have
192 * been measured), so the PMC must have the ability to generate
193 * interrupts.
194 *
195 * In counting modes, the PMC counts its configured events, with the
196 * value of the PMC being read whenever needed by its owner process.
197 *
198 * The thread specific modes "virtualize" the PMCs -- the PMCs appear
199 * to be thread private and count events only when the profiled thread
200 * actually executes on the CPU.
201 *
202 * The system-wide "global" modes keep the PMCs running all the time
203 * and are used to measure the behaviour of the whole system.
204 */
205
206#define __PMC_MODES() \
207 __PMC_MODE(SS, 0) \
208 __PMC_MODE(SC, 1) \
209 __PMC_MODE(TS, 2) \
210 __PMC_MODE(TC, 3)
211
212enum pmc_mode {
213#undef __PMC_MODE
214#define __PMC_MODE(M,N) PMC_MODE_##M = N,
215 __PMC_MODES()
216};
217
218#define PMC_MODE_FIRST PMC_MODE_SS
219#define PMC_MODE_LAST PMC_MODE_TC
220
221#define PMC_IS_COUNTING_MODE(mode) \
222 ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC)
223#define PMC_IS_SYSTEM_MODE(mode) \
224 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC)
225#define PMC_IS_SAMPLING_MODE(mode) \
226 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS)
227#define PMC_IS_VIRTUAL_MODE(mode) \
228 ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC)
229
230/*
231 * PMC row disposition
232 */
233
234#define __PMC_DISPOSITIONS(N) \
235 __PMC_DISP(STANDALONE) /* global/disabled counters */ \
236 __PMC_DISP(FREE) /* free/available */ \
237 __PMC_DISP(THREAD) /* thread-virtual PMCs */ \
238 __PMC_DISP(UNKNOWN) /* sentinel */
239
240enum pmc_disp {
241#undef __PMC_DISP
242#define __PMC_DISP(D) PMC_DISP_##D ,
243 __PMC_DISPOSITIONS()
244};
245
246#define PMC_DISP_FIRST PMC_DISP_STANDALONE
247#define PMC_DISP_LAST PMC_DISP_THREAD
248
249/*
250 * Counter capabilities
251 *
252 * __PMC_CAPS(NAME, VALUE, DESCRIPTION)
253 */
254
255#define __PMC_CAPS() \
256 __PMC_CAP(INTERRUPT, 0, "generate interrupts") \
257 __PMC_CAP(USER, 1, "count user-mode events") \
258 __PMC_CAP(SYSTEM, 2, "count system-mode events") \
259 __PMC_CAP(EDGE, 3, "do edge detection of events") \
260 __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \
261 __PMC_CAP(READ, 5, "read PMC counter") \
262 __PMC_CAP(WRITE, 6, "reprogram PMC counter") \
263 __PMC_CAP(INVERT, 7, "invert comparision sense") \
264 __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \
265 __PMC_CAP(PRECISE, 9, "perform precise sampling") \
266 __PMC_CAP(TAGGING, 10, "tag upstream events") \
267 __PMC_CAP(CASCADE, 11, "cascade counters")
268
269enum pmc_caps
270{
271#undef __PMC_CAP
272#define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) ,
273 __PMC_CAPS()
274};
275
276#define PMC_CAP_FIRST PMC_CAP_INTERRUPT
277#define PMC_CAP_LAST PMC_CAP_CASCADE
278
279/*
280 * PMC Event Numbers
281 *
282 * These are generated from the definitions in "dev/hwpmc/pmc_events.h".
283 */
284
285enum pmc_event {
286#undef __PMC_EV
287#undef __PMC_EV_BLOCK
288#define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 ,
289#define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N ,
290 __PMC_EVENTS()
291};
292
293/*
294 * PMC SYSCALL INTERFACE
295 */
296
297/*
298 * "PMC_OPS" -- these are the commands recognized by the kernel
299 * module, and are used when performing a system call from userland.
300 */
301#define __PMC_OPS() \
302 __PMC_OP(CONFIGURELOG, "Set log file") \
303 __PMC_OP(FLUSHLOG, "Flush log file") \
304 __PMC_OP(GETCPUINFO, "Get system CPU information") \
305 __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \
306 __PMC_OP(GETMODULEVERSION, "Get module version") \
307 __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \
308 __PMC_OP(PMCADMIN, "Set PMC state") \
309 __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \
310 __PMC_OP(PMCATTACH, "Attach a PMC to a process") \
311 __PMC_OP(PMCDETACH, "Detach a PMC from a process") \
312 __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \
313 __PMC_OP(PMCRELEASE, "Release a PMC") \
314 __PMC_OP(PMCRW, "Read/Set a PMC") \
315 __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \
316 __PMC_OP(PMCSTART, "Start a PMC") \
317 __PMC_OP(PMCSTOP, "Stop a PMC") \
318 __PMC_OP(WRITELOG, "Write a cookie to the log file") \
319 __PMC_OP(CLOSELOG, "Close log file") \
320 __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list")
321
322
323enum pmc_ops {
324#undef __PMC_OP
325#define __PMC_OP(N, D) PMC_OP_##N,
326 __PMC_OPS()
327};
328
329
330/*
331 * Flags used in operations on PMCs.
332 */
333
334#define PMC_F_FORCE 0x00000001 /*OP ADMIN force operation */
335#define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */
336#define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */
337#define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */
338#define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */
339#define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */
340#define PMC_F_KGMON 0x00000040 /*OP ALLOCATE kgmon(8) profiling */
341/* V2 API */
342#define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */
343
344/* internal flags */
345#define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/
346#define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */
347#define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */
348
349#define PMC_CALLCHAIN_DEPTH_MAX 32
350
351#define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/
352
353/*
354 * Cookies used to denote allocated PMCs, and the values of PMCs.
355 */
356
357typedef uint32_t pmc_id_t;
358typedef uint64_t pmc_value_t;
359
360#define PMC_ID_INVALID (~ (pmc_id_t) 0)
361
362/*
363 * PMC IDs have the following format:
364 *
365 * +--------+----------+-----------+-----------+
366 * | CPU | PMC MODE | PMC CLASS | ROW INDEX |
367 * +--------+----------+-----------+-----------+
368 *
369 * where each field is 8 bits wide. Field 'CPU' is set to the
370 * requested CPU for system-wide PMCs or PMC_CPU_ANY for process-mode
371 * PMCs. Field 'PMC MODE' is the allocated PMC mode. Field 'PMC
372 * CLASS' is the class of the PMC. Field 'ROW INDEX' is the row index
373 * for the PMC.
374 *
375 * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total
376 * number of hardware PMCs on this cpu.
377 */
378
379
380#define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF)
381#define PMC_ID_TO_CLASS(ID) (((ID) & 0xFF00) >> 8)
382#define PMC_ID_TO_MODE(ID) (((ID) & 0xFF0000) >> 16)
383#define PMC_ID_TO_CPU(ID) (((ID) & 0xFF000000) >> 24)
384#define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \
385 ((((CPU) & 0xFF) << 24) | (((MODE) & 0xFF) << 16) | \
386 (((CLASS) & 0xFF) << 8) | ((ROWINDEX) & 0xFF))
387
388/*
389 * Data structures for system calls supported by the pmc driver.
390 */
391
392/*
393 * OP PMCALLOCATE
394 *
395 * Allocate a PMC on the named CPU.
396 */
397
398#define PMC_CPU_ANY ~0
399
400struct pmc_op_pmcallocate {
401 uint32_t pm_caps; /* PMC_CAP_* */
402 uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */
403 enum pmc_class pm_class; /* class of PMC desired */
404 enum pmc_event pm_ev; /* [enum pmc_event] desired */
405 uint32_t pm_flags; /* additional modifiers PMC_F_* */
406 enum pmc_mode pm_mode; /* desired mode */
407 pmc_id_t pm_pmcid; /* [return] process pmc id */
408
409 union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */
410};
411
412/*
413 * OP PMCADMIN
414 *
415 * Set the administrative state (i.e., whether enabled or disabled) of
416 * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an
417 * absolute PMC number and need not have been first allocated by the
418 * calling process.
419 */
420
421struct pmc_op_pmcadmin {
422 int pm_cpu; /* CPU# */
423 uint32_t pm_flags; /* flags */
424 int pm_pmc; /* PMC# */
425 enum pmc_state pm_state; /* desired state */
426};
427
428/*
429 * OP PMCATTACH / OP PMCDETACH
430 *
431 * Attach/detach a PMC and a process.
432 */
433
434struct pmc_op_pmcattach {
435 pmc_id_t pm_pmc; /* PMC to attach to */
436 pid_t pm_pid; /* target process */
437};
438
439/*
440 * OP PMCSETCOUNT
441 *
442 * Set the sampling rate (i.e., the reload count) for statistical counters.
443 * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE.
444 */
445
446struct pmc_op_pmcsetcount {
447 pmc_value_t pm_count; /* initial/sample count */
448 pmc_id_t pm_pmcid; /* PMC id to set */
449};
450
451
452/*
453 * OP PMCRW
454 *
455 * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs
456 * to have been previously allocated using PMCALLOCATE.
457 */
458
459
460struct pmc_op_pmcrw {
461 uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/
462 pmc_id_t pm_pmcid; /* pmc id */
463 pmc_value_t pm_value; /* new&returned value */
464};
465
466
467/*
468 * OP GETPMCINFO
469 *
470 * retrieve PMC state for a named CPU. The caller is expected to
471 * allocate 'npmc' * 'struct pmc_info' bytes of space for the return
472 * values.
473 */
474
475struct pmc_info {
476 char pm_name[PMC_NAME_MAX]; /* pmc name */
477 enum pmc_class pm_class; /* enum pmc_class */
478 int pm_enabled; /* whether enabled */
479 enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */
480 pid_t pm_ownerpid; /* owner, or -1 */
481 enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */
482 enum pmc_event pm_event; /* current event */
483 uint32_t pm_flags; /* current flags */
484 pmc_value_t pm_reloadcount; /* sampling counters only */
485};
486
487struct pmc_op_getpmcinfo {
488 int32_t pm_cpu; /* 0 <= cpu < mp_maxid */
489 struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */
490};
491
492
493/*
494 * OP GETCPUINFO
495 *
496 * Retrieve system CPU information.
497 */
498
499
500struct pmc_classinfo {
501 enum pmc_class pm_class; /* class id */
502 uint32_t pm_caps; /* counter capabilities */
503 uint32_t pm_width; /* width of the PMC */
504 uint32_t pm_num; /* number of PMCs in class */
505};
506
507struct pmc_op_getcpuinfo {
508 enum pmc_cputype pm_cputype; /* what kind of CPU */
509 uint32_t pm_ncpu; /* max CPU number */
510 uint32_t pm_npmc; /* #PMCs per CPU */
511 uint32_t pm_nclass; /* #classes of PMCs */
512 struct pmc_classinfo pm_classes[PMC_CLASS_MAX];
513};
514
515/*
516 * OP CONFIGURELOG
517 *
518 * Configure a log file for writing system-wide statistics to.
519 */
520
521struct pmc_op_configurelog {
522 int pm_flags;
523 int pm_logfd; /* logfile fd (or -1) */
524};
525
526/*
527 * OP GETDRIVERSTATS
528 *
529 * Retrieve pmc(4) driver-wide statistics.
530 */
531
532struct pmc_op_getdriverstats {
533 int pm_intr_ignored; /* #interrupts ignored */
534 int pm_intr_processed; /* #interrupts processed */
535 int pm_intr_bufferfull; /* #interrupts with ENOSPC */
536 int pm_syscalls; /* #syscalls */
537 int pm_syscall_errors; /* #syscalls with errors */
538 int pm_buffer_requests; /* #buffer requests */
539 int pm_buffer_requests_failed; /* #failed buffer requests */
540 int pm_log_sweeps; /* #sample buffer processing passes */
541};
542
543/*
544 * OP RELEASE / OP START / OP STOP
545 *
546 * Simple operations on a PMC id.
547 */
548
549struct pmc_op_simple {
550 pmc_id_t pm_pmcid;
551};
552
553/*
554 * OP WRITELOG
555 *
556 * Flush the current log buffer and write 4 bytes of user data to it.
557 */
558
559struct pmc_op_writelog {
560 uint32_t pm_userdata;
561};
562
563/*
564 * OP GETMSR
565 *
566 * Retrieve the machine specific address assoicated with the allocated
567 * PMC. This number can be used subsequently with a read-performance-counter
568 * instruction.
569 */
570
571struct pmc_op_getmsr {
572 uint32_t pm_msr; /* machine specific address */
573 pmc_id_t pm_pmcid; /* allocated pmc id */
574};
575
576/*
577 * OP GETDYNEVENTINFO
578 *
579 * Retrieve a PMC dynamic class events list.
580 */
581
582struct pmc_dyn_event_descr {
583 char pm_ev_name[PMC_NAME_MAX];
584 enum pmc_event pm_ev_code;
585};
586
587struct pmc_op_getdyneventinfo {
588 enum pmc_class pm_class;
589 unsigned int pm_nevent;
590 struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT];
591};
592
593#ifdef _KERNEL
594
595#include <sys/malloc.h>
596#include <sys/sysctl.h>
597
598#include <machine/frame.h>
599
600#define PMC_HASH_SIZE 16
601#define PMC_MTXPOOL_SIZE 32
602#define PMC_LOG_BUFFER_SIZE 4
603#define PMC_NLOGBUFFERS 64
604#define PMC_NSAMPLES 512
605#define PMC_CALLCHAIN_DEPTH 8
606
607#define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "."
608
609/*
610 * Locking keys
611 *
612 * (b) - pmc_bufferlist_mtx (spin lock)
613 * (k) - pmc_kthread_mtx (sleep lock)
614 * (o) - po->po_mtx (spin lock)
615 */
616
617/*
618 * PMC commands
619 */
620
621struct pmc_syscall_args {
622 register_t pmop_code; /* one of PMC_OP_* */
623 void *pmop_data; /* syscall parameter */
624};
625
626/*
627 * Interface to processor specific s1tuff
628 */
629
630/*
631 * struct pmc_descr
632 *
633 * Machine independent (i.e., the common parts) of a human readable
634 * PMC description.
635 */
636
637struct pmc_descr {
638 char pd_name[PMC_NAME_MAX]; /* name */
639 uint32_t pd_caps; /* capabilities */
640 enum pmc_class pd_class; /* class of the PMC */
641 uint32_t pd_width; /* width in bits */
642};
643
644/*
645 * struct pmc_target
646 *
647 * This structure records all the target processes associated with a
648 * PMC.
649 */
650
651struct pmc_target {
652 LIST_ENTRY(pmc_target) pt_next;
653 struct pmc_process *pt_process; /* target descriptor */
654};
655
656/*
657 * struct pmc
658 *
659 * Describes each allocated PMC.
660 *
661 * Each PMC has precisely one owner, namely the process that allocated
662 * the PMC.
663 *
664 * A PMC may be attached to multiple target processes. The
665 * 'pm_targets' field links all the target processes being monitored
666 * by this PMC.
667 *
668 * The 'pm_savedvalue' field is protected by a mutex.
669 *
670 * On a multi-cpu machine, multiple target threads associated with a
671 * process-virtual PMC could be concurrently executing on different
672 * CPUs. The 'pm_runcount' field is atomically incremented every time
673 * the PMC gets scheduled on a CPU and atomically decremented when it
674 * get descheduled. Deletion of a PMC is only permitted when this
675 * field is '0'.
676 *
677 */
678
679struct pmc {
680 LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */
681 LIST_ENTRY(pmc) pm_next; /* owner's list */
682
683 /*
684 * System-wide PMCs are allocated on a CPU and are not moved
685 * around. For system-wide PMCs we record the CPU the PMC was
686 * allocated on in the 'CPU' field of the pmc ID.
687 *
688 * Virtual PMCs run on whichever CPU is currently executing
689 * their targets' threads. For these PMCs we need to save
690 * their current PMC counter values when they are taken off
691 * CPU.
692 */
693
694 union {
695 pmc_value_t pm_savedvalue; /* Virtual PMCS */
696 } pm_gv;
697
698 /*
699 * For sampling mode PMCs, we keep track of the PMC's "reload
700 * count", which is the counter value to be loaded in when
701 * arming the PMC for the next counting session. For counting
702 * modes on PMCs that are read-only (e.g., the x86 TSC), we
703 * keep track of the initial value at the start of
704 * counting-mode operation.
705 */
706
707 union {
708 pmc_value_t pm_reloadcount; /* sampling PMC modes */
709 pmc_value_t pm_initial; /* counting PMC modes */
710 } pm_sc;
711
712 uint32_t pm_stalled; /* marks stalled sampling PMCs */
713 uint32_t pm_caps; /* PMC capabilities */
714 enum pmc_event pm_event; /* event being measured */
715 uint32_t pm_flags; /* additional flags PMC_F_... */
716 struct pmc_owner *pm_owner; /* owner thread state */
717 int pm_runcount; /* #cpus currently on */
718 enum pmc_state pm_state; /* current PMC state */
719
720 /*
721 * The PMC ID field encodes the row-index for the PMC, its
722 * mode, class and the CPU# associated with the PMC.
723 */
724
725 pmc_id_t pm_id; /* allocated PMC id */
726
727 /* md extensions */
728 union pmc_md_pmc pm_md;
729};
730
731/*
732 * Accessor macros for 'struct pmc'
733 */
734
735#define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id)
736#define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id)
737#define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id)
738#define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id)
739
740
741/*
742 * struct pmc_process
743 *
744 * Record a 'target' process being profiled.
745 *
746 * The target process being profiled could be different from the owner
747 * process which allocated the PMCs. Each target process descriptor
748 * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a
749 * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]'
750 * array. The size of this structure is thus PMC architecture
751 * dependent.
752 *
753 */
754
755struct pmc_targetstate {
756 struct pmc *pp_pmc; /* target PMC */
757 pmc_value_t pp_pmcval; /* per-process value */
758};
759
760struct pmc_process {
761 LIST_ENTRY(pmc_process) pp_next; /* hash chain */
762 int pp_refcnt; /* reference count */
763 uint32_t pp_flags; /* flags PMC_PP_* */
764 struct proc *pp_proc; /* target thread */
765 struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */
766};
767
768#define PMC_PP_ENABLE_MSR_ACCESS 0x00000001
769
770/*
771 * struct pmc_owner
772 *
773 * We associate a PMC with an 'owner' process.
774 *
775 * A process can be associated with 0..NCPUS*NHWPMC PMCs during its
776 * lifetime, where NCPUS is the numbers of CPUS in the system and
777 * NHWPMC is the number of hardware PMCs per CPU. These are
778 * maintained in the list headed by the 'po_pmcs' to save on space.
779 *
780 */
781
782struct pmc_owner {
783 LIST_ENTRY(pmc_owner) po_next; /* hash chain */
784 LIST_ENTRY(pmc_owner) po_ssnext; /* list of SS PMC owners */
785 LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */
786 TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */
787 struct mtx po_mtx; /* spin lock for (o) */
788 struct proc *po_owner; /* owner proc */
789 uint32_t po_flags; /* (k) flags PMC_PO_* */
790 struct proc *po_kthread; /* (k) helper kthread */
791 struct pmclog_buffer *po_curbuf; /* current log buffer */
792 struct file *po_file; /* file reference */
793 int po_error; /* recorded error */
794 short po_sscount; /* # SS PMCs owned */
795 short po_logprocmaps; /* global mappings done */
796};
797
798#define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */
799#define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */
800#define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020
801
802/*
803 * struct pmc_hw -- describe the state of the PMC hardware
804 *
805 * When in use, a HW PMC is associated with one allocated 'struct pmc'
806 * pointed to by field 'phw_pmc'. When inactive, this field is NULL.
807 *
808 * On an SMP box, one or more HW PMC's in process virtual mode with
809 * the same 'phw_pmc' could be executing on different CPUs. In order
810 * to handle this case correctly, we need to ensure that only
811 * incremental counts get added to the saved value in the associated
812 * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC
813 * value at the time the hardware is started during this context
814 * switch (i.e., the difference between the new (hardware) count and
815 * the saved count is atomically added to the count field in 'struct
816 * pmc' at context switch time).
817 *
818 */
819
820struct pmc_hw {
821 uint32_t phw_state; /* see PHW_* macros below */
822 struct pmc *phw_pmc; /* current thread PMC */
823};
824
825#define PMC_PHW_RI_MASK 0x000000FF
826#define PMC_PHW_CPU_SHIFT 8
827#define PMC_PHW_CPU_MASK 0x0000FF00
828#define PMC_PHW_FLAGS_SHIFT 16
829#define PMC_PHW_FLAGS_MASK 0xFFFF0000
830
831#define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK)
832#define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK)
833#define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \
834 PMC_PHW_CPU_MASK)
835#define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \
836 PMC_PHW_CPU_SHIFT)
837#define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \
838 PMC_PHW_FLAGS_MASK)
839#define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \
840 PMC_PHW_FLAGS_SHIFT)
841#define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01))
842#define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02))
843
844/*
845 * struct pmc_sample
846 *
847 * Space for N (tunable) PC samples and associated control data.
848 */
849
850struct pmc_sample {
851 uint16_t ps_nsamples; /* callchain depth */
852 uint8_t ps_cpu; /* cpu number */
853 uint8_t ps_flags; /* other flags */
854 pid_t ps_pid; /* process PID or -1 */
855 struct thread *ps_td; /* which thread */
856 struct pmc *ps_pmc; /* interrupting PMC */
857 uintptr_t *ps_pc; /* (const) callchain start */
858};
859
860#define PMC_SAMPLE_FREE ((uint16_t) 0)
861#define PMC_SAMPLE_INUSE ((uint16_t) 0xFFFF)
862
863struct pmc_samplebuffer {
864 struct pmc_sample * volatile ps_read; /* read pointer */
865 struct pmc_sample * volatile ps_write; /* write pointer */
866 uintptr_t *ps_callchains; /* all saved call chains */
867 struct pmc_sample *ps_fence; /* one beyond ps_samples[] */
868 struct pmc_sample ps_samples[]; /* array of sample entries */
869};
870
871
872/*
873 * struct pmc_cpustate
874 *
875 * A CPU is modelled as a collection of HW PMCs with space for additional
876 * flags.
877 */
878
879struct pmc_cpu {
880 uint32_t pc_state; /* physical cpu number + flags */
881 struct pmc_samplebuffer *pc_sb[2]; /* space for samples */
882 struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */
883};
884
885#define PMC_PCPU_CPU_MASK 0x000000FF
886#define PMC_PCPU_FLAGS_MASK 0xFFFFFF00
887#define PMC_PCPU_FLAGS_SHIFT 8
888#define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK)
889#define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT)
890#define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK)
891#define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK)
892#define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1))
893
894/*
895 * struct pmc_binding
896 *
897 * CPU binding information.
898 */
899
900struct pmc_binding {
901 int pb_bound; /* is bound? */
902 int pb_cpu; /* if so, to which CPU */
903};
904
905
906struct pmc_mdep;
907
908/*
909 * struct pmc_classdep
910 *
911 * PMC class-dependent operations.
912 */
913struct pmc_classdep {
914 uint32_t pcd_caps; /* class capabilities */
915 enum pmc_class pcd_class; /* class id */
916 int pcd_num; /* number of PMCs */
917 int pcd_ri; /* row index of the first PMC in class */
918 int pcd_width; /* width of the PMC */
919
920 /* configuring/reading/writing the hardware PMCs */
921 int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm);
922 int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm);
923 int (*pcd_read_pmc)(int _cpu, int _ri, pmc_value_t *_value);
924 int (*pcd_write_pmc)(int _cpu, int _ri, pmc_value_t _value);
925
926 /* pmc allocation/release */
927 int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t,
928 const struct pmc_op_pmcallocate *_a);
929 int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm);
930
931 /* starting and stopping PMCs */
932 int (*pcd_start_pmc)(int _cpu, int _ri);
933 int (*pcd_stop_pmc)(int _cpu, int _ri);
934
935 /* description */
936 int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi,
937 struct pmc **_ppmc);
938
939 /* class-dependent initialization & finalization */
940 int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu);
941 int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu);
942
943 /* machine-specific interface */
944 int (*pcd_get_msr)(int _ri, uint32_t *_msr);
945};
946
947/*
948 * struct pmc_mdep
949 *
950 * Machine dependent bits needed per CPU type.
951 */
952
953struct pmc_mdep {
954 uint32_t pmd_cputype; /* from enum pmc_cputype */
955 uint32_t pmd_npmc; /* number of PMCs per CPU */
956 uint32_t pmd_nclass; /* number of PMC classes present */
957
958 /*
959 * Machine dependent methods.
960 */
961
962 /* per-cpu initialization and finalization */
963 int (*pmd_pcpu_init)(struct pmc_mdep *_md, int _cpu);
964 int (*pmd_pcpu_fini)(struct pmc_mdep *_md, int _cpu);
965
966 /* thread context switch in/out */
967 int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp);
968 int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp);
969
970 /* handle a PMC interrupt */
971 int (*pmd_intr)(int _cpu, struct trapframe *_tf);
972
973 /*
974 * PMC class dependent information.
975 */
976 struct pmc_classdep pmd_classdep[];
977};
978
979/*
980 * Per-CPU state. This is an array of 'mp_ncpu' pointers
981 * to struct pmc_cpu descriptors.
982 */
983
984extern struct pmc_cpu **pmc_pcpu;
985
986/* driver statistics */
987extern struct pmc_op_getdriverstats pmc_stats;
988
989#if defined(DEBUG)
990
991/* debug flags, major flag groups */
992struct pmc_debugflags {
993 int pdb_CPU;
994 int pdb_CSW;
995 int pdb_LOG;
996 int pdb_MDP;
997 int pdb_MOD;
998 int pdb_OWN;
999 int pdb_PMC;
1000 int pdb_PRC;
1001 int pdb_SAM;
1002};
1003
1004extern struct pmc_debugflags pmc_debugflags;
1005
1006#define PMC_DEBUG_STRSIZE 128
1007#define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0 }
1008
1009#define PMCDBG(M,N,L,F,...) do { \
1010 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1011 printf(#M ":" #N ":" #L ": " F "\n", __VA_ARGS__); \
1012} while (0)
1013
1014/* Major numbers */
1015#define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */
1016#define PMC_DEBUG_MAJ_CSW 1 /* context switches */
1017#define PMC_DEBUG_MAJ_LOG 2 /* logging */
1018#define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */
1019#define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */
1020#define PMC_DEBUG_MAJ_OWN 5 /* owner */
1021#define PMC_DEBUG_MAJ_PMC 6 /* pmc management */
1022#define PMC_DEBUG_MAJ_PRC 7 /* processes */
1023#define PMC_DEBUG_MAJ_SAM 8 /* sampling */
1024
1025/* Minor numbers */
1026
1027/* Common (8 bits) */
1028#define PMC_DEBUG_MIN_ALL 0 /* allocation */
1029#define PMC_DEBUG_MIN_REL 1 /* release */
1030#define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */
1031#define PMC_DEBUG_MIN_INI 3 /* init */
1032#define PMC_DEBUG_MIN_FND 4 /* find */
1033
1034/* MODULE */
1035#define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */
1036#define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */
1037
1038/* OWN */
1039#define PMC_DEBUG_MIN_ORM 8 /* owner remove */
1040#define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */
1041
1042/* PROCESSES */
1043#define PMC_DEBUG_MIN_TLK 8 /* link target */
1044#define PMC_DEBUG_MIN_TUL 9 /* unlink target */
1045#define PMC_DEBUG_MIN_EXT 10 /* process exit */
1046#define PMC_DEBUG_MIN_EXC 11 /* process exec */
1047#define PMC_DEBUG_MIN_FRK 12 /* process fork */
1048#define PMC_DEBUG_MIN_ATT 13 /* attach/detach */
1049#define PMC_DEBUG_MIN_SIG 14 /* signalling */
1050
1051/* CONTEXT SWITCHES */
1052#define PMC_DEBUG_MIN_SWI 8 /* switch in */
1053#define PMC_DEBUG_MIN_SWO 9 /* switch out */
1054
1055/* PMC */
1056#define PMC_DEBUG_MIN_REG 8 /* pmc register */
1057#define PMC_DEBUG_MIN_ALR 9 /* allocate row */
1058
1059/* MACHINE DEPENDENT LAYER */
1060#define PMC_DEBUG_MIN_REA 8 /* read */
1061#define PMC_DEBUG_MIN_WRI 9 /* write */
1062#define PMC_DEBUG_MIN_CFG 10 /* config */
1063#define PMC_DEBUG_MIN_STA 11 /* start */
1064#define PMC_DEBUG_MIN_STO 12 /* stop */
1065#define PMC_DEBUG_MIN_INT 13 /* interrupts */
1066
1067/* CPU */
1068#define PMC_DEBUG_MIN_BND 8 /* bind */
1069#define PMC_DEBUG_MIN_SEL 9 /* select */
1070
1071/* LOG */
1072#define PMC_DEBUG_MIN_GTB 8 /* get buf */
1073#define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */
1074#define PMC_DEBUG_MIN_FLS 10 /* flush */
1075#define PMC_DEBUG_MIN_SAM 11 /* sample */
1076#define PMC_DEBUG_MIN_CLO 12 /* close */
1077
1078#else
1079#define PMCDBG(M,N,L,F,...) /* nothing */
1080#endif
1081
1082/* declare a dedicated memory pool */
1083MALLOC_DECLARE(M_PMC);
1084
1085/*
1086 * Functions
1087 */
1088
1089struct pmc_mdep *pmc_md_initialize(void); /* MD init function */
1090void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */
1091int pmc_getrowdisp(int _ri);
1092int pmc_process_interrupt(int _cpu, int _soft, struct pmc *_pm,
1093 struct trapframe *_tf, int _inuserspace);
1094int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples,
1095 struct trapframe *_tf);
1096int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples,
1097 struct trapframe *_tf);
1098struct pmc_mdep *pmc_mdep_alloc(int nclasses);
1099void pmc_mdep_free(struct pmc_mdep *md);
1100#endif /* _KERNEL */
1101#endif /* _SYS_PMC_H_ */
2 * Copyright (c) 2003-2008, Joseph Koshy
3 * Copyright (c) 2007 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * Portions of this software were developed by A. Joseph Koshy under
7 * sponsorship from the FreeBSD Foundation and Google, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD: head/sys/sys/pmc.h 261342 2014-02-01 02:03:50Z jhibbits $
31 */
32
33#ifndef _SYS_PMC_H_
34#define _SYS_PMC_H_
35
36#include <dev/hwpmc/pmc_events.h>
37
38#include <machine/pmc_mdep.h>
39#include <machine/profile.h>
40
41#define PMC_MODULE_NAME "hwpmc"
42#define PMC_NAME_MAX 64 /* HW counter name size */
43#define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */
44
45/*
46 * Kernel<->userland API version number [MMmmpppp]
47 *
48 * Major numbers are to be incremented when an incompatible change to
49 * the ABI occurs that older clients will not be able to handle.
50 *
51 * Minor numbers are incremented when a backwards compatible change
52 * occurs that allows older correct programs to run unchanged. For
53 * example, when support for a new PMC type is added.
54 *
55 * The patch version is incremented for every bug fix.
56 */
57#define PMC_VERSION_MAJOR 0x03
58#define PMC_VERSION_MINOR 0x01
59#define PMC_VERSION_PATCH 0x0000
60
61#define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \
62 PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH)
63
64/*
65 * Kinds of CPUs known.
66 *
67 * We keep track of CPU variants that need to be distinguished in
68 * some way for PMC operations. CPU names are grouped by manufacturer
69 * and numbered sparsely in order to minimize changes to the ABI involved
70 * when new CPUs are added.
71 */
72
73#define __PMC_CPUS() \
74 __PMC_CPU(AMD_K7, 0x00, "AMD K7") \
75 __PMC_CPU(AMD_K8, 0x01, "AMD K8") \
76 __PMC_CPU(INTEL_P5, 0x80, "Intel Pentium") \
77 __PMC_CPU(INTEL_P6, 0x81, "Intel Pentium Pro") \
78 __PMC_CPU(INTEL_CL, 0x82, "Intel Celeron") \
79 __PMC_CPU(INTEL_PII, 0x83, "Intel Pentium II") \
80 __PMC_CPU(INTEL_PIII, 0x84, "Intel Pentium III") \
81 __PMC_CPU(INTEL_PM, 0x85, "Intel Pentium M") \
82 __PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \
83 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \
84 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \
85 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \
86 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \
87 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \
88 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \
89 __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \
90 __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \
91 __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \
92 __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \
93 __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \
94 __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \
95 __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \
96 __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \
97 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \
98 __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \
99 __PMC_CPU(GENERIC, 0x400, "Generic")
100
101enum pmc_cputype {
102#undef __PMC_CPU
103#define __PMC_CPU(S,V,D) PMC_CPU_##S = V,
104 __PMC_CPUS()
105};
106
107#define PMC_CPU_FIRST PMC_CPU_AMD_K7
108#define PMC_CPU_LAST PMC_CPU_GENERIC
109
110/*
111 * Classes of PMCs
112 */
113
114#define __PMC_CLASSES() \
115 __PMC_CLASS(TSC) /* CPU Timestamp counter */ \
116 __PMC_CLASS(K7) /* AMD K7 performance counters */ \
117 __PMC_CLASS(K8) /* AMD K8 performance counters */ \
118 __PMC_CLASS(P5) /* Intel Pentium counters */ \
119 __PMC_CLASS(P6) /* Intel Pentium Pro counters */ \
120 __PMC_CLASS(P4) /* Intel Pentium-IV counters */ \
121 __PMC_CLASS(IAF) /* Intel Core2/Atom, fixed function */ \
122 __PMC_CLASS(IAP) /* Intel Core...Atom, programmable */ \
123 __PMC_CLASS(UCF) /* Intel Uncore fixed function */ \
124 __PMC_CLASS(UCP) /* Intel Uncore programmable */ \
125 __PMC_CLASS(XSCALE) /* Intel XScale counters */ \
126 __PMC_CLASS(MIPS24K) /* MIPS 24K */ \
127 __PMC_CLASS(OCTEON) /* Cavium Octeon */ \
128 __PMC_CLASS(PPC7450) /* Motorola MPC7450 class */ \
129 __PMC_CLASS(PPC970) /* IBM PowerPC 970 class */ \
130 __PMC_CLASS(SOFT) /* Software events */
131
132enum pmc_class {
133#undef __PMC_CLASS
134#define __PMC_CLASS(N) PMC_CLASS_##N ,
135 __PMC_CLASSES()
136};
137
138#define PMC_CLASS_FIRST PMC_CLASS_TSC
139#define PMC_CLASS_LAST PMC_CLASS_SOFT
140
141/*
142 * A PMC can be in the following states:
143 *
144 * Hardware states:
145 * DISABLED -- administratively prohibited from being used.
146 * FREE -- HW available for use
147 * Software states:
148 * ALLOCATED -- allocated
149 * STOPPED -- allocated, but not counting events
150 * RUNNING -- allocated, and in operation; 'pm_runcount'
151 * holds the number of CPUs using this PMC at
152 * a given instant
153 * DELETED -- being destroyed
154 */
155
156#define __PMC_HWSTATES() \
157 __PMC_STATE(DISABLED) \
158 __PMC_STATE(FREE)
159
160#define __PMC_SWSTATES() \
161 __PMC_STATE(ALLOCATED) \
162 __PMC_STATE(STOPPED) \
163 __PMC_STATE(RUNNING) \
164 __PMC_STATE(DELETED)
165
166#define __PMC_STATES() \
167 __PMC_HWSTATES() \
168 __PMC_SWSTATES()
169
170enum pmc_state {
171#undef __PMC_STATE
172#define __PMC_STATE(S) PMC_STATE_##S,
173 __PMC_STATES()
174 __PMC_STATE(MAX)
175};
176
177#define PMC_STATE_FIRST PMC_STATE_DISABLED
178#define PMC_STATE_LAST PMC_STATE_DELETED
179
180/*
181 * An allocated PMC may used as a 'global' counter or as a
182 * 'thread-private' one. Each such mode of use can be in either
183 * statistical sampling mode or in counting mode. Thus a PMC in use
184 *
185 * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling
186 * SC i.e., SYSTEM COUNTER -- system-wide counting mode
187 * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling
188 * TC i.e., THREAD COUNTER -- thread virtual, counting mode
189 *
190 * Statistical profiling modes rely on the PMC periodically delivering
191 * a interrupt to the CPU (when the configured number of events have
192 * been measured), so the PMC must have the ability to generate
193 * interrupts.
194 *
195 * In counting modes, the PMC counts its configured events, with the
196 * value of the PMC being read whenever needed by its owner process.
197 *
198 * The thread specific modes "virtualize" the PMCs -- the PMCs appear
199 * to be thread private and count events only when the profiled thread
200 * actually executes on the CPU.
201 *
202 * The system-wide "global" modes keep the PMCs running all the time
203 * and are used to measure the behaviour of the whole system.
204 */
205
206#define __PMC_MODES() \
207 __PMC_MODE(SS, 0) \
208 __PMC_MODE(SC, 1) \
209 __PMC_MODE(TS, 2) \
210 __PMC_MODE(TC, 3)
211
212enum pmc_mode {
213#undef __PMC_MODE
214#define __PMC_MODE(M,N) PMC_MODE_##M = N,
215 __PMC_MODES()
216};
217
218#define PMC_MODE_FIRST PMC_MODE_SS
219#define PMC_MODE_LAST PMC_MODE_TC
220
221#define PMC_IS_COUNTING_MODE(mode) \
222 ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC)
223#define PMC_IS_SYSTEM_MODE(mode) \
224 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC)
225#define PMC_IS_SAMPLING_MODE(mode) \
226 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS)
227#define PMC_IS_VIRTUAL_MODE(mode) \
228 ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC)
229
230/*
231 * PMC row disposition
232 */
233
234#define __PMC_DISPOSITIONS(N) \
235 __PMC_DISP(STANDALONE) /* global/disabled counters */ \
236 __PMC_DISP(FREE) /* free/available */ \
237 __PMC_DISP(THREAD) /* thread-virtual PMCs */ \
238 __PMC_DISP(UNKNOWN) /* sentinel */
239
240enum pmc_disp {
241#undef __PMC_DISP
242#define __PMC_DISP(D) PMC_DISP_##D ,
243 __PMC_DISPOSITIONS()
244};
245
246#define PMC_DISP_FIRST PMC_DISP_STANDALONE
247#define PMC_DISP_LAST PMC_DISP_THREAD
248
249/*
250 * Counter capabilities
251 *
252 * __PMC_CAPS(NAME, VALUE, DESCRIPTION)
253 */
254
255#define __PMC_CAPS() \
256 __PMC_CAP(INTERRUPT, 0, "generate interrupts") \
257 __PMC_CAP(USER, 1, "count user-mode events") \
258 __PMC_CAP(SYSTEM, 2, "count system-mode events") \
259 __PMC_CAP(EDGE, 3, "do edge detection of events") \
260 __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \
261 __PMC_CAP(READ, 5, "read PMC counter") \
262 __PMC_CAP(WRITE, 6, "reprogram PMC counter") \
263 __PMC_CAP(INVERT, 7, "invert comparision sense") \
264 __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \
265 __PMC_CAP(PRECISE, 9, "perform precise sampling") \
266 __PMC_CAP(TAGGING, 10, "tag upstream events") \
267 __PMC_CAP(CASCADE, 11, "cascade counters")
268
269enum pmc_caps
270{
271#undef __PMC_CAP
272#define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) ,
273 __PMC_CAPS()
274};
275
276#define PMC_CAP_FIRST PMC_CAP_INTERRUPT
277#define PMC_CAP_LAST PMC_CAP_CASCADE
278
279/*
280 * PMC Event Numbers
281 *
282 * These are generated from the definitions in "dev/hwpmc/pmc_events.h".
283 */
284
285enum pmc_event {
286#undef __PMC_EV
287#undef __PMC_EV_BLOCK
288#define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 ,
289#define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N ,
290 __PMC_EVENTS()
291};
292
293/*
294 * PMC SYSCALL INTERFACE
295 */
296
297/*
298 * "PMC_OPS" -- these are the commands recognized by the kernel
299 * module, and are used when performing a system call from userland.
300 */
301#define __PMC_OPS() \
302 __PMC_OP(CONFIGURELOG, "Set log file") \
303 __PMC_OP(FLUSHLOG, "Flush log file") \
304 __PMC_OP(GETCPUINFO, "Get system CPU information") \
305 __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \
306 __PMC_OP(GETMODULEVERSION, "Get module version") \
307 __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \
308 __PMC_OP(PMCADMIN, "Set PMC state") \
309 __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \
310 __PMC_OP(PMCATTACH, "Attach a PMC to a process") \
311 __PMC_OP(PMCDETACH, "Detach a PMC from a process") \
312 __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \
313 __PMC_OP(PMCRELEASE, "Release a PMC") \
314 __PMC_OP(PMCRW, "Read/Set a PMC") \
315 __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \
316 __PMC_OP(PMCSTART, "Start a PMC") \
317 __PMC_OP(PMCSTOP, "Stop a PMC") \
318 __PMC_OP(WRITELOG, "Write a cookie to the log file") \
319 __PMC_OP(CLOSELOG, "Close log file") \
320 __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list")
321
322
323enum pmc_ops {
324#undef __PMC_OP
325#define __PMC_OP(N, D) PMC_OP_##N,
326 __PMC_OPS()
327};
328
329
330/*
331 * Flags used in operations on PMCs.
332 */
333
334#define PMC_F_FORCE 0x00000001 /*OP ADMIN force operation */
335#define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */
336#define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */
337#define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */
338#define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */
339#define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */
340#define PMC_F_KGMON 0x00000040 /*OP ALLOCATE kgmon(8) profiling */
341/* V2 API */
342#define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */
343
344/* internal flags */
345#define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/
346#define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */
347#define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */
348
349#define PMC_CALLCHAIN_DEPTH_MAX 32
350
351#define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/
352
353/*
354 * Cookies used to denote allocated PMCs, and the values of PMCs.
355 */
356
357typedef uint32_t pmc_id_t;
358typedef uint64_t pmc_value_t;
359
360#define PMC_ID_INVALID (~ (pmc_id_t) 0)
361
362/*
363 * PMC IDs have the following format:
364 *
365 * +--------+----------+-----------+-----------+
366 * | CPU | PMC MODE | PMC CLASS | ROW INDEX |
367 * +--------+----------+-----------+-----------+
368 *
369 * where each field is 8 bits wide. Field 'CPU' is set to the
370 * requested CPU for system-wide PMCs or PMC_CPU_ANY for process-mode
371 * PMCs. Field 'PMC MODE' is the allocated PMC mode. Field 'PMC
372 * CLASS' is the class of the PMC. Field 'ROW INDEX' is the row index
373 * for the PMC.
374 *
375 * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total
376 * number of hardware PMCs on this cpu.
377 */
378
379
380#define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF)
381#define PMC_ID_TO_CLASS(ID) (((ID) & 0xFF00) >> 8)
382#define PMC_ID_TO_MODE(ID) (((ID) & 0xFF0000) >> 16)
383#define PMC_ID_TO_CPU(ID) (((ID) & 0xFF000000) >> 24)
384#define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \
385 ((((CPU) & 0xFF) << 24) | (((MODE) & 0xFF) << 16) | \
386 (((CLASS) & 0xFF) << 8) | ((ROWINDEX) & 0xFF))
387
388/*
389 * Data structures for system calls supported by the pmc driver.
390 */
391
392/*
393 * OP PMCALLOCATE
394 *
395 * Allocate a PMC on the named CPU.
396 */
397
398#define PMC_CPU_ANY ~0
399
400struct pmc_op_pmcallocate {
401 uint32_t pm_caps; /* PMC_CAP_* */
402 uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */
403 enum pmc_class pm_class; /* class of PMC desired */
404 enum pmc_event pm_ev; /* [enum pmc_event] desired */
405 uint32_t pm_flags; /* additional modifiers PMC_F_* */
406 enum pmc_mode pm_mode; /* desired mode */
407 pmc_id_t pm_pmcid; /* [return] process pmc id */
408
409 union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */
410};
411
412/*
413 * OP PMCADMIN
414 *
415 * Set the administrative state (i.e., whether enabled or disabled) of
416 * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an
417 * absolute PMC number and need not have been first allocated by the
418 * calling process.
419 */
420
421struct pmc_op_pmcadmin {
422 int pm_cpu; /* CPU# */
423 uint32_t pm_flags; /* flags */
424 int pm_pmc; /* PMC# */
425 enum pmc_state pm_state; /* desired state */
426};
427
428/*
429 * OP PMCATTACH / OP PMCDETACH
430 *
431 * Attach/detach a PMC and a process.
432 */
433
434struct pmc_op_pmcattach {
435 pmc_id_t pm_pmc; /* PMC to attach to */
436 pid_t pm_pid; /* target process */
437};
438
439/*
440 * OP PMCSETCOUNT
441 *
442 * Set the sampling rate (i.e., the reload count) for statistical counters.
443 * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE.
444 */
445
446struct pmc_op_pmcsetcount {
447 pmc_value_t pm_count; /* initial/sample count */
448 pmc_id_t pm_pmcid; /* PMC id to set */
449};
450
451
452/*
453 * OP PMCRW
454 *
455 * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs
456 * to have been previously allocated using PMCALLOCATE.
457 */
458
459
460struct pmc_op_pmcrw {
461 uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/
462 pmc_id_t pm_pmcid; /* pmc id */
463 pmc_value_t pm_value; /* new&returned value */
464};
465
466
467/*
468 * OP GETPMCINFO
469 *
470 * retrieve PMC state for a named CPU. The caller is expected to
471 * allocate 'npmc' * 'struct pmc_info' bytes of space for the return
472 * values.
473 */
474
475struct pmc_info {
476 char pm_name[PMC_NAME_MAX]; /* pmc name */
477 enum pmc_class pm_class; /* enum pmc_class */
478 int pm_enabled; /* whether enabled */
479 enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */
480 pid_t pm_ownerpid; /* owner, or -1 */
481 enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */
482 enum pmc_event pm_event; /* current event */
483 uint32_t pm_flags; /* current flags */
484 pmc_value_t pm_reloadcount; /* sampling counters only */
485};
486
487struct pmc_op_getpmcinfo {
488 int32_t pm_cpu; /* 0 <= cpu < mp_maxid */
489 struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */
490};
491
492
493/*
494 * OP GETCPUINFO
495 *
496 * Retrieve system CPU information.
497 */
498
499
500struct pmc_classinfo {
501 enum pmc_class pm_class; /* class id */
502 uint32_t pm_caps; /* counter capabilities */
503 uint32_t pm_width; /* width of the PMC */
504 uint32_t pm_num; /* number of PMCs in class */
505};
506
507struct pmc_op_getcpuinfo {
508 enum pmc_cputype pm_cputype; /* what kind of CPU */
509 uint32_t pm_ncpu; /* max CPU number */
510 uint32_t pm_npmc; /* #PMCs per CPU */
511 uint32_t pm_nclass; /* #classes of PMCs */
512 struct pmc_classinfo pm_classes[PMC_CLASS_MAX];
513};
514
515/*
516 * OP CONFIGURELOG
517 *
518 * Configure a log file for writing system-wide statistics to.
519 */
520
521struct pmc_op_configurelog {
522 int pm_flags;
523 int pm_logfd; /* logfile fd (or -1) */
524};
525
526/*
527 * OP GETDRIVERSTATS
528 *
529 * Retrieve pmc(4) driver-wide statistics.
530 */
531
532struct pmc_op_getdriverstats {
533 int pm_intr_ignored; /* #interrupts ignored */
534 int pm_intr_processed; /* #interrupts processed */
535 int pm_intr_bufferfull; /* #interrupts with ENOSPC */
536 int pm_syscalls; /* #syscalls */
537 int pm_syscall_errors; /* #syscalls with errors */
538 int pm_buffer_requests; /* #buffer requests */
539 int pm_buffer_requests_failed; /* #failed buffer requests */
540 int pm_log_sweeps; /* #sample buffer processing passes */
541};
542
543/*
544 * OP RELEASE / OP START / OP STOP
545 *
546 * Simple operations on a PMC id.
547 */
548
549struct pmc_op_simple {
550 pmc_id_t pm_pmcid;
551};
552
553/*
554 * OP WRITELOG
555 *
556 * Flush the current log buffer and write 4 bytes of user data to it.
557 */
558
559struct pmc_op_writelog {
560 uint32_t pm_userdata;
561};
562
563/*
564 * OP GETMSR
565 *
566 * Retrieve the machine specific address assoicated with the allocated
567 * PMC. This number can be used subsequently with a read-performance-counter
568 * instruction.
569 */
570
571struct pmc_op_getmsr {
572 uint32_t pm_msr; /* machine specific address */
573 pmc_id_t pm_pmcid; /* allocated pmc id */
574};
575
576/*
577 * OP GETDYNEVENTINFO
578 *
579 * Retrieve a PMC dynamic class events list.
580 */
581
582struct pmc_dyn_event_descr {
583 char pm_ev_name[PMC_NAME_MAX];
584 enum pmc_event pm_ev_code;
585};
586
587struct pmc_op_getdyneventinfo {
588 enum pmc_class pm_class;
589 unsigned int pm_nevent;
590 struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT];
591};
592
593#ifdef _KERNEL
594
595#include <sys/malloc.h>
596#include <sys/sysctl.h>
597
598#include <machine/frame.h>
599
600#define PMC_HASH_SIZE 16
601#define PMC_MTXPOOL_SIZE 32
602#define PMC_LOG_BUFFER_SIZE 4
603#define PMC_NLOGBUFFERS 64
604#define PMC_NSAMPLES 512
605#define PMC_CALLCHAIN_DEPTH 8
606
607#define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "."
608
609/*
610 * Locking keys
611 *
612 * (b) - pmc_bufferlist_mtx (spin lock)
613 * (k) - pmc_kthread_mtx (sleep lock)
614 * (o) - po->po_mtx (spin lock)
615 */
616
617/*
618 * PMC commands
619 */
620
621struct pmc_syscall_args {
622 register_t pmop_code; /* one of PMC_OP_* */
623 void *pmop_data; /* syscall parameter */
624};
625
626/*
627 * Interface to processor specific s1tuff
628 */
629
630/*
631 * struct pmc_descr
632 *
633 * Machine independent (i.e., the common parts) of a human readable
634 * PMC description.
635 */
636
637struct pmc_descr {
638 char pd_name[PMC_NAME_MAX]; /* name */
639 uint32_t pd_caps; /* capabilities */
640 enum pmc_class pd_class; /* class of the PMC */
641 uint32_t pd_width; /* width in bits */
642};
643
644/*
645 * struct pmc_target
646 *
647 * This structure records all the target processes associated with a
648 * PMC.
649 */
650
651struct pmc_target {
652 LIST_ENTRY(pmc_target) pt_next;
653 struct pmc_process *pt_process; /* target descriptor */
654};
655
656/*
657 * struct pmc
658 *
659 * Describes each allocated PMC.
660 *
661 * Each PMC has precisely one owner, namely the process that allocated
662 * the PMC.
663 *
664 * A PMC may be attached to multiple target processes. The
665 * 'pm_targets' field links all the target processes being monitored
666 * by this PMC.
667 *
668 * The 'pm_savedvalue' field is protected by a mutex.
669 *
670 * On a multi-cpu machine, multiple target threads associated with a
671 * process-virtual PMC could be concurrently executing on different
672 * CPUs. The 'pm_runcount' field is atomically incremented every time
673 * the PMC gets scheduled on a CPU and atomically decremented when it
674 * get descheduled. Deletion of a PMC is only permitted when this
675 * field is '0'.
676 *
677 */
678
679struct pmc {
680 LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */
681 LIST_ENTRY(pmc) pm_next; /* owner's list */
682
683 /*
684 * System-wide PMCs are allocated on a CPU and are not moved
685 * around. For system-wide PMCs we record the CPU the PMC was
686 * allocated on in the 'CPU' field of the pmc ID.
687 *
688 * Virtual PMCs run on whichever CPU is currently executing
689 * their targets' threads. For these PMCs we need to save
690 * their current PMC counter values when they are taken off
691 * CPU.
692 */
693
694 union {
695 pmc_value_t pm_savedvalue; /* Virtual PMCS */
696 } pm_gv;
697
698 /*
699 * For sampling mode PMCs, we keep track of the PMC's "reload
700 * count", which is the counter value to be loaded in when
701 * arming the PMC for the next counting session. For counting
702 * modes on PMCs that are read-only (e.g., the x86 TSC), we
703 * keep track of the initial value at the start of
704 * counting-mode operation.
705 */
706
707 union {
708 pmc_value_t pm_reloadcount; /* sampling PMC modes */
709 pmc_value_t pm_initial; /* counting PMC modes */
710 } pm_sc;
711
712 uint32_t pm_stalled; /* marks stalled sampling PMCs */
713 uint32_t pm_caps; /* PMC capabilities */
714 enum pmc_event pm_event; /* event being measured */
715 uint32_t pm_flags; /* additional flags PMC_F_... */
716 struct pmc_owner *pm_owner; /* owner thread state */
717 int pm_runcount; /* #cpus currently on */
718 enum pmc_state pm_state; /* current PMC state */
719
720 /*
721 * The PMC ID field encodes the row-index for the PMC, its
722 * mode, class and the CPU# associated with the PMC.
723 */
724
725 pmc_id_t pm_id; /* allocated PMC id */
726
727 /* md extensions */
728 union pmc_md_pmc pm_md;
729};
730
731/*
732 * Accessor macros for 'struct pmc'
733 */
734
735#define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id)
736#define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id)
737#define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id)
738#define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id)
739
740
741/*
742 * struct pmc_process
743 *
744 * Record a 'target' process being profiled.
745 *
746 * The target process being profiled could be different from the owner
747 * process which allocated the PMCs. Each target process descriptor
748 * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a
749 * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]'
750 * array. The size of this structure is thus PMC architecture
751 * dependent.
752 *
753 */
754
755struct pmc_targetstate {
756 struct pmc *pp_pmc; /* target PMC */
757 pmc_value_t pp_pmcval; /* per-process value */
758};
759
760struct pmc_process {
761 LIST_ENTRY(pmc_process) pp_next; /* hash chain */
762 int pp_refcnt; /* reference count */
763 uint32_t pp_flags; /* flags PMC_PP_* */
764 struct proc *pp_proc; /* target thread */
765 struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */
766};
767
768#define PMC_PP_ENABLE_MSR_ACCESS 0x00000001
769
770/*
771 * struct pmc_owner
772 *
773 * We associate a PMC with an 'owner' process.
774 *
775 * A process can be associated with 0..NCPUS*NHWPMC PMCs during its
776 * lifetime, where NCPUS is the numbers of CPUS in the system and
777 * NHWPMC is the number of hardware PMCs per CPU. These are
778 * maintained in the list headed by the 'po_pmcs' to save on space.
779 *
780 */
781
782struct pmc_owner {
783 LIST_ENTRY(pmc_owner) po_next; /* hash chain */
784 LIST_ENTRY(pmc_owner) po_ssnext; /* list of SS PMC owners */
785 LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */
786 TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */
787 struct mtx po_mtx; /* spin lock for (o) */
788 struct proc *po_owner; /* owner proc */
789 uint32_t po_flags; /* (k) flags PMC_PO_* */
790 struct proc *po_kthread; /* (k) helper kthread */
791 struct pmclog_buffer *po_curbuf; /* current log buffer */
792 struct file *po_file; /* file reference */
793 int po_error; /* recorded error */
794 short po_sscount; /* # SS PMCs owned */
795 short po_logprocmaps; /* global mappings done */
796};
797
798#define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */
799#define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */
800#define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020
801
802/*
803 * struct pmc_hw -- describe the state of the PMC hardware
804 *
805 * When in use, a HW PMC is associated with one allocated 'struct pmc'
806 * pointed to by field 'phw_pmc'. When inactive, this field is NULL.
807 *
808 * On an SMP box, one or more HW PMC's in process virtual mode with
809 * the same 'phw_pmc' could be executing on different CPUs. In order
810 * to handle this case correctly, we need to ensure that only
811 * incremental counts get added to the saved value in the associated
812 * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC
813 * value at the time the hardware is started during this context
814 * switch (i.e., the difference between the new (hardware) count and
815 * the saved count is atomically added to the count field in 'struct
816 * pmc' at context switch time).
817 *
818 */
819
820struct pmc_hw {
821 uint32_t phw_state; /* see PHW_* macros below */
822 struct pmc *phw_pmc; /* current thread PMC */
823};
824
825#define PMC_PHW_RI_MASK 0x000000FF
826#define PMC_PHW_CPU_SHIFT 8
827#define PMC_PHW_CPU_MASK 0x0000FF00
828#define PMC_PHW_FLAGS_SHIFT 16
829#define PMC_PHW_FLAGS_MASK 0xFFFF0000
830
831#define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK)
832#define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK)
833#define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \
834 PMC_PHW_CPU_MASK)
835#define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \
836 PMC_PHW_CPU_SHIFT)
837#define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \
838 PMC_PHW_FLAGS_MASK)
839#define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \
840 PMC_PHW_FLAGS_SHIFT)
841#define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01))
842#define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02))
843
844/*
845 * struct pmc_sample
846 *
847 * Space for N (tunable) PC samples and associated control data.
848 */
849
850struct pmc_sample {
851 uint16_t ps_nsamples; /* callchain depth */
852 uint8_t ps_cpu; /* cpu number */
853 uint8_t ps_flags; /* other flags */
854 pid_t ps_pid; /* process PID or -1 */
855 struct thread *ps_td; /* which thread */
856 struct pmc *ps_pmc; /* interrupting PMC */
857 uintptr_t *ps_pc; /* (const) callchain start */
858};
859
860#define PMC_SAMPLE_FREE ((uint16_t) 0)
861#define PMC_SAMPLE_INUSE ((uint16_t) 0xFFFF)
862
863struct pmc_samplebuffer {
864 struct pmc_sample * volatile ps_read; /* read pointer */
865 struct pmc_sample * volatile ps_write; /* write pointer */
866 uintptr_t *ps_callchains; /* all saved call chains */
867 struct pmc_sample *ps_fence; /* one beyond ps_samples[] */
868 struct pmc_sample ps_samples[]; /* array of sample entries */
869};
870
871
872/*
873 * struct pmc_cpustate
874 *
875 * A CPU is modelled as a collection of HW PMCs with space for additional
876 * flags.
877 */
878
879struct pmc_cpu {
880 uint32_t pc_state; /* physical cpu number + flags */
881 struct pmc_samplebuffer *pc_sb[2]; /* space for samples */
882 struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */
883};
884
885#define PMC_PCPU_CPU_MASK 0x000000FF
886#define PMC_PCPU_FLAGS_MASK 0xFFFFFF00
887#define PMC_PCPU_FLAGS_SHIFT 8
888#define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK)
889#define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT)
890#define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK)
891#define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK)
892#define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1))
893
894/*
895 * struct pmc_binding
896 *
897 * CPU binding information.
898 */
899
900struct pmc_binding {
901 int pb_bound; /* is bound? */
902 int pb_cpu; /* if so, to which CPU */
903};
904
905
906struct pmc_mdep;
907
908/*
909 * struct pmc_classdep
910 *
911 * PMC class-dependent operations.
912 */
913struct pmc_classdep {
914 uint32_t pcd_caps; /* class capabilities */
915 enum pmc_class pcd_class; /* class id */
916 int pcd_num; /* number of PMCs */
917 int pcd_ri; /* row index of the first PMC in class */
918 int pcd_width; /* width of the PMC */
919
920 /* configuring/reading/writing the hardware PMCs */
921 int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm);
922 int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm);
923 int (*pcd_read_pmc)(int _cpu, int _ri, pmc_value_t *_value);
924 int (*pcd_write_pmc)(int _cpu, int _ri, pmc_value_t _value);
925
926 /* pmc allocation/release */
927 int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t,
928 const struct pmc_op_pmcallocate *_a);
929 int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm);
930
931 /* starting and stopping PMCs */
932 int (*pcd_start_pmc)(int _cpu, int _ri);
933 int (*pcd_stop_pmc)(int _cpu, int _ri);
934
935 /* description */
936 int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi,
937 struct pmc **_ppmc);
938
939 /* class-dependent initialization & finalization */
940 int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu);
941 int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu);
942
943 /* machine-specific interface */
944 int (*pcd_get_msr)(int _ri, uint32_t *_msr);
945};
946
947/*
948 * struct pmc_mdep
949 *
950 * Machine dependent bits needed per CPU type.
951 */
952
953struct pmc_mdep {
954 uint32_t pmd_cputype; /* from enum pmc_cputype */
955 uint32_t pmd_npmc; /* number of PMCs per CPU */
956 uint32_t pmd_nclass; /* number of PMC classes present */
957
958 /*
959 * Machine dependent methods.
960 */
961
962 /* per-cpu initialization and finalization */
963 int (*pmd_pcpu_init)(struct pmc_mdep *_md, int _cpu);
964 int (*pmd_pcpu_fini)(struct pmc_mdep *_md, int _cpu);
965
966 /* thread context switch in/out */
967 int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp);
968 int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp);
969
970 /* handle a PMC interrupt */
971 int (*pmd_intr)(int _cpu, struct trapframe *_tf);
972
973 /*
974 * PMC class dependent information.
975 */
976 struct pmc_classdep pmd_classdep[];
977};
978
979/*
980 * Per-CPU state. This is an array of 'mp_ncpu' pointers
981 * to struct pmc_cpu descriptors.
982 */
983
984extern struct pmc_cpu **pmc_pcpu;
985
986/* driver statistics */
987extern struct pmc_op_getdriverstats pmc_stats;
988
989#if defined(DEBUG)
990
991/* debug flags, major flag groups */
992struct pmc_debugflags {
993 int pdb_CPU;
994 int pdb_CSW;
995 int pdb_LOG;
996 int pdb_MDP;
997 int pdb_MOD;
998 int pdb_OWN;
999 int pdb_PMC;
1000 int pdb_PRC;
1001 int pdb_SAM;
1002};
1003
1004extern struct pmc_debugflags pmc_debugflags;
1005
1006#define PMC_DEBUG_STRSIZE 128
1007#define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0 }
1008
1009#define PMCDBG(M,N,L,F,...) do { \
1010 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1011 printf(#M ":" #N ":" #L ": " F "\n", __VA_ARGS__); \
1012} while (0)
1013
1014/* Major numbers */
1015#define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */
1016#define PMC_DEBUG_MAJ_CSW 1 /* context switches */
1017#define PMC_DEBUG_MAJ_LOG 2 /* logging */
1018#define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */
1019#define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */
1020#define PMC_DEBUG_MAJ_OWN 5 /* owner */
1021#define PMC_DEBUG_MAJ_PMC 6 /* pmc management */
1022#define PMC_DEBUG_MAJ_PRC 7 /* processes */
1023#define PMC_DEBUG_MAJ_SAM 8 /* sampling */
1024
1025/* Minor numbers */
1026
1027/* Common (8 bits) */
1028#define PMC_DEBUG_MIN_ALL 0 /* allocation */
1029#define PMC_DEBUG_MIN_REL 1 /* release */
1030#define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */
1031#define PMC_DEBUG_MIN_INI 3 /* init */
1032#define PMC_DEBUG_MIN_FND 4 /* find */
1033
1034/* MODULE */
1035#define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */
1036#define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */
1037
1038/* OWN */
1039#define PMC_DEBUG_MIN_ORM 8 /* owner remove */
1040#define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */
1041
1042/* PROCESSES */
1043#define PMC_DEBUG_MIN_TLK 8 /* link target */
1044#define PMC_DEBUG_MIN_TUL 9 /* unlink target */
1045#define PMC_DEBUG_MIN_EXT 10 /* process exit */
1046#define PMC_DEBUG_MIN_EXC 11 /* process exec */
1047#define PMC_DEBUG_MIN_FRK 12 /* process fork */
1048#define PMC_DEBUG_MIN_ATT 13 /* attach/detach */
1049#define PMC_DEBUG_MIN_SIG 14 /* signalling */
1050
1051/* CONTEXT SWITCHES */
1052#define PMC_DEBUG_MIN_SWI 8 /* switch in */
1053#define PMC_DEBUG_MIN_SWO 9 /* switch out */
1054
1055/* PMC */
1056#define PMC_DEBUG_MIN_REG 8 /* pmc register */
1057#define PMC_DEBUG_MIN_ALR 9 /* allocate row */
1058
1059/* MACHINE DEPENDENT LAYER */
1060#define PMC_DEBUG_MIN_REA 8 /* read */
1061#define PMC_DEBUG_MIN_WRI 9 /* write */
1062#define PMC_DEBUG_MIN_CFG 10 /* config */
1063#define PMC_DEBUG_MIN_STA 11 /* start */
1064#define PMC_DEBUG_MIN_STO 12 /* stop */
1065#define PMC_DEBUG_MIN_INT 13 /* interrupts */
1066
1067/* CPU */
1068#define PMC_DEBUG_MIN_BND 8 /* bind */
1069#define PMC_DEBUG_MIN_SEL 9 /* select */
1070
1071/* LOG */
1072#define PMC_DEBUG_MIN_GTB 8 /* get buf */
1073#define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */
1074#define PMC_DEBUG_MIN_FLS 10 /* flush */
1075#define PMC_DEBUG_MIN_SAM 11 /* sample */
1076#define PMC_DEBUG_MIN_CLO 12 /* close */
1077
1078#else
1079#define PMCDBG(M,N,L,F,...) /* nothing */
1080#endif
1081
1082/* declare a dedicated memory pool */
1083MALLOC_DECLARE(M_PMC);
1084
1085/*
1086 * Functions
1087 */
1088
1089struct pmc_mdep *pmc_md_initialize(void); /* MD init function */
1090void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */
1091int pmc_getrowdisp(int _ri);
1092int pmc_process_interrupt(int _cpu, int _soft, struct pmc *_pm,
1093 struct trapframe *_tf, int _inuserspace);
1094int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples,
1095 struct trapframe *_tf);
1096int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples,
1097 struct trapframe *_tf);
1098struct pmc_mdep *pmc_mdep_alloc(int nclasses);
1099void pmc_mdep_free(struct pmc_mdep *md);
1100#endif /* _KERNEL */
1101#endif /* _SYS_PMC_H_ */