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pmap.c (99999) pmap.c (100718)
1/*
2 * Copyright (c) 1991 Regents of the University of California.
3 * All rights reserved.
4 * Copyright (c) 1994 John S. Dyson
5 * All rights reserved.
6 * Copyright (c) 1994 David Greenman
7 * All rights reserved.
8 *

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34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * SUCH DAMAGE.
40 *
41 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
1/*
2 * Copyright (c) 1991 Regents of the University of California.
3 * All rights reserved.
4 * Copyright (c) 1994 John S. Dyson
5 * All rights reserved.
6 * Copyright (c) 1994 David Greenman
7 * All rights reserved.
8 *

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34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * SUCH DAMAGE.
40 *
41 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
42 * $FreeBSD: head/sys/sparc64/sparc64/pmap.c 99999 2002-07-14 23:23:47Z alc $
42 * $FreeBSD: head/sys/sparc64/sparc64/pmap.c 100718 2002-07-26 15:54:04Z jake $
43 */
44
45/*
46 * Manages physical address maps.
47 *
48 * In addition to hardware address maps, this module is called upon to
49 * provide software-use-only maps which may or may not be stored in the
50 * same form as hardware maps. These pseudo-maps are used to store

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597 PMAP_STATS_INC(pmap_ncache_enter_nc);
598 if ((m->md.flags & PG_UNCACHEABLE) != 0) {
599 CTR0(KTR_PMAP, "pmap_cache_enter: already uncacheable");
600 return (0);
601 }
602 CTR0(KTR_PMAP, "pmap_cache_enter: marking uncacheable");
603 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
604 tp->tte_data &= ~TD_CV;
43 */
44
45/*
46 * Manages physical address maps.
47 *
48 * In addition to hardware address maps, this module is called upon to
49 * provide software-use-only maps which may or may not be stored in the
50 * same form as hardware maps. These pseudo-maps are used to store

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597 PMAP_STATS_INC(pmap_ncache_enter_nc);
598 if ((m->md.flags & PG_UNCACHEABLE) != 0) {
599 CTR0(KTR_PMAP, "pmap_cache_enter: already uncacheable");
600 return (0);
601 }
602 CTR0(KTR_PMAP, "pmap_cache_enter: marking uncacheable");
603 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
604 tp->tte_data &= ~TD_CV;
605 tlb_page_demap(TLB_DTLB | TLB_ITLB, TTE_GET_PMAP(tp),
606 TTE_GET_VA(tp));
605 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
607 }
608 dcache_page_inval(VM_PAGE_TO_PHYS(m));
609 m->md.flags |= PG_UNCACHEABLE;
610 return (0);
611}
612
613void
614pmap_cache_remove(vm_page_t m, vm_offset_t va)

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625 for (i = 0, c = 0; i < DCACHE_COLORS; i++) {
626 if (m->md.colors[i] != 0)
627 c++;
628 }
629 if (c > 1 || (m->md.flags & PG_UNCACHEABLE) == 0)
630 return;
631 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
632 tp->tte_data |= TD_CV;
606 }
607 dcache_page_inval(VM_PAGE_TO_PHYS(m));
608 m->md.flags |= PG_UNCACHEABLE;
609 return (0);
610}
611
612void
613pmap_cache_remove(vm_page_t m, vm_offset_t va)

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624 for (i = 0, c = 0; i < DCACHE_COLORS; i++) {
625 if (m->md.colors[i] != 0)
626 c++;
627 }
628 if (c > 1 || (m->md.flags & PG_UNCACHEABLE) == 0)
629 return;
630 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
631 tp->tte_data |= TD_CV;
633 tlb_page_demap(TLB_DTLB | TLB_ITLB, TTE_GET_PMAP(tp),
634 TTE_GET_VA(tp));
632 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
635 }
636 m->md.flags &= ~PG_UNCACHEABLE;
637}
638
639/*
640 * Map a wired page into kernel virtual address space.
641 */
642void

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653 CTR4(KTR_PMAP, "pmap_kenter: va=%#lx pa=%#lx tp=%p data=%#lx",
654 va, pa, tp, tp->tte_data);
655 if ((tp->tte_data & TD_V) != 0) {
656 om = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
657 ova = TTE_GET_VA(tp);
658 STAILQ_REMOVE(&om->md.tte_list, tp, tte, tte_link);
659 pmap_cache_remove(om, ova);
660 if (va != ova)
633 }
634 m->md.flags &= ~PG_UNCACHEABLE;
635}
636
637/*
638 * Map a wired page into kernel virtual address space.
639 */
640void

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651 CTR4(KTR_PMAP, "pmap_kenter: va=%#lx pa=%#lx tp=%p data=%#lx",
652 va, pa, tp, tp->tte_data);
653 if ((tp->tte_data & TD_V) != 0) {
654 om = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
655 ova = TTE_GET_VA(tp);
656 STAILQ_REMOVE(&om->md.tte_list, tp, tte, tte_link);
657 pmap_cache_remove(om, ova);
658 if (va != ova)
661 tlb_page_demap(TLB_DTLB, kernel_pmap, ova);
659 tlb_page_demap(kernel_pmap, ova);
662 }
663 data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW | TD_CP | TD_P | TD_W;
664 if (pmap_cache_enter(m, va) != 0)
665 data |= TD_CV;
666 tp->tte_vpn = TV_VPN(va);
667 tp->tte_data = data;
668 STAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
669 tp->tte_pmap = kernel_pmap;

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834 /*
835 * Get a kernel virtual address for the kstack for this thread.
836 */
837 ks = kmem_alloc_nofault(kernel_map,
838 (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE);
839 if (ks == 0)
840 panic("pmap_new_thread: kstack allocation failed");
841 if (KSTACK_GUARD_PAGES != 0) {
660 }
661 data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW | TD_CP | TD_P | TD_W;
662 if (pmap_cache_enter(m, va) != 0)
663 data |= TD_CV;
664 tp->tte_vpn = TV_VPN(va);
665 tp->tte_data = data;
666 STAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
667 tp->tte_pmap = kernel_pmap;

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832 /*
833 * Get a kernel virtual address for the kstack for this thread.
834 */
835 ks = kmem_alloc_nofault(kernel_map,
836 (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE);
837 if (ks == 0)
838 panic("pmap_new_thread: kstack allocation failed");
839 if (KSTACK_GUARD_PAGES != 0) {
842 tlb_page_demap(TLB_DTLB, kernel_pmap, ks);
840 tlb_page_demap(kernel_pmap, ks);
843 ks += KSTACK_GUARD_PAGES * PAGE_SIZE;
844 }
845 td->td_kstack = ks;
846
847 for (i = 0; i < KSTACK_PAGES; i++) {
848 /*
849 * Get a kernel stack page.
850 */

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1150 if ((tp->tte_data & TD_WIRED) != 0)
1151 pm->pm_stats.wired_count--;
1152 if ((tp->tte_data & TD_REF) != 0)
1153 vm_page_flag_set(m, PG_REFERENCED);
1154 if ((tp->tte_data & TD_W) != 0 &&
1155 pmap_track_modified(pm, va))
1156 vm_page_dirty(m);
1157 tp->tte_data &= ~TD_V;
841 ks += KSTACK_GUARD_PAGES * PAGE_SIZE;
842 }
843 td->td_kstack = ks;
844
845 for (i = 0; i < KSTACK_PAGES; i++) {
846 /*
847 * Get a kernel stack page.
848 */

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1148 if ((tp->tte_data & TD_WIRED) != 0)
1149 pm->pm_stats.wired_count--;
1150 if ((tp->tte_data & TD_REF) != 0)
1151 vm_page_flag_set(m, PG_REFERENCED);
1152 if ((tp->tte_data & TD_W) != 0 &&
1153 pmap_track_modified(pm, va))
1154 vm_page_dirty(m);
1155 tp->tte_data &= ~TD_V;
1158 tlb_page_demap(TLB_DTLB | TLB_ITLB, pm, va);
1156 tlb_page_demap(pm, va);
1159 STAILQ_REMOVE(&m->md.tte_list, tp, tte, tte_link);
1160 pm->pm_stats.resident_count--;
1161 pmap_cache_remove(m, va);
1162 TTE_ZERO(tp);
1163 }
1164 vm_page_flag_clear(m, PG_MAPPED | PG_WRITEABLE);
1165}
1166

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1286 icache_page_inval(pa);
1287 }
1288 tp->tte_data |= TD_EXEC;
1289 }
1290
1291 /*
1292 * Delete the old mapping.
1293 */
1157 STAILQ_REMOVE(&m->md.tte_list, tp, tte, tte_link);
1158 pm->pm_stats.resident_count--;
1159 pmap_cache_remove(m, va);
1160 TTE_ZERO(tp);
1161 }
1162 vm_page_flag_clear(m, PG_MAPPED | PG_WRITEABLE);
1163}
1164

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1284 icache_page_inval(pa);
1285 }
1286 tp->tte_data |= TD_EXEC;
1287 }
1288
1289 /*
1290 * Delete the old mapping.
1291 */
1294 tlb_tte_demap(tp, pm);
1292 tlb_page_demap(pm, TTE_GET_VA(tp));
1295 } else {
1296 /*
1297 * If there is an existing mapping, but its for a different
1298 * phsyical address, delete the old mapping.
1299 */
1300 if (tp != NULL) {
1301 CTR0(KTR_PMAP, "pmap_enter: replace");
1302 PMAP_STATS_INC(pmap_enter_nreplace);
1303 pmap_remove_tte(pm, NULL, tp, va);
1293 } else {
1294 /*
1295 * If there is an existing mapping, but its for a different
1296 * phsyical address, delete the old mapping.
1297 */
1298 if (tp != NULL) {
1299 CTR0(KTR_PMAP, "pmap_enter: replace");
1300 PMAP_STATS_INC(pmap_enter_nreplace);
1301 pmap_remove_tte(pm, NULL, tp, va);
1304 tlb_page_demap(TLB_DTLB | TLB_ITLB, pm, va);
1302 tlb_page_demap(pm, va);
1305 } else {
1306 CTR0(KTR_PMAP, "pmap_enter: new");
1307 PMAP_STATS_INC(pmap_enter_nnew);
1308 }
1309
1310 /*
1311 * Now set up the data and install the new mapping.
1312 */

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1603
1604 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1605 return;
1606 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1607 if ((tp->tte_data & TD_PV) == 0)
1608 continue;
1609 if ((tp->tte_data & TD_W) != 0) {
1610 tp->tte_data &= ~TD_W;
1303 } else {
1304 CTR0(KTR_PMAP, "pmap_enter: new");
1305 PMAP_STATS_INC(pmap_enter_nnew);
1306 }
1307
1308 /*
1309 * Now set up the data and install the new mapping.
1310 */

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1601
1602 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1603 return;
1604 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1605 if ((tp->tte_data & TD_PV) == 0)
1606 continue;
1607 if ((tp->tte_data & TD_W) != 0) {
1608 tp->tte_data &= ~TD_W;
1611 tlb_tte_demap(tp, TTE_GET_PMAP(tp));
1609 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1612 }
1613 }
1614}
1615
1616void
1617pmap_clear_reference(vm_page_t m)
1618{
1619 struct tte *tp;
1620
1621 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1622 return;
1623 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1624 if ((tp->tte_data & TD_PV) == 0)
1625 continue;
1626 if ((tp->tte_data & TD_REF) != 0) {
1627 tp->tte_data &= ~TD_REF;
1610 }
1611 }
1612}
1613
1614void
1615pmap_clear_reference(vm_page_t m)
1616{
1617 struct tte *tp;
1618
1619 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1620 return;
1621 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1622 if ((tp->tte_data & TD_PV) == 0)
1623 continue;
1624 if ((tp->tte_data & TD_REF) != 0) {
1625 tp->tte_data &= ~TD_REF;
1628 tlb_tte_demap(tp, TTE_GET_PMAP(tp));
1626 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1629 }
1630 }
1631}
1632
1633void
1634pmap_clear_write(vm_page_t m)
1635{
1636 struct tte *tp;

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1641 if ((tp->tte_data & TD_PV) == 0)
1642 continue;
1643 if ((tp->tte_data & (TD_SW | TD_W)) != 0) {
1644 if ((tp->tte_data & TD_W) != 0 &&
1645 pmap_track_modified(TTE_GET_PMAP(tp),
1646 TTE_GET_VA(tp)))
1647 vm_page_dirty(m);
1648 tp->tte_data &= ~(TD_SW | TD_W);
1627 }
1628 }
1629}
1630
1631void
1632pmap_clear_write(vm_page_t m)
1633{
1634 struct tte *tp;

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1639 if ((tp->tte_data & TD_PV) == 0)
1640 continue;
1641 if ((tp->tte_data & (TD_SW | TD_W)) != 0) {
1642 if ((tp->tte_data & TD_W) != 0 &&
1643 pmap_track_modified(TTE_GET_PMAP(tp),
1644 TTE_GET_VA(tp)))
1645 vm_page_dirty(m);
1646 tp->tte_data &= ~(TD_SW | TD_W);
1649 tlb_tte_demap(tp, TTE_GET_PMAP(tp));
1647 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1650 }
1651 }
1652}
1653
1654int
1655pmap_mincore(pmap_t pm, vm_offset_t addr)
1656{
1657 TODO;

--- 46 unchanged lines hidden --- 		1648 }
1649 }
1650}
1651
1652int
1653pmap_mincore(pmap_t pm, vm_offset_t addr)
1654{
1655 TODO;

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