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mpc85xx.c (186227) mpc85xx.c (186288)
1/*-
2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
1/*-
2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <sys/cdefs.h>
13 *
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/powerpc/mpc85xx/mpc85xx.c 186227 2008-12-17 15:27:49Z raj $");
28__FBSDID("$FreeBSD: head/sys/powerpc/mpc85xx/mpc85xx.c 186288 2008-12-18 18:27:12Z raj $");
32
33#include <sys/param.h>
34#include <sys/systm.h>
35
36#include <vm/vm.h>
37#include <vm/vm_param.h>
38
39#include <machine/cpu.h>

--- 19 unchanged lines hidden (view full) ---

59ccsr_write4(uintptr_t addr, uint32_t val)
60{
61 volatile uint32_t *ptr = (void *)addr;
62
63 *ptr = val;
64 __asm __volatile("eieio; sync");
65}
66
29
30#include <sys/param.h>
31#include <sys/systm.h>
32
33#include <vm/vm.h>
34#include <vm/vm_param.h>
35
36#include <machine/cpu.h>

--- 19 unchanged lines hidden (view full) ---

56ccsr_write4(uintptr_t addr, uint32_t val)
57{
58 volatile uint32_t *ptr = (void *)addr;
59
60 *ptr = val;
61 __asm __volatile("eieio; sync");
62}
63
64static __inline int
65law_getmax(void)
66{
67 uint32_t ver;
68
69 ver = SVR_VER(mfspr(SPR_SVR));
70 if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
71 return (12);
72 else
73 return (8);
74}
75
76#define _LAW_SR(trgt,size) (0x80000000 | (trgt << 20) | (ffsl(size) - 2))
77#define _LAW_BAR(addr) (addr >> 12)
78
79int
80law_enable(int trgt, u_long addr, u_long size)
81{
82 uint32_t bar, sr;
83 int i, law_max;
84
85 law_max = law_getmax();
86 bar = _LAW_BAR(addr);
87 sr = _LAW_SR(trgt, size);
88
89 /* Bail if already programmed. */
90 for (i = 0; i < law_max; i++)
91 if (sr == ccsr_read4(OCP85XX_LAWSR(i)) &&
92 bar == ccsr_read4(OCP85XX_LAWBAR(i)))
93 return (0);
94
95 /* Find an unused access window. */
96 for (i = 0; i < law_max; i++)
97 if ((ccsr_read4(OCP85XX_LAWSR(i)) & 0x80000000) == 0)
98 break;
99
100 if (i == law_max)
101 return (ENOSPC);
102
103 ccsr_write4(OCP85XX_LAWBAR(i), bar);
104 ccsr_write4(OCP85XX_LAWSR(i), sr);
105 return (0);
106}
107
108int
109law_disable(int trgt, u_long addr, u_long size)
110{
111 uint32_t bar, sr;
112 int i, law_max;
113
114 law_max = law_getmax();
115 bar = _LAW_BAR(addr);
116 sr = _LAW_SR(trgt, size);
117
118 /* Find and disable requested LAW. */
119 for (i = 0; i < law_max; i++)
120 if (sr == ccsr_read4(OCP85XX_LAWSR(i)) &&
121 bar == ccsr_read4(OCP85XX_LAWBAR(i))) {
122 ccsr_write4(OCP85XX_LAWBAR(i), 0);
123 ccsr_write4(OCP85XX_LAWSR(i), 0);
124 return (0);
125 }
126
127 return (ENOENT);
128}
129
67void
68cpu_reset(void)
69{
70 uint32_t ver = SVR_VER(mfspr(SPR_SVR));
71
72 if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
73 /* Systems with dedicated reset register */
74 ccsr_write4(OCP85XX_RSTCR, 2);

--- 16 unchanged lines hidden --- 		130void
131cpu_reset(void)
132{
133 uint32_t ver = SVR_VER(mfspr(SPR_SVR));
134
135 if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
136 /* Systems with dedicated reset register */
137 ccsr_write4(OCP85XX_RSTCR, 2);

--- 16 unchanged lines hidden ---