| spr.h (194374) | spr.h (194678) |
|---|---|
| 1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ | 1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ |
| 34 * $FreeBSD: head/sys/powerpc/include/spr.h 194374 2009-06-17 16:34:40Z nwhitehorn $ | 34 * $FreeBSD: head/sys/powerpc/include/spr.h 194678 2009-06-23 04:02:36Z nwhitehorn $ |
| 35 */ 36#ifndef _POWERPC_SPR_H_ 37#define _POWERPC_SPR_H_ 38 39#ifndef _LOCORE 40#define mtspr(reg, val) \ 41 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 42#define mfspr(reg) \ --- 288 unchanged lines hidden (view full) --- 331#define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */ 332#define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */ 333#define SPR_MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */ 334#define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */ 335#define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */ 336#define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */ 337#define SPR_MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector */ 338#define SPR_MMCR0_PMC2SEL(x) ((x) << 0) /* PMC2 selector */ | 35 */ 36#ifndef _POWERPC_SPR_H_ 37#define _POWERPC_SPR_H_ 38 39#ifndef _LOCORE 40#define mtspr(reg, val) \ 41 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 42#define mfspr(reg) \ --- 288 unchanged lines hidden (view full) --- 331#define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */ 332#define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */ 333#define SPR_MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */ 334#define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */ 335#define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */ 336#define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */ 337#define SPR_MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector */ 338#define SPR_MMCR0_PMC2SEL(x) ((x) << 0) /* PMC2 selector */ |
| 339#define SPR_970MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector (970) */ | 339#define SPR_970MMCR0_PMC1SEL(x) ((x) << 8) /* PMC1 selector (970) */ |
| 340#define SPR_970MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */ 341#define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */ 342#define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */ 343#define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */ 344#define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */ 345#define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */ 346#define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */ 347#define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */ --- 351 unchanged lines hidden --- | 340#define SPR_970MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */ 341#define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */ 342#define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */ 343#define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */ 344#define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */ 345#define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */ 346#define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */ 347#define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */ --- 351 unchanged lines hidden --- |