| spr.h (190953) | spr.h (192067) |
|---|---|
| 1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ | 1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ |
| 34 * $FreeBSD: head/sys/powerpc/include/spr.h 190953 2009-04-12 03:03:55Z nwhitehorn $ | 34 * $FreeBSD: head/sys/powerpc/include/spr.h 192067 2009-05-14 00:34:26Z nwhitehorn $ |
| 35 */ 36#ifndef _POWERPC_SPR_H_ 37#define _POWERPC_SPR_H_ 38 39#ifndef _LOCORE 40#define mtspr(reg, val) \ 41 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 42#define mfspr(reg) \ --- 371 unchanged lines hidden (view full) --- 414#define SPR_DBCR0 0x3f2 /* 4.. Debug Control Register 0 */ 415#define SPR_DBCR1 0x3bd /* 4.. Debug Control Register 1 */ 416#define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */ 417#define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */ 418#define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */ 419#define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */ 420#define SPR_PIR 0x3ff /* .6. Processor Identification Register */ 421#elif defined(E500) | 35 */ 36#ifndef _POWERPC_SPR_H_ 37#define _POWERPC_SPR_H_ 38 39#ifndef _LOCORE 40#define mtspr(reg, val) \ 41 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 42#define mfspr(reg) \ --- 371 unchanged lines hidden (view full) --- 414#define SPR_DBCR0 0x3f2 /* 4.. Debug Control Register 0 */ 415#define SPR_DBCR1 0x3bd /* 4.. Debug Control Register 1 */ 416#define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */ 417#define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */ 418#define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */ 419#define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */ 420#define SPR_PIR 0x3ff /* .6. Processor Identification Register */ 421#elif defined(E500) |
| 422#define SPR_PIR 0x11e /* ..8 Processor Identification Register */ |
|
| 422#define SPR_DBSR 0x130 /* ..8 Debug Status Register */ 423#define DBSR_IDE 0x80000000 /* Imprecise debug event. */ 424#define DBSR_UDE 0x40000000 /* Unconditional debug event. */ 425#define DBSR_MRR 0x30000000 /* Most recent Reset (mask). */ 426#define DBSR_ICMP 0x08000000 /* Instr. complete debug event. */ 427#define DBSR_BRT 0x04000000 /* Branch taken debug event. */ 428#define DBSR_IRPT 0x02000000 /* Interrupt taken debug event. */ 429#define DBSR_TRAP 0x01000000 /* Trap instr. debug event. */ --- 244 unchanged lines hidden --- | 423#define SPR_DBSR 0x130 /* ..8 Debug Status Register */ 424#define DBSR_IDE 0x80000000 /* Imprecise debug event. */ 425#define DBSR_UDE 0x40000000 /* Unconditional debug event. */ 426#define DBSR_MRR 0x30000000 /* Most recent Reset (mask). */ 427#define DBSR_ICMP 0x08000000 /* Instr. complete debug event. */ 428#define DBSR_BRT 0x04000000 /* Branch taken debug event. */ 429#define DBSR_IRPT 0x02000000 /* Interrupt taken debug event. */ 430#define DBSR_TRAP 0x01000000 /* Trap instr. debug event. */ --- 244 unchanged lines hidden --- |