| intr.h (302408) | intr.h (308333) |
|---|---|
| 1/* $NetBSD: intr.h,v 1.7 2003/06/16 20:01:00 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 18 unchanged lines hidden (view full) --- 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * | 1/* $NetBSD: intr.h,v 1.7 2003/06/16 20:01:00 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 18 unchanged lines hidden (view full) --- 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * |
| 35 * $FreeBSD: stable/11/sys/mips/include/intr.h 298068 2016-04-15 16:05:41Z andrew $ | 35 * $FreeBSD: stable/11/sys/mips/include/intr.h 308333 2016-11-05 10:23:02Z mmel $ |
| 36 * 37 */ 38 39#ifndef _MACHINE_INTR_H_ 40#define _MACHINE_INTR_H_ 41 42#ifdef INTRNG 43 --- 14 unchanged lines hidden (view full) --- 58#define INTR_IRQ_NSPC_SWI 4 59 60/* MIPS compatibility for legacy mips code */ 61void cpu_init_interrupts(void); 62void cpu_establish_hardintr(const char *, driver_filter_t *, driver_intr_t *, 63 void *, int, int, void **); 64void cpu_establish_softintr(const char *, driver_filter_t *, void (*)(void*), 65 void *, int, int, void **); | 36 * 37 */ 38 39#ifndef _MACHINE_INTR_H_ 40#define _MACHINE_INTR_H_ 41 42#ifdef INTRNG 43 --- 14 unchanged lines hidden (view full) --- 58#define INTR_IRQ_NSPC_SWI 4 59 60/* MIPS compatibility for legacy mips code */ 61void cpu_init_interrupts(void); 62void cpu_establish_hardintr(const char *, driver_filter_t *, driver_intr_t *, 63 void *, int, int, void **); 64void cpu_establish_softintr(const char *, driver_filter_t *, void (*)(void*), 65 void *, int, int, void **); |
| 66int cpu_create_intr_map(int); 67struct resource *cpu_get_irq_resource(int); |
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| 66/* MIPS interrupt C entry point */ 67void cpu_intr(struct trapframe *); 68 69#endif /* INTRNG */ 70 71#endif /* _MACHINE_INTR_H */ | 68/* MIPS interrupt C entry point */ 69void cpu_intr(struct trapframe *); 70 71#endif /* INTRNG */ 72 73#endif /* _MACHINE_INTR_H */ |