| cpufunc.h (178172) | cpufunc.h (202031) |
|---|---|
| 1/* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */ 2 3/* 4 * Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 15 unchanged lines hidden (view full) --- 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta | 1/* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */ 2 3/* 4 * Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 15 unchanged lines hidden (view full) --- 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta |
| 32 * $FreeBSD: head/sys/mips/include/cpufunc.h 178172 2008-04-13 07:27:37Z imp $ | 32 * $FreeBSD: head/sys/mips/include/cpufunc.h 202031 2010-01-10 19:50:24Z imp $ |
| 33 */ 34 35#ifndef _MACHINE_CPUFUNC_H_ 36#define _MACHINE_CPUFUNC_H_ 37 38#include <sys/types.h> 39#include <machine/cpuregs.h> 40 --- 137 unchanged lines hidden (view full) --- 178 __XSTRING(COP0_SYNC)";" \ 179 "nop;" \ 180 "nop;" \ 181 : \ 182 : [a0] "r"(a0)); \ 183 mips_barrier(); \ 184} struct __hack 185 | 33 */ 34 35#ifndef _MACHINE_CPUFUNC_H_ 36#define _MACHINE_CPUFUNC_H_ 37 38#include <sys/types.h> 39#include <machine/cpuregs.h> 40 --- 137 unchanged lines hidden (view full) --- 178 __XSTRING(COP0_SYNC)";" \ 179 "nop;" \ 180 "nop;" \ 181 : \ 182 : [a0] "r"(a0)); \ 183 mips_barrier(); \ 184} struct __hack 185 |
| 186#define MIPS_RDRW32_COP0_SEL(n,r,s) \ 187static __inline uint32_t \ 188mips_rd_ ## n ## s(void) \ 189{ \ 190 int v0; \ 191 __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \ 192 : [v0] "=&r"(v0)); \ 193 mips_barrier(); \ 194 return (v0); \ 195} \ 196static __inline void \ 197mips_wr_ ## n ## s(uint32_t a0) \ 198{ \ 199 __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \ 200 __XSTRING(COP0_SYNC)";" \ 201 "nop;" \ 202 "nop;" \ 203 : \ 204 : [a0] "r"(a0)); \ 205 mips_barrier(); \ 206} struct __hack 207 |
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| 186#ifdef TARGET_OCTEON 187static __inline void mips_sync_icache (void) 188{ | 208#ifdef TARGET_OCTEON 209static __inline void mips_sync_icache (void) 210{ |
| 189 __asm __volatile ( 190 ".set mips64\n" 191 ".word 0x041f0000\n" 192 "nop\n" 193 ".set mips0\n" 194 : : ); | 211 __asm __volatile ( 212 ".set push\n" 213 ".set mips64\n" 214 ".word 0x041f0000\n" /* xxx ICACHE */ 215 "nop\n" 216 ".set pop\n" 217 : : ); |
| 195} 196#endif 197 198MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE); 199MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG); | 218} 219#endif 220 221MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE); 222MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG); |
| 223MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 1); 224MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 2); 225MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 3); |
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| 200MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT); 201MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX); 202MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED); 203MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE); 204MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS); 205 206/* XXX: Some of these registers are specific to MIPS32. */ 207MIPS_RDRW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0); 208MIPS_RDRW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1); 209MIPS_RDRW32_COP0(entrylow, MIPS_COP_0_TLB_LOW); 210MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI); 211MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); 212MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID); 213MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO); | 226MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT); 227MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX); 228MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED); 229MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE); 230MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS); 231 232/* XXX: Some of these registers are specific to MIPS32. */ 233MIPS_RDRW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0); 234MIPS_RDRW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1); 235MIPS_RDRW32_COP0(entrylow, MIPS_COP_0_TLB_LOW); 236MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI); 237MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); 238MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID); 239MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO); |
| 240MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 1); 241MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 2); 242MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 3); |
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| 214MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI); | 243MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI); |
| 215 216static __inline uint32_t 217mips_rd_config_sel1(void) 218{ 219 int v0; 220 __asm __volatile("mfc0 %[v0], $16, 1 ;" 221 : [v0] "=&r" (v0)); 222 mips_barrier(); 223 return (v0); 224} 225 | 244MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 1); 245MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 2); 246MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 3); |
| 226#undef MIPS_RDRW32_COP0 227 228static __inline register_t 229intr_disable(void) 230{ 231 register_t s; 232 233 s = mips_rd_status(); --- 113 unchanged lines hidden --- | 247#undef MIPS_RDRW32_COP0 248 249static __inline register_t 250intr_disable(void) 251{ 252 register_t s; 253 254 s = mips_rd_status(); --- 113 unchanged lines hidden --- |