32c32
< * $FreeBSD: head/sys/mips/include/cpufunc.h 178172 2008-04-13 07:27:37Z imp $
---
> * $FreeBSD: head/sys/mips/include/cpufunc.h 202031 2010-01-10 19:50:24Z imp $
185a186,207
> #define MIPS_RDRW32_COP0_SEL(n,r,s) \
> static __inline uint32_t \
> mips_rd_ ## n ## s(void) \
> { \
> int v0; \
> __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \
> : [v0] "=&r"(v0)); \
> mips_barrier(); \
> return (v0); \
> } \
> static __inline void \
> mips_wr_ ## n ## s(uint32_t a0) \
> { \
> __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \
> __XSTRING(COP0_SYNC)";" \
> "nop;" \
> "nop;" \
> : \
> : [a0] "r"(a0)); \
> mips_barrier(); \
> } struct __hack
>
189,194c211,217
< __asm __volatile (
< ".set mips64\n"
< ".word 0x041f0000\n"
< "nop\n"
< ".set mips0\n"
< : : );
---
> __asm __volatile (
> ".set push\n"
> ".set mips64\n"
> ".word 0x041f0000\n" /* xxx ICACHE */
> "nop\n"
> ".set pop\n"
> : : );
199a223,225
> MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 1);
> MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 2);
> MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 3);
213a240,242
> MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 1);
> MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 2);
> MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 3);
215,225c244,246
<
< static __inline uint32_t
< mips_rd_config_sel1(void)
< {
< int v0;
< __asm __volatile("mfc0 %[v0], $16, 1 ;"
< : [v0] "=&r" (v0));
< mips_barrier();
< return (v0);
< }
<
---
> MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 1);
> MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 2);
> MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 3);