1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
| 1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
|
32 * $FreeBSD: head/sys/pci/if_xl.c 69490 2000-12-01 19:41:14Z imp $
| 32 * $FreeBSD: head/sys/pci/if_xl.c 69583 2000-12-04 22:46:50Z wpaul $
|
33 */
34
35/*
36 * 3Com 3c90x Etherlink XL PCI NIC driver
37 *
38 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
39 * bus-master chips (3c90x cards and embedded controllers) including
40 * the following:
41 *
42 * 3Com 3c900-TPO 10Mbps/RJ-45
43 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
44 * 3Com 3c905-TX 10/100Mbps/RJ-45
45 * 3Com 3c905-T4 10/100Mbps/RJ-45
46 * 3Com 3c900B-TPO 10Mbps/RJ-45
47 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
48 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
49 * 3Com 3c900B-FL 10Mbps/Fiber-optic
50 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
51 * 3Com 3c905B-TX 10/100Mbps/RJ-45
52 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
53 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
54 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
55 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
56 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
57 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
58 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
59 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
60 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
61 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
62 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
65 * Dell on-board 3c920 10/100Mbps/RJ-45
66 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
67 * Dell Latitude laptop docking station embedded 3c905-TX
68 *
69 * Written by Bill Paul <wpaul@ctr.columbia.edu>
70 * Electrical Engineering Department
71 * Columbia University, New York City
72 */
73
74/*
75 * The 3c90x series chips use a bus-master DMA interface for transfering
76 * packets to and from the controller chip. Some of the "vortex" cards
77 * (3c59x) also supported a bus master mode, however for those chips
78 * you could only DMA packets to/from a contiguous memory buffer. For
79 * transmission this would mean copying the contents of the queued mbuf
80 * chain into a an mbuf cluster and then DMAing the cluster. This extra
81 * copy would sort of defeat the purpose of the bus master support for
82 * any packet that doesn't fit into a single mbuf.
83 *
84 * By contrast, the 3c90x cards support a fragment-based bus master
85 * mode where mbuf chains can be encapsulated using TX descriptors.
86 * This is similar to other PCI chips such as the Texas Instruments
87 * ThunderLAN and the Intel 82557/82558.
88 *
89 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
90 * bus master chips because they maintain the old PIO interface for
91 * backwards compatibility, but starting with the 3c905B and the
92 * "cyclone" chips, the compatibility interface has been dropped.
93 * Since using bus master DMA is a big win, we use this driver to
94 * support the PCI "boomerang" chips even though they work with the
95 * "vortex" driver in order to obtain better performance.
96 *
97 * This driver is in the /sys/pci directory because it only supports
98 * PCI-based NICs.
99 */
100
101#include <sys/param.h>
102#include <sys/systm.h>
103#include <sys/sockio.h>
104#include <sys/mbuf.h>
105#include <sys/malloc.h>
106#include <sys/kernel.h>
107#include <sys/socket.h>
108
109#include <net/if.h>
110#include <net/if_arp.h>
111#include <net/ethernet.h>
112#include <net/if_dl.h>
113#include <net/if_media.h>
114
115#include <net/bpf.h>
116
117#include <vm/vm.h> /* for vtophys */
118#include <vm/pmap.h> /* for vtophys */
119#include <machine/bus_memio.h>
120#include <machine/bus_pio.h>
121#include <machine/bus.h>
122#include <machine/resource.h>
123#include <sys/bus.h>
124#include <sys/rman.h>
125
126#include <dev/mii/mii.h>
127#include <dev/mii/miivar.h>
128
129#include <pci/pcireg.h>
130#include <pci/pcivar.h>
131
132MODULE_DEPEND(xl, miibus, 1, 1, 1);
133
134/* "controller miibus0" required. See GENERIC if you get errors here. */
135#include "miibus_if.h"
136
137/*
138 * The following #define causes the code to use PIO to access the
139 * chip's registers instead of memory mapped mode. The reason PIO mode
140 * is on by default is that the Etherlink XL manual seems to indicate
141 * that only the newer revision chips (3c905B) support both PIO and
142 * memory mapped access. Since we want to be compatible with the older
143 * bus master chips, we use PIO here. If you comment this out, the
144 * driver will use memory mapped I/O, which may be faster but which
145 * might not work on some devices.
146 */
147#define XL_USEIOSPACE
148
149#include <pci/if_xlreg.h>
150
151#if !defined(lint)
152static const char rcsid[] =
| 33 */
34
35/*
36 * 3Com 3c90x Etherlink XL PCI NIC driver
37 *
38 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
39 * bus-master chips (3c90x cards and embedded controllers) including
40 * the following:
41 *
42 * 3Com 3c900-TPO 10Mbps/RJ-45
43 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
44 * 3Com 3c905-TX 10/100Mbps/RJ-45
45 * 3Com 3c905-T4 10/100Mbps/RJ-45
46 * 3Com 3c900B-TPO 10Mbps/RJ-45
47 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
48 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
49 * 3Com 3c900B-FL 10Mbps/Fiber-optic
50 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
51 * 3Com 3c905B-TX 10/100Mbps/RJ-45
52 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
53 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
54 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
55 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
56 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
57 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
58 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
59 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
60 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
61 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
62 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
65 * Dell on-board 3c920 10/100Mbps/RJ-45
66 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
67 * Dell Latitude laptop docking station embedded 3c905-TX
68 *
69 * Written by Bill Paul <wpaul@ctr.columbia.edu>
70 * Electrical Engineering Department
71 * Columbia University, New York City
72 */
73
74/*
75 * The 3c90x series chips use a bus-master DMA interface for transfering
76 * packets to and from the controller chip. Some of the "vortex" cards
77 * (3c59x) also supported a bus master mode, however for those chips
78 * you could only DMA packets to/from a contiguous memory buffer. For
79 * transmission this would mean copying the contents of the queued mbuf
80 * chain into a an mbuf cluster and then DMAing the cluster. This extra
81 * copy would sort of defeat the purpose of the bus master support for
82 * any packet that doesn't fit into a single mbuf.
83 *
84 * By contrast, the 3c90x cards support a fragment-based bus master
85 * mode where mbuf chains can be encapsulated using TX descriptors.
86 * This is similar to other PCI chips such as the Texas Instruments
87 * ThunderLAN and the Intel 82557/82558.
88 *
89 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
90 * bus master chips because they maintain the old PIO interface for
91 * backwards compatibility, but starting with the 3c905B and the
92 * "cyclone" chips, the compatibility interface has been dropped.
93 * Since using bus master DMA is a big win, we use this driver to
94 * support the PCI "boomerang" chips even though they work with the
95 * "vortex" driver in order to obtain better performance.
96 *
97 * This driver is in the /sys/pci directory because it only supports
98 * PCI-based NICs.
99 */
100
101#include <sys/param.h>
102#include <sys/systm.h>
103#include <sys/sockio.h>
104#include <sys/mbuf.h>
105#include <sys/malloc.h>
106#include <sys/kernel.h>
107#include <sys/socket.h>
108
109#include <net/if.h>
110#include <net/if_arp.h>
111#include <net/ethernet.h>
112#include <net/if_dl.h>
113#include <net/if_media.h>
114
115#include <net/bpf.h>
116
117#include <vm/vm.h> /* for vtophys */
118#include <vm/pmap.h> /* for vtophys */
119#include <machine/bus_memio.h>
120#include <machine/bus_pio.h>
121#include <machine/bus.h>
122#include <machine/resource.h>
123#include <sys/bus.h>
124#include <sys/rman.h>
125
126#include <dev/mii/mii.h>
127#include <dev/mii/miivar.h>
128
129#include <pci/pcireg.h>
130#include <pci/pcivar.h>
131
132MODULE_DEPEND(xl, miibus, 1, 1, 1);
133
134/* "controller miibus0" required. See GENERIC if you get errors here. */
135#include "miibus_if.h"
136
137/*
138 * The following #define causes the code to use PIO to access the
139 * chip's registers instead of memory mapped mode. The reason PIO mode
140 * is on by default is that the Etherlink XL manual seems to indicate
141 * that only the newer revision chips (3c905B) support both PIO and
142 * memory mapped access. Since we want to be compatible with the older
143 * bus master chips, we use PIO here. If you comment this out, the
144 * driver will use memory mapped I/O, which may be faster but which
145 * might not work on some devices.
146 */
147#define XL_USEIOSPACE
148
149#include <pci/if_xlreg.h>
150
151#if !defined(lint)
152static const char rcsid[] =
|
153 "$FreeBSD: head/sys/pci/if_xl.c 69490 2000-12-01 19:41:14Z imp $";
| 153 "$FreeBSD: head/sys/pci/if_xl.c 69583 2000-12-04 22:46:50Z wpaul $";
|
154#endif
155
156/*
157 * Various supported device vendors/types and their names.
158 */
159static struct xl_type xl_devs[] = {
160 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
161 "3Com 3c900-TPO Etherlink XL" },
162 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
163 "3Com 3c900-COMBO Etherlink XL" },
164 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
165 "3Com 3c905-TX Fast Etherlink XL" },
166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
167 "3Com 3c905-T4 Fast Etherlink XL" },
168 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
169 "3Com 3c900B-TPO Etherlink XL" },
170 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
171 "3Com 3c900B-COMBO Etherlink XL" },
172 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
173 "3Com 3c900B-TPC Etherlink XL" },
174 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
175 "3Com 3c900B-FL Etherlink XL" },
176 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
177 "3Com 3c905B-TX Fast Etherlink XL" },
178 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
179 "3Com 3c905B-T4 Fast Etherlink XL" },
180 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
181 "3Com 3c905B-FX/SC Fast Etherlink XL" },
182 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
183 "3Com 3c905B-COMBO Fast Etherlink XL" },
184 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
185 "3Com 3c905C-TX Fast Etherlink XL" },
186 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
187 "3Com 3c980 Fast Etherlink XL" },
188 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
189 "3Com 3c980C Fast Etherlink XL" },
190 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
191 "3Com 3cSOHO100-TX OfficeConnect" },
192 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
193 "3Com 3c450-TX HomeConnect" },
194 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
195 "3Com 3c556 Fast Etherlink XL" },
196 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
197 "3Com 3c556B Fast Etherlink XL" },
198 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
199 "3Com 3c575TX Fast Etherlink XL" },
200 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
201 "3Com 3c575B Fast Etherlink XL" },
202 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
203 "3Com 3c575C Fast Etherlink XL" },
204 { TC_VENDORID, TC_DEVICEID_HURRICANE_656C,
205 "3Com 3c656C Fast Etherlink XL" },
206 { 0, 0, NULL }
207};
208
209static int xl_probe __P((device_t));
210static int xl_attach __P((device_t));
211static int xl_detach __P((device_t));
212
213static int xl_newbuf __P((struct xl_softc *,
214 struct xl_chain_onefrag *));
215static void xl_stats_update __P((void *));
216static int xl_encap __P((struct xl_softc *, struct xl_chain *,
217 struct mbuf * ));
218static int xl_encap_90xB __P((struct xl_softc *, struct xl_chain *,
219 struct mbuf * ));
220
221static void xl_rxeof __P((struct xl_softc *));
222static int xl_rx_resync __P((struct xl_softc *));
223static void xl_txeof __P((struct xl_softc *));
224static void xl_txeof_90xB __P((struct xl_softc *));
225static void xl_txeoc __P((struct xl_softc *));
226static void xl_intr __P((void *));
227static void xl_start __P((struct ifnet *));
228static void xl_start_90xB __P((struct ifnet *));
229static int xl_ioctl __P((struct ifnet *, u_long, caddr_t));
230static void xl_init __P((void *));
231static void xl_stop __P((struct xl_softc *));
232static void xl_watchdog __P((struct ifnet *));
233static void xl_shutdown __P((device_t));
234static int xl_ifmedia_upd __P((struct ifnet *));
235static void xl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
236
237static int xl_eeprom_wait __P((struct xl_softc *));
238static int xl_read_eeprom __P((struct xl_softc *, caddr_t, int,
239 int, int));
240static void xl_mii_sync __P((struct xl_softc *));
241static void xl_mii_send __P((struct xl_softc *, u_int32_t, int));
242static int xl_mii_readreg __P((struct xl_softc *, struct xl_mii_frame *));
243static int xl_mii_writereg __P((struct xl_softc *, struct xl_mii_frame *));
244
245static void xl_setcfg __P((struct xl_softc *));
246static void xl_setmode __P((struct xl_softc *, int));
247static u_int8_t xl_calchash __P((caddr_t));
248static void xl_setmulti __P((struct xl_softc *));
249static void xl_setmulti_hash __P((struct xl_softc *));
250static void xl_reset __P((struct xl_softc *));
251static int xl_list_rx_init __P((struct xl_softc *));
252static int xl_list_tx_init __P((struct xl_softc *));
253static int xl_list_tx_init_90xB __P((struct xl_softc *));
254static void xl_wait __P((struct xl_softc *));
255static void xl_mediacheck __P((struct xl_softc *));
256static void xl_choose_xcvr __P((struct xl_softc *, int));
257#ifdef notdef
258static void xl_testpacket __P((struct xl_softc *));
259#endif
260
261static int xl_miibus_readreg __P((device_t, int, int));
262static int xl_miibus_writereg __P((device_t, int, int, int));
263static void xl_miibus_statchg __P((device_t));
264static void xl_miibus_mediainit __P((device_t));
265
266#ifdef XL_USEIOSPACE
267#define XL_RES SYS_RES_IOPORT
268#define XL_RID XL_PCI_LOIO
269#else
270#define XL_RES SYS_RES_MEMORY
271#define XL_RID XL_PCI_LOMEM
272#endif
273
274static device_method_t xl_methods[] = {
275 /* Device interface */
276 DEVMETHOD(device_probe, xl_probe),
277 DEVMETHOD(device_attach, xl_attach),
278 DEVMETHOD(device_detach, xl_detach),
279 DEVMETHOD(device_shutdown, xl_shutdown),
280
281 /* bus interface */
282 DEVMETHOD(bus_print_child, bus_generic_print_child),
283 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
284
285 /* MII interface */
286 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
287 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
288 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
289 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
290
291 { 0, 0 }
292};
293
294static driver_t xl_driver = {
295 "xl",
296 xl_methods,
297 sizeof(struct xl_softc)
298};
299
300static devclass_t xl_devclass;
301
302DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0);
303DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0);
304DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
305
306/*
307 * Murphy's law says that it's possible the chip can wedge and
308 * the 'command in progress' bit may never clear. Hence, we wait
309 * only a finite amount of time to avoid getting caught in an
310 * infinite loop. Normally this delay routine would be a macro,
311 * but it isn't called during normal operation so we can afford
312 * to make it a function.
313 */
314static void xl_wait(sc)
315 struct xl_softc *sc;
316{
317 register int i;
318
319 for (i = 0; i < XL_TIMEOUT; i++) {
320 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
321 break;
322 }
323
324 if (i == XL_TIMEOUT)
325 printf("xl%d: command never completed!\n", sc->xl_unit);
326
327 return;
328}
329
330/*
331 * MII access routines are provided for adapters with external
332 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
333 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
334 * Note: if you don't perform the MDIO operations just right,
335 * it's possible to end up with code that works correctly with
336 * some chips/CPUs/processor speeds/bus speeds/etc but not
337 * with others.
338 */
339#define MII_SET(x) \
340 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
341 CSR_READ_2(sc, XL_W4_PHY_MGMT) | x)
342
343#define MII_CLR(x) \
344 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
345 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~x)
346
347/*
348 * Sync the PHYs by setting data bit and strobing the clock 32 times.
349 */
350static void xl_mii_sync(sc)
351 struct xl_softc *sc;
352{
353 register int i;
354
355 XL_SEL_WIN(4);
356 MII_SET(XL_MII_DIR|XL_MII_DATA);
357
358 for (i = 0; i < 32; i++) {
359 MII_SET(XL_MII_CLK);
360 DELAY(1);
361 MII_CLR(XL_MII_CLK);
362 DELAY(1);
363 }
364
365 return;
366}
367
368/*
369 * Clock a series of bits through the MII.
370 */
371static void xl_mii_send(sc, bits, cnt)
372 struct xl_softc *sc;
373 u_int32_t bits;
374 int cnt;
375{
376 int i;
377
378 XL_SEL_WIN(4);
379 MII_CLR(XL_MII_CLK);
380
381 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
382 if (bits & i) {
383 MII_SET(XL_MII_DATA);
384 } else {
385 MII_CLR(XL_MII_DATA);
386 }
387 DELAY(1);
388 MII_CLR(XL_MII_CLK);
389 DELAY(1);
390 MII_SET(XL_MII_CLK);
391 }
392}
393
394/*
395 * Read an PHY register through the MII.
396 */
397static int xl_mii_readreg(sc, frame)
398 struct xl_softc *sc;
399 struct xl_mii_frame *frame;
400
401{
402 int i, ack;
403
404 XL_LOCK(sc);
405
406 /*
407 * Set up frame for RX.
408 */
409 frame->mii_stdelim = XL_MII_STARTDELIM;
410 frame->mii_opcode = XL_MII_READOP;
411 frame->mii_turnaround = 0;
412 frame->mii_data = 0;
413
414 /*
415 * Select register window 4.
416 */
417
418 XL_SEL_WIN(4);
419
420 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
421 /*
422 * Turn on data xmit.
423 */
424 MII_SET(XL_MII_DIR);
425
426 xl_mii_sync(sc);
427
428 /*
429 * Send command/address info.
430 */
431 xl_mii_send(sc, frame->mii_stdelim, 2);
432 xl_mii_send(sc, frame->mii_opcode, 2);
433 xl_mii_send(sc, frame->mii_phyaddr, 5);
434 xl_mii_send(sc, frame->mii_regaddr, 5);
435
436 /* Idle bit */
437 MII_CLR((XL_MII_CLK|XL_MII_DATA));
438 DELAY(1);
439 MII_SET(XL_MII_CLK);
440 DELAY(1);
441
442 /* Turn off xmit. */
443 MII_CLR(XL_MII_DIR);
444
445 /* Check for ack */
446 MII_CLR(XL_MII_CLK);
447 DELAY(1);
448 MII_SET(XL_MII_CLK);
449 DELAY(1);
450 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
451
452 /*
453 * Now try reading data bits. If the ack failed, we still
454 * need to clock through 16 cycles to keep the PHY(s) in sync.
455 */
456 if (ack) {
457 for(i = 0; i < 16; i++) {
458 MII_CLR(XL_MII_CLK);
459 DELAY(1);
460 MII_SET(XL_MII_CLK);
461 DELAY(1);
462 }
463 goto fail;
464 }
465
466 for (i = 0x8000; i; i >>= 1) {
467 MII_CLR(XL_MII_CLK);
468 DELAY(1);
469 if (!ack) {
470 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
471 frame->mii_data |= i;
472 DELAY(1);
473 }
474 MII_SET(XL_MII_CLK);
475 DELAY(1);
476 }
477
478fail:
479
480 MII_CLR(XL_MII_CLK);
481 DELAY(1);
482 MII_SET(XL_MII_CLK);
483 DELAY(1);
484
485 XL_UNLOCK(sc);
486
487 if (ack)
488 return(1);
489 return(0);
490}
491
492/*
493 * Write to a PHY register through the MII.
494 */
495static int xl_mii_writereg(sc, frame)
496 struct xl_softc *sc;
497 struct xl_mii_frame *frame;
498
499{
500 XL_LOCK(sc);
501
502 /*
503 * Set up frame for TX.
504 */
505
506 frame->mii_stdelim = XL_MII_STARTDELIM;
507 frame->mii_opcode = XL_MII_WRITEOP;
508 frame->mii_turnaround = XL_MII_TURNAROUND;
509
510 /*
511 * Select the window 4.
512 */
513 XL_SEL_WIN(4);
514
515 /*
516 * Turn on data output.
517 */
518 MII_SET(XL_MII_DIR);
519
520 xl_mii_sync(sc);
521
522 xl_mii_send(sc, frame->mii_stdelim, 2);
523 xl_mii_send(sc, frame->mii_opcode, 2);
524 xl_mii_send(sc, frame->mii_phyaddr, 5);
525 xl_mii_send(sc, frame->mii_regaddr, 5);
526 xl_mii_send(sc, frame->mii_turnaround, 2);
527 xl_mii_send(sc, frame->mii_data, 16);
528
529 /* Idle bit. */
530 MII_SET(XL_MII_CLK);
531 DELAY(1);
532 MII_CLR(XL_MII_CLK);
533 DELAY(1);
534
535 /*
536 * Turn off xmit.
537 */
538 MII_CLR(XL_MII_DIR);
539
540 XL_UNLOCK(sc);
541
542 return(0);
543}
544
545static int xl_miibus_readreg(dev, phy, reg)
546 device_t dev;
547 int phy, reg;
548{
549 struct xl_softc *sc;
550 struct xl_mii_frame frame;
551
552 sc = device_get_softc(dev);
553
554 /*
555 * Pretend that PHYs are only available at MII address 24.
556 * This is to guard against problems with certain 3Com ASIC
557 * revisions that incorrectly map the internal transceiver
558 * control registers at all MII addresses. This can cause
559 * the miibus code to attach the same PHY several times over.
560 */
561 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
562 return(0);
563
564 bzero((char *)&frame, sizeof(frame));
565
566 frame.mii_phyaddr = phy;
567 frame.mii_regaddr = reg;
568 xl_mii_readreg(sc, &frame);
569
570 return(frame.mii_data);
571}
572
573static int xl_miibus_writereg(dev, phy, reg, data)
574 device_t dev;
575 int phy, reg, data;
576{
577 struct xl_softc *sc;
578 struct xl_mii_frame frame;
579
580 sc = device_get_softc(dev);
581
582 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
583 return(0);
584
585 bzero((char *)&frame, sizeof(frame));
586
587 frame.mii_phyaddr = phy;
588 frame.mii_regaddr = reg;
589 frame.mii_data = data;
590
591 xl_mii_writereg(sc, &frame);
592
593 return(0);
594}
595
596static void xl_miibus_statchg(dev)
597 device_t dev;
598{
599 struct xl_softc *sc;
600 struct mii_data *mii;
601
602
603 sc = device_get_softc(dev);
604 mii = device_get_softc(sc->xl_miibus);
605
606 XL_LOCK(sc);
607
608 xl_setcfg(sc);
609
610 /* Set ASIC's duplex mode to match the PHY. */
611 XL_SEL_WIN(3);
612 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
613 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
614 else
615 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
616 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
617
618 XL_UNLOCK(sc);
619
620 return;
621}
622
623/*
624 * Special support for the 3c905B-COMBO. This card has 10/100 support
625 * plus BNC and AUI ports. This means we will have both an miibus attached
626 * plus some non-MII media settings. In order to allow this, we have to
627 * add the extra media to the miibus's ifmedia struct, but we can't do
628 * that during xl_attach() because the miibus hasn't been attached yet.
629 * So instead, we wait until the miibus probe/attach is done, at which
630 * point we will get a callback telling is that it's safe to add our
631 * extra media.
632 */
633static void xl_miibus_mediainit(dev)
634 device_t dev;
635{
636 struct xl_softc *sc;
637 struct mii_data *mii;
638 struct ifmedia *ifm;
639
640 sc = device_get_softc(dev);
641 mii = device_get_softc(sc->xl_miibus);
642 ifm = &mii->mii_media;
643
644 XL_LOCK(sc);
645
646 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
647 /*
648 * Check for a 10baseFL board in disguise.
649 */
650 if (sc->xl_type == XL_TYPE_905B &&
651 sc->xl_media == XL_MEDIAOPT_10FL) {
652 if (bootverbose)
653 printf("xl%d: found 10baseFL\n", sc->xl_unit);
654 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
655 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
656 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
657 ifmedia_add(ifm,
658 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
659 } else {
660 if (bootverbose)
661 printf("xl%d: found AUI\n", sc->xl_unit);
662 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
663 }
664 }
665
666 if (sc->xl_media & XL_MEDIAOPT_BNC) {
667 if (bootverbose)
668 printf("xl%d: found BNC\n", sc->xl_unit);
669 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
670 }
671
672 XL_UNLOCK(sc);
673
674 return;
675}
676
677/*
678 * The EEPROM is slow: give it time to come ready after issuing
679 * it a command.
680 */
681static int xl_eeprom_wait(sc)
682 struct xl_softc *sc;
683{
684 int i;
685
686 for (i = 0; i < 100; i++) {
687 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
688 DELAY(162);
689 else
690 break;
691 }
692
693 if (i == 100) {
694 printf("xl%d: eeprom failed to come ready\n", sc->xl_unit);
695 return(1);
696 }
697
698 return(0);
699}
700
701/*
702 * Read a sequence of words from the EEPROM. Note that ethernet address
703 * data is stored in the EEPROM in network byte order.
704 */
705static int xl_read_eeprom(sc, dest, off, cnt, swap)
706 struct xl_softc *sc;
707 caddr_t dest;
708 int off;
709 int cnt;
710 int swap;
711{
712 int err = 0, i;
713 u_int16_t word = 0, *ptr;
714#define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
715#define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
716 /* WARNING! DANGER!
717 * It's easy to accidentally overwrite the rom content!
718 * Note: the 3c575 uses 8bit EEPROM offsets.
719 */
720 XL_SEL_WIN(0);
721
722 if (xl_eeprom_wait(sc))
723 return(1);
724
725 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
726 off += 0x30;
727
728 for (i = 0; i < cnt; i++) {
729 if (sc->xl_flags & XL_FLAG_8BITROM)
730 CSR_WRITE_2(sc, XL_W0_EE_CMD,
731 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
732 else
733 CSR_WRITE_2(sc, XL_W0_EE_CMD,
734 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
735 err = xl_eeprom_wait(sc);
736 if (err)
737 break;
738 word = CSR_READ_2(sc, XL_W0_EE_DATA);
739 ptr = (u_int16_t *)(dest + (i * 2));
740 if (swap)
741 *ptr = ntohs(word);
742 else
743 *ptr = word;
744 }
745
746 return(err ? 1 : 0);
747}
748
749/*
750 * This routine is taken from the 3Com Etherlink XL manual,
751 * page 10-7. It calculates a CRC of the supplied multicast
752 * group address and returns the lower 8 bits, which are used
753 * as the multicast filter position.
754 * Note: the 3c905B currently only supports a 64-bit hash table,
755 * which means we really only need 6 bits, but the manual indicates
756 * that future chip revisions will have a 256-bit hash table,
757 * hence the routine is set up to calculate 8 bits of position
758 * info in case we need it some day.
759 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a
760 * 256 bit hash table. This means we have to use all 8 bits regardless.
761 * On older cards, the upper 2 bits will be ignored. Grrrr....
762 */
763static u_int8_t xl_calchash(addr)
764 caddr_t addr;
765{
766 u_int32_t crc, carry;
767 int i, j;
768 u_int8_t c;
769
770 /* Compute CRC for the address value. */
771 crc = 0xFFFFFFFF; /* initial value */
772
773 for (i = 0; i < 6; i++) {
774 c = *(addr + i);
775 for (j = 0; j < 8; j++) {
776 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
777 crc <<= 1;
778 c >>= 1;
779 if (carry)
780 crc = (crc ^ 0x04c11db6) | carry;
781 }
782 }
783
784 /* return the filter bit position */
785 return(crc & 0x000000FF);
786}
787
788/*
789 * NICs older than the 3c905B have only one multicast option, which
790 * is to enable reception of all multicast frames.
791 */
792static void xl_setmulti(sc)
793 struct xl_softc *sc;
794{
795 struct ifnet *ifp;
796 struct ifmultiaddr *ifma;
797 u_int8_t rxfilt;
798 int mcnt = 0;
799
800 ifp = &sc->arpcom.ac_if;
801
802 XL_SEL_WIN(5);
803 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
804
805 if (ifp->if_flags & IFF_ALLMULTI) {
806 rxfilt |= XL_RXFILTER_ALLMULTI;
807 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
808 return;
809 }
810
811 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
812 ifma = ifma->ifma_link.le_next)
813 mcnt++;
814
815 if (mcnt)
816 rxfilt |= XL_RXFILTER_ALLMULTI;
817 else
818 rxfilt &= ~XL_RXFILTER_ALLMULTI;
819
820 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
821
822 return;
823}
824
825/*
826 * 3c905B adapters have a hash filter that we can program.
827 */
828static void xl_setmulti_hash(sc)
829 struct xl_softc *sc;
830{
831 struct ifnet *ifp;
832 int h = 0, i;
833 struct ifmultiaddr *ifma;
834 u_int8_t rxfilt;
835 int mcnt = 0;
836
837 ifp = &sc->arpcom.ac_if;
838
839 XL_SEL_WIN(5);
840 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
841
842 if (ifp->if_flags & IFF_ALLMULTI) {
843 rxfilt |= XL_RXFILTER_ALLMULTI;
844 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
845 return;
846 } else
847 rxfilt &= ~XL_RXFILTER_ALLMULTI;
848
849
850 /* first, zot all the existing hash bits */
851 for (i = 0; i < XL_HASHFILT_SIZE; i++)
852 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
853
854 /* now program new ones */
855 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
856 ifma = ifma->ifma_link.le_next) {
857 if (ifma->ifma_addr->sa_family != AF_LINK)
858 continue;
859 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
860 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
861 mcnt++;
862 }
863
864 if (mcnt)
865 rxfilt |= XL_RXFILTER_MULTIHASH;
866 else
867 rxfilt &= ~XL_RXFILTER_MULTIHASH;
868
869 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
870
871 return;
872}
873
874#ifdef notdef
875static void xl_testpacket(sc)
876 struct xl_softc *sc;
877{
878 struct mbuf *m;
879 struct ifnet *ifp;
880
881 ifp = &sc->arpcom.ac_if;
882
883 MGETHDR(m, M_DONTWAIT, MT_DATA);
884
885 if (m == NULL)
886 return;
887
888 bcopy(&sc->arpcom.ac_enaddr,
889 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
890 bcopy(&sc->arpcom.ac_enaddr,
891 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
892 mtod(m, struct ether_header *)->ether_type = htons(3);
893 mtod(m, unsigned char *)[14] = 0;
894 mtod(m, unsigned char *)[15] = 0;
895 mtod(m, unsigned char *)[16] = 0xE3;
896 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
897 IF_ENQUEUE(&ifp->if_snd, m);
898 xl_start(ifp);
899
900 return;
901}
902#endif
903
904static void xl_setcfg(sc)
905 struct xl_softc *sc;
906{
907 u_int32_t icfg;
908
909 XL_SEL_WIN(3);
910 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
911 icfg &= ~XL_ICFG_CONNECTOR_MASK;
912 if (sc->xl_media & XL_MEDIAOPT_MII ||
913 sc->xl_media & XL_MEDIAOPT_BT4)
914 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
915 if (sc->xl_media & XL_MEDIAOPT_BTX)
916 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
917
918 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
919 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
920
921 return;
922}
923
924static void xl_setmode(sc, media)
925 struct xl_softc *sc;
926 int media;
927{
928 u_int32_t icfg;
929 u_int16_t mediastat;
930
931 printf("xl%d: selecting ", sc->xl_unit);
932
933 XL_SEL_WIN(4);
934 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
935 XL_SEL_WIN(3);
936 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
937
938 if (sc->xl_media & XL_MEDIAOPT_BT) {
939 if (IFM_SUBTYPE(media) == IFM_10_T) {
940 printf("10baseT transceiver, ");
941 sc->xl_xcvr = XL_XCVR_10BT;
942 icfg &= ~XL_ICFG_CONNECTOR_MASK;
943 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
944 mediastat |= XL_MEDIASTAT_LINKBEAT|
945 XL_MEDIASTAT_JABGUARD;
946 mediastat &= ~XL_MEDIASTAT_SQEENB;
947 }
948 }
949
950 if (sc->xl_media & XL_MEDIAOPT_BFX) {
951 if (IFM_SUBTYPE(media) == IFM_100_FX) {
952 printf("100baseFX port, ");
953 sc->xl_xcvr = XL_XCVR_100BFX;
954 icfg &= ~XL_ICFG_CONNECTOR_MASK;
955 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
956 mediastat |= XL_MEDIASTAT_LINKBEAT;
957 mediastat &= ~XL_MEDIASTAT_SQEENB;
958 }
959 }
960
961 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
962 if (IFM_SUBTYPE(media) == IFM_10_5) {
963 printf("AUI port, ");
964 sc->xl_xcvr = XL_XCVR_AUI;
965 icfg &= ~XL_ICFG_CONNECTOR_MASK;
966 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
967 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
968 XL_MEDIASTAT_JABGUARD);
969 mediastat |= ~XL_MEDIASTAT_SQEENB;
970 }
971 if (IFM_SUBTYPE(media) == IFM_10_FL) {
972 printf("10baseFL transceiver, ");
973 sc->xl_xcvr = XL_XCVR_AUI;
974 icfg &= ~XL_ICFG_CONNECTOR_MASK;
975 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
976 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
977 XL_MEDIASTAT_JABGUARD);
978 mediastat |= ~XL_MEDIASTAT_SQEENB;
979 }
980 }
981
982 if (sc->xl_media & XL_MEDIAOPT_BNC) {
983 if (IFM_SUBTYPE(media) == IFM_10_2) {
984 printf("BNC port, ");
985 sc->xl_xcvr = XL_XCVR_COAX;
986 icfg &= ~XL_ICFG_CONNECTOR_MASK;
987 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
988 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
989 XL_MEDIASTAT_JABGUARD|
990 XL_MEDIASTAT_SQEENB);
991 }
992 }
993
994 if ((media & IFM_GMASK) == IFM_FDX ||
995 IFM_SUBTYPE(media) == IFM_100_FX) {
996 printf("full duplex\n");
997 XL_SEL_WIN(3);
998 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
999 } else {
1000 printf("half duplex\n");
1001 XL_SEL_WIN(3);
1002 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
1003 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
1004 }
1005
1006 if (IFM_SUBTYPE(media) == IFM_10_2)
1007 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
1008 else
1009 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
1010 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
1011 XL_SEL_WIN(4);
1012 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
1013 DELAY(800);
1014 XL_SEL_WIN(7);
1015
1016 return;
1017}
1018
1019static void xl_reset(sc)
1020 struct xl_softc *sc;
1021{
1022 register int i;
1023
1024 XL_SEL_WIN(0);
1025 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
1026 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
1027 XL_RESETOPT_DISADVFD:0));
1028
1029 for (i = 0; i < XL_TIMEOUT; i++) {
1030 DELAY(10);
1031 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1032 break;
1033 }
1034
1035 if (i == XL_TIMEOUT)
1036 printf("xl%d: reset didn't complete\n", sc->xl_unit);
1037
1038 DELAY(100000);
1039
1040 /* Reset TX and RX. */
1041 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1042 xl_wait(sc);
1043 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1044 xl_wait(sc);
1045
1046 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1047 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1048 XL_SEL_WIN(2);
1049 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
1050 XL_W2_RESET_OPTIONS)
1051 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
1052 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
1053 );
1054 }
1055
1056 /* Wait a little while for the chip to get its brains in order. */
1057 DELAY(100000);
1058 return;
1059}
1060
1061/*
1062 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1063 * IDs against our list and return a device name if we find a match.
1064 */
1065static int xl_probe(dev)
1066 device_t dev;
1067{
1068 struct xl_type *t;
1069
1070 t = xl_devs;
1071
1072 while(t->xl_name != NULL) {
1073 if ((pci_get_vendor(dev) == t->xl_vid) &&
1074 (pci_get_device(dev) == t->xl_did)) {
1075 device_set_desc(dev, t->xl_name);
1076 return(0);
1077 }
1078 t++;
1079 }
1080
1081 return(ENXIO);
1082}
1083
1084/*
1085 * This routine is a kludge to work around possible hardware faults
1086 * or manufacturing defects that can cause the media options register
1087 * (or reset options register, as it's called for the first generation
1088 * 3c90x adapters) to return an incorrect result. I have encountered
1089 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1090 * which doesn't have any of the 'mediaopt' bits set. This screws up
1091 * the attach routine pretty badly because it doesn't know what media
1092 * to look for. If we find ourselves in this predicament, this routine
1093 * will try to guess the media options values and warn the user of a
1094 * possible manufacturing defect with his adapter/system/whatever.
1095 */
1096static void xl_mediacheck(sc)
1097 struct xl_softc *sc;
1098{
1099
1100 /*
1101 * If some of the media options bits are set, assume they are
1102 * correct. If not, try to figure it out down below.
1103 * XXX I should check for 10baseFL, but I don't have an adapter
1104 * to test with.
1105 */
1106 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1107 /*
1108 * Check the XCVR value. If it's not in the normal range
1109 * of values, we need to fake it up here.
1110 */
1111 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1112 return;
1113 else {
1114 printf("xl%d: bogus xcvr value "
1115 "in EEPROM (%x)\n", sc->xl_unit, sc->xl_xcvr);
1116 printf("xl%d: choosing new default based "
1117 "on card type\n", sc->xl_unit);
1118 }
1119 } else {
1120 if (sc->xl_type == XL_TYPE_905B &&
1121 sc->xl_media & XL_MEDIAOPT_10FL)
1122 return;
1123 printf("xl%d: WARNING: no media options bits set in "
1124 "the media options register!!\n", sc->xl_unit);
1125 printf("xl%d: this could be a manufacturing defect in "
1126 "your adapter or system\n", sc->xl_unit);
1127 printf("xl%d: attempting to guess media type; you "
1128 "should probably consult your vendor\n", sc->xl_unit);
1129 }
1130
1131 xl_choose_xcvr(sc, 1);
1132
1133 return;
1134}
1135
1136static void xl_choose_xcvr(sc, verbose)
1137 struct xl_softc *sc;
1138 int verbose;
1139{
1140 u_int16_t devid;
1141
1142 /*
1143 * Read the device ID from the EEPROM.
1144 * This is what's loaded into the PCI device ID register, so it has
1145 * to be correct otherwise we wouldn't have gotten this far.
1146 */
1147 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1148
1149 switch(devid) {
1150 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1151 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1152 sc->xl_media = XL_MEDIAOPT_BT;
1153 sc->xl_xcvr = XL_XCVR_10BT;
1154 if (verbose)
1155 printf("xl%d: guessing 10BaseT "
1156 "transceiver\n", sc->xl_unit);
1157 break;
1158 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1159 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1160 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1161 sc->xl_xcvr = XL_XCVR_10BT;
1162 if (verbose)
1163 printf("xl%d: guessing COMBO "
1164 "(AUI/BNC/TP)\n", sc->xl_unit);
1165 break;
1166 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1167 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1168 sc->xl_xcvr = XL_XCVR_10BT;
1169 if (verbose)
1170 printf("xl%d: guessing TPC (BNC/TP)\n", sc->xl_unit);
1171 break;
1172 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1173 sc->xl_media = XL_MEDIAOPT_10FL;
1174 sc->xl_xcvr = XL_XCVR_AUI;
1175 if (verbose)
1176 printf("xl%d: guessing 10baseFL\n", sc->xl_unit);
1177 break;
1178 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1179 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1180 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1181 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1182 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1183 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1184 case TC_DEVICEID_HURRICANE_656C: /* 3c565C */
1185 sc->xl_media = XL_MEDIAOPT_MII;
1186 sc->xl_xcvr = XL_XCVR_MII;
1187 if (verbose)
1188 printf("xl%d: guessing MII\n", sc->xl_unit);
1189 break;
1190 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1191 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1192 sc->xl_media = XL_MEDIAOPT_BT4;
1193 sc->xl_xcvr = XL_XCVR_MII;
1194 if (verbose)
1195 printf("xl%d: guessing 100BaseT4/MII\n", sc->xl_unit);
1196 break;
1197 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1198 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1199 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1200 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1201 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1202 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1203 sc->xl_media = XL_MEDIAOPT_BTX;
1204 sc->xl_xcvr = XL_XCVR_AUTO;
1205 if (verbose)
1206 printf("xl%d: guessing 10/100 internal\n", sc->xl_unit);
1207 break;
1208 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1209 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1210 sc->xl_xcvr = XL_XCVR_AUTO;
1211 if (verbose)
1212 printf("xl%d: guessing 10/100 "
1213 "plus BNC/AUI\n", sc->xl_unit);
1214 break;
1215 default:
1216 printf("xl%d: unknown device ID: %x -- "
1217 "defaulting to 10baseT\n", sc->xl_unit, devid);
1218 sc->xl_media = XL_MEDIAOPT_BT;
1219 break;
1220 }
1221
1222 return;
1223}
1224
1225/*
1226 * Attach the interface. Allocate softc structures, do ifmedia
1227 * setup and ethernet/BPF attach.
1228 */
1229static int xl_attach(dev)
1230 device_t dev;
1231{
1232 u_char eaddr[ETHER_ADDR_LEN];
1233 u_int32_t command;
1234 struct xl_softc *sc;
1235 struct ifnet *ifp;
1236 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1237 int unit, error = 0, rid;
1238
1239 sc = device_get_softc(dev);
1240 unit = device_get_unit(dev);
1241
| 154#endif
155
156/*
157 * Various supported device vendors/types and their names.
158 */
159static struct xl_type xl_devs[] = {
160 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
161 "3Com 3c900-TPO Etherlink XL" },
162 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
163 "3Com 3c900-COMBO Etherlink XL" },
164 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
165 "3Com 3c905-TX Fast Etherlink XL" },
166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
167 "3Com 3c905-T4 Fast Etherlink XL" },
168 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
169 "3Com 3c900B-TPO Etherlink XL" },
170 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
171 "3Com 3c900B-COMBO Etherlink XL" },
172 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
173 "3Com 3c900B-TPC Etherlink XL" },
174 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
175 "3Com 3c900B-FL Etherlink XL" },
176 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
177 "3Com 3c905B-TX Fast Etherlink XL" },
178 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
179 "3Com 3c905B-T4 Fast Etherlink XL" },
180 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
181 "3Com 3c905B-FX/SC Fast Etherlink XL" },
182 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
183 "3Com 3c905B-COMBO Fast Etherlink XL" },
184 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
185 "3Com 3c905C-TX Fast Etherlink XL" },
186 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
187 "3Com 3c980 Fast Etherlink XL" },
188 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
189 "3Com 3c980C Fast Etherlink XL" },
190 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
191 "3Com 3cSOHO100-TX OfficeConnect" },
192 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
193 "3Com 3c450-TX HomeConnect" },
194 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
195 "3Com 3c556 Fast Etherlink XL" },
196 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
197 "3Com 3c556B Fast Etherlink XL" },
198 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
199 "3Com 3c575TX Fast Etherlink XL" },
200 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
201 "3Com 3c575B Fast Etherlink XL" },
202 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
203 "3Com 3c575C Fast Etherlink XL" },
204 { TC_VENDORID, TC_DEVICEID_HURRICANE_656C,
205 "3Com 3c656C Fast Etherlink XL" },
206 { 0, 0, NULL }
207};
208
209static int xl_probe __P((device_t));
210static int xl_attach __P((device_t));
211static int xl_detach __P((device_t));
212
213static int xl_newbuf __P((struct xl_softc *,
214 struct xl_chain_onefrag *));
215static void xl_stats_update __P((void *));
216static int xl_encap __P((struct xl_softc *, struct xl_chain *,
217 struct mbuf * ));
218static int xl_encap_90xB __P((struct xl_softc *, struct xl_chain *,
219 struct mbuf * ));
220
221static void xl_rxeof __P((struct xl_softc *));
222static int xl_rx_resync __P((struct xl_softc *));
223static void xl_txeof __P((struct xl_softc *));
224static void xl_txeof_90xB __P((struct xl_softc *));
225static void xl_txeoc __P((struct xl_softc *));
226static void xl_intr __P((void *));
227static void xl_start __P((struct ifnet *));
228static void xl_start_90xB __P((struct ifnet *));
229static int xl_ioctl __P((struct ifnet *, u_long, caddr_t));
230static void xl_init __P((void *));
231static void xl_stop __P((struct xl_softc *));
232static void xl_watchdog __P((struct ifnet *));
233static void xl_shutdown __P((device_t));
234static int xl_ifmedia_upd __P((struct ifnet *));
235static void xl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
236
237static int xl_eeprom_wait __P((struct xl_softc *));
238static int xl_read_eeprom __P((struct xl_softc *, caddr_t, int,
239 int, int));
240static void xl_mii_sync __P((struct xl_softc *));
241static void xl_mii_send __P((struct xl_softc *, u_int32_t, int));
242static int xl_mii_readreg __P((struct xl_softc *, struct xl_mii_frame *));
243static int xl_mii_writereg __P((struct xl_softc *, struct xl_mii_frame *));
244
245static void xl_setcfg __P((struct xl_softc *));
246static void xl_setmode __P((struct xl_softc *, int));
247static u_int8_t xl_calchash __P((caddr_t));
248static void xl_setmulti __P((struct xl_softc *));
249static void xl_setmulti_hash __P((struct xl_softc *));
250static void xl_reset __P((struct xl_softc *));
251static int xl_list_rx_init __P((struct xl_softc *));
252static int xl_list_tx_init __P((struct xl_softc *));
253static int xl_list_tx_init_90xB __P((struct xl_softc *));
254static void xl_wait __P((struct xl_softc *));
255static void xl_mediacheck __P((struct xl_softc *));
256static void xl_choose_xcvr __P((struct xl_softc *, int));
257#ifdef notdef
258static void xl_testpacket __P((struct xl_softc *));
259#endif
260
261static int xl_miibus_readreg __P((device_t, int, int));
262static int xl_miibus_writereg __P((device_t, int, int, int));
263static void xl_miibus_statchg __P((device_t));
264static void xl_miibus_mediainit __P((device_t));
265
266#ifdef XL_USEIOSPACE
267#define XL_RES SYS_RES_IOPORT
268#define XL_RID XL_PCI_LOIO
269#else
270#define XL_RES SYS_RES_MEMORY
271#define XL_RID XL_PCI_LOMEM
272#endif
273
274static device_method_t xl_methods[] = {
275 /* Device interface */
276 DEVMETHOD(device_probe, xl_probe),
277 DEVMETHOD(device_attach, xl_attach),
278 DEVMETHOD(device_detach, xl_detach),
279 DEVMETHOD(device_shutdown, xl_shutdown),
280
281 /* bus interface */
282 DEVMETHOD(bus_print_child, bus_generic_print_child),
283 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
284
285 /* MII interface */
286 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
287 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
288 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
289 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
290
291 { 0, 0 }
292};
293
294static driver_t xl_driver = {
295 "xl",
296 xl_methods,
297 sizeof(struct xl_softc)
298};
299
300static devclass_t xl_devclass;
301
302DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0);
303DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0);
304DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
305
306/*
307 * Murphy's law says that it's possible the chip can wedge and
308 * the 'command in progress' bit may never clear. Hence, we wait
309 * only a finite amount of time to avoid getting caught in an
310 * infinite loop. Normally this delay routine would be a macro,
311 * but it isn't called during normal operation so we can afford
312 * to make it a function.
313 */
314static void xl_wait(sc)
315 struct xl_softc *sc;
316{
317 register int i;
318
319 for (i = 0; i < XL_TIMEOUT; i++) {
320 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
321 break;
322 }
323
324 if (i == XL_TIMEOUT)
325 printf("xl%d: command never completed!\n", sc->xl_unit);
326
327 return;
328}
329
330/*
331 * MII access routines are provided for adapters with external
332 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
333 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
334 * Note: if you don't perform the MDIO operations just right,
335 * it's possible to end up with code that works correctly with
336 * some chips/CPUs/processor speeds/bus speeds/etc but not
337 * with others.
338 */
339#define MII_SET(x) \
340 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
341 CSR_READ_2(sc, XL_W4_PHY_MGMT) | x)
342
343#define MII_CLR(x) \
344 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
345 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~x)
346
347/*
348 * Sync the PHYs by setting data bit and strobing the clock 32 times.
349 */
350static void xl_mii_sync(sc)
351 struct xl_softc *sc;
352{
353 register int i;
354
355 XL_SEL_WIN(4);
356 MII_SET(XL_MII_DIR|XL_MII_DATA);
357
358 for (i = 0; i < 32; i++) {
359 MII_SET(XL_MII_CLK);
360 DELAY(1);
361 MII_CLR(XL_MII_CLK);
362 DELAY(1);
363 }
364
365 return;
366}
367
368/*
369 * Clock a series of bits through the MII.
370 */
371static void xl_mii_send(sc, bits, cnt)
372 struct xl_softc *sc;
373 u_int32_t bits;
374 int cnt;
375{
376 int i;
377
378 XL_SEL_WIN(4);
379 MII_CLR(XL_MII_CLK);
380
381 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
382 if (bits & i) {
383 MII_SET(XL_MII_DATA);
384 } else {
385 MII_CLR(XL_MII_DATA);
386 }
387 DELAY(1);
388 MII_CLR(XL_MII_CLK);
389 DELAY(1);
390 MII_SET(XL_MII_CLK);
391 }
392}
393
394/*
395 * Read an PHY register through the MII.
396 */
397static int xl_mii_readreg(sc, frame)
398 struct xl_softc *sc;
399 struct xl_mii_frame *frame;
400
401{
402 int i, ack;
403
404 XL_LOCK(sc);
405
406 /*
407 * Set up frame for RX.
408 */
409 frame->mii_stdelim = XL_MII_STARTDELIM;
410 frame->mii_opcode = XL_MII_READOP;
411 frame->mii_turnaround = 0;
412 frame->mii_data = 0;
413
414 /*
415 * Select register window 4.
416 */
417
418 XL_SEL_WIN(4);
419
420 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
421 /*
422 * Turn on data xmit.
423 */
424 MII_SET(XL_MII_DIR);
425
426 xl_mii_sync(sc);
427
428 /*
429 * Send command/address info.
430 */
431 xl_mii_send(sc, frame->mii_stdelim, 2);
432 xl_mii_send(sc, frame->mii_opcode, 2);
433 xl_mii_send(sc, frame->mii_phyaddr, 5);
434 xl_mii_send(sc, frame->mii_regaddr, 5);
435
436 /* Idle bit */
437 MII_CLR((XL_MII_CLK|XL_MII_DATA));
438 DELAY(1);
439 MII_SET(XL_MII_CLK);
440 DELAY(1);
441
442 /* Turn off xmit. */
443 MII_CLR(XL_MII_DIR);
444
445 /* Check for ack */
446 MII_CLR(XL_MII_CLK);
447 DELAY(1);
448 MII_SET(XL_MII_CLK);
449 DELAY(1);
450 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
451
452 /*
453 * Now try reading data bits. If the ack failed, we still
454 * need to clock through 16 cycles to keep the PHY(s) in sync.
455 */
456 if (ack) {
457 for(i = 0; i < 16; i++) {
458 MII_CLR(XL_MII_CLK);
459 DELAY(1);
460 MII_SET(XL_MII_CLK);
461 DELAY(1);
462 }
463 goto fail;
464 }
465
466 for (i = 0x8000; i; i >>= 1) {
467 MII_CLR(XL_MII_CLK);
468 DELAY(1);
469 if (!ack) {
470 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
471 frame->mii_data |= i;
472 DELAY(1);
473 }
474 MII_SET(XL_MII_CLK);
475 DELAY(1);
476 }
477
478fail:
479
480 MII_CLR(XL_MII_CLK);
481 DELAY(1);
482 MII_SET(XL_MII_CLK);
483 DELAY(1);
484
485 XL_UNLOCK(sc);
486
487 if (ack)
488 return(1);
489 return(0);
490}
491
492/*
493 * Write to a PHY register through the MII.
494 */
495static int xl_mii_writereg(sc, frame)
496 struct xl_softc *sc;
497 struct xl_mii_frame *frame;
498
499{
500 XL_LOCK(sc);
501
502 /*
503 * Set up frame for TX.
504 */
505
506 frame->mii_stdelim = XL_MII_STARTDELIM;
507 frame->mii_opcode = XL_MII_WRITEOP;
508 frame->mii_turnaround = XL_MII_TURNAROUND;
509
510 /*
511 * Select the window 4.
512 */
513 XL_SEL_WIN(4);
514
515 /*
516 * Turn on data output.
517 */
518 MII_SET(XL_MII_DIR);
519
520 xl_mii_sync(sc);
521
522 xl_mii_send(sc, frame->mii_stdelim, 2);
523 xl_mii_send(sc, frame->mii_opcode, 2);
524 xl_mii_send(sc, frame->mii_phyaddr, 5);
525 xl_mii_send(sc, frame->mii_regaddr, 5);
526 xl_mii_send(sc, frame->mii_turnaround, 2);
527 xl_mii_send(sc, frame->mii_data, 16);
528
529 /* Idle bit. */
530 MII_SET(XL_MII_CLK);
531 DELAY(1);
532 MII_CLR(XL_MII_CLK);
533 DELAY(1);
534
535 /*
536 * Turn off xmit.
537 */
538 MII_CLR(XL_MII_DIR);
539
540 XL_UNLOCK(sc);
541
542 return(0);
543}
544
545static int xl_miibus_readreg(dev, phy, reg)
546 device_t dev;
547 int phy, reg;
548{
549 struct xl_softc *sc;
550 struct xl_mii_frame frame;
551
552 sc = device_get_softc(dev);
553
554 /*
555 * Pretend that PHYs are only available at MII address 24.
556 * This is to guard against problems with certain 3Com ASIC
557 * revisions that incorrectly map the internal transceiver
558 * control registers at all MII addresses. This can cause
559 * the miibus code to attach the same PHY several times over.
560 */
561 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
562 return(0);
563
564 bzero((char *)&frame, sizeof(frame));
565
566 frame.mii_phyaddr = phy;
567 frame.mii_regaddr = reg;
568 xl_mii_readreg(sc, &frame);
569
570 return(frame.mii_data);
571}
572
573static int xl_miibus_writereg(dev, phy, reg, data)
574 device_t dev;
575 int phy, reg, data;
576{
577 struct xl_softc *sc;
578 struct xl_mii_frame frame;
579
580 sc = device_get_softc(dev);
581
582 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
583 return(0);
584
585 bzero((char *)&frame, sizeof(frame));
586
587 frame.mii_phyaddr = phy;
588 frame.mii_regaddr = reg;
589 frame.mii_data = data;
590
591 xl_mii_writereg(sc, &frame);
592
593 return(0);
594}
595
596static void xl_miibus_statchg(dev)
597 device_t dev;
598{
599 struct xl_softc *sc;
600 struct mii_data *mii;
601
602
603 sc = device_get_softc(dev);
604 mii = device_get_softc(sc->xl_miibus);
605
606 XL_LOCK(sc);
607
608 xl_setcfg(sc);
609
610 /* Set ASIC's duplex mode to match the PHY. */
611 XL_SEL_WIN(3);
612 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
613 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
614 else
615 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
616 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
617
618 XL_UNLOCK(sc);
619
620 return;
621}
622
623/*
624 * Special support for the 3c905B-COMBO. This card has 10/100 support
625 * plus BNC and AUI ports. This means we will have both an miibus attached
626 * plus some non-MII media settings. In order to allow this, we have to
627 * add the extra media to the miibus's ifmedia struct, but we can't do
628 * that during xl_attach() because the miibus hasn't been attached yet.
629 * So instead, we wait until the miibus probe/attach is done, at which
630 * point we will get a callback telling is that it's safe to add our
631 * extra media.
632 */
633static void xl_miibus_mediainit(dev)
634 device_t dev;
635{
636 struct xl_softc *sc;
637 struct mii_data *mii;
638 struct ifmedia *ifm;
639
640 sc = device_get_softc(dev);
641 mii = device_get_softc(sc->xl_miibus);
642 ifm = &mii->mii_media;
643
644 XL_LOCK(sc);
645
646 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
647 /*
648 * Check for a 10baseFL board in disguise.
649 */
650 if (sc->xl_type == XL_TYPE_905B &&
651 sc->xl_media == XL_MEDIAOPT_10FL) {
652 if (bootverbose)
653 printf("xl%d: found 10baseFL\n", sc->xl_unit);
654 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
655 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
656 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
657 ifmedia_add(ifm,
658 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
659 } else {
660 if (bootverbose)
661 printf("xl%d: found AUI\n", sc->xl_unit);
662 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
663 }
664 }
665
666 if (sc->xl_media & XL_MEDIAOPT_BNC) {
667 if (bootverbose)
668 printf("xl%d: found BNC\n", sc->xl_unit);
669 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
670 }
671
672 XL_UNLOCK(sc);
673
674 return;
675}
676
677/*
678 * The EEPROM is slow: give it time to come ready after issuing
679 * it a command.
680 */
681static int xl_eeprom_wait(sc)
682 struct xl_softc *sc;
683{
684 int i;
685
686 for (i = 0; i < 100; i++) {
687 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
688 DELAY(162);
689 else
690 break;
691 }
692
693 if (i == 100) {
694 printf("xl%d: eeprom failed to come ready\n", sc->xl_unit);
695 return(1);
696 }
697
698 return(0);
699}
700
701/*
702 * Read a sequence of words from the EEPROM. Note that ethernet address
703 * data is stored in the EEPROM in network byte order.
704 */
705static int xl_read_eeprom(sc, dest, off, cnt, swap)
706 struct xl_softc *sc;
707 caddr_t dest;
708 int off;
709 int cnt;
710 int swap;
711{
712 int err = 0, i;
713 u_int16_t word = 0, *ptr;
714#define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
715#define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
716 /* WARNING! DANGER!
717 * It's easy to accidentally overwrite the rom content!
718 * Note: the 3c575 uses 8bit EEPROM offsets.
719 */
720 XL_SEL_WIN(0);
721
722 if (xl_eeprom_wait(sc))
723 return(1);
724
725 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
726 off += 0x30;
727
728 for (i = 0; i < cnt; i++) {
729 if (sc->xl_flags & XL_FLAG_8BITROM)
730 CSR_WRITE_2(sc, XL_W0_EE_CMD,
731 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
732 else
733 CSR_WRITE_2(sc, XL_W0_EE_CMD,
734 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
735 err = xl_eeprom_wait(sc);
736 if (err)
737 break;
738 word = CSR_READ_2(sc, XL_W0_EE_DATA);
739 ptr = (u_int16_t *)(dest + (i * 2));
740 if (swap)
741 *ptr = ntohs(word);
742 else
743 *ptr = word;
744 }
745
746 return(err ? 1 : 0);
747}
748
749/*
750 * This routine is taken from the 3Com Etherlink XL manual,
751 * page 10-7. It calculates a CRC of the supplied multicast
752 * group address and returns the lower 8 bits, which are used
753 * as the multicast filter position.
754 * Note: the 3c905B currently only supports a 64-bit hash table,
755 * which means we really only need 6 bits, but the manual indicates
756 * that future chip revisions will have a 256-bit hash table,
757 * hence the routine is set up to calculate 8 bits of position
758 * info in case we need it some day.
759 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a
760 * 256 bit hash table. This means we have to use all 8 bits regardless.
761 * On older cards, the upper 2 bits will be ignored. Grrrr....
762 */
763static u_int8_t xl_calchash(addr)
764 caddr_t addr;
765{
766 u_int32_t crc, carry;
767 int i, j;
768 u_int8_t c;
769
770 /* Compute CRC for the address value. */
771 crc = 0xFFFFFFFF; /* initial value */
772
773 for (i = 0; i < 6; i++) {
774 c = *(addr + i);
775 for (j = 0; j < 8; j++) {
776 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
777 crc <<= 1;
778 c >>= 1;
779 if (carry)
780 crc = (crc ^ 0x04c11db6) | carry;
781 }
782 }
783
784 /* return the filter bit position */
785 return(crc & 0x000000FF);
786}
787
788/*
789 * NICs older than the 3c905B have only one multicast option, which
790 * is to enable reception of all multicast frames.
791 */
792static void xl_setmulti(sc)
793 struct xl_softc *sc;
794{
795 struct ifnet *ifp;
796 struct ifmultiaddr *ifma;
797 u_int8_t rxfilt;
798 int mcnt = 0;
799
800 ifp = &sc->arpcom.ac_if;
801
802 XL_SEL_WIN(5);
803 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
804
805 if (ifp->if_flags & IFF_ALLMULTI) {
806 rxfilt |= XL_RXFILTER_ALLMULTI;
807 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
808 return;
809 }
810
811 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
812 ifma = ifma->ifma_link.le_next)
813 mcnt++;
814
815 if (mcnt)
816 rxfilt |= XL_RXFILTER_ALLMULTI;
817 else
818 rxfilt &= ~XL_RXFILTER_ALLMULTI;
819
820 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
821
822 return;
823}
824
825/*
826 * 3c905B adapters have a hash filter that we can program.
827 */
828static void xl_setmulti_hash(sc)
829 struct xl_softc *sc;
830{
831 struct ifnet *ifp;
832 int h = 0, i;
833 struct ifmultiaddr *ifma;
834 u_int8_t rxfilt;
835 int mcnt = 0;
836
837 ifp = &sc->arpcom.ac_if;
838
839 XL_SEL_WIN(5);
840 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
841
842 if (ifp->if_flags & IFF_ALLMULTI) {
843 rxfilt |= XL_RXFILTER_ALLMULTI;
844 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
845 return;
846 } else
847 rxfilt &= ~XL_RXFILTER_ALLMULTI;
848
849
850 /* first, zot all the existing hash bits */
851 for (i = 0; i < XL_HASHFILT_SIZE; i++)
852 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
853
854 /* now program new ones */
855 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
856 ifma = ifma->ifma_link.le_next) {
857 if (ifma->ifma_addr->sa_family != AF_LINK)
858 continue;
859 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
860 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
861 mcnt++;
862 }
863
864 if (mcnt)
865 rxfilt |= XL_RXFILTER_MULTIHASH;
866 else
867 rxfilt &= ~XL_RXFILTER_MULTIHASH;
868
869 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
870
871 return;
872}
873
874#ifdef notdef
875static void xl_testpacket(sc)
876 struct xl_softc *sc;
877{
878 struct mbuf *m;
879 struct ifnet *ifp;
880
881 ifp = &sc->arpcom.ac_if;
882
883 MGETHDR(m, M_DONTWAIT, MT_DATA);
884
885 if (m == NULL)
886 return;
887
888 bcopy(&sc->arpcom.ac_enaddr,
889 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
890 bcopy(&sc->arpcom.ac_enaddr,
891 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
892 mtod(m, struct ether_header *)->ether_type = htons(3);
893 mtod(m, unsigned char *)[14] = 0;
894 mtod(m, unsigned char *)[15] = 0;
895 mtod(m, unsigned char *)[16] = 0xE3;
896 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
897 IF_ENQUEUE(&ifp->if_snd, m);
898 xl_start(ifp);
899
900 return;
901}
902#endif
903
904static void xl_setcfg(sc)
905 struct xl_softc *sc;
906{
907 u_int32_t icfg;
908
909 XL_SEL_WIN(3);
910 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
911 icfg &= ~XL_ICFG_CONNECTOR_MASK;
912 if (sc->xl_media & XL_MEDIAOPT_MII ||
913 sc->xl_media & XL_MEDIAOPT_BT4)
914 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
915 if (sc->xl_media & XL_MEDIAOPT_BTX)
916 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
917
918 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
919 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
920
921 return;
922}
923
924static void xl_setmode(sc, media)
925 struct xl_softc *sc;
926 int media;
927{
928 u_int32_t icfg;
929 u_int16_t mediastat;
930
931 printf("xl%d: selecting ", sc->xl_unit);
932
933 XL_SEL_WIN(4);
934 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
935 XL_SEL_WIN(3);
936 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
937
938 if (sc->xl_media & XL_MEDIAOPT_BT) {
939 if (IFM_SUBTYPE(media) == IFM_10_T) {
940 printf("10baseT transceiver, ");
941 sc->xl_xcvr = XL_XCVR_10BT;
942 icfg &= ~XL_ICFG_CONNECTOR_MASK;
943 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
944 mediastat |= XL_MEDIASTAT_LINKBEAT|
945 XL_MEDIASTAT_JABGUARD;
946 mediastat &= ~XL_MEDIASTAT_SQEENB;
947 }
948 }
949
950 if (sc->xl_media & XL_MEDIAOPT_BFX) {
951 if (IFM_SUBTYPE(media) == IFM_100_FX) {
952 printf("100baseFX port, ");
953 sc->xl_xcvr = XL_XCVR_100BFX;
954 icfg &= ~XL_ICFG_CONNECTOR_MASK;
955 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
956 mediastat |= XL_MEDIASTAT_LINKBEAT;
957 mediastat &= ~XL_MEDIASTAT_SQEENB;
958 }
959 }
960
961 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
962 if (IFM_SUBTYPE(media) == IFM_10_5) {
963 printf("AUI port, ");
964 sc->xl_xcvr = XL_XCVR_AUI;
965 icfg &= ~XL_ICFG_CONNECTOR_MASK;
966 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
967 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
968 XL_MEDIASTAT_JABGUARD);
969 mediastat |= ~XL_MEDIASTAT_SQEENB;
970 }
971 if (IFM_SUBTYPE(media) == IFM_10_FL) {
972 printf("10baseFL transceiver, ");
973 sc->xl_xcvr = XL_XCVR_AUI;
974 icfg &= ~XL_ICFG_CONNECTOR_MASK;
975 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
976 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
977 XL_MEDIASTAT_JABGUARD);
978 mediastat |= ~XL_MEDIASTAT_SQEENB;
979 }
980 }
981
982 if (sc->xl_media & XL_MEDIAOPT_BNC) {
983 if (IFM_SUBTYPE(media) == IFM_10_2) {
984 printf("BNC port, ");
985 sc->xl_xcvr = XL_XCVR_COAX;
986 icfg &= ~XL_ICFG_CONNECTOR_MASK;
987 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
988 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
989 XL_MEDIASTAT_JABGUARD|
990 XL_MEDIASTAT_SQEENB);
991 }
992 }
993
994 if ((media & IFM_GMASK) == IFM_FDX ||
995 IFM_SUBTYPE(media) == IFM_100_FX) {
996 printf("full duplex\n");
997 XL_SEL_WIN(3);
998 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
999 } else {
1000 printf("half duplex\n");
1001 XL_SEL_WIN(3);
1002 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
1003 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
1004 }
1005
1006 if (IFM_SUBTYPE(media) == IFM_10_2)
1007 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
1008 else
1009 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
1010 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
1011 XL_SEL_WIN(4);
1012 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
1013 DELAY(800);
1014 XL_SEL_WIN(7);
1015
1016 return;
1017}
1018
1019static void xl_reset(sc)
1020 struct xl_softc *sc;
1021{
1022 register int i;
1023
1024 XL_SEL_WIN(0);
1025 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
1026 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
1027 XL_RESETOPT_DISADVFD:0));
1028
1029 for (i = 0; i < XL_TIMEOUT; i++) {
1030 DELAY(10);
1031 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1032 break;
1033 }
1034
1035 if (i == XL_TIMEOUT)
1036 printf("xl%d: reset didn't complete\n", sc->xl_unit);
1037
1038 DELAY(100000);
1039
1040 /* Reset TX and RX. */
1041 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1042 xl_wait(sc);
1043 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1044 xl_wait(sc);
1045
1046 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1047 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1048 XL_SEL_WIN(2);
1049 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
1050 XL_W2_RESET_OPTIONS)
1051 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
1052 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
1053 );
1054 }
1055
1056 /* Wait a little while for the chip to get its brains in order. */
1057 DELAY(100000);
1058 return;
1059}
1060
1061/*
1062 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1063 * IDs against our list and return a device name if we find a match.
1064 */
1065static int xl_probe(dev)
1066 device_t dev;
1067{
1068 struct xl_type *t;
1069
1070 t = xl_devs;
1071
1072 while(t->xl_name != NULL) {
1073 if ((pci_get_vendor(dev) == t->xl_vid) &&
1074 (pci_get_device(dev) == t->xl_did)) {
1075 device_set_desc(dev, t->xl_name);
1076 return(0);
1077 }
1078 t++;
1079 }
1080
1081 return(ENXIO);
1082}
1083
1084/*
1085 * This routine is a kludge to work around possible hardware faults
1086 * or manufacturing defects that can cause the media options register
1087 * (or reset options register, as it's called for the first generation
1088 * 3c90x adapters) to return an incorrect result. I have encountered
1089 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1090 * which doesn't have any of the 'mediaopt' bits set. This screws up
1091 * the attach routine pretty badly because it doesn't know what media
1092 * to look for. If we find ourselves in this predicament, this routine
1093 * will try to guess the media options values and warn the user of a
1094 * possible manufacturing defect with his adapter/system/whatever.
1095 */
1096static void xl_mediacheck(sc)
1097 struct xl_softc *sc;
1098{
1099
1100 /*
1101 * If some of the media options bits are set, assume they are
1102 * correct. If not, try to figure it out down below.
1103 * XXX I should check for 10baseFL, but I don't have an adapter
1104 * to test with.
1105 */
1106 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1107 /*
1108 * Check the XCVR value. If it's not in the normal range
1109 * of values, we need to fake it up here.
1110 */
1111 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1112 return;
1113 else {
1114 printf("xl%d: bogus xcvr value "
1115 "in EEPROM (%x)\n", sc->xl_unit, sc->xl_xcvr);
1116 printf("xl%d: choosing new default based "
1117 "on card type\n", sc->xl_unit);
1118 }
1119 } else {
1120 if (sc->xl_type == XL_TYPE_905B &&
1121 sc->xl_media & XL_MEDIAOPT_10FL)
1122 return;
1123 printf("xl%d: WARNING: no media options bits set in "
1124 "the media options register!!\n", sc->xl_unit);
1125 printf("xl%d: this could be a manufacturing defect in "
1126 "your adapter or system\n", sc->xl_unit);
1127 printf("xl%d: attempting to guess media type; you "
1128 "should probably consult your vendor\n", sc->xl_unit);
1129 }
1130
1131 xl_choose_xcvr(sc, 1);
1132
1133 return;
1134}
1135
1136static void xl_choose_xcvr(sc, verbose)
1137 struct xl_softc *sc;
1138 int verbose;
1139{
1140 u_int16_t devid;
1141
1142 /*
1143 * Read the device ID from the EEPROM.
1144 * This is what's loaded into the PCI device ID register, so it has
1145 * to be correct otherwise we wouldn't have gotten this far.
1146 */
1147 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1148
1149 switch(devid) {
1150 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1151 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1152 sc->xl_media = XL_MEDIAOPT_BT;
1153 sc->xl_xcvr = XL_XCVR_10BT;
1154 if (verbose)
1155 printf("xl%d: guessing 10BaseT "
1156 "transceiver\n", sc->xl_unit);
1157 break;
1158 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1159 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1160 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1161 sc->xl_xcvr = XL_XCVR_10BT;
1162 if (verbose)
1163 printf("xl%d: guessing COMBO "
1164 "(AUI/BNC/TP)\n", sc->xl_unit);
1165 break;
1166 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1167 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1168 sc->xl_xcvr = XL_XCVR_10BT;
1169 if (verbose)
1170 printf("xl%d: guessing TPC (BNC/TP)\n", sc->xl_unit);
1171 break;
1172 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1173 sc->xl_media = XL_MEDIAOPT_10FL;
1174 sc->xl_xcvr = XL_XCVR_AUI;
1175 if (verbose)
1176 printf("xl%d: guessing 10baseFL\n", sc->xl_unit);
1177 break;
1178 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1179 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1180 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1181 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1182 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1183 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1184 case TC_DEVICEID_HURRICANE_656C: /* 3c565C */
1185 sc->xl_media = XL_MEDIAOPT_MII;
1186 sc->xl_xcvr = XL_XCVR_MII;
1187 if (verbose)
1188 printf("xl%d: guessing MII\n", sc->xl_unit);
1189 break;
1190 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1191 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1192 sc->xl_media = XL_MEDIAOPT_BT4;
1193 sc->xl_xcvr = XL_XCVR_MII;
1194 if (verbose)
1195 printf("xl%d: guessing 100BaseT4/MII\n", sc->xl_unit);
1196 break;
1197 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1198 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1199 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1200 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1201 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1202 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1203 sc->xl_media = XL_MEDIAOPT_BTX;
1204 sc->xl_xcvr = XL_XCVR_AUTO;
1205 if (verbose)
1206 printf("xl%d: guessing 10/100 internal\n", sc->xl_unit);
1207 break;
1208 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1209 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1210 sc->xl_xcvr = XL_XCVR_AUTO;
1211 if (verbose)
1212 printf("xl%d: guessing 10/100 "
1213 "plus BNC/AUI\n", sc->xl_unit);
1214 break;
1215 default:
1216 printf("xl%d: unknown device ID: %x -- "
1217 "defaulting to 10baseT\n", sc->xl_unit, devid);
1218 sc->xl_media = XL_MEDIAOPT_BT;
1219 break;
1220 }
1221
1222 return;
1223}
1224
1225/*
1226 * Attach the interface. Allocate softc structures, do ifmedia
1227 * setup and ethernet/BPF attach.
1228 */
1229static int xl_attach(dev)
1230 device_t dev;
1231{
1232 u_char eaddr[ETHER_ADDR_LEN];
1233 u_int32_t command;
1234 struct xl_softc *sc;
1235 struct ifnet *ifp;
1236 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1237 int unit, error = 0, rid;
1238
1239 sc = device_get_softc(dev);
1240 unit = device_get_unit(dev);
1241
|
| 1242 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_DEF);
1243 XL_LOCK(sc);
1244
|
1242 sc->xl_flags = 0;
1243 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 ||
1244 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1245 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1246 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1247 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1248 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556)
1249 sc->xl_flags |= XL_FLAG_8BITROM;
1250
1251 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A ||
1252 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B ||
1253 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C ||
1254 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656C)
1255 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1256 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM;
1257 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B)
1258 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1259 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C)
1260 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1261 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656C)
1262 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1263
1264 /*
1265 * If this is a 3c905B, we have to check one extra thing.
1266 * The 905B supports power management and may be placed in
1267 * a low-power mode (D3 mode), typically by certain operating
1268 * systems which shall not be named. The PCI BIOS is supposed
1269 * to reset the NIC and bring it out of low-power mode, but
1270 * some do not. Consequently, we have to see if this chip
1271 * supports power management, and if so, make sure it's not
1272 * in low-power mode. If power management is available, the
1273 * capid byte will be 0x01.
1274 *
1275 * I _think_ that what actually happens is that the chip
1276 * loses its PCI configuration during the transition from
1277 * D3 back to D0; this means that it should be possible for
1278 * us to save the PCI iobase, membase and IRQ, put the chip
1279 * back in the D0 state, then restore the PCI config ourselves.
1280 */
1281
1282 command = pci_read_config(dev, XL_PCI_CAPID, 4) & 0x000000FF;
1283 if (command == 0x01) {
1284
1285 command = pci_read_config(dev, XL_PCI_PWRMGMTCTRL, 4);
1286 if (command & XL_PSTATE_MASK) {
1287 u_int32_t iobase, membase, irq;
1288
1289 /* Save important PCI config data. */
1290 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1291 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1292 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1293
1294 /* Reset the power state. */
1295 printf("xl%d: chip is in D%d power mode "
1296 "-- setting to D0\n", unit, command & XL_PSTATE_MASK);
1297 command &= 0xFFFFFFFC;
1298 pci_write_config(dev, XL_PCI_PWRMGMTCTRL, command, 4);
1299
1300 /* Restore PCI config data. */
1301 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1302 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1303 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1304 }
1305 }
1306
1307 /*
1308 * Map control/status registers.
1309 */
1310 command = pci_read_config(dev, PCIR_COMMAND, 4);
1311 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1312 pci_write_config(dev, PCIR_COMMAND, command, 4);
1313 command = pci_read_config(dev, PCIR_COMMAND, 4);
1314
1315#ifdef XL_USEIOSPACE
1316 if (!(command & PCIM_CMD_PORTEN)) {
1317 printf("xl%d: failed to enable I/O ports!\n", unit);
1318 error = ENXIO;
1319 goto fail;
1320 }
1321#else
1322 if (!(command & PCIM_CMD_MEMEN)) {
1323 printf("xl%d: failed to enable memory mapping!\n", unit);
1324 error = ENXIO;
1325 goto fail;
1326 }
1327#endif
1328
1329 rid = XL_RID;
1330 sc->xl_res = bus_alloc_resource(dev, XL_RES, &rid,
1331 0, ~0, 1, RF_ACTIVE);
1332
1333 if (sc->xl_res == NULL) {
1334 printf ("xl%d: couldn't map ports/memory\n", unit);
1335 error = ENXIO;
1336 goto fail;
1337 }
1338
1339 sc->xl_btag = rman_get_bustag(sc->xl_res);
1340 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1341
1342 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1343 rid = XL_PCI_FUNCMEM;
1344 sc->xl_fres = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1345 0, ~0, 1, RF_ACTIVE);
1346
1347 if (sc->xl_fres == NULL) {
1348 printf ("xl%d: couldn't map ports/memory\n", unit);
1349 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1350 error = ENXIO;
1351 goto fail;
1352 }
1353
1354 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1355 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1356 }
1357
1358 rid = 0;
1359 sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1360 RF_SHAREABLE | RF_ACTIVE);
1361
1362 if (sc->xl_irq == NULL) {
1363 printf("xl%d: couldn't map interrupt\n", unit);
1364 if (sc->xl_fres != NULL)
1365 bus_release_resource(dev, SYS_RES_MEMORY,
1366 XL_PCI_FUNCMEM, sc->xl_fres);
1367 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1368 error = ENXIO;
1369 goto fail;
1370 }
1371
1372 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET,
1373 xl_intr, sc, &sc->xl_intrhand);
1374
1375 if (error) {
1376 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1377 if (sc->xl_fres != NULL)
1378 bus_release_resource(dev, SYS_RES_MEMORY,
1379 XL_PCI_FUNCMEM, sc->xl_fres);
1380 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1381 printf("xl%d: couldn't set up irq\n", unit);
1382 goto fail;
1383 }
1384
| 1245 sc->xl_flags = 0;
1246 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 ||
1247 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1248 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1249 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1250 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1251 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556)
1252 sc->xl_flags |= XL_FLAG_8BITROM;
1253
1254 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A ||
1255 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B ||
1256 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C ||
1257 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656C)
1258 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1259 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM;
1260 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B)
1261 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1262 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C)
1263 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1264 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656C)
1265 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1266
1267 /*
1268 * If this is a 3c905B, we have to check one extra thing.
1269 * The 905B supports power management and may be placed in
1270 * a low-power mode (D3 mode), typically by certain operating
1271 * systems which shall not be named. The PCI BIOS is supposed
1272 * to reset the NIC and bring it out of low-power mode, but
1273 * some do not. Consequently, we have to see if this chip
1274 * supports power management, and if so, make sure it's not
1275 * in low-power mode. If power management is available, the
1276 * capid byte will be 0x01.
1277 *
1278 * I _think_ that what actually happens is that the chip
1279 * loses its PCI configuration during the transition from
1280 * D3 back to D0; this means that it should be possible for
1281 * us to save the PCI iobase, membase and IRQ, put the chip
1282 * back in the D0 state, then restore the PCI config ourselves.
1283 */
1284
1285 command = pci_read_config(dev, XL_PCI_CAPID, 4) & 0x000000FF;
1286 if (command == 0x01) {
1287
1288 command = pci_read_config(dev, XL_PCI_PWRMGMTCTRL, 4);
1289 if (command & XL_PSTATE_MASK) {
1290 u_int32_t iobase, membase, irq;
1291
1292 /* Save important PCI config data. */
1293 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1294 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1295 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1296
1297 /* Reset the power state. */
1298 printf("xl%d: chip is in D%d power mode "
1299 "-- setting to D0\n", unit, command & XL_PSTATE_MASK);
1300 command &= 0xFFFFFFFC;
1301 pci_write_config(dev, XL_PCI_PWRMGMTCTRL, command, 4);
1302
1303 /* Restore PCI config data. */
1304 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1305 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1306 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1307 }
1308 }
1309
1310 /*
1311 * Map control/status registers.
1312 */
1313 command = pci_read_config(dev, PCIR_COMMAND, 4);
1314 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1315 pci_write_config(dev, PCIR_COMMAND, command, 4);
1316 command = pci_read_config(dev, PCIR_COMMAND, 4);
1317
1318#ifdef XL_USEIOSPACE
1319 if (!(command & PCIM_CMD_PORTEN)) {
1320 printf("xl%d: failed to enable I/O ports!\n", unit);
1321 error = ENXIO;
1322 goto fail;
1323 }
1324#else
1325 if (!(command & PCIM_CMD_MEMEN)) {
1326 printf("xl%d: failed to enable memory mapping!\n", unit);
1327 error = ENXIO;
1328 goto fail;
1329 }
1330#endif
1331
1332 rid = XL_RID;
1333 sc->xl_res = bus_alloc_resource(dev, XL_RES, &rid,
1334 0, ~0, 1, RF_ACTIVE);
1335
1336 if (sc->xl_res == NULL) {
1337 printf ("xl%d: couldn't map ports/memory\n", unit);
1338 error = ENXIO;
1339 goto fail;
1340 }
1341
1342 sc->xl_btag = rman_get_bustag(sc->xl_res);
1343 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1344
1345 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1346 rid = XL_PCI_FUNCMEM;
1347 sc->xl_fres = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1348 0, ~0, 1, RF_ACTIVE);
1349
1350 if (sc->xl_fres == NULL) {
1351 printf ("xl%d: couldn't map ports/memory\n", unit);
1352 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1353 error = ENXIO;
1354 goto fail;
1355 }
1356
1357 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1358 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1359 }
1360
1361 rid = 0;
1362 sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1363 RF_SHAREABLE | RF_ACTIVE);
1364
1365 if (sc->xl_irq == NULL) {
1366 printf("xl%d: couldn't map interrupt\n", unit);
1367 if (sc->xl_fres != NULL)
1368 bus_release_resource(dev, SYS_RES_MEMORY,
1369 XL_PCI_FUNCMEM, sc->xl_fres);
1370 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1371 error = ENXIO;
1372 goto fail;
1373 }
1374
1375 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET,
1376 xl_intr, sc, &sc->xl_intrhand);
1377
1378 if (error) {
1379 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1380 if (sc->xl_fres != NULL)
1381 bus_release_resource(dev, SYS_RES_MEMORY,
1382 XL_PCI_FUNCMEM, sc->xl_fres);
1383 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1384 printf("xl%d: couldn't set up irq\n", unit);
1385 goto fail;
1386 }
1387
|
1385 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_DEF);
1386 XL_LOCK(sc);
1387
| |
1388 /* Reset the adapter. */
1389 xl_reset(sc);
1390
1391 /*
1392 * Get station address from the EEPROM.
1393 */
1394 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1395 printf("xl%d: failed to read station address\n", sc->xl_unit);
1396 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1397 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1398 if (sc->xl_fres != NULL)
1399 bus_release_resource(dev, SYS_RES_MEMORY,
1400 XL_PCI_FUNCMEM, sc->xl_fres);
1401 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1402 error = ENXIO;
1403 goto fail;
1404 }
1405
1406 /*
1407 * A 3Com chip was detected. Inform the world.
1408 */
1409 printf("xl%d: Ethernet address: %6D\n", unit, eaddr, ":");
1410
1411 sc->xl_unit = unit;
1412 callout_handle_init(&sc->xl_stat_ch);
1413 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1414
1415 sc->xl_ldata = contigmalloc(sizeof(struct xl_list_data), M_DEVBUF,
1416 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1417
1418 if (sc->xl_ldata == NULL) {
1419 printf("xl%d: no memory for list buffers!\n", unit);
1420 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1421 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1422 if (sc->xl_fres != NULL)
1423 bus_release_resource(dev, SYS_RES_MEMORY,
1424 XL_PCI_FUNCMEM, sc->xl_fres);
1425 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1426 error = ENXIO;
1427 goto fail;
1428 }
1429
1430 bzero(sc->xl_ldata, sizeof(struct xl_list_data));
1431
1432 /*
1433 * Figure out the card type. 3c905B adapters have the
1434 * 'supportsNoTxLength' bit set in the capabilities
1435 * word in the EEPROM.
1436 */
1437 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1438 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH)
1439 sc->xl_type = XL_TYPE_905B;
1440 else
1441 sc->xl_type = XL_TYPE_90X;
1442
1443 ifp = &sc->arpcom.ac_if;
1444 ifp->if_softc = sc;
1445 ifp->if_unit = unit;
1446 ifp->if_name = "xl";
1447 ifp->if_mtu = ETHERMTU;
1448 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1449 ifp->if_ioctl = xl_ioctl;
1450 ifp->if_output = ether_output;
1451 if (sc->xl_type == XL_TYPE_905B)
1452 ifp->if_start = xl_start_90xB;
1453 else
1454 ifp->if_start = xl_start;
1455 ifp->if_watchdog = xl_watchdog;
1456 ifp->if_init = xl_init;
1457 ifp->if_baudrate = 10000000;
1458 ifp->if_snd.ifq_maxlen = XL_TX_LIST_CNT - 1;
1459
1460 /*
1461 * Now we have to see what sort of media we have.
1462 * This includes probing for an MII interace and a
1463 * possible PHY.
1464 */
1465 XL_SEL_WIN(3);
1466 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1467 if (bootverbose)
1468 printf("xl%d: media options word: %x\n", sc->xl_unit,
1469 sc->xl_media);
1470
1471 xl_read_eeprom(sc, (char *)&sc->xl_xcvr, XL_EE_ICFG_0, 2, 0);
1472 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1473 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1474
1475 xl_mediacheck(sc);
1476
1477 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1478 || sc->xl_media & XL_MEDIAOPT_BT4) {
1479 if (bootverbose)
1480 printf("xl%d: found MII/AUTO\n", sc->xl_unit);
1481 xl_setcfg(sc);
1482 if (mii_phy_probe(dev, &sc->xl_miibus,
1483 xl_ifmedia_upd, xl_ifmedia_sts)) {
1484 printf("xl%d: no PHY found!\n", sc->xl_unit);
1485 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1486 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1487 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1488 contigfree(sc->xl_ldata,
1489 sizeof(struct xl_list_data), M_DEVBUF);
1490 error = ENXIO;
1491 goto fail;
1492 }
1493
1494 goto done;
1495 }
1496
1497 /*
1498 * Sanity check. If the user has selected "auto" and this isn't
1499 * a 10/100 card of some kind, we need to force the transceiver
1500 * type to something sane.
1501 */
1502 if (sc->xl_xcvr == XL_XCVR_AUTO)
1503 xl_choose_xcvr(sc, bootverbose);
1504
1505 /*
1506 * Do ifmedia setup.
1507 */
1508
1509 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1510
1511 if (sc->xl_media & XL_MEDIAOPT_BT) {
1512 if (bootverbose)
1513 printf("xl%d: found 10baseT\n", sc->xl_unit);
1514 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1515 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1516 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1517 ifmedia_add(&sc->ifmedia,
1518 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1519 }
1520
1521 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1522 /*
1523 * Check for a 10baseFL board in disguise.
1524 */
1525 if (sc->xl_type == XL_TYPE_905B &&
1526 sc->xl_media == XL_MEDIAOPT_10FL) {
1527 if (bootverbose)
1528 printf("xl%d: found 10baseFL\n", sc->xl_unit);
1529 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1530 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1531 0, NULL);
1532 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1533 ifmedia_add(&sc->ifmedia,
1534 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1535 } else {
1536 if (bootverbose)
1537 printf("xl%d: found AUI\n", sc->xl_unit);
1538 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1539 }
1540 }
1541
1542 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1543 if (bootverbose)
1544 printf("xl%d: found BNC\n", sc->xl_unit);
1545 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1546 }
1547
1548 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1549 if (bootverbose)
1550 printf("xl%d: found 100baseFX\n", sc->xl_unit);
1551 ifp->if_baudrate = 100000000;
1552 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1553 }
1554
1555 /* Choose a default media. */
1556 switch(sc->xl_xcvr) {
1557 case XL_XCVR_10BT:
1558 media = IFM_ETHER|IFM_10_T;
1559 xl_setmode(sc, media);
1560 break;
1561 case XL_XCVR_AUI:
1562 if (sc->xl_type == XL_TYPE_905B &&
1563 sc->xl_media == XL_MEDIAOPT_10FL) {
1564 media = IFM_ETHER|IFM_10_FL;
1565 xl_setmode(sc, media);
1566 } else {
1567 media = IFM_ETHER|IFM_10_5;
1568 xl_setmode(sc, media);
1569 }
1570 break;
1571 case XL_XCVR_COAX:
1572 media = IFM_ETHER|IFM_10_2;
1573 xl_setmode(sc, media);
1574 break;
1575 case XL_XCVR_AUTO:
1576 case XL_XCVR_100BTX:
1577 case XL_XCVR_MII:
1578 /* Chosen by miibus */
1579 break;
1580 case XL_XCVR_100BFX:
1581 media = IFM_ETHER|IFM_100_FX;
1582 break;
1583 default:
1584 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit,
1585 sc->xl_xcvr);
1586 /*
1587 * This will probably be wrong, but it prevents
1588 * the ifmedia code from panicking.
1589 */
1590 media = IFM_ETHER|IFM_10_T;
1591 break;
1592 }
1593
1594 if (sc->xl_miibus == NULL)
1595 ifmedia_set(&sc->ifmedia, media);
1596
1597done:
1598
1599 /*
1600 * Call MI attach routine.
1601 */
1602 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1603 XL_UNLOCK(sc);
1604 return(0);
1605
1606fail:
1607 XL_UNLOCK(sc);
1608 mtx_destroy(&sc->xl_mtx);
1609
1610 return(error);
1611}
1612
1613static int xl_detach(dev)
1614 device_t dev;
1615{
1616 struct xl_softc *sc;
1617 struct ifnet *ifp;
1618
1619 sc = device_get_softc(dev);
1620 XL_LOCK(sc);
1621 ifp = &sc->arpcom.ac_if;
1622
1623 xl_reset(sc);
1624 xl_stop(sc);
1625 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1626
1627 /* Delete any miibus and phy devices attached to this interface */
1628 if (sc->xl_miibus != NULL) {
1629 bus_generic_detach(dev);
1630 device_delete_child(dev, sc->xl_miibus);
1631 }
1632
1633 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1634 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1635 if (sc->xl_fres != NULL)
1636 bus_release_resource(dev, SYS_RES_MEMORY,
1637 XL_PCI_FUNCMEM, sc->xl_fres);
1638 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1639
1640 ifmedia_removeall(&sc->ifmedia);
1641 contigfree(sc->xl_ldata, sizeof(struct xl_list_data), M_DEVBUF);
1642
1643 XL_UNLOCK(sc);
1644 mtx_destroy(&sc->xl_mtx);
1645
1646 return(0);
1647}
1648
1649/*
1650 * Initialize the transmit descriptors.
1651 */
1652static int xl_list_tx_init(sc)
1653 struct xl_softc *sc;
1654{
1655 struct xl_chain_data *cd;
1656 struct xl_list_data *ld;
1657 int i;
1658
1659 cd = &sc->xl_cdata;
1660 ld = sc->xl_ldata;
1661 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1662 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1663 if (i == (XL_TX_LIST_CNT - 1))
1664 cd->xl_tx_chain[i].xl_next = NULL;
1665 else
1666 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1667 }
1668
1669 cd->xl_tx_free = &cd->xl_tx_chain[0];
1670 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1671
1672 return(0);
1673}
1674
1675/*
1676 * Initialize the transmit descriptors.
1677 */
1678static int xl_list_tx_init_90xB(sc)
1679 struct xl_softc *sc;
1680{
1681 struct xl_chain_data *cd;
1682 struct xl_list_data *ld;
1683 int i;
1684
1685 cd = &sc->xl_cdata;
1686 ld = sc->xl_ldata;
1687 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1688 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1689 cd->xl_tx_chain[i].xl_phys = vtophys(&ld->xl_tx_list[i]);
1690 if (i == (XL_TX_LIST_CNT - 1))
1691 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1692 else
1693 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1694 if (i == 0)
1695 cd->xl_tx_chain[i].xl_prev =
1696 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1697 else
1698 cd->xl_tx_chain[i].xl_prev =
1699 &cd->xl_tx_chain[i - 1];
1700 }
1701
1702 bzero((char *)ld->xl_tx_list,
1703 sizeof(struct xl_list) * XL_TX_LIST_CNT);
1704 ld->xl_tx_list[0].xl_status = XL_TXSTAT_EMPTY;
1705
1706 cd->xl_tx_prod = 1;
1707 cd->xl_tx_cons = 1;
1708 cd->xl_tx_cnt = 0;
1709
1710 return(0);
1711}
1712
1713/*
1714 * Initialize the RX descriptors and allocate mbufs for them. Note that
1715 * we arrange the descriptors in a closed ring, so that the last descriptor
1716 * points back to the first.
1717 */
1718static int xl_list_rx_init(sc)
1719 struct xl_softc *sc;
1720{
1721 struct xl_chain_data *cd;
1722 struct xl_list_data *ld;
1723 int i;
1724
1725 cd = &sc->xl_cdata;
1726 ld = sc->xl_ldata;
1727
1728 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1729 cd->xl_rx_chain[i].xl_ptr =
1730 (struct xl_list_onefrag *)&ld->xl_rx_list[i];
1731 if (xl_newbuf(sc, &cd->xl_rx_chain[i]) == ENOBUFS)
1732 return(ENOBUFS);
1733 if (i == (XL_RX_LIST_CNT - 1)) {
1734 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[0];
1735 ld->xl_rx_list[i].xl_next =
1736 vtophys(&ld->xl_rx_list[0]);
1737 } else {
1738 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[i + 1];
1739 ld->xl_rx_list[i].xl_next =
1740 vtophys(&ld->xl_rx_list[i + 1]);
1741 }
1742 }
1743
1744 cd->xl_rx_head = &cd->xl_rx_chain[0];
1745
1746 return(0);
1747}
1748
1749/*
1750 * Initialize an RX descriptor and attach an MBUF cluster.
1751 */
1752static int xl_newbuf(sc, c)
1753 struct xl_softc *sc;
1754 struct xl_chain_onefrag *c;
1755{
1756 struct mbuf *m_new = NULL;
1757
1758 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1759 if (m_new == NULL) {
1760 printf("xl%d: no memory for rx list -- "
1761 "packet dropped!\n", sc->xl_unit);
1762 return(ENOBUFS);
1763 }
1764
1765 MCLGET(m_new, M_DONTWAIT);
1766 if (!(m_new->m_flags & M_EXT)) {
1767 printf("xl%d: no memory for rx list -- "
1768 "packet dropped!\n", sc->xl_unit);
1769 m_freem(m_new);
1770 return(ENOBUFS);
1771 }
1772
1773 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1774
1775 /* Force longword alignment for packet payload. */
1776 m_adj(m_new, ETHER_ALIGN);
1777
1778 c->xl_mbuf = m_new;
1779 c->xl_ptr->xl_frag.xl_addr = vtophys(mtod(m_new, caddr_t));
1780 c->xl_ptr->xl_frag.xl_len = MCLBYTES | XL_LAST_FRAG;
1781 c->xl_ptr->xl_status = 0;
1782
1783 return(0);
1784}
1785
1786static int xl_rx_resync(sc)
1787 struct xl_softc *sc;
1788{
1789 struct xl_chain_onefrag *pos;
1790 int i;
1791
1792 pos = sc->xl_cdata.xl_rx_head;
1793
1794 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1795 if (pos->xl_ptr->xl_status)
1796 break;
1797 pos = pos->xl_next;
1798 }
1799
1800 if (i == XL_RX_LIST_CNT)
1801 return(0);
1802
1803 sc->xl_cdata.xl_rx_head = pos;
1804
1805 return(EAGAIN);
1806}
1807
1808/*
1809 * A frame has been uploaded: pass the resulting mbuf chain up to
1810 * the higher level protocols.
1811 */
1812static void xl_rxeof(sc)
1813 struct xl_softc *sc;
1814{
1815 struct ether_header *eh;
1816 struct mbuf *m;
1817 struct ifnet *ifp;
1818 struct xl_chain_onefrag *cur_rx;
1819 int total_len = 0;
1820 u_int16_t rxstat;
1821
1822 ifp = &sc->arpcom.ac_if;
1823
1824again:
1825
1826 while((rxstat = sc->xl_cdata.xl_rx_head->xl_ptr->xl_status)) {
1827 cur_rx = sc->xl_cdata.xl_rx_head;
1828 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1829
1830 /*
1831 * If an error occurs, update stats, clear the
1832 * status word and leave the mbuf cluster in place:
1833 * it should simply get re-used next time this descriptor
1834 * comes up in the ring.
1835 */
1836 if (rxstat & XL_RXSTAT_UP_ERROR) {
1837 ifp->if_ierrors++;
1838 cur_rx->xl_ptr->xl_status = 0;
1839 continue;
1840 }
1841
1842 /*
1843 * If there error bit was not set, the upload complete
1844 * bit should be set which means we have a valid packet.
1845 * If not, something truly strange has happened.
1846 */
1847 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1848 printf("xl%d: bad receive status -- "
1849 "packet dropped", sc->xl_unit);
1850 ifp->if_ierrors++;
1851 cur_rx->xl_ptr->xl_status = 0;
1852 continue;
1853 }
1854
1855 /* No errors; receive the packet. */
1856 m = cur_rx->xl_mbuf;
1857 total_len = cur_rx->xl_ptr->xl_status & XL_RXSTAT_LENMASK;
1858
1859 /*
1860 * Try to conjure up a new mbuf cluster. If that
1861 * fails, it means we have an out of memory condition and
1862 * should leave the buffer in place and continue. This will
1863 * result in a lost packet, but there's little else we
1864 * can do in this situation.
1865 */
1866 if (xl_newbuf(sc, cur_rx) == ENOBUFS) {
1867 ifp->if_ierrors++;
1868 cur_rx->xl_ptr->xl_status = 0;
1869 continue;
1870 }
1871
1872 ifp->if_ipackets++;
1873 eh = mtod(m, struct ether_header *);
1874 m->m_pkthdr.rcvif = ifp;
1875 m->m_pkthdr.len = m->m_len = total_len;
1876
1877 /* Remove header from mbuf and pass it on. */
1878 m_adj(m, sizeof(struct ether_header));
1879 ether_input(ifp, eh, m);
1880 }
1881
1882 /*
1883 * Handle the 'end of channel' condition. When the upload
1884 * engine hits the end of the RX ring, it will stall. This
1885 * is our cue to flush the RX ring, reload the uplist pointer
1886 * register and unstall the engine.
1887 * XXX This is actually a little goofy. With the ThunderLAN
1888 * chip, you get an interrupt when the receiver hits the end
1889 * of the receive ring, which tells you exactly when you
1890 * you need to reload the ring pointer. Here we have to
1891 * fake it. I'm mad at myself for not being clever enough
1892 * to avoid the use of a goto here.
1893 */
1894 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
1895 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
1896 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1897 xl_wait(sc);
1898 CSR_WRITE_4(sc, XL_UPLIST_PTR,
1899 vtophys(&sc->xl_ldata->xl_rx_list[0]));
1900 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
1901 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1902 goto again;
1903 }
1904
1905 return;
1906}
1907
1908/*
1909 * A frame was downloaded to the chip. It's safe for us to clean up
1910 * the list buffers.
1911 */
1912static void xl_txeof(sc)
1913 struct xl_softc *sc;
1914{
1915 struct xl_chain *cur_tx;
1916 struct ifnet *ifp;
1917
1918 ifp = &sc->arpcom.ac_if;
1919
1920 /* Clear the timeout timer. */
1921 ifp->if_timer = 0;
1922
1923 /*
1924 * Go through our tx list and free mbufs for those
1925 * frames that have been uploaded. Note: the 3c905B
1926 * sets a special bit in the status word to let us
1927 * know that a frame has been downloaded, but the
1928 * original 3c900/3c905 adapters don't do that.
1929 * Consequently, we have to use a different test if
1930 * xl_type != XL_TYPE_905B.
1931 */
1932 while(sc->xl_cdata.xl_tx_head != NULL) {
1933 cur_tx = sc->xl_cdata.xl_tx_head;
1934
1935 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
1936 break;
1937
1938 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
1939 m_freem(cur_tx->xl_mbuf);
1940 cur_tx->xl_mbuf = NULL;
1941 ifp->if_opackets++;
1942
1943 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
1944 sc->xl_cdata.xl_tx_free = cur_tx;
1945 }
1946
1947 if (sc->xl_cdata.xl_tx_head == NULL) {
1948 ifp->if_flags &= ~IFF_OACTIVE;
1949 sc->xl_cdata.xl_tx_tail = NULL;
1950 } else {
1951 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
1952 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
1953 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
1954 vtophys(sc->xl_cdata.xl_tx_head->xl_ptr));
1955 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
1956 }
1957 }
1958
1959 return;
1960}
1961
1962static void xl_txeof_90xB(sc)
1963 struct xl_softc *sc;
1964{
1965 struct xl_chain *cur_tx = NULL;
1966 struct ifnet *ifp;
1967 int idx;
1968
1969 ifp = &sc->arpcom.ac_if;
1970
1971 idx = sc->xl_cdata.xl_tx_cons;
1972 while(idx != sc->xl_cdata.xl_tx_prod) {
1973
1974 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
1975
1976 if (!(cur_tx->xl_ptr->xl_status & XL_TXSTAT_DL_COMPLETE))
1977 break;
1978
1979 if (cur_tx->xl_mbuf != NULL) {
1980 m_freem(cur_tx->xl_mbuf);
1981 cur_tx->xl_mbuf = NULL;
1982 }
1983
1984 ifp->if_opackets++;
1985
1986 sc->xl_cdata.xl_tx_cnt--;
1987 XL_INC(idx, XL_TX_LIST_CNT);
1988 ifp->if_timer = 0;
1989 }
1990
1991 sc->xl_cdata.xl_tx_cons = idx;
1992
1993 if (cur_tx != NULL)
1994 ifp->if_flags &= ~IFF_OACTIVE;
1995
1996 return;
1997}
1998
1999/*
2000 * TX 'end of channel' interrupt handler. Actually, we should
2001 * only get a 'TX complete' interrupt if there's a transmit error,
2002 * so this is really TX error handler.
2003 */
2004static void xl_txeoc(sc)
2005 struct xl_softc *sc;
2006{
2007 u_int8_t txstat;
2008
2009 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2010 if (txstat & XL_TXSTATUS_UNDERRUN ||
2011 txstat & XL_TXSTATUS_JABBER ||
2012 txstat & XL_TXSTATUS_RECLAIM) {
2013 printf("xl%d: transmission error: %x\n",
2014 sc->xl_unit, txstat);
2015 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2016 xl_wait(sc);
2017 if (sc->xl_type == XL_TYPE_905B) {
2018 if (sc->xl_cdata.xl_tx_cnt) {
2019 int i;
2020 struct xl_chain *c;
2021 i = sc->xl_cdata.xl_tx_cons;
2022 c = &sc->xl_cdata.xl_tx_chain[i];
2023 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2024 c->xl_phys);
2025 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2026 }
2027 } else {
2028 if (sc->xl_cdata.xl_tx_head != NULL)
2029 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2030 vtophys(sc->xl_cdata.xl_tx_head->xl_ptr));
2031 }
2032 /*
2033 * Remember to set this for the
2034 * first generation 3c90X chips.
2035 */
2036 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2037 if (txstat & XL_TXSTATUS_UNDERRUN &&
2038 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2039 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2040 printf("xl%d: tx underrun, increasing tx start"
2041 " threshold to %d bytes\n", sc->xl_unit,
2042 sc->xl_tx_thresh);
2043 }
2044 CSR_WRITE_2(sc, XL_COMMAND,
2045 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2046 if (sc->xl_type == XL_TYPE_905B) {
2047 CSR_WRITE_2(sc, XL_COMMAND,
2048 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2049 }
2050 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2051 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2052 } else {
2053 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2054 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2055 }
2056 /*
2057 * Write an arbitrary byte to the TX_STATUS register
2058 * to clear this interrupt/error and advance to the next.
2059 */
2060 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2061 }
2062
2063 return;
2064}
2065
2066static void xl_intr(arg)
2067 void *arg;
2068{
2069 struct xl_softc *sc;
2070 struct ifnet *ifp;
2071 u_int16_t status;
2072
2073 sc = arg;
2074 XL_LOCK(sc);
2075 ifp = &sc->arpcom.ac_if;
2076
2077 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) {
2078
2079 CSR_WRITE_2(sc, XL_COMMAND,
2080 XL_CMD_INTR_ACK|(status & XL_INTRS));
2081
2082 if (status & XL_STAT_UP_COMPLETE) {
2083 int curpkts;
2084
2085 curpkts = ifp->if_ipackets;
2086 xl_rxeof(sc);
2087 if (curpkts == ifp->if_ipackets) {
2088 while (xl_rx_resync(sc))
2089 xl_rxeof(sc);
2090 }
2091 }
2092
2093 if (status & XL_STAT_DOWN_COMPLETE) {
2094 if (sc->xl_type == XL_TYPE_905B)
2095 xl_txeof_90xB(sc);
2096 else
2097 xl_txeof(sc);
2098 }
2099
2100 if (status & XL_STAT_TX_COMPLETE) {
2101 ifp->if_oerrors++;
2102 xl_txeoc(sc);
2103 }
2104
2105 if (status & XL_STAT_ADFAIL) {
2106 xl_reset(sc);
2107 xl_init(sc);
2108 }
2109
2110 if (status & XL_STAT_STATSOFLOW) {
2111 sc->xl_stats_no_timeout = 1;
2112 xl_stats_update(sc);
2113 sc->xl_stats_no_timeout = 0;
2114 }
2115 }
2116
2117 if (ifp->if_snd.ifq_head != NULL)
2118 (*ifp->if_start)(ifp);
2119
2120 XL_UNLOCK(sc);
2121
2122 return;
2123}
2124
2125static void xl_stats_update(xsc)
2126 void *xsc;
2127{
2128 struct xl_softc *sc;
2129 struct ifnet *ifp;
2130 struct xl_stats xl_stats;
2131 u_int8_t *p;
2132 int i;
2133 struct mii_data *mii = NULL;
2134
2135 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2136
2137 sc = xsc;
2138 ifp = &sc->arpcom.ac_if;
2139 if (sc->xl_miibus != NULL)
2140 mii = device_get_softc(sc->xl_miibus);
2141
2142 p = (u_int8_t *)&xl_stats;
2143
2144 /* Read all the stats registers. */
2145 XL_SEL_WIN(6);
2146
2147 for (i = 0; i < 16; i++)
2148 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2149
2150 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2151
2152 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2153 xl_stats.xl_tx_single_collision +
2154 xl_stats.xl_tx_late_collision;
2155
2156 /*
2157 * Boomerang and cyclone chips have an extra stats counter
2158 * in window 4 (BadSSD). We have to read this too in order
2159 * to clear out all the stats registers and avoid a statsoflow
2160 * interrupt.
2161 */
2162 XL_SEL_WIN(4);
2163 CSR_READ_1(sc, XL_W4_BADSSD);
2164
2165 if (mii != NULL)
2166 mii_tick(mii);
2167
2168 XL_SEL_WIN(7);
2169
2170 if (!sc->xl_stats_no_timeout)
2171 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2172
2173 return;
2174}
2175
2176/*
2177 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2178 * pointers to the fragment pointers.
2179 */
2180static int xl_encap(sc, c, m_head)
2181 struct xl_softc *sc;
2182 struct xl_chain *c;
2183 struct mbuf *m_head;
2184{
2185 int frag = 0;
2186 struct xl_frag *f = NULL;
2187 int total_len;
2188 struct mbuf *m;
2189
2190 /*
2191 * Start packing the mbufs in this chain into
2192 * the fragment pointers. Stop when we run out
2193 * of fragments or hit the end of the mbuf chain.
2194 */
2195 m = m_head;
2196 total_len = 0;
2197
2198 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
2199 if (m->m_len != 0) {
2200 if (frag == XL_MAXFRAGS)
2201 break;
2202 total_len+= m->m_len;
2203 c->xl_ptr->xl_frag[frag].xl_addr =
2204 vtophys(mtod(m, vm_offset_t));
2205 c->xl_ptr->xl_frag[frag].xl_len = m->m_len;
2206 frag++;
2207 }
2208 }
2209
2210 /*
2211 * Handle special case: we used up all 63 fragments,
2212 * but we have more mbufs left in the chain. Copy the
2213 * data into an mbuf cluster. Note that we don't
2214 * bother clearing the values in the other fragment
2215 * pointers/counters; it wouldn't gain us anything,
2216 * and would waste cycles.
2217 */
2218 if (m != NULL) {
2219 struct mbuf *m_new = NULL;
2220
2221 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
2222 if (m_new == NULL) {
2223 printf("xl%d: no memory for tx list", sc->xl_unit);
2224 return(1);
2225 }
2226 if (m_head->m_pkthdr.len > MHLEN) {
2227 MCLGET(m_new, M_DONTWAIT);
2228 if (!(m_new->m_flags & M_EXT)) {
2229 m_freem(m_new);
2230 printf("xl%d: no memory for tx list",
2231 sc->xl_unit);
2232 return(1);
2233 }
2234 }
2235 m_copydata(m_head, 0, m_head->m_pkthdr.len,
2236 mtod(m_new, caddr_t));
2237 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
2238 m_freem(m_head);
2239 m_head = m_new;
2240 f = &c->xl_ptr->xl_frag[0];
2241 f->xl_addr = vtophys(mtod(m_new, caddr_t));
2242 f->xl_len = total_len = m_new->m_len;
2243 frag = 1;
2244 }
2245
2246 c->xl_mbuf = m_head;
2247 c->xl_ptr->xl_frag[frag - 1].xl_len |= XL_LAST_FRAG;
2248 c->xl_ptr->xl_status = total_len;
2249 c->xl_ptr->xl_next = 0;
2250
2251 return(0);
2252}
2253
2254/*
2255 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2256 * to the mbuf data regions directly in the transmit lists. We also save a
2257 * copy of the pointers since the transmit list fragment pointers are
2258 * physical addresses.
2259 */
2260static void xl_start(ifp)
2261 struct ifnet *ifp;
2262{
2263 struct xl_softc *sc;
2264 struct mbuf *m_head = NULL;
2265 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2266
2267 sc = ifp->if_softc;
2268 XL_LOCK(sc);
2269 /*
2270 * Check for an available queue slot. If there are none,
2271 * punt.
2272 */
2273 if (sc->xl_cdata.xl_tx_free == NULL) {
2274 xl_txeoc(sc);
2275 xl_txeof(sc);
2276 if (sc->xl_cdata.xl_tx_free == NULL) {
2277 ifp->if_flags |= IFF_OACTIVE;
2278 XL_UNLOCK(sc);
2279 return;
2280 }
2281 }
2282
2283 start_tx = sc->xl_cdata.xl_tx_free;
2284
2285 while(sc->xl_cdata.xl_tx_free != NULL) {
2286 IF_DEQUEUE(&ifp->if_snd, m_head);
2287 if (m_head == NULL)
2288 break;
2289
2290 /* Pick a descriptor off the free list. */
2291 cur_tx = sc->xl_cdata.xl_tx_free;
2292 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2293
2294 cur_tx->xl_next = NULL;
2295
2296 /* Pack the data into the descriptor. */
2297 xl_encap(sc, cur_tx, m_head);
2298
2299 /* Chain it together. */
2300 if (prev != NULL) {
2301 prev->xl_next = cur_tx;
2302 prev->xl_ptr->xl_next = vtophys(cur_tx->xl_ptr);
2303 }
2304 prev = cur_tx;
2305
2306 /*
2307 * If there's a BPF listener, bounce a copy of this frame
2308 * to him.
2309 */
2310 if (ifp->if_bpf)
2311 bpf_mtap(ifp, cur_tx->xl_mbuf);
2312 }
2313
2314 /*
2315 * If there are no packets queued, bail.
2316 */
2317 if (cur_tx == NULL) {
2318 XL_UNLOCK(sc);
2319 return;
2320 }
2321
2322 /*
2323 * Place the request for the upload interrupt
2324 * in the last descriptor in the chain. This way, if
2325 * we're chaining several packets at once, we'll only
2326 * get an interupt once for the whole chain rather than
2327 * once for each packet.
2328 */
2329 cur_tx->xl_ptr->xl_status |= XL_TXSTAT_DL_INTR;
2330
2331 /*
2332 * Queue the packets. If the TX channel is clear, update
2333 * the downlist pointer register.
2334 */
2335 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2336 xl_wait(sc);
2337
2338 if (sc->xl_cdata.xl_tx_head != NULL) {
2339 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2340 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2341 vtophys(start_tx->xl_ptr);
2342 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
2343 ~XL_TXSTAT_DL_INTR;
2344 sc->xl_cdata.xl_tx_tail = cur_tx;
2345 } else {
2346 sc->xl_cdata.xl_tx_head = start_tx;
2347 sc->xl_cdata.xl_tx_tail = cur_tx;
2348 }
2349 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2350 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, vtophys(start_tx->xl_ptr));
2351
2352 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2353
2354 XL_SEL_WIN(7);
2355
2356 /*
2357 * Set a timeout in case the chip goes out to lunch.
2358 */
2359 ifp->if_timer = 5;
2360
2361 /*
2362 * XXX Under certain conditions, usually on slower machines
2363 * where interrupts may be dropped, it's possible for the
2364 * adapter to chew up all the buffers in the receive ring
2365 * and stall, without us being able to do anything about it.
2366 * To guard against this, we need to make a pass over the
2367 * RX queue to make sure there aren't any packets pending.
2368 * Doing it here means we can flush the receive ring at the
2369 * same time the chip is DMAing the transmit descriptors we
2370 * just gave it.
2371 *
2372 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2373 * nature of their chips in all their marketing literature;
2374 * we may as well take advantage of it. :)
2375 */
2376 xl_rxeof(sc);
2377
2378 XL_UNLOCK(sc);
2379
2380 return;
2381}
2382
2383static int xl_encap_90xB(sc, c, m_head)
2384 struct xl_softc *sc;
2385 struct xl_chain *c;
2386 struct mbuf *m_head;
2387{
2388 int frag = 0;
2389 struct xl_frag *f = NULL;
2390 struct mbuf *m;
2391 struct xl_list *d;
2392
2393 /*
2394 * Start packing the mbufs in this chain into
2395 * the fragment pointers. Stop when we run out
2396 * of fragments or hit the end of the mbuf chain.
2397 */
2398 d = c->xl_ptr;
2399 d->xl_status = 0;
2400 d->xl_next = 0;
2401
2402 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
2403 if (m->m_len != 0) {
2404 if (frag == XL_MAXFRAGS)
2405 break;
2406 f = &d->xl_frag[frag];
2407 f->xl_addr = vtophys(mtod(m, vm_offset_t));
2408 f->xl_len = m->m_len;
2409 frag++;
2410 }
2411 }
2412
2413 c->xl_mbuf = m_head;
2414 c->xl_ptr->xl_frag[frag - 1].xl_len |= XL_LAST_FRAG;
2415 c->xl_ptr->xl_status = XL_TXSTAT_RND_DEFEAT;
2416
2417 return(0);
2418}
2419
2420static void xl_start_90xB(ifp)
2421 struct ifnet *ifp;
2422{
2423 struct xl_softc *sc;
2424 struct mbuf *m_head = NULL;
2425 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2426 int idx;
2427
2428 sc = ifp->if_softc;
2429 XL_LOCK(sc);
2430
2431 if (ifp->if_flags & IFF_OACTIVE) {
2432 XL_UNLOCK(sc);
2433 return;
2434 }
2435
2436 idx = sc->xl_cdata.xl_tx_prod;
2437 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2438
2439 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2440
2441 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2442 ifp->if_flags |= IFF_OACTIVE;
2443 break;
2444 }
2445
2446 IF_DEQUEUE(&ifp->if_snd, m_head);
2447 if (m_head == NULL)
2448 break;
2449
2450 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2451
2452 /* Pack the data into the descriptor. */
2453 xl_encap_90xB(sc, cur_tx, m_head);
2454
2455 /* Chain it together. */
2456 if (prev != NULL)
2457 prev->xl_ptr->xl_next = cur_tx->xl_phys;
2458 prev = cur_tx;
2459
2460 /*
2461 * If there's a BPF listener, bounce a copy of this frame
2462 * to him.
2463 */
2464 if (ifp->if_bpf)
2465 bpf_mtap(ifp, cur_tx->xl_mbuf);
2466
2467 XL_INC(idx, XL_TX_LIST_CNT);
2468 sc->xl_cdata.xl_tx_cnt++;
2469 }
2470
2471 /*
2472 * If there are no packets queued, bail.
2473 */
2474 if (cur_tx == NULL) {
2475 XL_UNLOCK(sc);
2476 return;
2477 }
2478
2479 /*
2480 * Place the request for the upload interrupt
2481 * in the last descriptor in the chain. This way, if
2482 * we're chaining several packets at once, we'll only
2483 * get an interupt once for the whole chain rather than
2484 * once for each packet.
2485 */
2486 cur_tx->xl_ptr->xl_status |= XL_TXSTAT_DL_INTR;
2487
2488 /* Start transmission */
2489 sc->xl_cdata.xl_tx_prod = idx;
2490 start_tx->xl_prev->xl_ptr->xl_next = start_tx->xl_phys;
2491
2492 /*
2493 * Set a timeout in case the chip goes out to lunch.
2494 */
2495 ifp->if_timer = 5;
2496
2497 XL_UNLOCK(sc);
2498
2499 return;
2500}
2501
2502static void xl_init(xsc)
2503 void *xsc;
2504{
2505 struct xl_softc *sc = xsc;
2506 struct ifnet *ifp = &sc->arpcom.ac_if;
2507 int i;
2508 u_int16_t rxfilt = 0;
2509 struct mii_data *mii = NULL;
2510
2511 XL_LOCK(sc);
2512
2513 /*
2514 * Cancel pending I/O and free all RX/TX buffers.
2515 */
2516 xl_stop(sc);
2517
2518 if (sc->xl_miibus == NULL) {
2519 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2520 xl_wait(sc);
2521 }
2522 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2523 xl_wait(sc);
2524 DELAY(10000);
2525
2526 if (sc->xl_miibus != NULL)
2527 mii = device_get_softc(sc->xl_miibus);
2528
2529 /* Init our MAC address */
2530 XL_SEL_WIN(2);
2531 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2532 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2533 sc->arpcom.ac_enaddr[i]);
2534 }
2535
2536 /* Clear the station mask. */
2537 for (i = 0; i < 3; i++)
2538 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2539#ifdef notdef
2540 /* Reset TX and RX. */
2541 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2542 xl_wait(sc);
2543 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2544 xl_wait(sc);
2545#endif
2546 /* Init circular RX list. */
2547 if (xl_list_rx_init(sc) == ENOBUFS) {
2548 printf("xl%d: initialization failed: no "
2549 "memory for rx buffers\n", sc->xl_unit);
2550 xl_stop(sc);
2551 return;
2552 }
2553
2554 /* Init TX descriptors. */
2555 if (sc->xl_type == XL_TYPE_905B)
2556 xl_list_tx_init_90xB(sc);
2557 else
2558 xl_list_tx_init(sc);
2559
2560 /*
2561 * Set the TX freethresh value.
2562 * Note that this has no effect on 3c905B "cyclone"
2563 * cards but is required for 3c900/3c905 "boomerang"
2564 * cards in order to enable the download engine.
2565 */
2566 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2567
2568 /* Set the TX start threshold for best performance. */
2569 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2570 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2571
2572 /*
2573 * If this is a 3c905B, also set the tx reclaim threshold.
2574 * This helps cut down on the number of tx reclaim errors
2575 * that could happen on a busy network. The chip multiplies
2576 * the register value by 16 to obtain the actual threshold
2577 * in bytes, so we divide by 16 when setting the value here.
2578 * The existing threshold value can be examined by reading
2579 * the register at offset 9 in window 5.
2580 */
2581 if (sc->xl_type == XL_TYPE_905B) {
2582 CSR_WRITE_2(sc, XL_COMMAND,
2583 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2584 }
2585
2586 /* Set RX filter bits. */
2587 XL_SEL_WIN(5);
2588 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2589
2590 /* Set the individual bit to receive frames for this host only. */
2591 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2592
2593 /* If we want promiscuous mode, set the allframes bit. */
2594 if (ifp->if_flags & IFF_PROMISC) {
2595 rxfilt |= XL_RXFILTER_ALLFRAMES;
2596 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2597 } else {
2598 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2599 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2600 }
2601
2602 /*
2603 * Set capture broadcast bit to capture broadcast frames.
2604 */
2605 if (ifp->if_flags & IFF_BROADCAST) {
2606 rxfilt |= XL_RXFILTER_BROADCAST;
2607 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2608 } else {
2609 rxfilt &= ~XL_RXFILTER_BROADCAST;
2610 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2611 }
2612
2613 /*
2614 * Program the multicast filter, if necessary.
2615 */
2616 if (sc->xl_type == XL_TYPE_905B)
2617 xl_setmulti_hash(sc);
2618 else
2619 xl_setmulti(sc);
2620
2621 /*
2622 * Load the address of the RX list. We have to
2623 * stall the upload engine before we can manipulate
2624 * the uplist pointer register, then unstall it when
2625 * we're finished. We also have to wait for the
2626 * stall command to complete before proceeding.
2627 * Note that we have to do this after any RX resets
2628 * have completed since the uplist register is cleared
2629 * by a reset.
2630 */
2631 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2632 xl_wait(sc);
2633 CSR_WRITE_4(sc, XL_UPLIST_PTR, vtophys(&sc->xl_ldata->xl_rx_list[0]));
2634 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2635 xl_wait(sc);
2636
2637
2638 if (sc->xl_type == XL_TYPE_905B) {
2639 /* Set polling interval */
2640 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2641 /* Load the address of the TX list */
2642 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2643 xl_wait(sc);
2644 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2645 vtophys(&sc->xl_ldata->xl_tx_list[0]));
2646 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2647 xl_wait(sc);
2648 }
2649
2650 /*
2651 * If the coax transceiver is on, make sure to enable
2652 * the DC-DC converter.
2653 */
2654 XL_SEL_WIN(3);
2655 if (sc->xl_xcvr == XL_XCVR_COAX)
2656 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2657 else
2658 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2659
2660 /* Clear out the stats counters. */
2661 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2662 sc->xl_stats_no_timeout = 1;
2663 xl_stats_update(sc);
2664 sc->xl_stats_no_timeout = 0;
2665 XL_SEL_WIN(4);
2666 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2667 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2668
2669 /*
2670 * Enable interrupts.
2671 */
2672 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2673 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2674 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2675 if (sc->xl_flags & XL_FLAG_FUNCREG)
2676 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2677
2678 /* Set the RX early threshold */
2679 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2680 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2681
2682 /* Enable receiver and transmitter. */
2683 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2684 xl_wait(sc);
2685 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2686 xl_wait(sc);
2687
2688 if (mii != NULL)
2689 mii_mediachg(mii);
2690
2691 /* Select window 7 for normal operations. */
2692 XL_SEL_WIN(7);
2693
2694 ifp->if_flags |= IFF_RUNNING;
2695 ifp->if_flags &= ~IFF_OACTIVE;
2696
2697 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2698
2699 XL_UNLOCK(sc);
2700
2701 return;
2702}
2703
2704/*
2705 * Set media options.
2706 */
2707static int xl_ifmedia_upd(ifp)
2708 struct ifnet *ifp;
2709{
2710 struct xl_softc *sc;
2711 struct ifmedia *ifm = NULL;
2712 struct mii_data *mii = NULL;
2713
2714 sc = ifp->if_softc;
2715 if (sc->xl_miibus != NULL)
2716 mii = device_get_softc(sc->xl_miibus);
2717 if (mii == NULL)
2718 ifm = &sc->ifmedia;
2719 else
2720 ifm = &mii->mii_media;
2721
2722 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2723 case IFM_100_FX:
2724 case IFM_10_FL:
2725 case IFM_10_2:
2726 case IFM_10_5:
2727 xl_setmode(sc, ifm->ifm_media);
2728 return(0);
2729 break;
2730 default:
2731 break;
2732 }
2733
2734 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
2735 || sc->xl_media & XL_MEDIAOPT_BT4) {
2736 xl_init(sc);
2737 } else {
2738 xl_setmode(sc, ifm->ifm_media);
2739 }
2740
2741 return(0);
2742}
2743
2744/*
2745 * Report current media status.
2746 */
2747static void xl_ifmedia_sts(ifp, ifmr)
2748 struct ifnet *ifp;
2749 struct ifmediareq *ifmr;
2750{
2751 struct xl_softc *sc;
2752 u_int32_t icfg;
2753 struct mii_data *mii = NULL;
2754
2755 sc = ifp->if_softc;
2756 if (sc->xl_miibus != NULL)
2757 mii = device_get_softc(sc->xl_miibus);
2758
2759 XL_SEL_WIN(3);
2760 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2761 icfg >>= XL_ICFG_CONNECTOR_BITS;
2762
2763 ifmr->ifm_active = IFM_ETHER;
2764
2765 switch(icfg) {
2766 case XL_XCVR_10BT:
2767 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2768 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2769 ifmr->ifm_active |= IFM_FDX;
2770 else
2771 ifmr->ifm_active |= IFM_HDX;
2772 break;
2773 case XL_XCVR_AUI:
2774 if (sc->xl_type == XL_TYPE_905B &&
2775 sc->xl_media == XL_MEDIAOPT_10FL) {
2776 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
2777 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2778 ifmr->ifm_active |= IFM_FDX;
2779 else
2780 ifmr->ifm_active |= IFM_HDX;
2781 } else
2782 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2783 break;
2784 case XL_XCVR_COAX:
2785 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
2786 break;
2787 /*
2788 * XXX MII and BTX/AUTO should be separate cases.
2789 */
2790
2791 case XL_XCVR_100BTX:
2792 case XL_XCVR_AUTO:
2793 case XL_XCVR_MII:
2794 if (mii != NULL) {
2795 mii_pollstat(mii);
2796 ifmr->ifm_active = mii->mii_media_active;
2797 ifmr->ifm_status = mii->mii_media_status;
2798 }
2799 break;
2800 case XL_XCVR_100BFX:
2801 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
2802 break;
2803 default:
2804 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, icfg);
2805 break;
2806 }
2807
2808 return;
2809}
2810
2811static int xl_ioctl(ifp, command, data)
2812 struct ifnet *ifp;
2813 u_long command;
2814 caddr_t data;
2815{
2816 struct xl_softc *sc = ifp->if_softc;
2817 struct ifreq *ifr = (struct ifreq *) data;
2818 int error = 0;
2819 struct mii_data *mii = NULL;
2820 u_int8_t rxfilt;
2821
2822 XL_LOCK(sc);
2823
2824 switch(command) {
2825 case SIOCSIFADDR:
2826 case SIOCGIFADDR:
2827 case SIOCSIFMTU:
2828 error = ether_ioctl(ifp, command, data);
2829 break;
2830 case SIOCSIFFLAGS:
2831 XL_SEL_WIN(5);
2832 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2833 if (ifp->if_flags & IFF_UP) {
2834 if (ifp->if_flags & IFF_RUNNING &&
2835 ifp->if_flags & IFF_PROMISC &&
2836 !(sc->xl_if_flags & IFF_PROMISC)) {
2837 rxfilt |= XL_RXFILTER_ALLFRAMES;
2838 CSR_WRITE_2(sc, XL_COMMAND,
2839 XL_CMD_RX_SET_FILT|rxfilt);
2840 XL_SEL_WIN(7);
2841 } else if (ifp->if_flags & IFF_RUNNING &&
2842 !(ifp->if_flags & IFF_PROMISC) &&
2843 sc->xl_if_flags & IFF_PROMISC) {
2844 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2845 CSR_WRITE_2(sc, XL_COMMAND,
2846 XL_CMD_RX_SET_FILT|rxfilt);
2847 XL_SEL_WIN(7);
2848 } else
2849 xl_init(sc);
2850 } else {
2851 if (ifp->if_flags & IFF_RUNNING)
2852 xl_stop(sc);
2853 }
2854 sc->xl_if_flags = ifp->if_flags;
2855 error = 0;
2856 break;
2857 case SIOCADDMULTI:
2858 case SIOCDELMULTI:
2859 if (sc->xl_type == XL_TYPE_905B)
2860 xl_setmulti_hash(sc);
2861 else
2862 xl_setmulti(sc);
2863 error = 0;
2864 break;
2865 case SIOCGIFMEDIA:
2866 case SIOCSIFMEDIA:
2867 if (sc->xl_miibus != NULL)
2868 mii = device_get_softc(sc->xl_miibus);
2869 if (mii == NULL)
2870 error = ifmedia_ioctl(ifp, ifr,
2871 &sc->ifmedia, command);
2872 else
2873 error = ifmedia_ioctl(ifp, ifr,
2874 &mii->mii_media, command);
2875 break;
2876 default:
2877 error = EINVAL;
2878 break;
2879 }
2880
2881 XL_UNLOCK(sc);
2882
2883 return(error);
2884}
2885
2886static void xl_watchdog(ifp)
2887 struct ifnet *ifp;
2888{
2889 struct xl_softc *sc;
2890 u_int16_t status = 0;
2891
2892 sc = ifp->if_softc;
2893
2894 XL_LOCK(sc);
2895
2896 ifp->if_oerrors++;
2897 XL_SEL_WIN(4);
2898 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2899 printf("xl%d: watchdog timeout\n", sc->xl_unit);
2900
2901 if (status & XL_MEDIASTAT_CARRIER)
2902 printf("xl%d: no carrier - transceiver cable problem?\n",
2903 sc->xl_unit);
2904 xl_txeoc(sc);
2905 xl_txeof(sc);
2906 xl_rxeof(sc);
2907 xl_reset(sc);
2908 xl_init(sc);
2909
2910 if (ifp->if_snd.ifq_head != NULL)
2911 (*ifp->if_start)(ifp);
2912
2913 XL_UNLOCK(sc);
2914
2915 return;
2916}
2917
2918/*
2919 * Stop the adapter and free any mbufs allocated to the
2920 * RX and TX lists.
2921 */
2922static void xl_stop(sc)
2923 struct xl_softc *sc;
2924{
2925 register int i;
2926 struct ifnet *ifp;
2927
2928 XL_LOCK(sc);
2929
2930 ifp = &sc->arpcom.ac_if;
2931 ifp->if_timer = 0;
2932
2933 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
2934 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2935 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
2936 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
2937 xl_wait(sc);
2938 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
2939 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2940 DELAY(800);
2941
2942#ifdef foo
2943 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2944 xl_wait(sc);
2945 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2946 xl_wait(sc);
2947#endif
2948
2949 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
2950 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
2951 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2952 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2953
2954 /* Stop the stats updater. */
2955 untimeout(xl_stats_update, sc, sc->xl_stat_ch);
2956
2957 /*
2958 * Free data in the RX lists.
2959 */
2960 for (i = 0; i < XL_RX_LIST_CNT; i++) {
2961 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
2962 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
2963 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
2964 }
2965 }
2966 bzero((char *)&sc->xl_ldata->xl_rx_list,
2967 sizeof(sc->xl_ldata->xl_rx_list));
2968 /*
2969 * Free the TX list buffers.
2970 */
2971 for (i = 0; i < XL_TX_LIST_CNT; i++) {
2972 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
2973 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
2974 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
2975 }
2976 }
2977 bzero((char *)&sc->xl_ldata->xl_tx_list,
2978 sizeof(sc->xl_ldata->xl_tx_list));
2979
2980 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2981
2982 XL_UNLOCK(sc);
2983
2984 return;
2985}
2986
2987/*
2988 * Stop all chip I/O so that the kernel's probe routines don't
2989 * get confused by errant DMAs when rebooting.
2990 */
2991static void xl_shutdown(dev)
2992 device_t dev;
2993{
2994 struct xl_softc *sc;
2995
2996 sc = device_get_softc(dev);
2997
2998 XL_LOCK(sc);
2999 xl_reset(sc);
3000 xl_stop(sc);
3001 XL_UNLOCK(sc);
3002
3003 return;
3004}
| 1388 /* Reset the adapter. */
1389 xl_reset(sc);
1390
1391 /*
1392 * Get station address from the EEPROM.
1393 */
1394 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1395 printf("xl%d: failed to read station address\n", sc->xl_unit);
1396 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1397 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1398 if (sc->xl_fres != NULL)
1399 bus_release_resource(dev, SYS_RES_MEMORY,
1400 XL_PCI_FUNCMEM, sc->xl_fres);
1401 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1402 error = ENXIO;
1403 goto fail;
1404 }
1405
1406 /*
1407 * A 3Com chip was detected. Inform the world.
1408 */
1409 printf("xl%d: Ethernet address: %6D\n", unit, eaddr, ":");
1410
1411 sc->xl_unit = unit;
1412 callout_handle_init(&sc->xl_stat_ch);
1413 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1414
1415 sc->xl_ldata = contigmalloc(sizeof(struct xl_list_data), M_DEVBUF,
1416 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1417
1418 if (sc->xl_ldata == NULL) {
1419 printf("xl%d: no memory for list buffers!\n", unit);
1420 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1421 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1422 if (sc->xl_fres != NULL)
1423 bus_release_resource(dev, SYS_RES_MEMORY,
1424 XL_PCI_FUNCMEM, sc->xl_fres);
1425 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1426 error = ENXIO;
1427 goto fail;
1428 }
1429
1430 bzero(sc->xl_ldata, sizeof(struct xl_list_data));
1431
1432 /*
1433 * Figure out the card type. 3c905B adapters have the
1434 * 'supportsNoTxLength' bit set in the capabilities
1435 * word in the EEPROM.
1436 */
1437 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1438 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH)
1439 sc->xl_type = XL_TYPE_905B;
1440 else
1441 sc->xl_type = XL_TYPE_90X;
1442
1443 ifp = &sc->arpcom.ac_if;
1444 ifp->if_softc = sc;
1445 ifp->if_unit = unit;
1446 ifp->if_name = "xl";
1447 ifp->if_mtu = ETHERMTU;
1448 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1449 ifp->if_ioctl = xl_ioctl;
1450 ifp->if_output = ether_output;
1451 if (sc->xl_type == XL_TYPE_905B)
1452 ifp->if_start = xl_start_90xB;
1453 else
1454 ifp->if_start = xl_start;
1455 ifp->if_watchdog = xl_watchdog;
1456 ifp->if_init = xl_init;
1457 ifp->if_baudrate = 10000000;
1458 ifp->if_snd.ifq_maxlen = XL_TX_LIST_CNT - 1;
1459
1460 /*
1461 * Now we have to see what sort of media we have.
1462 * This includes probing for an MII interace and a
1463 * possible PHY.
1464 */
1465 XL_SEL_WIN(3);
1466 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1467 if (bootverbose)
1468 printf("xl%d: media options word: %x\n", sc->xl_unit,
1469 sc->xl_media);
1470
1471 xl_read_eeprom(sc, (char *)&sc->xl_xcvr, XL_EE_ICFG_0, 2, 0);
1472 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1473 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1474
1475 xl_mediacheck(sc);
1476
1477 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1478 || sc->xl_media & XL_MEDIAOPT_BT4) {
1479 if (bootverbose)
1480 printf("xl%d: found MII/AUTO\n", sc->xl_unit);
1481 xl_setcfg(sc);
1482 if (mii_phy_probe(dev, &sc->xl_miibus,
1483 xl_ifmedia_upd, xl_ifmedia_sts)) {
1484 printf("xl%d: no PHY found!\n", sc->xl_unit);
1485 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1486 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1487 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1488 contigfree(sc->xl_ldata,
1489 sizeof(struct xl_list_data), M_DEVBUF);
1490 error = ENXIO;
1491 goto fail;
1492 }
1493
1494 goto done;
1495 }
1496
1497 /*
1498 * Sanity check. If the user has selected "auto" and this isn't
1499 * a 10/100 card of some kind, we need to force the transceiver
1500 * type to something sane.
1501 */
1502 if (sc->xl_xcvr == XL_XCVR_AUTO)
1503 xl_choose_xcvr(sc, bootverbose);
1504
1505 /*
1506 * Do ifmedia setup.
1507 */
1508
1509 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1510
1511 if (sc->xl_media & XL_MEDIAOPT_BT) {
1512 if (bootverbose)
1513 printf("xl%d: found 10baseT\n", sc->xl_unit);
1514 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1515 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1516 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1517 ifmedia_add(&sc->ifmedia,
1518 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1519 }
1520
1521 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1522 /*
1523 * Check for a 10baseFL board in disguise.
1524 */
1525 if (sc->xl_type == XL_TYPE_905B &&
1526 sc->xl_media == XL_MEDIAOPT_10FL) {
1527 if (bootverbose)
1528 printf("xl%d: found 10baseFL\n", sc->xl_unit);
1529 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1530 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1531 0, NULL);
1532 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1533 ifmedia_add(&sc->ifmedia,
1534 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1535 } else {
1536 if (bootverbose)
1537 printf("xl%d: found AUI\n", sc->xl_unit);
1538 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1539 }
1540 }
1541
1542 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1543 if (bootverbose)
1544 printf("xl%d: found BNC\n", sc->xl_unit);
1545 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1546 }
1547
1548 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1549 if (bootverbose)
1550 printf("xl%d: found 100baseFX\n", sc->xl_unit);
1551 ifp->if_baudrate = 100000000;
1552 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1553 }
1554
1555 /* Choose a default media. */
1556 switch(sc->xl_xcvr) {
1557 case XL_XCVR_10BT:
1558 media = IFM_ETHER|IFM_10_T;
1559 xl_setmode(sc, media);
1560 break;
1561 case XL_XCVR_AUI:
1562 if (sc->xl_type == XL_TYPE_905B &&
1563 sc->xl_media == XL_MEDIAOPT_10FL) {
1564 media = IFM_ETHER|IFM_10_FL;
1565 xl_setmode(sc, media);
1566 } else {
1567 media = IFM_ETHER|IFM_10_5;
1568 xl_setmode(sc, media);
1569 }
1570 break;
1571 case XL_XCVR_COAX:
1572 media = IFM_ETHER|IFM_10_2;
1573 xl_setmode(sc, media);
1574 break;
1575 case XL_XCVR_AUTO:
1576 case XL_XCVR_100BTX:
1577 case XL_XCVR_MII:
1578 /* Chosen by miibus */
1579 break;
1580 case XL_XCVR_100BFX:
1581 media = IFM_ETHER|IFM_100_FX;
1582 break;
1583 default:
1584 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit,
1585 sc->xl_xcvr);
1586 /*
1587 * This will probably be wrong, but it prevents
1588 * the ifmedia code from panicking.
1589 */
1590 media = IFM_ETHER|IFM_10_T;
1591 break;
1592 }
1593
1594 if (sc->xl_miibus == NULL)
1595 ifmedia_set(&sc->ifmedia, media);
1596
1597done:
1598
1599 /*
1600 * Call MI attach routine.
1601 */
1602 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1603 XL_UNLOCK(sc);
1604 return(0);
1605
1606fail:
1607 XL_UNLOCK(sc);
1608 mtx_destroy(&sc->xl_mtx);
1609
1610 return(error);
1611}
1612
1613static int xl_detach(dev)
1614 device_t dev;
1615{
1616 struct xl_softc *sc;
1617 struct ifnet *ifp;
1618
1619 sc = device_get_softc(dev);
1620 XL_LOCK(sc);
1621 ifp = &sc->arpcom.ac_if;
1622
1623 xl_reset(sc);
1624 xl_stop(sc);
1625 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1626
1627 /* Delete any miibus and phy devices attached to this interface */
1628 if (sc->xl_miibus != NULL) {
1629 bus_generic_detach(dev);
1630 device_delete_child(dev, sc->xl_miibus);
1631 }
1632
1633 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1634 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1635 if (sc->xl_fres != NULL)
1636 bus_release_resource(dev, SYS_RES_MEMORY,
1637 XL_PCI_FUNCMEM, sc->xl_fres);
1638 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1639
1640 ifmedia_removeall(&sc->ifmedia);
1641 contigfree(sc->xl_ldata, sizeof(struct xl_list_data), M_DEVBUF);
1642
1643 XL_UNLOCK(sc);
1644 mtx_destroy(&sc->xl_mtx);
1645
1646 return(0);
1647}
1648
1649/*
1650 * Initialize the transmit descriptors.
1651 */
1652static int xl_list_tx_init(sc)
1653 struct xl_softc *sc;
1654{
1655 struct xl_chain_data *cd;
1656 struct xl_list_data *ld;
1657 int i;
1658
1659 cd = &sc->xl_cdata;
1660 ld = sc->xl_ldata;
1661 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1662 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1663 if (i == (XL_TX_LIST_CNT - 1))
1664 cd->xl_tx_chain[i].xl_next = NULL;
1665 else
1666 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1667 }
1668
1669 cd->xl_tx_free = &cd->xl_tx_chain[0];
1670 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1671
1672 return(0);
1673}
1674
1675/*
1676 * Initialize the transmit descriptors.
1677 */
1678static int xl_list_tx_init_90xB(sc)
1679 struct xl_softc *sc;
1680{
1681 struct xl_chain_data *cd;
1682 struct xl_list_data *ld;
1683 int i;
1684
1685 cd = &sc->xl_cdata;
1686 ld = sc->xl_ldata;
1687 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1688 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1689 cd->xl_tx_chain[i].xl_phys = vtophys(&ld->xl_tx_list[i]);
1690 if (i == (XL_TX_LIST_CNT - 1))
1691 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1692 else
1693 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1694 if (i == 0)
1695 cd->xl_tx_chain[i].xl_prev =
1696 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1697 else
1698 cd->xl_tx_chain[i].xl_prev =
1699 &cd->xl_tx_chain[i - 1];
1700 }
1701
1702 bzero((char *)ld->xl_tx_list,
1703 sizeof(struct xl_list) * XL_TX_LIST_CNT);
1704 ld->xl_tx_list[0].xl_status = XL_TXSTAT_EMPTY;
1705
1706 cd->xl_tx_prod = 1;
1707 cd->xl_tx_cons = 1;
1708 cd->xl_tx_cnt = 0;
1709
1710 return(0);
1711}
1712
1713/*
1714 * Initialize the RX descriptors and allocate mbufs for them. Note that
1715 * we arrange the descriptors in a closed ring, so that the last descriptor
1716 * points back to the first.
1717 */
1718static int xl_list_rx_init(sc)
1719 struct xl_softc *sc;
1720{
1721 struct xl_chain_data *cd;
1722 struct xl_list_data *ld;
1723 int i;
1724
1725 cd = &sc->xl_cdata;
1726 ld = sc->xl_ldata;
1727
1728 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1729 cd->xl_rx_chain[i].xl_ptr =
1730 (struct xl_list_onefrag *)&ld->xl_rx_list[i];
1731 if (xl_newbuf(sc, &cd->xl_rx_chain[i]) == ENOBUFS)
1732 return(ENOBUFS);
1733 if (i == (XL_RX_LIST_CNT - 1)) {
1734 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[0];
1735 ld->xl_rx_list[i].xl_next =
1736 vtophys(&ld->xl_rx_list[0]);
1737 } else {
1738 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[i + 1];
1739 ld->xl_rx_list[i].xl_next =
1740 vtophys(&ld->xl_rx_list[i + 1]);
1741 }
1742 }
1743
1744 cd->xl_rx_head = &cd->xl_rx_chain[0];
1745
1746 return(0);
1747}
1748
1749/*
1750 * Initialize an RX descriptor and attach an MBUF cluster.
1751 */
1752static int xl_newbuf(sc, c)
1753 struct xl_softc *sc;
1754 struct xl_chain_onefrag *c;
1755{
1756 struct mbuf *m_new = NULL;
1757
1758 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1759 if (m_new == NULL) {
1760 printf("xl%d: no memory for rx list -- "
1761 "packet dropped!\n", sc->xl_unit);
1762 return(ENOBUFS);
1763 }
1764
1765 MCLGET(m_new, M_DONTWAIT);
1766 if (!(m_new->m_flags & M_EXT)) {
1767 printf("xl%d: no memory for rx list -- "
1768 "packet dropped!\n", sc->xl_unit);
1769 m_freem(m_new);
1770 return(ENOBUFS);
1771 }
1772
1773 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1774
1775 /* Force longword alignment for packet payload. */
1776 m_adj(m_new, ETHER_ALIGN);
1777
1778 c->xl_mbuf = m_new;
1779 c->xl_ptr->xl_frag.xl_addr = vtophys(mtod(m_new, caddr_t));
1780 c->xl_ptr->xl_frag.xl_len = MCLBYTES | XL_LAST_FRAG;
1781 c->xl_ptr->xl_status = 0;
1782
1783 return(0);
1784}
1785
1786static int xl_rx_resync(sc)
1787 struct xl_softc *sc;
1788{
1789 struct xl_chain_onefrag *pos;
1790 int i;
1791
1792 pos = sc->xl_cdata.xl_rx_head;
1793
1794 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1795 if (pos->xl_ptr->xl_status)
1796 break;
1797 pos = pos->xl_next;
1798 }
1799
1800 if (i == XL_RX_LIST_CNT)
1801 return(0);
1802
1803 sc->xl_cdata.xl_rx_head = pos;
1804
1805 return(EAGAIN);
1806}
1807
1808/*
1809 * A frame has been uploaded: pass the resulting mbuf chain up to
1810 * the higher level protocols.
1811 */
1812static void xl_rxeof(sc)
1813 struct xl_softc *sc;
1814{
1815 struct ether_header *eh;
1816 struct mbuf *m;
1817 struct ifnet *ifp;
1818 struct xl_chain_onefrag *cur_rx;
1819 int total_len = 0;
1820 u_int16_t rxstat;
1821
1822 ifp = &sc->arpcom.ac_if;
1823
1824again:
1825
1826 while((rxstat = sc->xl_cdata.xl_rx_head->xl_ptr->xl_status)) {
1827 cur_rx = sc->xl_cdata.xl_rx_head;
1828 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1829
1830 /*
1831 * If an error occurs, update stats, clear the
1832 * status word and leave the mbuf cluster in place:
1833 * it should simply get re-used next time this descriptor
1834 * comes up in the ring.
1835 */
1836 if (rxstat & XL_RXSTAT_UP_ERROR) {
1837 ifp->if_ierrors++;
1838 cur_rx->xl_ptr->xl_status = 0;
1839 continue;
1840 }
1841
1842 /*
1843 * If there error bit was not set, the upload complete
1844 * bit should be set which means we have a valid packet.
1845 * If not, something truly strange has happened.
1846 */
1847 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1848 printf("xl%d: bad receive status -- "
1849 "packet dropped", sc->xl_unit);
1850 ifp->if_ierrors++;
1851 cur_rx->xl_ptr->xl_status = 0;
1852 continue;
1853 }
1854
1855 /* No errors; receive the packet. */
1856 m = cur_rx->xl_mbuf;
1857 total_len = cur_rx->xl_ptr->xl_status & XL_RXSTAT_LENMASK;
1858
1859 /*
1860 * Try to conjure up a new mbuf cluster. If that
1861 * fails, it means we have an out of memory condition and
1862 * should leave the buffer in place and continue. This will
1863 * result in a lost packet, but there's little else we
1864 * can do in this situation.
1865 */
1866 if (xl_newbuf(sc, cur_rx) == ENOBUFS) {
1867 ifp->if_ierrors++;
1868 cur_rx->xl_ptr->xl_status = 0;
1869 continue;
1870 }
1871
1872 ifp->if_ipackets++;
1873 eh = mtod(m, struct ether_header *);
1874 m->m_pkthdr.rcvif = ifp;
1875 m->m_pkthdr.len = m->m_len = total_len;
1876
1877 /* Remove header from mbuf and pass it on. */
1878 m_adj(m, sizeof(struct ether_header));
1879 ether_input(ifp, eh, m);
1880 }
1881
1882 /*
1883 * Handle the 'end of channel' condition. When the upload
1884 * engine hits the end of the RX ring, it will stall. This
1885 * is our cue to flush the RX ring, reload the uplist pointer
1886 * register and unstall the engine.
1887 * XXX This is actually a little goofy. With the ThunderLAN
1888 * chip, you get an interrupt when the receiver hits the end
1889 * of the receive ring, which tells you exactly when you
1890 * you need to reload the ring pointer. Here we have to
1891 * fake it. I'm mad at myself for not being clever enough
1892 * to avoid the use of a goto here.
1893 */
1894 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
1895 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
1896 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1897 xl_wait(sc);
1898 CSR_WRITE_4(sc, XL_UPLIST_PTR,
1899 vtophys(&sc->xl_ldata->xl_rx_list[0]));
1900 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
1901 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1902 goto again;
1903 }
1904
1905 return;
1906}
1907
1908/*
1909 * A frame was downloaded to the chip. It's safe for us to clean up
1910 * the list buffers.
1911 */
1912static void xl_txeof(sc)
1913 struct xl_softc *sc;
1914{
1915 struct xl_chain *cur_tx;
1916 struct ifnet *ifp;
1917
1918 ifp = &sc->arpcom.ac_if;
1919
1920 /* Clear the timeout timer. */
1921 ifp->if_timer = 0;
1922
1923 /*
1924 * Go through our tx list and free mbufs for those
1925 * frames that have been uploaded. Note: the 3c905B
1926 * sets a special bit in the status word to let us
1927 * know that a frame has been downloaded, but the
1928 * original 3c900/3c905 adapters don't do that.
1929 * Consequently, we have to use a different test if
1930 * xl_type != XL_TYPE_905B.
1931 */
1932 while(sc->xl_cdata.xl_tx_head != NULL) {
1933 cur_tx = sc->xl_cdata.xl_tx_head;
1934
1935 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
1936 break;
1937
1938 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
1939 m_freem(cur_tx->xl_mbuf);
1940 cur_tx->xl_mbuf = NULL;
1941 ifp->if_opackets++;
1942
1943 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
1944 sc->xl_cdata.xl_tx_free = cur_tx;
1945 }
1946
1947 if (sc->xl_cdata.xl_tx_head == NULL) {
1948 ifp->if_flags &= ~IFF_OACTIVE;
1949 sc->xl_cdata.xl_tx_tail = NULL;
1950 } else {
1951 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
1952 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
1953 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
1954 vtophys(sc->xl_cdata.xl_tx_head->xl_ptr));
1955 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
1956 }
1957 }
1958
1959 return;
1960}
1961
1962static void xl_txeof_90xB(sc)
1963 struct xl_softc *sc;
1964{
1965 struct xl_chain *cur_tx = NULL;
1966 struct ifnet *ifp;
1967 int idx;
1968
1969 ifp = &sc->arpcom.ac_if;
1970
1971 idx = sc->xl_cdata.xl_tx_cons;
1972 while(idx != sc->xl_cdata.xl_tx_prod) {
1973
1974 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
1975
1976 if (!(cur_tx->xl_ptr->xl_status & XL_TXSTAT_DL_COMPLETE))
1977 break;
1978
1979 if (cur_tx->xl_mbuf != NULL) {
1980 m_freem(cur_tx->xl_mbuf);
1981 cur_tx->xl_mbuf = NULL;
1982 }
1983
1984 ifp->if_opackets++;
1985
1986 sc->xl_cdata.xl_tx_cnt--;
1987 XL_INC(idx, XL_TX_LIST_CNT);
1988 ifp->if_timer = 0;
1989 }
1990
1991 sc->xl_cdata.xl_tx_cons = idx;
1992
1993 if (cur_tx != NULL)
1994 ifp->if_flags &= ~IFF_OACTIVE;
1995
1996 return;
1997}
1998
1999/*
2000 * TX 'end of channel' interrupt handler. Actually, we should
2001 * only get a 'TX complete' interrupt if there's a transmit error,
2002 * so this is really TX error handler.
2003 */
2004static void xl_txeoc(sc)
2005 struct xl_softc *sc;
2006{
2007 u_int8_t txstat;
2008
2009 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2010 if (txstat & XL_TXSTATUS_UNDERRUN ||
2011 txstat & XL_TXSTATUS_JABBER ||
2012 txstat & XL_TXSTATUS_RECLAIM) {
2013 printf("xl%d: transmission error: %x\n",
2014 sc->xl_unit, txstat);
2015 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2016 xl_wait(sc);
2017 if (sc->xl_type == XL_TYPE_905B) {
2018 if (sc->xl_cdata.xl_tx_cnt) {
2019 int i;
2020 struct xl_chain *c;
2021 i = sc->xl_cdata.xl_tx_cons;
2022 c = &sc->xl_cdata.xl_tx_chain[i];
2023 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2024 c->xl_phys);
2025 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2026 }
2027 } else {
2028 if (sc->xl_cdata.xl_tx_head != NULL)
2029 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2030 vtophys(sc->xl_cdata.xl_tx_head->xl_ptr));
2031 }
2032 /*
2033 * Remember to set this for the
2034 * first generation 3c90X chips.
2035 */
2036 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2037 if (txstat & XL_TXSTATUS_UNDERRUN &&
2038 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2039 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2040 printf("xl%d: tx underrun, increasing tx start"
2041 " threshold to %d bytes\n", sc->xl_unit,
2042 sc->xl_tx_thresh);
2043 }
2044 CSR_WRITE_2(sc, XL_COMMAND,
2045 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2046 if (sc->xl_type == XL_TYPE_905B) {
2047 CSR_WRITE_2(sc, XL_COMMAND,
2048 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2049 }
2050 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2051 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2052 } else {
2053 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2054 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2055 }
2056 /*
2057 * Write an arbitrary byte to the TX_STATUS register
2058 * to clear this interrupt/error and advance to the next.
2059 */
2060 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2061 }
2062
2063 return;
2064}
2065
2066static void xl_intr(arg)
2067 void *arg;
2068{
2069 struct xl_softc *sc;
2070 struct ifnet *ifp;
2071 u_int16_t status;
2072
2073 sc = arg;
2074 XL_LOCK(sc);
2075 ifp = &sc->arpcom.ac_if;
2076
2077 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) {
2078
2079 CSR_WRITE_2(sc, XL_COMMAND,
2080 XL_CMD_INTR_ACK|(status & XL_INTRS));
2081
2082 if (status & XL_STAT_UP_COMPLETE) {
2083 int curpkts;
2084
2085 curpkts = ifp->if_ipackets;
2086 xl_rxeof(sc);
2087 if (curpkts == ifp->if_ipackets) {
2088 while (xl_rx_resync(sc))
2089 xl_rxeof(sc);
2090 }
2091 }
2092
2093 if (status & XL_STAT_DOWN_COMPLETE) {
2094 if (sc->xl_type == XL_TYPE_905B)
2095 xl_txeof_90xB(sc);
2096 else
2097 xl_txeof(sc);
2098 }
2099
2100 if (status & XL_STAT_TX_COMPLETE) {
2101 ifp->if_oerrors++;
2102 xl_txeoc(sc);
2103 }
2104
2105 if (status & XL_STAT_ADFAIL) {
2106 xl_reset(sc);
2107 xl_init(sc);
2108 }
2109
2110 if (status & XL_STAT_STATSOFLOW) {
2111 sc->xl_stats_no_timeout = 1;
2112 xl_stats_update(sc);
2113 sc->xl_stats_no_timeout = 0;
2114 }
2115 }
2116
2117 if (ifp->if_snd.ifq_head != NULL)
2118 (*ifp->if_start)(ifp);
2119
2120 XL_UNLOCK(sc);
2121
2122 return;
2123}
2124
2125static void xl_stats_update(xsc)
2126 void *xsc;
2127{
2128 struct xl_softc *sc;
2129 struct ifnet *ifp;
2130 struct xl_stats xl_stats;
2131 u_int8_t *p;
2132 int i;
2133 struct mii_data *mii = NULL;
2134
2135 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2136
2137 sc = xsc;
2138 ifp = &sc->arpcom.ac_if;
2139 if (sc->xl_miibus != NULL)
2140 mii = device_get_softc(sc->xl_miibus);
2141
2142 p = (u_int8_t *)&xl_stats;
2143
2144 /* Read all the stats registers. */
2145 XL_SEL_WIN(6);
2146
2147 for (i = 0; i < 16; i++)
2148 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2149
2150 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2151
2152 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2153 xl_stats.xl_tx_single_collision +
2154 xl_stats.xl_tx_late_collision;
2155
2156 /*
2157 * Boomerang and cyclone chips have an extra stats counter
2158 * in window 4 (BadSSD). We have to read this too in order
2159 * to clear out all the stats registers and avoid a statsoflow
2160 * interrupt.
2161 */
2162 XL_SEL_WIN(4);
2163 CSR_READ_1(sc, XL_W4_BADSSD);
2164
2165 if (mii != NULL)
2166 mii_tick(mii);
2167
2168 XL_SEL_WIN(7);
2169
2170 if (!sc->xl_stats_no_timeout)
2171 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2172
2173 return;
2174}
2175
2176/*
2177 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2178 * pointers to the fragment pointers.
2179 */
2180static int xl_encap(sc, c, m_head)
2181 struct xl_softc *sc;
2182 struct xl_chain *c;
2183 struct mbuf *m_head;
2184{
2185 int frag = 0;
2186 struct xl_frag *f = NULL;
2187 int total_len;
2188 struct mbuf *m;
2189
2190 /*
2191 * Start packing the mbufs in this chain into
2192 * the fragment pointers. Stop when we run out
2193 * of fragments or hit the end of the mbuf chain.
2194 */
2195 m = m_head;
2196 total_len = 0;
2197
2198 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
2199 if (m->m_len != 0) {
2200 if (frag == XL_MAXFRAGS)
2201 break;
2202 total_len+= m->m_len;
2203 c->xl_ptr->xl_frag[frag].xl_addr =
2204 vtophys(mtod(m, vm_offset_t));
2205 c->xl_ptr->xl_frag[frag].xl_len = m->m_len;
2206 frag++;
2207 }
2208 }
2209
2210 /*
2211 * Handle special case: we used up all 63 fragments,
2212 * but we have more mbufs left in the chain. Copy the
2213 * data into an mbuf cluster. Note that we don't
2214 * bother clearing the values in the other fragment
2215 * pointers/counters; it wouldn't gain us anything,
2216 * and would waste cycles.
2217 */
2218 if (m != NULL) {
2219 struct mbuf *m_new = NULL;
2220
2221 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
2222 if (m_new == NULL) {
2223 printf("xl%d: no memory for tx list", sc->xl_unit);
2224 return(1);
2225 }
2226 if (m_head->m_pkthdr.len > MHLEN) {
2227 MCLGET(m_new, M_DONTWAIT);
2228 if (!(m_new->m_flags & M_EXT)) {
2229 m_freem(m_new);
2230 printf("xl%d: no memory for tx list",
2231 sc->xl_unit);
2232 return(1);
2233 }
2234 }
2235 m_copydata(m_head, 0, m_head->m_pkthdr.len,
2236 mtod(m_new, caddr_t));
2237 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
2238 m_freem(m_head);
2239 m_head = m_new;
2240 f = &c->xl_ptr->xl_frag[0];
2241 f->xl_addr = vtophys(mtod(m_new, caddr_t));
2242 f->xl_len = total_len = m_new->m_len;
2243 frag = 1;
2244 }
2245
2246 c->xl_mbuf = m_head;
2247 c->xl_ptr->xl_frag[frag - 1].xl_len |= XL_LAST_FRAG;
2248 c->xl_ptr->xl_status = total_len;
2249 c->xl_ptr->xl_next = 0;
2250
2251 return(0);
2252}
2253
2254/*
2255 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2256 * to the mbuf data regions directly in the transmit lists. We also save a
2257 * copy of the pointers since the transmit list fragment pointers are
2258 * physical addresses.
2259 */
2260static void xl_start(ifp)
2261 struct ifnet *ifp;
2262{
2263 struct xl_softc *sc;
2264 struct mbuf *m_head = NULL;
2265 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2266
2267 sc = ifp->if_softc;
2268 XL_LOCK(sc);
2269 /*
2270 * Check for an available queue slot. If there are none,
2271 * punt.
2272 */
2273 if (sc->xl_cdata.xl_tx_free == NULL) {
2274 xl_txeoc(sc);
2275 xl_txeof(sc);
2276 if (sc->xl_cdata.xl_tx_free == NULL) {
2277 ifp->if_flags |= IFF_OACTIVE;
2278 XL_UNLOCK(sc);
2279 return;
2280 }
2281 }
2282
2283 start_tx = sc->xl_cdata.xl_tx_free;
2284
2285 while(sc->xl_cdata.xl_tx_free != NULL) {
2286 IF_DEQUEUE(&ifp->if_snd, m_head);
2287 if (m_head == NULL)
2288 break;
2289
2290 /* Pick a descriptor off the free list. */
2291 cur_tx = sc->xl_cdata.xl_tx_free;
2292 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2293
2294 cur_tx->xl_next = NULL;
2295
2296 /* Pack the data into the descriptor. */
2297 xl_encap(sc, cur_tx, m_head);
2298
2299 /* Chain it together. */
2300 if (prev != NULL) {
2301 prev->xl_next = cur_tx;
2302 prev->xl_ptr->xl_next = vtophys(cur_tx->xl_ptr);
2303 }
2304 prev = cur_tx;
2305
2306 /*
2307 * If there's a BPF listener, bounce a copy of this frame
2308 * to him.
2309 */
2310 if (ifp->if_bpf)
2311 bpf_mtap(ifp, cur_tx->xl_mbuf);
2312 }
2313
2314 /*
2315 * If there are no packets queued, bail.
2316 */
2317 if (cur_tx == NULL) {
2318 XL_UNLOCK(sc);
2319 return;
2320 }
2321
2322 /*
2323 * Place the request for the upload interrupt
2324 * in the last descriptor in the chain. This way, if
2325 * we're chaining several packets at once, we'll only
2326 * get an interupt once for the whole chain rather than
2327 * once for each packet.
2328 */
2329 cur_tx->xl_ptr->xl_status |= XL_TXSTAT_DL_INTR;
2330
2331 /*
2332 * Queue the packets. If the TX channel is clear, update
2333 * the downlist pointer register.
2334 */
2335 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2336 xl_wait(sc);
2337
2338 if (sc->xl_cdata.xl_tx_head != NULL) {
2339 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2340 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2341 vtophys(start_tx->xl_ptr);
2342 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
2343 ~XL_TXSTAT_DL_INTR;
2344 sc->xl_cdata.xl_tx_tail = cur_tx;
2345 } else {
2346 sc->xl_cdata.xl_tx_head = start_tx;
2347 sc->xl_cdata.xl_tx_tail = cur_tx;
2348 }
2349 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2350 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, vtophys(start_tx->xl_ptr));
2351
2352 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2353
2354 XL_SEL_WIN(7);
2355
2356 /*
2357 * Set a timeout in case the chip goes out to lunch.
2358 */
2359 ifp->if_timer = 5;
2360
2361 /*
2362 * XXX Under certain conditions, usually on slower machines
2363 * where interrupts may be dropped, it's possible for the
2364 * adapter to chew up all the buffers in the receive ring
2365 * and stall, without us being able to do anything about it.
2366 * To guard against this, we need to make a pass over the
2367 * RX queue to make sure there aren't any packets pending.
2368 * Doing it here means we can flush the receive ring at the
2369 * same time the chip is DMAing the transmit descriptors we
2370 * just gave it.
2371 *
2372 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2373 * nature of their chips in all their marketing literature;
2374 * we may as well take advantage of it. :)
2375 */
2376 xl_rxeof(sc);
2377
2378 XL_UNLOCK(sc);
2379
2380 return;
2381}
2382
2383static int xl_encap_90xB(sc, c, m_head)
2384 struct xl_softc *sc;
2385 struct xl_chain *c;
2386 struct mbuf *m_head;
2387{
2388 int frag = 0;
2389 struct xl_frag *f = NULL;
2390 struct mbuf *m;
2391 struct xl_list *d;
2392
2393 /*
2394 * Start packing the mbufs in this chain into
2395 * the fragment pointers. Stop when we run out
2396 * of fragments or hit the end of the mbuf chain.
2397 */
2398 d = c->xl_ptr;
2399 d->xl_status = 0;
2400 d->xl_next = 0;
2401
2402 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
2403 if (m->m_len != 0) {
2404 if (frag == XL_MAXFRAGS)
2405 break;
2406 f = &d->xl_frag[frag];
2407 f->xl_addr = vtophys(mtod(m, vm_offset_t));
2408 f->xl_len = m->m_len;
2409 frag++;
2410 }
2411 }
2412
2413 c->xl_mbuf = m_head;
2414 c->xl_ptr->xl_frag[frag - 1].xl_len |= XL_LAST_FRAG;
2415 c->xl_ptr->xl_status = XL_TXSTAT_RND_DEFEAT;
2416
2417 return(0);
2418}
2419
2420static void xl_start_90xB(ifp)
2421 struct ifnet *ifp;
2422{
2423 struct xl_softc *sc;
2424 struct mbuf *m_head = NULL;
2425 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2426 int idx;
2427
2428 sc = ifp->if_softc;
2429 XL_LOCK(sc);
2430
2431 if (ifp->if_flags & IFF_OACTIVE) {
2432 XL_UNLOCK(sc);
2433 return;
2434 }
2435
2436 idx = sc->xl_cdata.xl_tx_prod;
2437 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2438
2439 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2440
2441 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2442 ifp->if_flags |= IFF_OACTIVE;
2443 break;
2444 }
2445
2446 IF_DEQUEUE(&ifp->if_snd, m_head);
2447 if (m_head == NULL)
2448 break;
2449
2450 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2451
2452 /* Pack the data into the descriptor. */
2453 xl_encap_90xB(sc, cur_tx, m_head);
2454
2455 /* Chain it together. */
2456 if (prev != NULL)
2457 prev->xl_ptr->xl_next = cur_tx->xl_phys;
2458 prev = cur_tx;
2459
2460 /*
2461 * If there's a BPF listener, bounce a copy of this frame
2462 * to him.
2463 */
2464 if (ifp->if_bpf)
2465 bpf_mtap(ifp, cur_tx->xl_mbuf);
2466
2467 XL_INC(idx, XL_TX_LIST_CNT);
2468 sc->xl_cdata.xl_tx_cnt++;
2469 }
2470
2471 /*
2472 * If there are no packets queued, bail.
2473 */
2474 if (cur_tx == NULL) {
2475 XL_UNLOCK(sc);
2476 return;
2477 }
2478
2479 /*
2480 * Place the request for the upload interrupt
2481 * in the last descriptor in the chain. This way, if
2482 * we're chaining several packets at once, we'll only
2483 * get an interupt once for the whole chain rather than
2484 * once for each packet.
2485 */
2486 cur_tx->xl_ptr->xl_status |= XL_TXSTAT_DL_INTR;
2487
2488 /* Start transmission */
2489 sc->xl_cdata.xl_tx_prod = idx;
2490 start_tx->xl_prev->xl_ptr->xl_next = start_tx->xl_phys;
2491
2492 /*
2493 * Set a timeout in case the chip goes out to lunch.
2494 */
2495 ifp->if_timer = 5;
2496
2497 XL_UNLOCK(sc);
2498
2499 return;
2500}
2501
2502static void xl_init(xsc)
2503 void *xsc;
2504{
2505 struct xl_softc *sc = xsc;
2506 struct ifnet *ifp = &sc->arpcom.ac_if;
2507 int i;
2508 u_int16_t rxfilt = 0;
2509 struct mii_data *mii = NULL;
2510
2511 XL_LOCK(sc);
2512
2513 /*
2514 * Cancel pending I/O and free all RX/TX buffers.
2515 */
2516 xl_stop(sc);
2517
2518 if (sc->xl_miibus == NULL) {
2519 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2520 xl_wait(sc);
2521 }
2522 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2523 xl_wait(sc);
2524 DELAY(10000);
2525
2526 if (sc->xl_miibus != NULL)
2527 mii = device_get_softc(sc->xl_miibus);
2528
2529 /* Init our MAC address */
2530 XL_SEL_WIN(2);
2531 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2532 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2533 sc->arpcom.ac_enaddr[i]);
2534 }
2535
2536 /* Clear the station mask. */
2537 for (i = 0; i < 3; i++)
2538 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2539#ifdef notdef
2540 /* Reset TX and RX. */
2541 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2542 xl_wait(sc);
2543 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2544 xl_wait(sc);
2545#endif
2546 /* Init circular RX list. */
2547 if (xl_list_rx_init(sc) == ENOBUFS) {
2548 printf("xl%d: initialization failed: no "
2549 "memory for rx buffers\n", sc->xl_unit);
2550 xl_stop(sc);
2551 return;
2552 }
2553
2554 /* Init TX descriptors. */
2555 if (sc->xl_type == XL_TYPE_905B)
2556 xl_list_tx_init_90xB(sc);
2557 else
2558 xl_list_tx_init(sc);
2559
2560 /*
2561 * Set the TX freethresh value.
2562 * Note that this has no effect on 3c905B "cyclone"
2563 * cards but is required for 3c900/3c905 "boomerang"
2564 * cards in order to enable the download engine.
2565 */
2566 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2567
2568 /* Set the TX start threshold for best performance. */
2569 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2570 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2571
2572 /*
2573 * If this is a 3c905B, also set the tx reclaim threshold.
2574 * This helps cut down on the number of tx reclaim errors
2575 * that could happen on a busy network. The chip multiplies
2576 * the register value by 16 to obtain the actual threshold
2577 * in bytes, so we divide by 16 when setting the value here.
2578 * The existing threshold value can be examined by reading
2579 * the register at offset 9 in window 5.
2580 */
2581 if (sc->xl_type == XL_TYPE_905B) {
2582 CSR_WRITE_2(sc, XL_COMMAND,
2583 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2584 }
2585
2586 /* Set RX filter bits. */
2587 XL_SEL_WIN(5);
2588 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2589
2590 /* Set the individual bit to receive frames for this host only. */
2591 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2592
2593 /* If we want promiscuous mode, set the allframes bit. */
2594 if (ifp->if_flags & IFF_PROMISC) {
2595 rxfilt |= XL_RXFILTER_ALLFRAMES;
2596 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2597 } else {
2598 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2599 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2600 }
2601
2602 /*
2603 * Set capture broadcast bit to capture broadcast frames.
2604 */
2605 if (ifp->if_flags & IFF_BROADCAST) {
2606 rxfilt |= XL_RXFILTER_BROADCAST;
2607 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2608 } else {
2609 rxfilt &= ~XL_RXFILTER_BROADCAST;
2610 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2611 }
2612
2613 /*
2614 * Program the multicast filter, if necessary.
2615 */
2616 if (sc->xl_type == XL_TYPE_905B)
2617 xl_setmulti_hash(sc);
2618 else
2619 xl_setmulti(sc);
2620
2621 /*
2622 * Load the address of the RX list. We have to
2623 * stall the upload engine before we can manipulate
2624 * the uplist pointer register, then unstall it when
2625 * we're finished. We also have to wait for the
2626 * stall command to complete before proceeding.
2627 * Note that we have to do this after any RX resets
2628 * have completed since the uplist register is cleared
2629 * by a reset.
2630 */
2631 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2632 xl_wait(sc);
2633 CSR_WRITE_4(sc, XL_UPLIST_PTR, vtophys(&sc->xl_ldata->xl_rx_list[0]));
2634 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2635 xl_wait(sc);
2636
2637
2638 if (sc->xl_type == XL_TYPE_905B) {
2639 /* Set polling interval */
2640 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2641 /* Load the address of the TX list */
2642 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2643 xl_wait(sc);
2644 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2645 vtophys(&sc->xl_ldata->xl_tx_list[0]));
2646 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2647 xl_wait(sc);
2648 }
2649
2650 /*
2651 * If the coax transceiver is on, make sure to enable
2652 * the DC-DC converter.
2653 */
2654 XL_SEL_WIN(3);
2655 if (sc->xl_xcvr == XL_XCVR_COAX)
2656 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2657 else
2658 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2659
2660 /* Clear out the stats counters. */
2661 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2662 sc->xl_stats_no_timeout = 1;
2663 xl_stats_update(sc);
2664 sc->xl_stats_no_timeout = 0;
2665 XL_SEL_WIN(4);
2666 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2667 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2668
2669 /*
2670 * Enable interrupts.
2671 */
2672 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2673 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2674 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2675 if (sc->xl_flags & XL_FLAG_FUNCREG)
2676 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2677
2678 /* Set the RX early threshold */
2679 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2680 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2681
2682 /* Enable receiver and transmitter. */
2683 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2684 xl_wait(sc);
2685 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2686 xl_wait(sc);
2687
2688 if (mii != NULL)
2689 mii_mediachg(mii);
2690
2691 /* Select window 7 for normal operations. */
2692 XL_SEL_WIN(7);
2693
2694 ifp->if_flags |= IFF_RUNNING;
2695 ifp->if_flags &= ~IFF_OACTIVE;
2696
2697 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2698
2699 XL_UNLOCK(sc);
2700
2701 return;
2702}
2703
2704/*
2705 * Set media options.
2706 */
2707static int xl_ifmedia_upd(ifp)
2708 struct ifnet *ifp;
2709{
2710 struct xl_softc *sc;
2711 struct ifmedia *ifm = NULL;
2712 struct mii_data *mii = NULL;
2713
2714 sc = ifp->if_softc;
2715 if (sc->xl_miibus != NULL)
2716 mii = device_get_softc(sc->xl_miibus);
2717 if (mii == NULL)
2718 ifm = &sc->ifmedia;
2719 else
2720 ifm = &mii->mii_media;
2721
2722 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2723 case IFM_100_FX:
2724 case IFM_10_FL:
2725 case IFM_10_2:
2726 case IFM_10_5:
2727 xl_setmode(sc, ifm->ifm_media);
2728 return(0);
2729 break;
2730 default:
2731 break;
2732 }
2733
2734 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
2735 || sc->xl_media & XL_MEDIAOPT_BT4) {
2736 xl_init(sc);
2737 } else {
2738 xl_setmode(sc, ifm->ifm_media);
2739 }
2740
2741 return(0);
2742}
2743
2744/*
2745 * Report current media status.
2746 */
2747static void xl_ifmedia_sts(ifp, ifmr)
2748 struct ifnet *ifp;
2749 struct ifmediareq *ifmr;
2750{
2751 struct xl_softc *sc;
2752 u_int32_t icfg;
2753 struct mii_data *mii = NULL;
2754
2755 sc = ifp->if_softc;
2756 if (sc->xl_miibus != NULL)
2757 mii = device_get_softc(sc->xl_miibus);
2758
2759 XL_SEL_WIN(3);
2760 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2761 icfg >>= XL_ICFG_CONNECTOR_BITS;
2762
2763 ifmr->ifm_active = IFM_ETHER;
2764
2765 switch(icfg) {
2766 case XL_XCVR_10BT:
2767 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2768 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2769 ifmr->ifm_active |= IFM_FDX;
2770 else
2771 ifmr->ifm_active |= IFM_HDX;
2772 break;
2773 case XL_XCVR_AUI:
2774 if (sc->xl_type == XL_TYPE_905B &&
2775 sc->xl_media == XL_MEDIAOPT_10FL) {
2776 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
2777 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2778 ifmr->ifm_active |= IFM_FDX;
2779 else
2780 ifmr->ifm_active |= IFM_HDX;
2781 } else
2782 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2783 break;
2784 case XL_XCVR_COAX:
2785 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
2786 break;
2787 /*
2788 * XXX MII and BTX/AUTO should be separate cases.
2789 */
2790
2791 case XL_XCVR_100BTX:
2792 case XL_XCVR_AUTO:
2793 case XL_XCVR_MII:
2794 if (mii != NULL) {
2795 mii_pollstat(mii);
2796 ifmr->ifm_active = mii->mii_media_active;
2797 ifmr->ifm_status = mii->mii_media_status;
2798 }
2799 break;
2800 case XL_XCVR_100BFX:
2801 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
2802 break;
2803 default:
2804 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, icfg);
2805 break;
2806 }
2807
2808 return;
2809}
2810
2811static int xl_ioctl(ifp, command, data)
2812 struct ifnet *ifp;
2813 u_long command;
2814 caddr_t data;
2815{
2816 struct xl_softc *sc = ifp->if_softc;
2817 struct ifreq *ifr = (struct ifreq *) data;
2818 int error = 0;
2819 struct mii_data *mii = NULL;
2820 u_int8_t rxfilt;
2821
2822 XL_LOCK(sc);
2823
2824 switch(command) {
2825 case SIOCSIFADDR:
2826 case SIOCGIFADDR:
2827 case SIOCSIFMTU:
2828 error = ether_ioctl(ifp, command, data);
2829 break;
2830 case SIOCSIFFLAGS:
2831 XL_SEL_WIN(5);
2832 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2833 if (ifp->if_flags & IFF_UP) {
2834 if (ifp->if_flags & IFF_RUNNING &&
2835 ifp->if_flags & IFF_PROMISC &&
2836 !(sc->xl_if_flags & IFF_PROMISC)) {
2837 rxfilt |= XL_RXFILTER_ALLFRAMES;
2838 CSR_WRITE_2(sc, XL_COMMAND,
2839 XL_CMD_RX_SET_FILT|rxfilt);
2840 XL_SEL_WIN(7);
2841 } else if (ifp->if_flags & IFF_RUNNING &&
2842 !(ifp->if_flags & IFF_PROMISC) &&
2843 sc->xl_if_flags & IFF_PROMISC) {
2844 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2845 CSR_WRITE_2(sc, XL_COMMAND,
2846 XL_CMD_RX_SET_FILT|rxfilt);
2847 XL_SEL_WIN(7);
2848 } else
2849 xl_init(sc);
2850 } else {
2851 if (ifp->if_flags & IFF_RUNNING)
2852 xl_stop(sc);
2853 }
2854 sc->xl_if_flags = ifp->if_flags;
2855 error = 0;
2856 break;
2857 case SIOCADDMULTI:
2858 case SIOCDELMULTI:
2859 if (sc->xl_type == XL_TYPE_905B)
2860 xl_setmulti_hash(sc);
2861 else
2862 xl_setmulti(sc);
2863 error = 0;
2864 break;
2865 case SIOCGIFMEDIA:
2866 case SIOCSIFMEDIA:
2867 if (sc->xl_miibus != NULL)
2868 mii = device_get_softc(sc->xl_miibus);
2869 if (mii == NULL)
2870 error = ifmedia_ioctl(ifp, ifr,
2871 &sc->ifmedia, command);
2872 else
2873 error = ifmedia_ioctl(ifp, ifr,
2874 &mii->mii_media, command);
2875 break;
2876 default:
2877 error = EINVAL;
2878 break;
2879 }
2880
2881 XL_UNLOCK(sc);
2882
2883 return(error);
2884}
2885
2886static void xl_watchdog(ifp)
2887 struct ifnet *ifp;
2888{
2889 struct xl_softc *sc;
2890 u_int16_t status = 0;
2891
2892 sc = ifp->if_softc;
2893
2894 XL_LOCK(sc);
2895
2896 ifp->if_oerrors++;
2897 XL_SEL_WIN(4);
2898 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2899 printf("xl%d: watchdog timeout\n", sc->xl_unit);
2900
2901 if (status & XL_MEDIASTAT_CARRIER)
2902 printf("xl%d: no carrier - transceiver cable problem?\n",
2903 sc->xl_unit);
2904 xl_txeoc(sc);
2905 xl_txeof(sc);
2906 xl_rxeof(sc);
2907 xl_reset(sc);
2908 xl_init(sc);
2909
2910 if (ifp->if_snd.ifq_head != NULL)
2911 (*ifp->if_start)(ifp);
2912
2913 XL_UNLOCK(sc);
2914
2915 return;
2916}
2917
2918/*
2919 * Stop the adapter and free any mbufs allocated to the
2920 * RX and TX lists.
2921 */
2922static void xl_stop(sc)
2923 struct xl_softc *sc;
2924{
2925 register int i;
2926 struct ifnet *ifp;
2927
2928 XL_LOCK(sc);
2929
2930 ifp = &sc->arpcom.ac_if;
2931 ifp->if_timer = 0;
2932
2933 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
2934 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2935 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
2936 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
2937 xl_wait(sc);
2938 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
2939 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2940 DELAY(800);
2941
2942#ifdef foo
2943 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2944 xl_wait(sc);
2945 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2946 xl_wait(sc);
2947#endif
2948
2949 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
2950 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
2951 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2952 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2953
2954 /* Stop the stats updater. */
2955 untimeout(xl_stats_update, sc, sc->xl_stat_ch);
2956
2957 /*
2958 * Free data in the RX lists.
2959 */
2960 for (i = 0; i < XL_RX_LIST_CNT; i++) {
2961 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
2962 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
2963 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
2964 }
2965 }
2966 bzero((char *)&sc->xl_ldata->xl_rx_list,
2967 sizeof(sc->xl_ldata->xl_rx_list));
2968 /*
2969 * Free the TX list buffers.
2970 */
2971 for (i = 0; i < XL_TX_LIST_CNT; i++) {
2972 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
2973 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
2974 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
2975 }
2976 }
2977 bzero((char *)&sc->xl_ldata->xl_tx_list,
2978 sizeof(sc->xl_ldata->xl_tx_list));
2979
2980 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2981
2982 XL_UNLOCK(sc);
2983
2984 return;
2985}
2986
2987/*
2988 * Stop all chip I/O so that the kernel's probe routines don't
2989 * get confused by errant DMAs when rebooting.
2990 */
2991static void xl_shutdown(dev)
2992 device_t dev;
2993{
2994 struct xl_softc *sc;
2995
2996 sc = device_get_softc(dev);
2997
2998 XL_LOCK(sc);
2999 xl_reset(sc);
3000 xl_stop(sc);
3001 XL_UNLOCK(sc);
3002
3003 return;
3004}
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