149#endif
150
151/*
152 * Various supported device vendors/types and their names.
153 */
154static struct xl_type xl_devs[] = {
155 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
156 "3Com 3c900-TPO Etherlink XL" },
157 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
158 "3Com 3c900-COMBO Etherlink XL" },
159 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
160 "3Com 3c905-TX Fast Etherlink XL" },
161 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
162 "3Com 3c905-T4 Fast Etherlink XL" },
163 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
164 "3Com 3c900B-TPO Etherlink XL" },
165 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
166 "3Com 3c900B-COMBO Etherlink XL" },
167 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
168 "3Com 3c900B-TPC Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
170 "3Com 3c900B-FL Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
172 "3Com 3c905B-TX Fast Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
174 "3Com 3c905B-T4 Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
176 "3Com 3c905B-FX/SC Fast Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
178 "3Com 3c905B-COMBO Fast Etherlink XL" },
179 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
180 "3Com 3c905C-TX Fast Etherlink XL" },
181 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
182 "3Com 3c980 Fast Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
184 "3Com 3c980C Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
186 "3Com 3cSOHO100-TX OfficeConnect" },
187 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
188 "3Com 3c450-TX HomeConnect" },
189 { 0, 0, NULL }
190};
191
192static int xl_probe __P((device_t));
193static int xl_attach __P((device_t));
194static int xl_detach __P((device_t));
195
196static int xl_newbuf __P((struct xl_softc *,
197 struct xl_chain_onefrag *));
198static void xl_stats_update __P((void *));
199static int xl_encap __P((struct xl_softc *, struct xl_chain *,
200 struct mbuf * ));
201static int xl_encap_90xB __P((struct xl_softc *, struct xl_chain *,
202 struct mbuf * ));
203
204static void xl_rxeof __P((struct xl_softc *));
205static int xl_rx_resync __P((struct xl_softc *));
206static void xl_txeof __P((struct xl_softc *));
207static void xl_txeof_90xB __P((struct xl_softc *));
208static void xl_txeoc __P((struct xl_softc *));
209static void xl_intr __P((void *));
210static void xl_start __P((struct ifnet *));
211static void xl_start_90xB __P((struct ifnet *));
212static int xl_ioctl __P((struct ifnet *, u_long, caddr_t));
213static void xl_init __P((void *));
214static void xl_stop __P((struct xl_softc *));
215static void xl_watchdog __P((struct ifnet *));
216static void xl_shutdown __P((device_t));
217static int xl_ifmedia_upd __P((struct ifnet *));
218static void xl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
219
220static int xl_eeprom_wait __P((struct xl_softc *));
221static int xl_read_eeprom __P((struct xl_softc *, caddr_t, int,
222 int, int));
223static void xl_mii_sync __P((struct xl_softc *));
224static void xl_mii_send __P((struct xl_softc *, u_int32_t, int));
225static int xl_mii_readreg __P((struct xl_softc *, struct xl_mii_frame *));
226static int xl_mii_writereg __P((struct xl_softc *, struct xl_mii_frame *));
227
228static void xl_setcfg __P((struct xl_softc *));
229static void xl_setmode __P((struct xl_softc *, int));
230static u_int8_t xl_calchash __P((caddr_t));
231static void xl_setmulti __P((struct xl_softc *));
232static void xl_setmulti_hash __P((struct xl_softc *));
233static void xl_reset __P((struct xl_softc *));
234static int xl_list_rx_init __P((struct xl_softc *));
235static int xl_list_tx_init __P((struct xl_softc *));
236static int xl_list_tx_init_90xB __P((struct xl_softc *));
237static void xl_wait __P((struct xl_softc *));
238static void xl_mediacheck __P((struct xl_softc *));
239static void xl_choose_xcvr __P((struct xl_softc *, int));
240#ifdef notdef
241static void xl_testpacket __P((struct xl_softc *));
242#endif
243
244static int xl_miibus_readreg __P((device_t, int, int));
245static int xl_miibus_writereg __P((device_t, int, int, int));
246static void xl_miibus_statchg __P((device_t));
247static void xl_miibus_mediainit __P((device_t));
248
249#ifdef XL_USEIOSPACE
250#define XL_RES SYS_RES_IOPORT
251#define XL_RID XL_PCI_LOIO
252#else
253#define XL_RES SYS_RES_MEMORY
254#define XL_RID XL_PCI_LOMEM
255#endif
256
257static device_method_t xl_methods[] = {
258 /* Device interface */
259 DEVMETHOD(device_probe, xl_probe),
260 DEVMETHOD(device_attach, xl_attach),
261 DEVMETHOD(device_detach, xl_detach),
262 DEVMETHOD(device_shutdown, xl_shutdown),
263
264 /* bus interface */
265 DEVMETHOD(bus_print_child, bus_generic_print_child),
266 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
267
268 /* MII interface */
269 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
270 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
271 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
272 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
273
274 { 0, 0 }
275};
276
277static driver_t xl_driver = {
278 "xl",
279 xl_methods,
280 sizeof(struct xl_softc)
281};
282
283static devclass_t xl_devclass;
284
285DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0);
286DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
287
288/*
289 * Murphy's law says that it's possible the chip can wedge and
290 * the 'command in progress' bit may never clear. Hence, we wait
291 * only a finite amount of time to avoid getting caught in an
292 * infinite loop. Normally this delay routine would be a macro,
293 * but it isn't called during normal operation so we can afford
294 * to make it a function.
295 */
296static void xl_wait(sc)
297 struct xl_softc *sc;
298{
299 register int i;
300
301 for (i = 0; i < XL_TIMEOUT; i++) {
302 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
303 break;
304 }
305
306 if (i == XL_TIMEOUT)
307 printf("xl%d: command never completed!\n", sc->xl_unit);
308
309 return;
310}
311
312/*
313 * MII access routines are provided for adapters with external
314 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
315 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
316 * Note: if you don't perform the MDIO operations just right,
317 * it's possible to end up with code that works correctly with
318 * some chips/CPUs/processor speeds/bus speeds/etc but not
319 * with others.
320 */
321#define MII_SET(x) \
322 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
323 CSR_READ_2(sc, XL_W4_PHY_MGMT) | x)
324
325#define MII_CLR(x) \
326 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
327 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~x)
328
329/*
330 * Sync the PHYs by setting data bit and strobing the clock 32 times.
331 */
332static void xl_mii_sync(sc)
333 struct xl_softc *sc;
334{
335 register int i;
336
337 XL_SEL_WIN(4);
338 MII_SET(XL_MII_DIR|XL_MII_DATA);
339
340 for (i = 0; i < 32; i++) {
341 MII_SET(XL_MII_CLK);
342 DELAY(1);
343 MII_CLR(XL_MII_CLK);
344 DELAY(1);
345 }
346
347 return;
348}
349
350/*
351 * Clock a series of bits through the MII.
352 */
353static void xl_mii_send(sc, bits, cnt)
354 struct xl_softc *sc;
355 u_int32_t bits;
356 int cnt;
357{
358 int i;
359
360 XL_SEL_WIN(4);
361 MII_CLR(XL_MII_CLK);
362
363 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
364 if (bits & i) {
365 MII_SET(XL_MII_DATA);
366 } else {
367 MII_CLR(XL_MII_DATA);
368 }
369 DELAY(1);
370 MII_CLR(XL_MII_CLK);
371 DELAY(1);
372 MII_SET(XL_MII_CLK);
373 }
374}
375
376/*
377 * Read an PHY register through the MII.
378 */
379static int xl_mii_readreg(sc, frame)
380 struct xl_softc *sc;
381 struct xl_mii_frame *frame;
382
383{
384 int i, ack, s;
385
386 s = splimp();
387
388 /*
389 * Set up frame for RX.
390 */
391 frame->mii_stdelim = XL_MII_STARTDELIM;
392 frame->mii_opcode = XL_MII_READOP;
393 frame->mii_turnaround = 0;
394 frame->mii_data = 0;
395
396 /*
397 * Select register window 4.
398 */
399
400 XL_SEL_WIN(4);
401
402 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
403 /*
404 * Turn on data xmit.
405 */
406 MII_SET(XL_MII_DIR);
407
408 xl_mii_sync(sc);
409
410 /*
411 * Send command/address info.
412 */
413 xl_mii_send(sc, frame->mii_stdelim, 2);
414 xl_mii_send(sc, frame->mii_opcode, 2);
415 xl_mii_send(sc, frame->mii_phyaddr, 5);
416 xl_mii_send(sc, frame->mii_regaddr, 5);
417
418 /* Idle bit */
419 MII_CLR((XL_MII_CLK|XL_MII_DATA));
420 DELAY(1);
421 MII_SET(XL_MII_CLK);
422 DELAY(1);
423
424 /* Turn off xmit. */
425 MII_CLR(XL_MII_DIR);
426
427 /* Check for ack */
428 MII_CLR(XL_MII_CLK);
429 DELAY(1);
430 MII_SET(XL_MII_CLK);
431 DELAY(1);
432 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
433
434 /*
435 * Now try reading data bits. If the ack failed, we still
436 * need to clock through 16 cycles to keep the PHY(s) in sync.
437 */
438 if (ack) {
439 for(i = 0; i < 16; i++) {
440 MII_CLR(XL_MII_CLK);
441 DELAY(1);
442 MII_SET(XL_MII_CLK);
443 DELAY(1);
444 }
445 goto fail;
446 }
447
448 for (i = 0x8000; i; i >>= 1) {
449 MII_CLR(XL_MII_CLK);
450 DELAY(1);
451 if (!ack) {
452 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
453 frame->mii_data |= i;
454 DELAY(1);
455 }
456 MII_SET(XL_MII_CLK);
457 DELAY(1);
458 }
459
460fail:
461
462 MII_CLR(XL_MII_CLK);
463 DELAY(1);
464 MII_SET(XL_MII_CLK);
465 DELAY(1);
466
467 splx(s);
468
469 if (ack)
470 return(1);
471 return(0);
472}
473
474/*
475 * Write to a PHY register through the MII.
476 */
477static int xl_mii_writereg(sc, frame)
478 struct xl_softc *sc;
479 struct xl_mii_frame *frame;
480
481{
482 int s;
483
484 s = splimp();
485 /*
486 * Set up frame for TX.
487 */
488
489 frame->mii_stdelim = XL_MII_STARTDELIM;
490 frame->mii_opcode = XL_MII_WRITEOP;
491 frame->mii_turnaround = XL_MII_TURNAROUND;
492
493 /*
494 * Select the window 4.
495 */
496 XL_SEL_WIN(4);
497
498 /*
499 * Turn on data output.
500 */
501 MII_SET(XL_MII_DIR);
502
503 xl_mii_sync(sc);
504
505 xl_mii_send(sc, frame->mii_stdelim, 2);
506 xl_mii_send(sc, frame->mii_opcode, 2);
507 xl_mii_send(sc, frame->mii_phyaddr, 5);
508 xl_mii_send(sc, frame->mii_regaddr, 5);
509 xl_mii_send(sc, frame->mii_turnaround, 2);
510 xl_mii_send(sc, frame->mii_data, 16);
511
512 /* Idle bit. */
513 MII_SET(XL_MII_CLK);
514 DELAY(1);
515 MII_CLR(XL_MII_CLK);
516 DELAY(1);
517
518 /*
519 * Turn off xmit.
520 */
521 MII_CLR(XL_MII_DIR);
522
523 splx(s);
524
525 return(0);
526}
527
528static int xl_miibus_readreg(dev, phy, reg)
529 device_t dev;
530 int phy, reg;
531{
532 struct xl_softc *sc;
533 struct xl_mii_frame frame;
534
535 /*
536 * Pretend that PHYs are only available at MII address 24.
537 * This is to guard against problems with certain 3Com ASIC
538 * revisions that incorrectly map the internal transceiver
539 * control registers at all MII addresses. This can cause
540 * the miibus code to attach the same PHY several times over.
541 */
542 if (phy != 24)
543 return(0);
544
545 sc = device_get_softc(dev);
546
547 bzero((char *)&frame, sizeof(frame));
548
549 frame.mii_phyaddr = phy;
550 frame.mii_regaddr = reg;
551 xl_mii_readreg(sc, &frame);
552
553 return(frame.mii_data);
554}
555
556static int xl_miibus_writereg(dev, phy, reg, data)
557 device_t dev;
558 int phy, reg, data;
559{
560 struct xl_softc *sc;
561 struct xl_mii_frame frame;
562
563 if (phy != 24)
564 return(0);
565
566 sc = device_get_softc(dev);
567
568 bzero((char *)&frame, sizeof(frame));
569
570 frame.mii_phyaddr = phy;
571 frame.mii_regaddr = reg;
572 frame.mii_data = data;
573
574 xl_mii_writereg(sc, &frame);
575
576 return(0);
577}
578
579static void xl_miibus_statchg(dev)
580 device_t dev;
581{
582 struct xl_softc *sc;
583 struct mii_data *mii;
584
585
586 sc = device_get_softc(dev);
587 mii = device_get_softc(sc->xl_miibus);
588
589 xl_setcfg(sc);
590
591 /* Set ASIC's duplex mode to match the PHY. */
592 XL_SEL_WIN(3);
593 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
594 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
595 else
596 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
597 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
598
599 return;
600}
601
602/*
603 * Special support for the 3c905B-COMBO. This card has 10/100 support
604 * plus BNC and AUI ports. This means we will have both an miibus attached
605 * plus some non-MII media settings. In order to allow this, we have to
606 * add the extra media to the miibus's ifmedia struct, but we can't do
607 * that during xl_attach() because the miibus hasn't been attached yet.
608 * So instead, we wait until the miibus probe/attach is done, at which
609 * point we will get a callback telling is that it's safe to add our
610 * extra media.
611 */
612static void xl_miibus_mediainit(dev)
613 device_t dev;
614{
615 struct xl_softc *sc;
616 struct mii_data *mii;
617 struct ifmedia *ifm;
618
619 sc = device_get_softc(dev);
620 mii = device_get_softc(sc->xl_miibus);
621 ifm = &mii->mii_media;
622
623 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
624 /*
625 * Check for a 10baseFL board in disguise.
626 */
627 if (sc->xl_type == XL_TYPE_905B &&
628 sc->xl_media == XL_MEDIAOPT_10FL) {
629 if (bootverbose)
630 printf("xl%d: found 10baseFL\n", sc->xl_unit);
631 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
632 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
633 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
634 ifmedia_add(ifm,
635 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
636 } else {
637 if (bootverbose)
638 printf("xl%d: found AUI\n", sc->xl_unit);
639 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
640 }
641 }
642
643 if (sc->xl_media & XL_MEDIAOPT_BNC) {
644 if (bootverbose)
645 printf("xl%d: found BNC\n", sc->xl_unit);
646 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
647 }
648
649 return;
650}
651
652/*
653 * The EEPROM is slow: give it time to come ready after issuing
654 * it a command.
655 */
656static int xl_eeprom_wait(sc)
657 struct xl_softc *sc;
658{
659 int i;
660
661 for (i = 0; i < 100; i++) {
662 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
663 DELAY(162);
664 else
665 break;
666 }
667
668 if (i == 100) {
669 printf("xl%d: eeprom failed to come ready\n", sc->xl_unit);
670 return(1);
671 }
672
673 return(0);
674}
675
676/*
677 * Read a sequence of words from the EEPROM. Note that ethernet address
678 * data is stored in the EEPROM in network byte order.
679 */
680static int xl_read_eeprom(sc, dest, off, cnt, swap)
681 struct xl_softc *sc;
682 caddr_t dest;
683 int off;
684 int cnt;
685 int swap;
686{
687 int err = 0, i;
688 u_int16_t word = 0, *ptr;
689
690 XL_SEL_WIN(0);
691
692 if (xl_eeprom_wait(sc))
693 return(1);
694
695 for (i = 0; i < cnt; i++) {
696 CSR_WRITE_2(sc, XL_W0_EE_CMD, XL_EE_READ | (off + i));
697 err = xl_eeprom_wait(sc);
698 if (err)
699 break;
700 word = CSR_READ_2(sc, XL_W0_EE_DATA);
701 ptr = (u_int16_t *)(dest + (i * 2));
702 if (swap)
703 *ptr = ntohs(word);
704 else
705 *ptr = word;
706 }
707
708 return(err ? 1 : 0);
709}
710
711/*
712 * This routine is taken from the 3Com Etherlink XL manual,
713 * page 10-7. It calculates a CRC of the supplied multicast
714 * group address and returns the lower 8 bits, which are used
715 * as the multicast filter position.
716 * Note: the 3c905B currently only supports a 64-bit hash table,
717 * which means we really only need 6 bits, but the manual indicates
718 * that future chip revisions will have a 256-bit hash table,
719 * hence the routine is set up to calculate 8 bits of position
720 * info in case we need it some day.
721 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a
722 * 256 bit hash table. This means we have to use all 8 bits regardless.
723 * On older cards, the upper 2 bits will be ignored. Grrrr....
724 */
725static u_int8_t xl_calchash(addr)
726 caddr_t addr;
727{
728 u_int32_t crc, carry;
729 int i, j;
730 u_int8_t c;
731
732 /* Compute CRC for the address value. */
733 crc = 0xFFFFFFFF; /* initial value */
734
735 for (i = 0; i < 6; i++) {
736 c = *(addr + i);
737 for (j = 0; j < 8; j++) {
738 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
739 crc <<= 1;
740 c >>= 1;
741 if (carry)
742 crc = (crc ^ 0x04c11db6) | carry;
743 }
744 }
745
746 /* return the filter bit position */
747 return(crc & 0x000000FF);
748}
749
750/*
751 * NICs older than the 3c905B have only one multicast option, which
752 * is to enable reception of all multicast frames.
753 */
754static void xl_setmulti(sc)
755 struct xl_softc *sc;
756{
757 struct ifnet *ifp;
758 struct ifmultiaddr *ifma;
759 u_int8_t rxfilt;
760 int mcnt = 0;
761
762 ifp = &sc->arpcom.ac_if;
763
764 XL_SEL_WIN(5);
765 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
766
767 if (ifp->if_flags & IFF_ALLMULTI) {
768 rxfilt |= XL_RXFILTER_ALLMULTI;
769 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
770 return;
771 }
772
773 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
774 ifma = ifma->ifma_link.le_next)
775 mcnt++;
776
777 if (mcnt)
778 rxfilt |= XL_RXFILTER_ALLMULTI;
779 else
780 rxfilt &= ~XL_RXFILTER_ALLMULTI;
781
782 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
783
784 return;
785}
786
787/*
788 * 3c905B adapters have a hash filter that we can program.
789 */
790static void xl_setmulti_hash(sc)
791 struct xl_softc *sc;
792{
793 struct ifnet *ifp;
794 int h = 0, i;
795 struct ifmultiaddr *ifma;
796 u_int8_t rxfilt;
797 int mcnt = 0;
798
799 ifp = &sc->arpcom.ac_if;
800
801 XL_SEL_WIN(5);
802 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
803
804 if (ifp->if_flags & IFF_ALLMULTI) {
805 rxfilt |= XL_RXFILTER_ALLMULTI;
806 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
807 return;
808 } else
809 rxfilt &= ~XL_RXFILTER_ALLMULTI;
810
811
812 /* first, zot all the existing hash bits */
813 for (i = 0; i < XL_HASHFILT_SIZE; i++)
814 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
815
816 /* now program new ones */
817 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
818 ifma = ifma->ifma_link.le_next) {
819 if (ifma->ifma_addr->sa_family != AF_LINK)
820 continue;
821 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
822 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
823 mcnt++;
824 }
825
826 if (mcnt)
827 rxfilt |= XL_RXFILTER_MULTIHASH;
828 else
829 rxfilt &= ~XL_RXFILTER_MULTIHASH;
830
831 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
832
833 return;
834}
835
836#ifdef notdef
837static void xl_testpacket(sc)
838 struct xl_softc *sc;
839{
840 struct mbuf *m;
841 struct ifnet *ifp;
842
843 ifp = &sc->arpcom.ac_if;
844
845 MGETHDR(m, M_DONTWAIT, MT_DATA);
846
847 if (m == NULL)
848 return;
849
850 bcopy(&sc->arpcom.ac_enaddr,
851 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
852 bcopy(&sc->arpcom.ac_enaddr,
853 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
854 mtod(m, struct ether_header *)->ether_type = htons(3);
855 mtod(m, unsigned char *)[14] = 0;
856 mtod(m, unsigned char *)[15] = 0;
857 mtod(m, unsigned char *)[16] = 0xE3;
858 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
859 IF_ENQUEUE(&ifp->if_snd, m);
860 xl_start(ifp);
861
862 return;
863}
864#endif
865
866static void xl_setcfg(sc)
867 struct xl_softc *sc;
868{
869 u_int32_t icfg;
870
871 XL_SEL_WIN(3);
872 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
873 icfg &= ~XL_ICFG_CONNECTOR_MASK;
874 if (sc->xl_media & XL_MEDIAOPT_MII ||
875 sc->xl_media & XL_MEDIAOPT_BT4)
876 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
877 if (sc->xl_media & XL_MEDIAOPT_BTX)
878 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
879
880 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
881 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
882
883 return;
884}
885
886static void xl_setmode(sc, media)
887 struct xl_softc *sc;
888 int media;
889{
890 u_int32_t icfg;
891 u_int16_t mediastat;
892
893 printf("xl%d: selecting ", sc->xl_unit);
894
895 XL_SEL_WIN(4);
896 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
897 XL_SEL_WIN(3);
898 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
899
900 if (sc->xl_media & XL_MEDIAOPT_BT) {
901 if (IFM_SUBTYPE(media) == IFM_10_T) {
902 printf("10baseT transceiver, ");
903 sc->xl_xcvr = XL_XCVR_10BT;
904 icfg &= ~XL_ICFG_CONNECTOR_MASK;
905 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
906 mediastat |= XL_MEDIASTAT_LINKBEAT|
907 XL_MEDIASTAT_JABGUARD;
908 mediastat &= ~XL_MEDIASTAT_SQEENB;
909 }
910 }
911
912 if (sc->xl_media & XL_MEDIAOPT_BFX) {
913 if (IFM_SUBTYPE(media) == IFM_100_FX) {
914 printf("100baseFX port, ");
915 sc->xl_xcvr = XL_XCVR_100BFX;
916 icfg &= ~XL_ICFG_CONNECTOR_MASK;
917 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
918 mediastat |= XL_MEDIASTAT_LINKBEAT;
919 mediastat &= ~XL_MEDIASTAT_SQEENB;
920 }
921 }
922
923 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
924 if (IFM_SUBTYPE(media) == IFM_10_5) {
925 printf("AUI port, ");
926 sc->xl_xcvr = XL_XCVR_AUI;
927 icfg &= ~XL_ICFG_CONNECTOR_MASK;
928 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
929 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
930 XL_MEDIASTAT_JABGUARD);
931 mediastat |= ~XL_MEDIASTAT_SQEENB;
932 }
933 if (IFM_SUBTYPE(media) == IFM_10_FL) {
934 printf("10baseFL transceiver, ");
935 sc->xl_xcvr = XL_XCVR_AUI;
936 icfg &= ~XL_ICFG_CONNECTOR_MASK;
937 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
938 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
939 XL_MEDIASTAT_JABGUARD);
940 mediastat |= ~XL_MEDIASTAT_SQEENB;
941 }
942 }
943
944 if (sc->xl_media & XL_MEDIAOPT_BNC) {
945 if (IFM_SUBTYPE(media) == IFM_10_2) {
946 printf("BNC port, ");
947 sc->xl_xcvr = XL_XCVR_COAX;
948 icfg &= ~XL_ICFG_CONNECTOR_MASK;
949 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
950 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
951 XL_MEDIASTAT_JABGUARD|
952 XL_MEDIASTAT_SQEENB);
953 }
954 }
955
956 if ((media & IFM_GMASK) == IFM_FDX ||
957 IFM_SUBTYPE(media) == IFM_100_FX) {
958 printf("full duplex\n");
959 XL_SEL_WIN(3);
960 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
961 } else {
962 printf("half duplex\n");
963 XL_SEL_WIN(3);
964 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
965 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
966 }
967
968 if (IFM_SUBTYPE(media) == IFM_10_2)
969 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
970 else
971 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
972 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
973 XL_SEL_WIN(4);
974 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
975 DELAY(800);
976 XL_SEL_WIN(7);
977
978 return;
979}
980
981static void xl_reset(sc)
982 struct xl_softc *sc;
983{
984 register int i;
985
986 XL_SEL_WIN(0);
987 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET);
988
989 for (i = 0; i < XL_TIMEOUT; i++) {
990 DELAY(10);
991 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
992 break;
993 }
994
995 if (i == XL_TIMEOUT)
996 printf("xl%d: reset didn't complete\n", sc->xl_unit);
997
998 DELAY(100000);
999
1000 /* Reset TX and RX. */
1001 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1002 xl_wait(sc);
1003 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1004 xl_wait(sc);
1005
1006 /* Wait a little while for the chip to get its brains in order. */
1007 DELAY(100000);
1008 return;
1009}
1010
1011/*
1012 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1013 * IDs against our list and return a device name if we find a match.
1014 */
1015static int xl_probe(dev)
1016 device_t dev;
1017{
1018 struct xl_type *t;
1019
1020 t = xl_devs;
1021
1022 while(t->xl_name != NULL) {
1023 if ((pci_get_vendor(dev) == t->xl_vid) &&
1024 (pci_get_device(dev) == t->xl_did)) {
1025 device_set_desc(dev, t->xl_name);
1026 return(0);
1027 }
1028 t++;
1029 }
1030
1031 return(ENXIO);
1032}
1033
1034/*
1035 * This routine is a kludge to work around possible hardware faults
1036 * or manufacturing defects that can cause the media options register
1037 * (or reset options register, as it's called for the first generation
1038 * 3c90x adapters) to return an incorrect result. I have encountered
1039 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1040 * which doesn't have any of the 'mediaopt' bits set. This screws up
1041 * the attach routine pretty badly because it doesn't know what media
1042 * to look for. If we find ourselves in this predicament, this routine
1043 * will try to guess the media options values and warn the user of a
1044 * possible manufacturing defect with his adapter/system/whatever.
1045 */
1046static void xl_mediacheck(sc)
1047 struct xl_softc *sc;
1048{
1049
1050 /*
1051 * If some of the media options bits are set, assume they are
1052 * correct. If not, try to figure it out down below.
1053 * XXX I should check for 10baseFL, but I don't have an adapter
1054 * to test with.
1055 */
1056 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1057 /*
1058 * Check the XCVR value. If it's not in the normal range
1059 * of values, we need to fake it up here.
1060 */
1061 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1062 return;
1063 else {
1064 printf("xl%d: bogus xcvr value "
1065 "in EEPROM (%x)\n", sc->xl_unit, sc->xl_xcvr);
1066 printf("xl%d: choosing new default based "
1067 "on card type\n", sc->xl_unit);
1068 }
1069 } else {
1070 if (sc->xl_type == XL_TYPE_905B &&
1071 sc->xl_media & XL_MEDIAOPT_10FL)
1072 return;
1073 printf("xl%d: WARNING: no media options bits set in "
1074 "the media options register!!\n", sc->xl_unit);
1075 printf("xl%d: this could be a manufacturing defect in "
1076 "your adapter or system\n", sc->xl_unit);
1077 printf("xl%d: attempting to guess media type; you "
1078 "should probably consult your vendor\n", sc->xl_unit);
1079 }
1080
1081 xl_choose_xcvr(sc, 1);
1082
1083 return;
1084}
1085
1086static void xl_choose_xcvr(sc, verbose)
1087 struct xl_softc *sc;
1088 int verbose;
1089{
1090 u_int16_t devid;
1091
1092 /*
1093 * Read the device ID from the EEPROM.
1094 * This is what's loaded into the PCI device ID register, so it has
1095 * to be correct otherwise we wouldn't have gotten this far.
1096 */
1097 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1098
1099 switch(devid) {
1100 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1101 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1102 sc->xl_media = XL_MEDIAOPT_BT;
1103 sc->xl_xcvr = XL_XCVR_10BT;
1104 if (verbose)
1105 printf("xl%d: guessing 10BaseT "
1106 "transceiver\n", sc->xl_unit);
1107 break;
1108 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1109 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1110 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1111 sc->xl_xcvr = XL_XCVR_10BT;
1112 if (verbose)
1113 printf("xl%d: guessing COMBO "
1114 "(AUI/BNC/TP)\n", sc->xl_unit);
1115 break;
1116 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1117 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1118 sc->xl_xcvr = XL_XCVR_10BT;
1119 if (verbose)
1120 printf("xl%d: guessing TPC (BNC/TP)\n", sc->xl_unit);
1121 break;
1122 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1123 sc->xl_media = XL_MEDIAOPT_10FL;
1124 sc->xl_xcvr = XL_XCVR_AUI;
1125 if (verbose)
1126 printf("xl%d: guessing 10baseFL\n", sc->xl_unit);
1127 break;
1128 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1129 sc->xl_media = XL_MEDIAOPT_MII;
1130 sc->xl_xcvr = XL_XCVR_MII;
1131 if (verbose)
1132 printf("xl%d: guessing MII\n", sc->xl_unit);
1133 break;
1134 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1135 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1136 sc->xl_media = XL_MEDIAOPT_BT4;
1137 sc->xl_xcvr = XL_XCVR_MII;
1138 if (verbose)
1139 printf("xl%d: guessing 100BaseT4/MII\n", sc->xl_unit);
1140 break;
1141 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1142 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1143 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1144 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1145 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1146 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1147 sc->xl_media = XL_MEDIAOPT_BTX;
1148 sc->xl_xcvr = XL_XCVR_AUTO;
1149 if (verbose)
1150 printf("xl%d: guessing 10/100 internal\n", sc->xl_unit);
1151 break;
1152 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1153 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1154 sc->xl_xcvr = XL_XCVR_AUTO;
1155 if (verbose)
1156 printf("xl%d: guessing 10/100 "
1157 "plus BNC/AUI\n", sc->xl_unit);
1158 break;
1159 default:
1160 printf("xl%d: unknown device ID: %x -- "
1161 "defaulting to 10baseT\n", sc->xl_unit, devid);
1162 sc->xl_media = XL_MEDIAOPT_BT;
1163 break;
1164 }
1165
1166 return;
1167}
1168
1169/*
1170 * Attach the interface. Allocate softc structures, do ifmedia
1171 * setup and ethernet/BPF attach.
1172 */
1173static int xl_attach(dev)
1174 device_t dev;
1175{
1176 int s;
1177 u_char eaddr[ETHER_ADDR_LEN];
1178 u_int32_t command;
1179 struct xl_softc *sc;
1180 struct ifnet *ifp;
1181 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1182 int unit, error = 0, rid;
1183
1184 s = splimp();
1185
1186 sc = device_get_softc(dev);
1187 unit = device_get_unit(dev);
1188
1189 /*
1190 * If this is a 3c905B, we have to check one extra thing.
1191 * The 905B supports power management and may be placed in
1192 * a low-power mode (D3 mode), typically by certain operating
1193 * systems which shall not be named. The PCI BIOS is supposed
1194 * to reset the NIC and bring it out of low-power mode, but
1195 * some do not. Consequently, we have to see if this chip
1196 * supports power management, and if so, make sure it's not
1197 * in low-power mode. If power management is available, the
1198 * capid byte will be 0x01.
1199 *
1200 * I _think_ that what actually happens is that the chip
1201 * loses its PCI configuration during the transition from
1202 * D3 back to D0; this means that it should be possible for
1203 * us to save the PCI iobase, membase and IRQ, put the chip
1204 * back in the D0 state, then restore the PCI config ourselves.
1205 */
1206
1207 command = pci_read_config(dev, XL_PCI_CAPID, 4) & 0x000000FF;
1208 if (command == 0x01) {
1209
1210 command = pci_read_config(dev, XL_PCI_PWRMGMTCTRL, 4);
1211 if (command & XL_PSTATE_MASK) {
1212 u_int32_t iobase, membase, irq;
1213
1214 /* Save important PCI config data. */
1215 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1216 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1217 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1218
1219 /* Reset the power state. */
1220 printf("xl%d: chip is in D%d power mode "
1221 "-- setting to D0\n", unit, command & XL_PSTATE_MASK);
1222 command &= 0xFFFFFFFC;
1223 pci_write_config(dev, XL_PCI_PWRMGMTCTRL, command, 4);
1224
1225 /* Restore PCI config data. */
1226 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1227 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1228 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1229 }
1230 }
1231
1232 /*
1233 * Map control/status registers.
1234 */
1235 command = pci_read_config(dev, PCIR_COMMAND, 4);
1236 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1237 pci_write_config(dev, PCIR_COMMAND, command, 4);
1238 command = pci_read_config(dev, PCIR_COMMAND, 4);
1239
1240#ifdef XL_USEIOSPACE
1241 if (!(command & PCIM_CMD_PORTEN)) {
1242 printf("xl%d: failed to enable I/O ports!\n", unit);
1243 error = ENXIO;
1244 goto fail;
1245 }
1246#else
1247 if (!(command & PCIM_CMD_MEMEN)) {
1248 printf("xl%d: failed to enable memory mapping!\n", unit);
1249 error = ENXIO;
1250 goto fail;
1251 }
1252#endif
1253
1254 rid = XL_RID;
1255 sc->xl_res = bus_alloc_resource(dev, XL_RES, &rid,
1256 0, ~0, 1, RF_ACTIVE);
1257
1258 if (sc->xl_res == NULL) {
1259 printf ("xl%d: couldn't map ports/memory\n", unit);
1260 error = ENXIO;
1261 goto fail;
1262 }
1263
1264 sc->xl_btag = rman_get_bustag(sc->xl_res);
1265 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1266
1267 rid = 0;
1268 sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1269 RF_SHAREABLE | RF_ACTIVE);
1270
1271 if (sc->xl_irq == NULL) {
1272 printf("xl%d: couldn't map interrupt\n", unit);
1273 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1274 error = ENXIO;
1275 goto fail;
1276 }
1277
1278 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET,
1279 xl_intr, sc, &sc->xl_intrhand);
1280
1281 if (error) {
1282 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1283 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1284 printf("xl%d: couldn't set up irq\n", unit);
1285 goto fail;
1286 }
1287
1288 /* Reset the adapter. */
1289 xl_reset(sc);
1290
1291 /*
1292 * Get station address from the EEPROM.
1293 */
1294 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1295 printf("xl%d: failed to read station address\n", sc->xl_unit);
1296 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1297 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1298 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1299 error = ENXIO;
1300 goto fail;
1301 }
1302
1303 /*
1304 * A 3Com chip was detected. Inform the world.
1305 */
1306 printf("xl%d: Ethernet address: %6D\n", unit, eaddr, ":");
1307
1308 sc->xl_unit = unit;
1309 callout_handle_init(&sc->xl_stat_ch);
1310 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1311
1312 sc->xl_ldata = contigmalloc(sizeof(struct xl_list_data), M_DEVBUF,
1313 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1314
1315 if (sc->xl_ldata == NULL) {
1316 printf("xl%d: no memory for list buffers!\n", unit);
1317 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1318 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1319 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1320 error = ENXIO;
1321 goto fail;
1322 }
1323
1324 bzero(sc->xl_ldata, sizeof(struct xl_list_data));
1325
1326 /*
1327 * Figure out the card type. 3c905B adapters have the
1328 * 'supportsNoTxLength' bit set in the capabilities
1329 * word in the EEPROM.
1330 */
1331 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1332 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH)
1333 sc->xl_type = XL_TYPE_905B;
1334 else
1335 sc->xl_type = XL_TYPE_90X;
1336
1337 ifp = &sc->arpcom.ac_if;
1338 ifp->if_softc = sc;
1339 ifp->if_unit = unit;
1340 ifp->if_name = "xl";
1341 ifp->if_mtu = ETHERMTU;
1342 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1343 ifp->if_ioctl = xl_ioctl;
1344 ifp->if_output = ether_output;
1345 if (sc->xl_type == XL_TYPE_905B)
1346 ifp->if_start = xl_start_90xB;
1347 else
1348 ifp->if_start = xl_start;
1349 ifp->if_watchdog = xl_watchdog;
1350 ifp->if_init = xl_init;
1351 ifp->if_baudrate = 10000000;
1352 ifp->if_snd.ifq_maxlen = XL_TX_LIST_CNT - 1;
1353
1354 /*
1355 * Now we have to see what sort of media we have.
1356 * This includes probing for an MII interace and a
1357 * possible PHY.
1358 */
1359 XL_SEL_WIN(3);
1360 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1361 if (bootverbose)
1362 printf("xl%d: media options word: %x\n", sc->xl_unit,
1363 sc->xl_media);
1364
1365 xl_read_eeprom(sc, (char *)&sc->xl_xcvr, XL_EE_ICFG_0, 2, 0);
1366 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1367 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1368
1369 xl_mediacheck(sc);
1370
1371 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1372 || sc->xl_media & XL_MEDIAOPT_BT4) {
1373 if (bootverbose)
1374 printf("xl%d: found MII/AUTO\n", sc->xl_unit);
1375 xl_setcfg(sc);
1376 if (mii_phy_probe(dev, &sc->xl_miibus,
1377 xl_ifmedia_upd, xl_ifmedia_sts)) {
1378 printf("xl%d: no PHY found!\n", sc->xl_unit);
1379 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1380 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1381 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1382 contigfree(sc->xl_ldata,
1383 sizeof(struct xl_list_data), M_DEVBUF);
1384 error = ENXIO;
1385 goto fail;
1386 }
1387
1388 goto done;
1389 }
1390
1391 /*
1392 * Sanity check. If the user has selected "auto" and this isn't
1393 * a 10/100 card of some kind, we need to force the transceiver
1394 * type to something sane.
1395 */
1396 if (sc->xl_xcvr == XL_XCVR_AUTO)
1397 xl_choose_xcvr(sc, bootverbose);
1398
1399 /*
1400 * Do ifmedia setup.
1401 */
1402
1403 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1404
1405 if (sc->xl_media & XL_MEDIAOPT_BT) {
1406 if (bootverbose)
1407 printf("xl%d: found 10baseT\n", sc->xl_unit);
1408 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1409 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1410 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1411 ifmedia_add(&sc->ifmedia,
1412 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1413 }
1414
1415 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1416 /*
1417 * Check for a 10baseFL board in disguise.
1418 */
1419 if (sc->xl_type == XL_TYPE_905B &&
1420 sc->xl_media == XL_MEDIAOPT_10FL) {
1421 if (bootverbose)
1422 printf("xl%d: found 10baseFL\n", sc->xl_unit);
1423 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1424 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1425 0, NULL);
1426 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1427 ifmedia_add(&sc->ifmedia,
1428 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1429 } else {
1430 if (bootverbose)
1431 printf("xl%d: found AUI\n", sc->xl_unit);
1432 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1433 }
1434 }
1435
1436 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1437 if (bootverbose)
1438 printf("xl%d: found BNC\n", sc->xl_unit);
1439 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1440 }
1441
1442 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1443 if (bootverbose)
1444 printf("xl%d: found 100baseFX\n", sc->xl_unit);
1445 ifp->if_baudrate = 100000000;
1446 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1447 }
1448
1449 /* Choose a default media. */
1450 switch(sc->xl_xcvr) {
1451 case XL_XCVR_10BT:
1452 media = IFM_ETHER|IFM_10_T;
1453 xl_setmode(sc, media);
1454 break;
1455 case XL_XCVR_AUI:
1456 if (sc->xl_type == XL_TYPE_905B &&
1457 sc->xl_media == XL_MEDIAOPT_10FL) {
1458 media = IFM_ETHER|IFM_10_FL;
1459 xl_setmode(sc, media);
1460 } else {
1461 media = IFM_ETHER|IFM_10_5;
1462 xl_setmode(sc, media);
1463 }
1464 break;
1465 case XL_XCVR_COAX:
1466 media = IFM_ETHER|IFM_10_2;
1467 xl_setmode(sc, media);
1468 break;
1469 case XL_XCVR_AUTO:
1470 case XL_XCVR_100BTX:
1471 case XL_XCVR_MII:
1472 /* Chosen by miibus */
1473 break;
1474 case XL_XCVR_100BFX:
1475 media = IFM_ETHER|IFM_100_FX;
1476 break;
1477 default:
1478 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit,
1479 sc->xl_xcvr);
1480 /*
1481 * This will probably be wrong, but it prevents
1482 * the ifmedia code from panicking.
1483 */
1484 media = IFM_ETHER|IFM_10_T;
1485 break;
1486 }
1487
1488 if (sc->xl_miibus == NULL)
1489 ifmedia_set(&sc->ifmedia, media);
1490
1491done:
1492
1493 /*
| 149#endif
150
151/*
152 * Various supported device vendors/types and their names.
153 */
154static struct xl_type xl_devs[] = {
155 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
156 "3Com 3c900-TPO Etherlink XL" },
157 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
158 "3Com 3c900-COMBO Etherlink XL" },
159 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
160 "3Com 3c905-TX Fast Etherlink XL" },
161 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
162 "3Com 3c905-T4 Fast Etherlink XL" },
163 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
164 "3Com 3c900B-TPO Etherlink XL" },
165 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
166 "3Com 3c900B-COMBO Etherlink XL" },
167 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
168 "3Com 3c900B-TPC Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
170 "3Com 3c900B-FL Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
172 "3Com 3c905B-TX Fast Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
174 "3Com 3c905B-T4 Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
176 "3Com 3c905B-FX/SC Fast Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
178 "3Com 3c905B-COMBO Fast Etherlink XL" },
179 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
180 "3Com 3c905C-TX Fast Etherlink XL" },
181 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
182 "3Com 3c980 Fast Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
184 "3Com 3c980C Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
186 "3Com 3cSOHO100-TX OfficeConnect" },
187 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
188 "3Com 3c450-TX HomeConnect" },
189 { 0, 0, NULL }
190};
191
192static int xl_probe __P((device_t));
193static int xl_attach __P((device_t));
194static int xl_detach __P((device_t));
195
196static int xl_newbuf __P((struct xl_softc *,
197 struct xl_chain_onefrag *));
198static void xl_stats_update __P((void *));
199static int xl_encap __P((struct xl_softc *, struct xl_chain *,
200 struct mbuf * ));
201static int xl_encap_90xB __P((struct xl_softc *, struct xl_chain *,
202 struct mbuf * ));
203
204static void xl_rxeof __P((struct xl_softc *));
205static int xl_rx_resync __P((struct xl_softc *));
206static void xl_txeof __P((struct xl_softc *));
207static void xl_txeof_90xB __P((struct xl_softc *));
208static void xl_txeoc __P((struct xl_softc *));
209static void xl_intr __P((void *));
210static void xl_start __P((struct ifnet *));
211static void xl_start_90xB __P((struct ifnet *));
212static int xl_ioctl __P((struct ifnet *, u_long, caddr_t));
213static void xl_init __P((void *));
214static void xl_stop __P((struct xl_softc *));
215static void xl_watchdog __P((struct ifnet *));
216static void xl_shutdown __P((device_t));
217static int xl_ifmedia_upd __P((struct ifnet *));
218static void xl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
219
220static int xl_eeprom_wait __P((struct xl_softc *));
221static int xl_read_eeprom __P((struct xl_softc *, caddr_t, int,
222 int, int));
223static void xl_mii_sync __P((struct xl_softc *));
224static void xl_mii_send __P((struct xl_softc *, u_int32_t, int));
225static int xl_mii_readreg __P((struct xl_softc *, struct xl_mii_frame *));
226static int xl_mii_writereg __P((struct xl_softc *, struct xl_mii_frame *));
227
228static void xl_setcfg __P((struct xl_softc *));
229static void xl_setmode __P((struct xl_softc *, int));
230static u_int8_t xl_calchash __P((caddr_t));
231static void xl_setmulti __P((struct xl_softc *));
232static void xl_setmulti_hash __P((struct xl_softc *));
233static void xl_reset __P((struct xl_softc *));
234static int xl_list_rx_init __P((struct xl_softc *));
235static int xl_list_tx_init __P((struct xl_softc *));
236static int xl_list_tx_init_90xB __P((struct xl_softc *));
237static void xl_wait __P((struct xl_softc *));
238static void xl_mediacheck __P((struct xl_softc *));
239static void xl_choose_xcvr __P((struct xl_softc *, int));
240#ifdef notdef
241static void xl_testpacket __P((struct xl_softc *));
242#endif
243
244static int xl_miibus_readreg __P((device_t, int, int));
245static int xl_miibus_writereg __P((device_t, int, int, int));
246static void xl_miibus_statchg __P((device_t));
247static void xl_miibus_mediainit __P((device_t));
248
249#ifdef XL_USEIOSPACE
250#define XL_RES SYS_RES_IOPORT
251#define XL_RID XL_PCI_LOIO
252#else
253#define XL_RES SYS_RES_MEMORY
254#define XL_RID XL_PCI_LOMEM
255#endif
256
257static device_method_t xl_methods[] = {
258 /* Device interface */
259 DEVMETHOD(device_probe, xl_probe),
260 DEVMETHOD(device_attach, xl_attach),
261 DEVMETHOD(device_detach, xl_detach),
262 DEVMETHOD(device_shutdown, xl_shutdown),
263
264 /* bus interface */
265 DEVMETHOD(bus_print_child, bus_generic_print_child),
266 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
267
268 /* MII interface */
269 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
270 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
271 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
272 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
273
274 { 0, 0 }
275};
276
277static driver_t xl_driver = {
278 "xl",
279 xl_methods,
280 sizeof(struct xl_softc)
281};
282
283static devclass_t xl_devclass;
284
285DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0);
286DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
287
288/*
289 * Murphy's law says that it's possible the chip can wedge and
290 * the 'command in progress' bit may never clear. Hence, we wait
291 * only a finite amount of time to avoid getting caught in an
292 * infinite loop. Normally this delay routine would be a macro,
293 * but it isn't called during normal operation so we can afford
294 * to make it a function.
295 */
296static void xl_wait(sc)
297 struct xl_softc *sc;
298{
299 register int i;
300
301 for (i = 0; i < XL_TIMEOUT; i++) {
302 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
303 break;
304 }
305
306 if (i == XL_TIMEOUT)
307 printf("xl%d: command never completed!\n", sc->xl_unit);
308
309 return;
310}
311
312/*
313 * MII access routines are provided for adapters with external
314 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
315 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
316 * Note: if you don't perform the MDIO operations just right,
317 * it's possible to end up with code that works correctly with
318 * some chips/CPUs/processor speeds/bus speeds/etc but not
319 * with others.
320 */
321#define MII_SET(x) \
322 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
323 CSR_READ_2(sc, XL_W4_PHY_MGMT) | x)
324
325#define MII_CLR(x) \
326 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
327 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~x)
328
329/*
330 * Sync the PHYs by setting data bit and strobing the clock 32 times.
331 */
332static void xl_mii_sync(sc)
333 struct xl_softc *sc;
334{
335 register int i;
336
337 XL_SEL_WIN(4);
338 MII_SET(XL_MII_DIR|XL_MII_DATA);
339
340 for (i = 0; i < 32; i++) {
341 MII_SET(XL_MII_CLK);
342 DELAY(1);
343 MII_CLR(XL_MII_CLK);
344 DELAY(1);
345 }
346
347 return;
348}
349
350/*
351 * Clock a series of bits through the MII.
352 */
353static void xl_mii_send(sc, bits, cnt)
354 struct xl_softc *sc;
355 u_int32_t bits;
356 int cnt;
357{
358 int i;
359
360 XL_SEL_WIN(4);
361 MII_CLR(XL_MII_CLK);
362
363 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
364 if (bits & i) {
365 MII_SET(XL_MII_DATA);
366 } else {
367 MII_CLR(XL_MII_DATA);
368 }
369 DELAY(1);
370 MII_CLR(XL_MII_CLK);
371 DELAY(1);
372 MII_SET(XL_MII_CLK);
373 }
374}
375
376/*
377 * Read an PHY register through the MII.
378 */
379static int xl_mii_readreg(sc, frame)
380 struct xl_softc *sc;
381 struct xl_mii_frame *frame;
382
383{
384 int i, ack, s;
385
386 s = splimp();
387
388 /*
389 * Set up frame for RX.
390 */
391 frame->mii_stdelim = XL_MII_STARTDELIM;
392 frame->mii_opcode = XL_MII_READOP;
393 frame->mii_turnaround = 0;
394 frame->mii_data = 0;
395
396 /*
397 * Select register window 4.
398 */
399
400 XL_SEL_WIN(4);
401
402 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
403 /*
404 * Turn on data xmit.
405 */
406 MII_SET(XL_MII_DIR);
407
408 xl_mii_sync(sc);
409
410 /*
411 * Send command/address info.
412 */
413 xl_mii_send(sc, frame->mii_stdelim, 2);
414 xl_mii_send(sc, frame->mii_opcode, 2);
415 xl_mii_send(sc, frame->mii_phyaddr, 5);
416 xl_mii_send(sc, frame->mii_regaddr, 5);
417
418 /* Idle bit */
419 MII_CLR((XL_MII_CLK|XL_MII_DATA));
420 DELAY(1);
421 MII_SET(XL_MII_CLK);
422 DELAY(1);
423
424 /* Turn off xmit. */
425 MII_CLR(XL_MII_DIR);
426
427 /* Check for ack */
428 MII_CLR(XL_MII_CLK);
429 DELAY(1);
430 MII_SET(XL_MII_CLK);
431 DELAY(1);
432 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
433
434 /*
435 * Now try reading data bits. If the ack failed, we still
436 * need to clock through 16 cycles to keep the PHY(s) in sync.
437 */
438 if (ack) {
439 for(i = 0; i < 16; i++) {
440 MII_CLR(XL_MII_CLK);
441 DELAY(1);
442 MII_SET(XL_MII_CLK);
443 DELAY(1);
444 }
445 goto fail;
446 }
447
448 for (i = 0x8000; i; i >>= 1) {
449 MII_CLR(XL_MII_CLK);
450 DELAY(1);
451 if (!ack) {
452 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
453 frame->mii_data |= i;
454 DELAY(1);
455 }
456 MII_SET(XL_MII_CLK);
457 DELAY(1);
458 }
459
460fail:
461
462 MII_CLR(XL_MII_CLK);
463 DELAY(1);
464 MII_SET(XL_MII_CLK);
465 DELAY(1);
466
467 splx(s);
468
469 if (ack)
470 return(1);
471 return(0);
472}
473
474/*
475 * Write to a PHY register through the MII.
476 */
477static int xl_mii_writereg(sc, frame)
478 struct xl_softc *sc;
479 struct xl_mii_frame *frame;
480
481{
482 int s;
483
484 s = splimp();
485 /*
486 * Set up frame for TX.
487 */
488
489 frame->mii_stdelim = XL_MII_STARTDELIM;
490 frame->mii_opcode = XL_MII_WRITEOP;
491 frame->mii_turnaround = XL_MII_TURNAROUND;
492
493 /*
494 * Select the window 4.
495 */
496 XL_SEL_WIN(4);
497
498 /*
499 * Turn on data output.
500 */
501 MII_SET(XL_MII_DIR);
502
503 xl_mii_sync(sc);
504
505 xl_mii_send(sc, frame->mii_stdelim, 2);
506 xl_mii_send(sc, frame->mii_opcode, 2);
507 xl_mii_send(sc, frame->mii_phyaddr, 5);
508 xl_mii_send(sc, frame->mii_regaddr, 5);
509 xl_mii_send(sc, frame->mii_turnaround, 2);
510 xl_mii_send(sc, frame->mii_data, 16);
511
512 /* Idle bit. */
513 MII_SET(XL_MII_CLK);
514 DELAY(1);
515 MII_CLR(XL_MII_CLK);
516 DELAY(1);
517
518 /*
519 * Turn off xmit.
520 */
521 MII_CLR(XL_MII_DIR);
522
523 splx(s);
524
525 return(0);
526}
527
528static int xl_miibus_readreg(dev, phy, reg)
529 device_t dev;
530 int phy, reg;
531{
532 struct xl_softc *sc;
533 struct xl_mii_frame frame;
534
535 /*
536 * Pretend that PHYs are only available at MII address 24.
537 * This is to guard against problems with certain 3Com ASIC
538 * revisions that incorrectly map the internal transceiver
539 * control registers at all MII addresses. This can cause
540 * the miibus code to attach the same PHY several times over.
541 */
542 if (phy != 24)
543 return(0);
544
545 sc = device_get_softc(dev);
546
547 bzero((char *)&frame, sizeof(frame));
548
549 frame.mii_phyaddr = phy;
550 frame.mii_regaddr = reg;
551 xl_mii_readreg(sc, &frame);
552
553 return(frame.mii_data);
554}
555
556static int xl_miibus_writereg(dev, phy, reg, data)
557 device_t dev;
558 int phy, reg, data;
559{
560 struct xl_softc *sc;
561 struct xl_mii_frame frame;
562
563 if (phy != 24)
564 return(0);
565
566 sc = device_get_softc(dev);
567
568 bzero((char *)&frame, sizeof(frame));
569
570 frame.mii_phyaddr = phy;
571 frame.mii_regaddr = reg;
572 frame.mii_data = data;
573
574 xl_mii_writereg(sc, &frame);
575
576 return(0);
577}
578
579static void xl_miibus_statchg(dev)
580 device_t dev;
581{
582 struct xl_softc *sc;
583 struct mii_data *mii;
584
585
586 sc = device_get_softc(dev);
587 mii = device_get_softc(sc->xl_miibus);
588
589 xl_setcfg(sc);
590
591 /* Set ASIC's duplex mode to match the PHY. */
592 XL_SEL_WIN(3);
593 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
594 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
595 else
596 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
597 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
598
599 return;
600}
601
602/*
603 * Special support for the 3c905B-COMBO. This card has 10/100 support
604 * plus BNC and AUI ports. This means we will have both an miibus attached
605 * plus some non-MII media settings. In order to allow this, we have to
606 * add the extra media to the miibus's ifmedia struct, but we can't do
607 * that during xl_attach() because the miibus hasn't been attached yet.
608 * So instead, we wait until the miibus probe/attach is done, at which
609 * point we will get a callback telling is that it's safe to add our
610 * extra media.
611 */
612static void xl_miibus_mediainit(dev)
613 device_t dev;
614{
615 struct xl_softc *sc;
616 struct mii_data *mii;
617 struct ifmedia *ifm;
618
619 sc = device_get_softc(dev);
620 mii = device_get_softc(sc->xl_miibus);
621 ifm = &mii->mii_media;
622
623 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
624 /*
625 * Check for a 10baseFL board in disguise.
626 */
627 if (sc->xl_type == XL_TYPE_905B &&
628 sc->xl_media == XL_MEDIAOPT_10FL) {
629 if (bootverbose)
630 printf("xl%d: found 10baseFL\n", sc->xl_unit);
631 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
632 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
633 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
634 ifmedia_add(ifm,
635 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
636 } else {
637 if (bootverbose)
638 printf("xl%d: found AUI\n", sc->xl_unit);
639 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
640 }
641 }
642
643 if (sc->xl_media & XL_MEDIAOPT_BNC) {
644 if (bootverbose)
645 printf("xl%d: found BNC\n", sc->xl_unit);
646 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
647 }
648
649 return;
650}
651
652/*
653 * The EEPROM is slow: give it time to come ready after issuing
654 * it a command.
655 */
656static int xl_eeprom_wait(sc)
657 struct xl_softc *sc;
658{
659 int i;
660
661 for (i = 0; i < 100; i++) {
662 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
663 DELAY(162);
664 else
665 break;
666 }
667
668 if (i == 100) {
669 printf("xl%d: eeprom failed to come ready\n", sc->xl_unit);
670 return(1);
671 }
672
673 return(0);
674}
675
676/*
677 * Read a sequence of words from the EEPROM. Note that ethernet address
678 * data is stored in the EEPROM in network byte order.
679 */
680static int xl_read_eeprom(sc, dest, off, cnt, swap)
681 struct xl_softc *sc;
682 caddr_t dest;
683 int off;
684 int cnt;
685 int swap;
686{
687 int err = 0, i;
688 u_int16_t word = 0, *ptr;
689
690 XL_SEL_WIN(0);
691
692 if (xl_eeprom_wait(sc))
693 return(1);
694
695 for (i = 0; i < cnt; i++) {
696 CSR_WRITE_2(sc, XL_W0_EE_CMD, XL_EE_READ | (off + i));
697 err = xl_eeprom_wait(sc);
698 if (err)
699 break;
700 word = CSR_READ_2(sc, XL_W0_EE_DATA);
701 ptr = (u_int16_t *)(dest + (i * 2));
702 if (swap)
703 *ptr = ntohs(word);
704 else
705 *ptr = word;
706 }
707
708 return(err ? 1 : 0);
709}
710
711/*
712 * This routine is taken from the 3Com Etherlink XL manual,
713 * page 10-7. It calculates a CRC of the supplied multicast
714 * group address and returns the lower 8 bits, which are used
715 * as the multicast filter position.
716 * Note: the 3c905B currently only supports a 64-bit hash table,
717 * which means we really only need 6 bits, but the manual indicates
718 * that future chip revisions will have a 256-bit hash table,
719 * hence the routine is set up to calculate 8 bits of position
720 * info in case we need it some day.
721 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a
722 * 256 bit hash table. This means we have to use all 8 bits regardless.
723 * On older cards, the upper 2 bits will be ignored. Grrrr....
724 */
725static u_int8_t xl_calchash(addr)
726 caddr_t addr;
727{
728 u_int32_t crc, carry;
729 int i, j;
730 u_int8_t c;
731
732 /* Compute CRC for the address value. */
733 crc = 0xFFFFFFFF; /* initial value */
734
735 for (i = 0; i < 6; i++) {
736 c = *(addr + i);
737 for (j = 0; j < 8; j++) {
738 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
739 crc <<= 1;
740 c >>= 1;
741 if (carry)
742 crc = (crc ^ 0x04c11db6) | carry;
743 }
744 }
745
746 /* return the filter bit position */
747 return(crc & 0x000000FF);
748}
749
750/*
751 * NICs older than the 3c905B have only one multicast option, which
752 * is to enable reception of all multicast frames.
753 */
754static void xl_setmulti(sc)
755 struct xl_softc *sc;
756{
757 struct ifnet *ifp;
758 struct ifmultiaddr *ifma;
759 u_int8_t rxfilt;
760 int mcnt = 0;
761
762 ifp = &sc->arpcom.ac_if;
763
764 XL_SEL_WIN(5);
765 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
766
767 if (ifp->if_flags & IFF_ALLMULTI) {
768 rxfilt |= XL_RXFILTER_ALLMULTI;
769 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
770 return;
771 }
772
773 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
774 ifma = ifma->ifma_link.le_next)
775 mcnt++;
776
777 if (mcnt)
778 rxfilt |= XL_RXFILTER_ALLMULTI;
779 else
780 rxfilt &= ~XL_RXFILTER_ALLMULTI;
781
782 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
783
784 return;
785}
786
787/*
788 * 3c905B adapters have a hash filter that we can program.
789 */
790static void xl_setmulti_hash(sc)
791 struct xl_softc *sc;
792{
793 struct ifnet *ifp;
794 int h = 0, i;
795 struct ifmultiaddr *ifma;
796 u_int8_t rxfilt;
797 int mcnt = 0;
798
799 ifp = &sc->arpcom.ac_if;
800
801 XL_SEL_WIN(5);
802 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
803
804 if (ifp->if_flags & IFF_ALLMULTI) {
805 rxfilt |= XL_RXFILTER_ALLMULTI;
806 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
807 return;
808 } else
809 rxfilt &= ~XL_RXFILTER_ALLMULTI;
810
811
812 /* first, zot all the existing hash bits */
813 for (i = 0; i < XL_HASHFILT_SIZE; i++)
814 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
815
816 /* now program new ones */
817 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
818 ifma = ifma->ifma_link.le_next) {
819 if (ifma->ifma_addr->sa_family != AF_LINK)
820 continue;
821 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
822 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
823 mcnt++;
824 }
825
826 if (mcnt)
827 rxfilt |= XL_RXFILTER_MULTIHASH;
828 else
829 rxfilt &= ~XL_RXFILTER_MULTIHASH;
830
831 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
832
833 return;
834}
835
836#ifdef notdef
837static void xl_testpacket(sc)
838 struct xl_softc *sc;
839{
840 struct mbuf *m;
841 struct ifnet *ifp;
842
843 ifp = &sc->arpcom.ac_if;
844
845 MGETHDR(m, M_DONTWAIT, MT_DATA);
846
847 if (m == NULL)
848 return;
849
850 bcopy(&sc->arpcom.ac_enaddr,
851 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
852 bcopy(&sc->arpcom.ac_enaddr,
853 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
854 mtod(m, struct ether_header *)->ether_type = htons(3);
855 mtod(m, unsigned char *)[14] = 0;
856 mtod(m, unsigned char *)[15] = 0;
857 mtod(m, unsigned char *)[16] = 0xE3;
858 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
859 IF_ENQUEUE(&ifp->if_snd, m);
860 xl_start(ifp);
861
862 return;
863}
864#endif
865
866static void xl_setcfg(sc)
867 struct xl_softc *sc;
868{
869 u_int32_t icfg;
870
871 XL_SEL_WIN(3);
872 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
873 icfg &= ~XL_ICFG_CONNECTOR_MASK;
874 if (sc->xl_media & XL_MEDIAOPT_MII ||
875 sc->xl_media & XL_MEDIAOPT_BT4)
876 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
877 if (sc->xl_media & XL_MEDIAOPT_BTX)
878 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
879
880 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
881 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
882
883 return;
884}
885
886static void xl_setmode(sc, media)
887 struct xl_softc *sc;
888 int media;
889{
890 u_int32_t icfg;
891 u_int16_t mediastat;
892
893 printf("xl%d: selecting ", sc->xl_unit);
894
895 XL_SEL_WIN(4);
896 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
897 XL_SEL_WIN(3);
898 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
899
900 if (sc->xl_media & XL_MEDIAOPT_BT) {
901 if (IFM_SUBTYPE(media) == IFM_10_T) {
902 printf("10baseT transceiver, ");
903 sc->xl_xcvr = XL_XCVR_10BT;
904 icfg &= ~XL_ICFG_CONNECTOR_MASK;
905 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
906 mediastat |= XL_MEDIASTAT_LINKBEAT|
907 XL_MEDIASTAT_JABGUARD;
908 mediastat &= ~XL_MEDIASTAT_SQEENB;
909 }
910 }
911
912 if (sc->xl_media & XL_MEDIAOPT_BFX) {
913 if (IFM_SUBTYPE(media) == IFM_100_FX) {
914 printf("100baseFX port, ");
915 sc->xl_xcvr = XL_XCVR_100BFX;
916 icfg &= ~XL_ICFG_CONNECTOR_MASK;
917 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
918 mediastat |= XL_MEDIASTAT_LINKBEAT;
919 mediastat &= ~XL_MEDIASTAT_SQEENB;
920 }
921 }
922
923 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
924 if (IFM_SUBTYPE(media) == IFM_10_5) {
925 printf("AUI port, ");
926 sc->xl_xcvr = XL_XCVR_AUI;
927 icfg &= ~XL_ICFG_CONNECTOR_MASK;
928 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
929 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
930 XL_MEDIASTAT_JABGUARD);
931 mediastat |= ~XL_MEDIASTAT_SQEENB;
932 }
933 if (IFM_SUBTYPE(media) == IFM_10_FL) {
934 printf("10baseFL transceiver, ");
935 sc->xl_xcvr = XL_XCVR_AUI;
936 icfg &= ~XL_ICFG_CONNECTOR_MASK;
937 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
938 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
939 XL_MEDIASTAT_JABGUARD);
940 mediastat |= ~XL_MEDIASTAT_SQEENB;
941 }
942 }
943
944 if (sc->xl_media & XL_MEDIAOPT_BNC) {
945 if (IFM_SUBTYPE(media) == IFM_10_2) {
946 printf("BNC port, ");
947 sc->xl_xcvr = XL_XCVR_COAX;
948 icfg &= ~XL_ICFG_CONNECTOR_MASK;
949 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
950 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
951 XL_MEDIASTAT_JABGUARD|
952 XL_MEDIASTAT_SQEENB);
953 }
954 }
955
956 if ((media & IFM_GMASK) == IFM_FDX ||
957 IFM_SUBTYPE(media) == IFM_100_FX) {
958 printf("full duplex\n");
959 XL_SEL_WIN(3);
960 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
961 } else {
962 printf("half duplex\n");
963 XL_SEL_WIN(3);
964 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
965 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
966 }
967
968 if (IFM_SUBTYPE(media) == IFM_10_2)
969 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
970 else
971 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
972 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
973 XL_SEL_WIN(4);
974 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
975 DELAY(800);
976 XL_SEL_WIN(7);
977
978 return;
979}
980
981static void xl_reset(sc)
982 struct xl_softc *sc;
983{
984 register int i;
985
986 XL_SEL_WIN(0);
987 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET);
988
989 for (i = 0; i < XL_TIMEOUT; i++) {
990 DELAY(10);
991 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
992 break;
993 }
994
995 if (i == XL_TIMEOUT)
996 printf("xl%d: reset didn't complete\n", sc->xl_unit);
997
998 DELAY(100000);
999
1000 /* Reset TX and RX. */
1001 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1002 xl_wait(sc);
1003 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1004 xl_wait(sc);
1005
1006 /* Wait a little while for the chip to get its brains in order. */
1007 DELAY(100000);
1008 return;
1009}
1010
1011/*
1012 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1013 * IDs against our list and return a device name if we find a match.
1014 */
1015static int xl_probe(dev)
1016 device_t dev;
1017{
1018 struct xl_type *t;
1019
1020 t = xl_devs;
1021
1022 while(t->xl_name != NULL) {
1023 if ((pci_get_vendor(dev) == t->xl_vid) &&
1024 (pci_get_device(dev) == t->xl_did)) {
1025 device_set_desc(dev, t->xl_name);
1026 return(0);
1027 }
1028 t++;
1029 }
1030
1031 return(ENXIO);
1032}
1033
1034/*
1035 * This routine is a kludge to work around possible hardware faults
1036 * or manufacturing defects that can cause the media options register
1037 * (or reset options register, as it's called for the first generation
1038 * 3c90x adapters) to return an incorrect result. I have encountered
1039 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1040 * which doesn't have any of the 'mediaopt' bits set. This screws up
1041 * the attach routine pretty badly because it doesn't know what media
1042 * to look for. If we find ourselves in this predicament, this routine
1043 * will try to guess the media options values and warn the user of a
1044 * possible manufacturing defect with his adapter/system/whatever.
1045 */
1046static void xl_mediacheck(sc)
1047 struct xl_softc *sc;
1048{
1049
1050 /*
1051 * If some of the media options bits are set, assume they are
1052 * correct. If not, try to figure it out down below.
1053 * XXX I should check for 10baseFL, but I don't have an adapter
1054 * to test with.
1055 */
1056 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1057 /*
1058 * Check the XCVR value. If it's not in the normal range
1059 * of values, we need to fake it up here.
1060 */
1061 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1062 return;
1063 else {
1064 printf("xl%d: bogus xcvr value "
1065 "in EEPROM (%x)\n", sc->xl_unit, sc->xl_xcvr);
1066 printf("xl%d: choosing new default based "
1067 "on card type\n", sc->xl_unit);
1068 }
1069 } else {
1070 if (sc->xl_type == XL_TYPE_905B &&
1071 sc->xl_media & XL_MEDIAOPT_10FL)
1072 return;
1073 printf("xl%d: WARNING: no media options bits set in "
1074 "the media options register!!\n", sc->xl_unit);
1075 printf("xl%d: this could be a manufacturing defect in "
1076 "your adapter or system\n", sc->xl_unit);
1077 printf("xl%d: attempting to guess media type; you "
1078 "should probably consult your vendor\n", sc->xl_unit);
1079 }
1080
1081 xl_choose_xcvr(sc, 1);
1082
1083 return;
1084}
1085
1086static void xl_choose_xcvr(sc, verbose)
1087 struct xl_softc *sc;
1088 int verbose;
1089{
1090 u_int16_t devid;
1091
1092 /*
1093 * Read the device ID from the EEPROM.
1094 * This is what's loaded into the PCI device ID register, so it has
1095 * to be correct otherwise we wouldn't have gotten this far.
1096 */
1097 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1098
1099 switch(devid) {
1100 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1101 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1102 sc->xl_media = XL_MEDIAOPT_BT;
1103 sc->xl_xcvr = XL_XCVR_10BT;
1104 if (verbose)
1105 printf("xl%d: guessing 10BaseT "
1106 "transceiver\n", sc->xl_unit);
1107 break;
1108 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1109 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1110 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1111 sc->xl_xcvr = XL_XCVR_10BT;
1112 if (verbose)
1113 printf("xl%d: guessing COMBO "
1114 "(AUI/BNC/TP)\n", sc->xl_unit);
1115 break;
1116 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1117 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1118 sc->xl_xcvr = XL_XCVR_10BT;
1119 if (verbose)
1120 printf("xl%d: guessing TPC (BNC/TP)\n", sc->xl_unit);
1121 break;
1122 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1123 sc->xl_media = XL_MEDIAOPT_10FL;
1124 sc->xl_xcvr = XL_XCVR_AUI;
1125 if (verbose)
1126 printf("xl%d: guessing 10baseFL\n", sc->xl_unit);
1127 break;
1128 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1129 sc->xl_media = XL_MEDIAOPT_MII;
1130 sc->xl_xcvr = XL_XCVR_MII;
1131 if (verbose)
1132 printf("xl%d: guessing MII\n", sc->xl_unit);
1133 break;
1134 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1135 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1136 sc->xl_media = XL_MEDIAOPT_BT4;
1137 sc->xl_xcvr = XL_XCVR_MII;
1138 if (verbose)
1139 printf("xl%d: guessing 100BaseT4/MII\n", sc->xl_unit);
1140 break;
1141 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1142 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1143 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1144 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1145 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1146 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1147 sc->xl_media = XL_MEDIAOPT_BTX;
1148 sc->xl_xcvr = XL_XCVR_AUTO;
1149 if (verbose)
1150 printf("xl%d: guessing 10/100 internal\n", sc->xl_unit);
1151 break;
1152 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1153 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1154 sc->xl_xcvr = XL_XCVR_AUTO;
1155 if (verbose)
1156 printf("xl%d: guessing 10/100 "
1157 "plus BNC/AUI\n", sc->xl_unit);
1158 break;
1159 default:
1160 printf("xl%d: unknown device ID: %x -- "
1161 "defaulting to 10baseT\n", sc->xl_unit, devid);
1162 sc->xl_media = XL_MEDIAOPT_BT;
1163 break;
1164 }
1165
1166 return;
1167}
1168
1169/*
1170 * Attach the interface. Allocate softc structures, do ifmedia
1171 * setup and ethernet/BPF attach.
1172 */
1173static int xl_attach(dev)
1174 device_t dev;
1175{
1176 int s;
1177 u_char eaddr[ETHER_ADDR_LEN];
1178 u_int32_t command;
1179 struct xl_softc *sc;
1180 struct ifnet *ifp;
1181 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1182 int unit, error = 0, rid;
1183
1184 s = splimp();
1185
1186 sc = device_get_softc(dev);
1187 unit = device_get_unit(dev);
1188
1189 /*
1190 * If this is a 3c905B, we have to check one extra thing.
1191 * The 905B supports power management and may be placed in
1192 * a low-power mode (D3 mode), typically by certain operating
1193 * systems which shall not be named. The PCI BIOS is supposed
1194 * to reset the NIC and bring it out of low-power mode, but
1195 * some do not. Consequently, we have to see if this chip
1196 * supports power management, and if so, make sure it's not
1197 * in low-power mode. If power management is available, the
1198 * capid byte will be 0x01.
1199 *
1200 * I _think_ that what actually happens is that the chip
1201 * loses its PCI configuration during the transition from
1202 * D3 back to D0; this means that it should be possible for
1203 * us to save the PCI iobase, membase and IRQ, put the chip
1204 * back in the D0 state, then restore the PCI config ourselves.
1205 */
1206
1207 command = pci_read_config(dev, XL_PCI_CAPID, 4) & 0x000000FF;
1208 if (command == 0x01) {
1209
1210 command = pci_read_config(dev, XL_PCI_PWRMGMTCTRL, 4);
1211 if (command & XL_PSTATE_MASK) {
1212 u_int32_t iobase, membase, irq;
1213
1214 /* Save important PCI config data. */
1215 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1216 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1217 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1218
1219 /* Reset the power state. */
1220 printf("xl%d: chip is in D%d power mode "
1221 "-- setting to D0\n", unit, command & XL_PSTATE_MASK);
1222 command &= 0xFFFFFFFC;
1223 pci_write_config(dev, XL_PCI_PWRMGMTCTRL, command, 4);
1224
1225 /* Restore PCI config data. */
1226 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1227 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1228 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1229 }
1230 }
1231
1232 /*
1233 * Map control/status registers.
1234 */
1235 command = pci_read_config(dev, PCIR_COMMAND, 4);
1236 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1237 pci_write_config(dev, PCIR_COMMAND, command, 4);
1238 command = pci_read_config(dev, PCIR_COMMAND, 4);
1239
1240#ifdef XL_USEIOSPACE
1241 if (!(command & PCIM_CMD_PORTEN)) {
1242 printf("xl%d: failed to enable I/O ports!\n", unit);
1243 error = ENXIO;
1244 goto fail;
1245 }
1246#else
1247 if (!(command & PCIM_CMD_MEMEN)) {
1248 printf("xl%d: failed to enable memory mapping!\n", unit);
1249 error = ENXIO;
1250 goto fail;
1251 }
1252#endif
1253
1254 rid = XL_RID;
1255 sc->xl_res = bus_alloc_resource(dev, XL_RES, &rid,
1256 0, ~0, 1, RF_ACTIVE);
1257
1258 if (sc->xl_res == NULL) {
1259 printf ("xl%d: couldn't map ports/memory\n", unit);
1260 error = ENXIO;
1261 goto fail;
1262 }
1263
1264 sc->xl_btag = rman_get_bustag(sc->xl_res);
1265 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1266
1267 rid = 0;
1268 sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1269 RF_SHAREABLE | RF_ACTIVE);
1270
1271 if (sc->xl_irq == NULL) {
1272 printf("xl%d: couldn't map interrupt\n", unit);
1273 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1274 error = ENXIO;
1275 goto fail;
1276 }
1277
1278 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET,
1279 xl_intr, sc, &sc->xl_intrhand);
1280
1281 if (error) {
1282 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1283 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1284 printf("xl%d: couldn't set up irq\n", unit);
1285 goto fail;
1286 }
1287
1288 /* Reset the adapter. */
1289 xl_reset(sc);
1290
1291 /*
1292 * Get station address from the EEPROM.
1293 */
1294 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1295 printf("xl%d: failed to read station address\n", sc->xl_unit);
1296 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1297 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1298 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1299 error = ENXIO;
1300 goto fail;
1301 }
1302
1303 /*
1304 * A 3Com chip was detected. Inform the world.
1305 */
1306 printf("xl%d: Ethernet address: %6D\n", unit, eaddr, ":");
1307
1308 sc->xl_unit = unit;
1309 callout_handle_init(&sc->xl_stat_ch);
1310 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1311
1312 sc->xl_ldata = contigmalloc(sizeof(struct xl_list_data), M_DEVBUF,
1313 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1314
1315 if (sc->xl_ldata == NULL) {
1316 printf("xl%d: no memory for list buffers!\n", unit);
1317 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1318 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1319 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1320 error = ENXIO;
1321 goto fail;
1322 }
1323
1324 bzero(sc->xl_ldata, sizeof(struct xl_list_data));
1325
1326 /*
1327 * Figure out the card type. 3c905B adapters have the
1328 * 'supportsNoTxLength' bit set in the capabilities
1329 * word in the EEPROM.
1330 */
1331 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1332 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH)
1333 sc->xl_type = XL_TYPE_905B;
1334 else
1335 sc->xl_type = XL_TYPE_90X;
1336
1337 ifp = &sc->arpcom.ac_if;
1338 ifp->if_softc = sc;
1339 ifp->if_unit = unit;
1340 ifp->if_name = "xl";
1341 ifp->if_mtu = ETHERMTU;
1342 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1343 ifp->if_ioctl = xl_ioctl;
1344 ifp->if_output = ether_output;
1345 if (sc->xl_type == XL_TYPE_905B)
1346 ifp->if_start = xl_start_90xB;
1347 else
1348 ifp->if_start = xl_start;
1349 ifp->if_watchdog = xl_watchdog;
1350 ifp->if_init = xl_init;
1351 ifp->if_baudrate = 10000000;
1352 ifp->if_snd.ifq_maxlen = XL_TX_LIST_CNT - 1;
1353
1354 /*
1355 * Now we have to see what sort of media we have.
1356 * This includes probing for an MII interace and a
1357 * possible PHY.
1358 */
1359 XL_SEL_WIN(3);
1360 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1361 if (bootverbose)
1362 printf("xl%d: media options word: %x\n", sc->xl_unit,
1363 sc->xl_media);
1364
1365 xl_read_eeprom(sc, (char *)&sc->xl_xcvr, XL_EE_ICFG_0, 2, 0);
1366 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1367 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1368
1369 xl_mediacheck(sc);
1370
1371 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1372 || sc->xl_media & XL_MEDIAOPT_BT4) {
1373 if (bootverbose)
1374 printf("xl%d: found MII/AUTO\n", sc->xl_unit);
1375 xl_setcfg(sc);
1376 if (mii_phy_probe(dev, &sc->xl_miibus,
1377 xl_ifmedia_upd, xl_ifmedia_sts)) {
1378 printf("xl%d: no PHY found!\n", sc->xl_unit);
1379 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1380 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1381 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1382 contigfree(sc->xl_ldata,
1383 sizeof(struct xl_list_data), M_DEVBUF);
1384 error = ENXIO;
1385 goto fail;
1386 }
1387
1388 goto done;
1389 }
1390
1391 /*
1392 * Sanity check. If the user has selected "auto" and this isn't
1393 * a 10/100 card of some kind, we need to force the transceiver
1394 * type to something sane.
1395 */
1396 if (sc->xl_xcvr == XL_XCVR_AUTO)
1397 xl_choose_xcvr(sc, bootverbose);
1398
1399 /*
1400 * Do ifmedia setup.
1401 */
1402
1403 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1404
1405 if (sc->xl_media & XL_MEDIAOPT_BT) {
1406 if (bootverbose)
1407 printf("xl%d: found 10baseT\n", sc->xl_unit);
1408 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1409 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1410 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1411 ifmedia_add(&sc->ifmedia,
1412 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1413 }
1414
1415 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1416 /*
1417 * Check for a 10baseFL board in disguise.
1418 */
1419 if (sc->xl_type == XL_TYPE_905B &&
1420 sc->xl_media == XL_MEDIAOPT_10FL) {
1421 if (bootverbose)
1422 printf("xl%d: found 10baseFL\n", sc->xl_unit);
1423 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1424 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1425 0, NULL);
1426 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1427 ifmedia_add(&sc->ifmedia,
1428 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1429 } else {
1430 if (bootverbose)
1431 printf("xl%d: found AUI\n", sc->xl_unit);
1432 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1433 }
1434 }
1435
1436 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1437 if (bootverbose)
1438 printf("xl%d: found BNC\n", sc->xl_unit);
1439 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1440 }
1441
1442 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1443 if (bootverbose)
1444 printf("xl%d: found 100baseFX\n", sc->xl_unit);
1445 ifp->if_baudrate = 100000000;
1446 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1447 }
1448
1449 /* Choose a default media. */
1450 switch(sc->xl_xcvr) {
1451 case XL_XCVR_10BT:
1452 media = IFM_ETHER|IFM_10_T;
1453 xl_setmode(sc, media);
1454 break;
1455 case XL_XCVR_AUI:
1456 if (sc->xl_type == XL_TYPE_905B &&
1457 sc->xl_media == XL_MEDIAOPT_10FL) {
1458 media = IFM_ETHER|IFM_10_FL;
1459 xl_setmode(sc, media);
1460 } else {
1461 media = IFM_ETHER|IFM_10_5;
1462 xl_setmode(sc, media);
1463 }
1464 break;
1465 case XL_XCVR_COAX:
1466 media = IFM_ETHER|IFM_10_2;
1467 xl_setmode(sc, media);
1468 break;
1469 case XL_XCVR_AUTO:
1470 case XL_XCVR_100BTX:
1471 case XL_XCVR_MII:
1472 /* Chosen by miibus */
1473 break;
1474 case XL_XCVR_100BFX:
1475 media = IFM_ETHER|IFM_100_FX;
1476 break;
1477 default:
1478 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit,
1479 sc->xl_xcvr);
1480 /*
1481 * This will probably be wrong, but it prevents
1482 * the ifmedia code from panicking.
1483 */
1484 media = IFM_ETHER|IFM_10_T;
1485 break;
1486 }
1487
1488 if (sc->xl_miibus == NULL)
1489 ifmedia_set(&sc->ifmedia, media);
1490
1491done:
1492
1493 /*
|
1521
1522 /* Delete any miibus and phy devices attached to this interface */
1523 if (sc->xl_miibus != NULL) {
1524 bus_generic_detach(dev);
1525 device_delete_child(dev, sc->xl_miibus);
1526 }
1527
1528 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1529 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1530 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1531
1532 ifmedia_removeall(&sc->ifmedia);
1533 contigfree(sc->xl_ldata, sizeof(struct xl_list_data), M_DEVBUF);
1534
1535 splx(s);
1536
1537 return(0);
1538}
1539
1540/*
1541 * Initialize the transmit descriptors.
1542 */
1543static int xl_list_tx_init(sc)
1544 struct xl_softc *sc;
1545{
1546 struct xl_chain_data *cd;
1547 struct xl_list_data *ld;
1548 int i;
1549
1550 cd = &sc->xl_cdata;
1551 ld = sc->xl_ldata;
1552 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1553 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1554 if (i == (XL_TX_LIST_CNT - 1))
1555 cd->xl_tx_chain[i].xl_next = NULL;
1556 else
1557 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1558 }
1559
1560 cd->xl_tx_free = &cd->xl_tx_chain[0];
1561 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1562
1563 return(0);
1564}
1565
1566/*
1567 * Initialize the transmit descriptors.
1568 */
1569static int xl_list_tx_init_90xB(sc)
1570 struct xl_softc *sc;
1571{
1572 struct xl_chain_data *cd;
1573 struct xl_list_data *ld;
1574 int i;
1575
1576 cd = &sc->xl_cdata;
1577 ld = sc->xl_ldata;
1578 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1579 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1580 cd->xl_tx_chain[i].xl_phys = vtophys(&ld->xl_tx_list[i]);
1581 if (i == (XL_TX_LIST_CNT - 1))
1582 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1583 else
1584 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1585 if (i == 0)
1586 cd->xl_tx_chain[i].xl_prev =
1587 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1588 else
1589 cd->xl_tx_chain[i].xl_prev =
1590 &cd->xl_tx_chain[i - 1];
1591 }
1592
1593 bzero((char *)ld->xl_tx_list,
1594 sizeof(struct xl_list) * XL_TX_LIST_CNT);
1595 ld->xl_tx_list[0].xl_status = XL_TXSTAT_EMPTY;
1596
1597 cd->xl_tx_prod = 1;
1598 cd->xl_tx_cons = 1;
1599 cd->xl_tx_cnt = 0;
1600
1601 return(0);
1602}
1603
1604/*
1605 * Initialize the RX descriptors and allocate mbufs for them. Note that
1606 * we arrange the descriptors in a closed ring, so that the last descriptor
1607 * points back to the first.
1608 */
1609static int xl_list_rx_init(sc)
1610 struct xl_softc *sc;
1611{
1612 struct xl_chain_data *cd;
1613 struct xl_list_data *ld;
1614 int i;
1615
1616 cd = &sc->xl_cdata;
1617 ld = sc->xl_ldata;
1618
1619 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1620 cd->xl_rx_chain[i].xl_ptr =
1621 (struct xl_list_onefrag *)&ld->xl_rx_list[i];
1622 if (xl_newbuf(sc, &cd->xl_rx_chain[i]) == ENOBUFS)
1623 return(ENOBUFS);
1624 if (i == (XL_RX_LIST_CNT - 1)) {
1625 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[0];
1626 ld->xl_rx_list[i].xl_next =
1627 vtophys(&ld->xl_rx_list[0]);
1628 } else {
1629 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[i + 1];
1630 ld->xl_rx_list[i].xl_next =
1631 vtophys(&ld->xl_rx_list[i + 1]);
1632 }
1633 }
1634
1635 cd->xl_rx_head = &cd->xl_rx_chain[0];
1636
1637 return(0);
1638}
1639
1640/*
1641 * Initialize an RX descriptor and attach an MBUF cluster.
1642 */
1643static int xl_newbuf(sc, c)
1644 struct xl_softc *sc;
1645 struct xl_chain_onefrag *c;
1646{
1647 struct mbuf *m_new = NULL;
1648
1649 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1650 if (m_new == NULL) {
1651 printf("xl%d: no memory for rx list -- "
1652 "packet dropped!\n", sc->xl_unit);
1653 return(ENOBUFS);
1654 }
1655
1656 MCLGET(m_new, M_DONTWAIT);
1657 if (!(m_new->m_flags & M_EXT)) {
1658 printf("xl%d: no memory for rx list -- "
1659 "packet dropped!\n", sc->xl_unit);
1660 m_freem(m_new);
1661 return(ENOBUFS);
1662 }
1663
1664 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1665
1666 /* Force longword alignment for packet payload. */
1667 m_adj(m_new, ETHER_ALIGN);
1668
1669 c->xl_mbuf = m_new;
1670 c->xl_ptr->xl_frag.xl_addr = vtophys(mtod(m_new, caddr_t));
1671 c->xl_ptr->xl_frag.xl_len = MCLBYTES | XL_LAST_FRAG;
1672 c->xl_ptr->xl_status = 0;
1673
1674 return(0);
1675}
1676
1677static int xl_rx_resync(sc)
1678 struct xl_softc *sc;
1679{
1680 struct xl_chain_onefrag *pos;
1681 int i;
1682
1683 pos = sc->xl_cdata.xl_rx_head;
1684
1685 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1686 if (pos->xl_ptr->xl_status)
1687 break;
1688 pos = pos->xl_next;
1689 }
1690
1691 if (i == XL_RX_LIST_CNT)
1692 return(0);
1693
1694 sc->xl_cdata.xl_rx_head = pos;
1695
1696 return(EAGAIN);
1697}
1698
1699/*
1700 * A frame has been uploaded: pass the resulting mbuf chain up to
1701 * the higher level protocols.
1702 */
1703static void xl_rxeof(sc)
1704 struct xl_softc *sc;
1705{
1706 struct ether_header *eh;
1707 struct mbuf *m;
1708 struct ifnet *ifp;
1709 struct xl_chain_onefrag *cur_rx;
1710 int total_len = 0;
1711 u_int16_t rxstat;
1712
1713 ifp = &sc->arpcom.ac_if;
1714
1715again:
1716
1717 while((rxstat = sc->xl_cdata.xl_rx_head->xl_ptr->xl_status)) {
1718 cur_rx = sc->xl_cdata.xl_rx_head;
1719 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1720
1721 /*
1722 * If an error occurs, update stats, clear the
1723 * status word and leave the mbuf cluster in place:
1724 * it should simply get re-used next time this descriptor
1725 * comes up in the ring.
1726 */
1727 if (rxstat & XL_RXSTAT_UP_ERROR) {
1728 ifp->if_ierrors++;
1729 cur_rx->xl_ptr->xl_status = 0;
1730 continue;
1731 }
1732
1733 /*
1734 * If there error bit was not set, the upload complete
1735 * bit should be set which means we have a valid packet.
1736 * If not, something truly strange has happened.
1737 */
1738 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1739 printf("xl%d: bad receive status -- "
1740 "packet dropped", sc->xl_unit);
1741 ifp->if_ierrors++;
1742 cur_rx->xl_ptr->xl_status = 0;
1743 continue;
1744 }
1745
1746 /* No errors; receive the packet. */
1747 m = cur_rx->xl_mbuf;
1748 total_len = cur_rx->xl_ptr->xl_status & XL_RXSTAT_LENMASK;
1749
1750 /*
1751 * Try to conjure up a new mbuf cluster. If that
1752 * fails, it means we have an out of memory condition and
1753 * should leave the buffer in place and continue. This will
1754 * result in a lost packet, but there's little else we
1755 * can do in this situation.
1756 */
1757 if (xl_newbuf(sc, cur_rx) == ENOBUFS) {
1758 ifp->if_ierrors++;
1759 cur_rx->xl_ptr->xl_status = 0;
1760 continue;
1761 }
1762
1763 ifp->if_ipackets++;
1764 eh = mtod(m, struct ether_header *);
1765 m->m_pkthdr.rcvif = ifp;
1766 m->m_pkthdr.len = m->m_len = total_len;
1767
1768 /* Remove header from mbuf and pass it on. */
1769 m_adj(m, sizeof(struct ether_header));
1770 ether_input(ifp, eh, m);
1771 }
1772
1773 /*
1774 * Handle the 'end of channel' condition. When the upload
1775 * engine hits the end of the RX ring, it will stall. This
1776 * is our cue to flush the RX ring, reload the uplist pointer
1777 * register and unstall the engine.
1778 * XXX This is actually a little goofy. With the ThunderLAN
1779 * chip, you get an interrupt when the receiver hits the end
1780 * of the receive ring, which tells you exactly when you
1781 * you need to reload the ring pointer. Here we have to
1782 * fake it. I'm mad at myself for not being clever enough
1783 * to avoid the use of a goto here.
1784 */
1785 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
1786 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
1787 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1788 xl_wait(sc);
1789 CSR_WRITE_4(sc, XL_UPLIST_PTR,
1790 vtophys(&sc->xl_ldata->xl_rx_list[0]));
1791 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
1792 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1793 goto again;
1794 }
1795
1796 return;
1797}
1798
1799/*
1800 * A frame was downloaded to the chip. It's safe for us to clean up
1801 * the list buffers.
1802 */
1803static void xl_txeof(sc)
1804 struct xl_softc *sc;
1805{
1806 struct xl_chain *cur_tx;
1807 struct ifnet *ifp;
1808
1809 ifp = &sc->arpcom.ac_if;
1810
1811 /* Clear the timeout timer. */
1812 ifp->if_timer = 0;
1813
1814 /*
1815 * Go through our tx list and free mbufs for those
1816 * frames that have been uploaded. Note: the 3c905B
1817 * sets a special bit in the status word to let us
1818 * know that a frame has been downloaded, but the
1819 * original 3c900/3c905 adapters don't do that.
1820 * Consequently, we have to use a different test if
1821 * xl_type != XL_TYPE_905B.
1822 */
1823 while(sc->xl_cdata.xl_tx_head != NULL) {
1824 cur_tx = sc->xl_cdata.xl_tx_head;
1825
1826 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
1827 break;
1828
1829 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
1830 m_freem(cur_tx->xl_mbuf);
1831 cur_tx->xl_mbuf = NULL;
1832 ifp->if_opackets++;
1833
1834 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
1835 sc->xl_cdata.xl_tx_free = cur_tx;
1836 }
1837
1838 if (sc->xl_cdata.xl_tx_head == NULL) {
1839 ifp->if_flags &= ~IFF_OACTIVE;
1840 sc->xl_cdata.xl_tx_tail = NULL;
1841 } else {
1842 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
1843 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
1844 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
1845 vtophys(sc->xl_cdata.xl_tx_head->xl_ptr));
1846 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
1847 }
1848 }
1849
1850 return;
1851}
1852
1853static void xl_txeof_90xB(sc)
1854 struct xl_softc *sc;
1855{
1856 struct xl_chain *cur_tx = NULL;
1857 struct ifnet *ifp;
1858 int idx;
1859
1860 ifp = &sc->arpcom.ac_if;
1861
1862 idx = sc->xl_cdata.xl_tx_cons;
1863 while(idx != sc->xl_cdata.xl_tx_prod) {
1864
1865 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
1866
1867 if (!(cur_tx->xl_ptr->xl_status & XL_TXSTAT_DL_COMPLETE))
1868 break;
1869
1870 if (cur_tx->xl_mbuf != NULL) {
1871 m_freem(cur_tx->xl_mbuf);
1872 cur_tx->xl_mbuf = NULL;
1873 }
1874
1875 ifp->if_opackets++;
1876
1877 sc->xl_cdata.xl_tx_cnt--;
1878 XL_INC(idx, XL_TX_LIST_CNT);
1879 ifp->if_timer = 0;
1880 }
1881
1882 sc->xl_cdata.xl_tx_cons = idx;
1883
1884 if (cur_tx != NULL)
1885 ifp->if_flags &= ~IFF_OACTIVE;
1886
1887 return;
1888}
1889
1890/*
1891 * TX 'end of channel' interrupt handler. Actually, we should
1892 * only get a 'TX complete' interrupt if there's a transmit error,
1893 * so this is really TX error handler.
1894 */
1895static void xl_txeoc(sc)
1896 struct xl_softc *sc;
1897{
1898 u_int8_t txstat;
1899
1900 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
1901 if (txstat & XL_TXSTATUS_UNDERRUN ||
1902 txstat & XL_TXSTATUS_JABBER ||
1903 txstat & XL_TXSTATUS_RECLAIM) {
1904 printf("xl%d: transmission error: %x\n",
1905 sc->xl_unit, txstat);
1906 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1907 xl_wait(sc);
1908 if (sc->xl_type == XL_TYPE_905B) {
1909 if (sc->xl_cdata.xl_tx_cnt) {
1910 int i;
1911 struct xl_chain *c;
1912 i = sc->xl_cdata.xl_tx_cons;
1913 c = &sc->xl_cdata.xl_tx_chain[i];
1914 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
1915 c->xl_phys);
1916 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
1917 }
1918 } else {
1919 if (sc->xl_cdata.xl_tx_head != NULL)
1920 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
1921 vtophys(sc->xl_cdata.xl_tx_head->xl_ptr));
1922 }
1923 /*
1924 * Remember to set this for the
1925 * first generation 3c90X chips.
1926 */
1927 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
1928 if (txstat & XL_TXSTATUS_UNDERRUN &&
1929 sc->xl_tx_thresh < XL_PACKET_SIZE) {
1930 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
1931 printf("xl%d: tx underrun, increasing tx start"
1932 " threshold to %d bytes\n", sc->xl_unit,
1933 sc->xl_tx_thresh);
1934 }
1935 CSR_WRITE_2(sc, XL_COMMAND,
1936 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
1937 if (sc->xl_type == XL_TYPE_905B) {
1938 CSR_WRITE_2(sc, XL_COMMAND,
1939 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
1940 }
1941 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
1942 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
1943 } else {
1944 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
1945 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
1946 }
1947 /*
1948 * Write an arbitrary byte to the TX_STATUS register
1949 * to clear this interrupt/error and advance to the next.
1950 */
1951 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
1952 }
1953
1954 return;
1955}
1956
1957static void xl_intr(arg)
1958 void *arg;
1959{
1960 struct xl_softc *sc;
1961 struct ifnet *ifp;
1962 u_int16_t status;
1963
1964 sc = arg;
1965 ifp = &sc->arpcom.ac_if;
1966
1967 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) {
1968
1969 CSR_WRITE_2(sc, XL_COMMAND,
1970 XL_CMD_INTR_ACK|(status & XL_INTRS));
1971
1972 if (status & XL_STAT_UP_COMPLETE) {
1973 int curpkts;
1974
1975 curpkts = ifp->if_ipackets;
1976 xl_rxeof(sc);
1977 if (curpkts == ifp->if_ipackets) {
1978 while (xl_rx_resync(sc))
1979 xl_rxeof(sc);
1980 }
1981 }
1982
1983 if (status & XL_STAT_DOWN_COMPLETE) {
1984 if (sc->xl_type == XL_TYPE_905B)
1985 xl_txeof_90xB(sc);
1986 else
1987 xl_txeof(sc);
1988 }
1989
1990 if (status & XL_STAT_TX_COMPLETE) {
1991 ifp->if_oerrors++;
1992 xl_txeoc(sc);
1993 }
1994
1995 if (status & XL_STAT_ADFAIL) {
1996 xl_reset(sc);
1997 xl_init(sc);
1998 }
1999
2000 if (status & XL_STAT_STATSOFLOW) {
2001 sc->xl_stats_no_timeout = 1;
2002 xl_stats_update(sc);
2003 sc->xl_stats_no_timeout = 0;
2004 }
2005 }
2006
2007 if (ifp->if_snd.ifq_head != NULL)
2008 (*ifp->if_start)(ifp);
2009
2010 return;
2011}
2012
2013static void xl_stats_update(xsc)
2014 void *xsc;
2015{
2016 struct xl_softc *sc;
2017 struct ifnet *ifp;
2018 struct xl_stats xl_stats;
2019 u_int8_t *p;
2020 int i;
2021 struct mii_data *mii = NULL;
2022
2023 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2024
2025 sc = xsc;
2026 ifp = &sc->arpcom.ac_if;
2027 if (sc->xl_miibus != NULL)
2028 mii = device_get_softc(sc->xl_miibus);
2029
2030 p = (u_int8_t *)&xl_stats;
2031
2032 /* Read all the stats registers. */
2033 XL_SEL_WIN(6);
2034
2035 for (i = 0; i < 16; i++)
2036 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2037
2038 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2039
2040 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2041 xl_stats.xl_tx_single_collision +
2042 xl_stats.xl_tx_late_collision;
2043
2044 /*
2045 * Boomerang and cyclone chips have an extra stats counter
2046 * in window 4 (BadSSD). We have to read this too in order
2047 * to clear out all the stats registers and avoid a statsoflow
2048 * interrupt.
2049 */
2050 XL_SEL_WIN(4);
2051 CSR_READ_1(sc, XL_W4_BADSSD);
2052
2053 if (mii != NULL)
2054 mii_tick(mii);
2055
2056 XL_SEL_WIN(7);
2057
2058 if (!sc->xl_stats_no_timeout)
2059 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2060
2061 return;
2062}
2063
2064/*
2065 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2066 * pointers to the fragment pointers.
2067 */
2068static int xl_encap(sc, c, m_head)
2069 struct xl_softc *sc;
2070 struct xl_chain *c;
2071 struct mbuf *m_head;
2072{
2073 int frag = 0;
2074 struct xl_frag *f = NULL;
2075 int total_len;
2076 struct mbuf *m;
2077
2078 /*
2079 * Start packing the mbufs in this chain into
2080 * the fragment pointers. Stop when we run out
2081 * of fragments or hit the end of the mbuf chain.
2082 */
2083 m = m_head;
2084 total_len = 0;
2085
2086 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
2087 if (m->m_len != 0) {
2088 if (frag == XL_MAXFRAGS)
2089 break;
2090 total_len+= m->m_len;
2091 c->xl_ptr->xl_frag[frag].xl_addr =
2092 vtophys(mtod(m, vm_offset_t));
2093 c->xl_ptr->xl_frag[frag].xl_len = m->m_len;
2094 frag++;
2095 }
2096 }
2097
2098 /*
2099 * Handle special case: we used up all 63 fragments,
2100 * but we have more mbufs left in the chain. Copy the
2101 * data into an mbuf cluster. Note that we don't
2102 * bother clearing the values in the other fragment
2103 * pointers/counters; it wouldn't gain us anything,
2104 * and would waste cycles.
2105 */
2106 if (m != NULL) {
2107 struct mbuf *m_new = NULL;
2108
2109 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
2110 if (m_new == NULL) {
2111 printf("xl%d: no memory for tx list", sc->xl_unit);
2112 return(1);
2113 }
2114 if (m_head->m_pkthdr.len > MHLEN) {
2115 MCLGET(m_new, M_DONTWAIT);
2116 if (!(m_new->m_flags & M_EXT)) {
2117 m_freem(m_new);
2118 printf("xl%d: no memory for tx list",
2119 sc->xl_unit);
2120 return(1);
2121 }
2122 }
2123 m_copydata(m_head, 0, m_head->m_pkthdr.len,
2124 mtod(m_new, caddr_t));
2125 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
2126 m_freem(m_head);
2127 m_head = m_new;
2128 f = &c->xl_ptr->xl_frag[0];
2129 f->xl_addr = vtophys(mtod(m_new, caddr_t));
2130 f->xl_len = total_len = m_new->m_len;
2131 frag = 1;
2132 }
2133
2134 c->xl_mbuf = m_head;
2135 c->xl_ptr->xl_frag[frag - 1].xl_len |= XL_LAST_FRAG;
2136 c->xl_ptr->xl_status = total_len;
2137 c->xl_ptr->xl_next = 0;
2138
2139 return(0);
2140}
2141
2142/*
2143 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2144 * to the mbuf data regions directly in the transmit lists. We also save a
2145 * copy of the pointers since the transmit list fragment pointers are
2146 * physical addresses.
2147 */
2148static void xl_start(ifp)
2149 struct ifnet *ifp;
2150{
2151 struct xl_softc *sc;
2152 struct mbuf *m_head = NULL;
2153 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2154
2155 sc = ifp->if_softc;
2156
2157 /*
2158 * Check for an available queue slot. If there are none,
2159 * punt.
2160 */
2161 if (sc->xl_cdata.xl_tx_free == NULL) {
2162 xl_txeoc(sc);
2163 xl_txeof(sc);
2164 if (sc->xl_cdata.xl_tx_free == NULL) {
2165 ifp->if_flags |= IFF_OACTIVE;
2166 return;
2167 }
2168 }
2169
2170 start_tx = sc->xl_cdata.xl_tx_free;
2171
2172 while(sc->xl_cdata.xl_tx_free != NULL) {
2173 IF_DEQUEUE(&ifp->if_snd, m_head);
2174 if (m_head == NULL)
2175 break;
2176
2177 /* Pick a descriptor off the free list. */
2178 cur_tx = sc->xl_cdata.xl_tx_free;
2179 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2180
2181 cur_tx->xl_next = NULL;
2182
2183 /* Pack the data into the descriptor. */
2184 xl_encap(sc, cur_tx, m_head);
2185
2186 /* Chain it together. */
2187 if (prev != NULL) {
2188 prev->xl_next = cur_tx;
2189 prev->xl_ptr->xl_next = vtophys(cur_tx->xl_ptr);
2190 }
2191 prev = cur_tx;
2192
2193 /*
2194 * If there's a BPF listener, bounce a copy of this frame
2195 * to him.
2196 */
2197 if (ifp->if_bpf)
2198 bpf_mtap(ifp, cur_tx->xl_mbuf);
2199 }
2200
2201 /*
2202 * If there are no packets queued, bail.
2203 */
2204 if (cur_tx == NULL)
2205 return;
2206
2207 /*
2208 * Place the request for the upload interrupt
2209 * in the last descriptor in the chain. This way, if
2210 * we're chaining several packets at once, we'll only
2211 * get an interupt once for the whole chain rather than
2212 * once for each packet.
2213 */
2214 cur_tx->xl_ptr->xl_status |= XL_TXSTAT_DL_INTR;
2215
2216 /*
2217 * Queue the packets. If the TX channel is clear, update
2218 * the downlist pointer register.
2219 */
2220 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2221 xl_wait(sc);
2222
2223 if (sc->xl_cdata.xl_tx_head != NULL) {
2224 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2225 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2226 vtophys(start_tx->xl_ptr);
2227 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
2228 ~XL_TXSTAT_DL_INTR;
2229 sc->xl_cdata.xl_tx_tail = cur_tx;
2230 } else {
2231 sc->xl_cdata.xl_tx_head = start_tx;
2232 sc->xl_cdata.xl_tx_tail = cur_tx;
2233 }
2234 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2235 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, vtophys(start_tx->xl_ptr));
2236
2237 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2238
2239 XL_SEL_WIN(7);
2240
2241 /*
2242 * Set a timeout in case the chip goes out to lunch.
2243 */
2244 ifp->if_timer = 5;
2245
2246 /*
2247 * XXX Under certain conditions, usually on slower machines
2248 * where interrupts may be dropped, it's possible for the
2249 * adapter to chew up all the buffers in the receive ring
2250 * and stall, without us being able to do anything about it.
2251 * To guard against this, we need to make a pass over the
2252 * RX queue to make sure there aren't any packets pending.
2253 * Doing it here means we can flush the receive ring at the
2254 * same time the chip is DMAing the transmit descriptors we
2255 * just gave it.
2256 *
2257 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2258 * nature of their chips in all their marketing literature;
2259 * we may as well take advantage of it. :)
2260 */
2261 xl_rxeof(sc);
2262
2263 return;
2264}
2265
2266static int xl_encap_90xB(sc, c, m_head)
2267 struct xl_softc *sc;
2268 struct xl_chain *c;
2269 struct mbuf *m_head;
2270{
2271 int frag = 0;
2272 struct xl_frag *f = NULL;
2273 struct mbuf *m;
2274 struct xl_list *d;
2275
2276 /*
2277 * Start packing the mbufs in this chain into
2278 * the fragment pointers. Stop when we run out
2279 * of fragments or hit the end of the mbuf chain.
2280 */
2281 d = c->xl_ptr;
2282 d->xl_status = 0;
2283 d->xl_next = 0;
2284
2285 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
2286 if (m->m_len != 0) {
2287 if (frag == XL_MAXFRAGS)
2288 break;
2289 f = &d->xl_frag[frag];
2290 f->xl_addr = vtophys(mtod(m, vm_offset_t));
2291 f->xl_len = m->m_len;
2292 frag++;
2293 }
2294 }
2295
2296 c->xl_mbuf = m_head;
2297 c->xl_ptr->xl_frag[frag - 1].xl_len |= XL_LAST_FRAG;
2298 c->xl_ptr->xl_status = XL_TXSTAT_RND_DEFEAT;
2299
2300 return(0);
2301}
2302
2303static void xl_start_90xB(ifp)
2304 struct ifnet *ifp;
2305{
2306 struct xl_softc *sc;
2307 struct mbuf *m_head = NULL;
2308 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2309 int idx;
2310
2311 sc = ifp->if_softc;
2312
2313 if (ifp->if_flags & IFF_OACTIVE)
2314 return;
2315
2316 idx = sc->xl_cdata.xl_tx_prod;
2317 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2318
2319 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2320
2321 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2322 ifp->if_flags |= IFF_OACTIVE;
2323 break;
2324 }
2325
2326 IF_DEQUEUE(&ifp->if_snd, m_head);
2327 if (m_head == NULL)
2328 break;
2329
2330 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2331
2332 /* Pack the data into the descriptor. */
2333 xl_encap_90xB(sc, cur_tx, m_head);
2334
2335 /* Chain it together. */
2336 if (prev != NULL)
2337 prev->xl_ptr->xl_next = cur_tx->xl_phys;
2338 prev = cur_tx;
2339
2340 /*
2341 * If there's a BPF listener, bounce a copy of this frame
2342 * to him.
2343 */
2344 if (ifp->if_bpf)
2345 bpf_mtap(ifp, cur_tx->xl_mbuf);
2346
2347 XL_INC(idx, XL_TX_LIST_CNT);
2348 sc->xl_cdata.xl_tx_cnt++;
2349 }
2350
2351 /*
2352 * If there are no packets queued, bail.
2353 */
2354 if (cur_tx == NULL)
2355 return;
2356
2357 /*
2358 * Place the request for the upload interrupt
2359 * in the last descriptor in the chain. This way, if
2360 * we're chaining several packets at once, we'll only
2361 * get an interupt once for the whole chain rather than
2362 * once for each packet.
2363 */
2364 cur_tx->xl_ptr->xl_status |= XL_TXSTAT_DL_INTR;
2365
2366 /* Start transmission */
2367 sc->xl_cdata.xl_tx_prod = idx;
2368 start_tx->xl_prev->xl_ptr->xl_next = start_tx->xl_phys;
2369
2370 /*
2371 * Set a timeout in case the chip goes out to lunch.
2372 */
2373 ifp->if_timer = 5;
2374
2375 return;
2376}
2377
2378static void xl_init(xsc)
2379 void *xsc;
2380{
2381 struct xl_softc *sc = xsc;
2382 struct ifnet *ifp = &sc->arpcom.ac_if;
2383 int s, i;
2384 u_int16_t rxfilt = 0;
2385 struct mii_data *mii = NULL;
2386
2387 s = splimp();
2388
2389 /*
2390 * Cancel pending I/O and free all RX/TX buffers.
2391 */
2392 xl_stop(sc);
2393
2394 if (sc->xl_miibus == NULL) {
2395 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2396 xl_wait(sc);
2397 }
2398 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2399 xl_wait(sc);
2400 DELAY(10000);
2401
2402 if (sc->xl_miibus != NULL)
2403 mii = device_get_softc(sc->xl_miibus);
2404
2405 /* Init our MAC address */
2406 XL_SEL_WIN(2);
2407 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2408 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2409 sc->arpcom.ac_enaddr[i]);
2410 }
2411
2412 /* Clear the station mask. */
2413 for (i = 0; i < 3; i++)
2414 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2415#ifdef notdef
2416 /* Reset TX and RX. */
2417 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2418 xl_wait(sc);
2419 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2420 xl_wait(sc);
2421#endif
2422 /* Init circular RX list. */
2423 if (xl_list_rx_init(sc) == ENOBUFS) {
2424 printf("xl%d: initialization failed: no "
2425 "memory for rx buffers\n", sc->xl_unit);
2426 xl_stop(sc);
2427 return;
2428 }
2429
2430 /* Init TX descriptors. */
2431 if (sc->xl_type == XL_TYPE_905B)
2432 xl_list_tx_init_90xB(sc);
2433 else
2434 xl_list_tx_init(sc);
2435
2436 /*
2437 * Set the TX freethresh value.
2438 * Note that this has no effect on 3c905B "cyclone"
2439 * cards but is required for 3c900/3c905 "boomerang"
2440 * cards in order to enable the download engine.
2441 */
2442 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2443
2444 /* Set the TX start threshold for best performance. */
2445 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2446 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2447
2448 /*
2449 * If this is a 3c905B, also set the tx reclaim threshold.
2450 * This helps cut down on the number of tx reclaim errors
2451 * that could happen on a busy network. The chip multiplies
2452 * the register value by 16 to obtain the actual threshold
2453 * in bytes, so we divide by 16 when setting the value here.
2454 * The existing threshold value can be examined by reading
2455 * the register at offset 9 in window 5.
2456 */
2457 if (sc->xl_type == XL_TYPE_905B) {
2458 CSR_WRITE_2(sc, XL_COMMAND,
2459 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2460 }
2461
2462 /* Set RX filter bits. */
2463 XL_SEL_WIN(5);
2464 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2465
2466 /* Set the individual bit to receive frames for this host only. */
2467 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2468
2469 /* If we want promiscuous mode, set the allframes bit. */
2470 if (ifp->if_flags & IFF_PROMISC) {
2471 rxfilt |= XL_RXFILTER_ALLFRAMES;
2472 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2473 } else {
2474 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2475 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2476 }
2477
2478 /*
2479 * Set capture broadcast bit to capture broadcast frames.
2480 */
2481 if (ifp->if_flags & IFF_BROADCAST) {
2482 rxfilt |= XL_RXFILTER_BROADCAST;
2483 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2484 } else {
2485 rxfilt &= ~XL_RXFILTER_BROADCAST;
2486 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2487 }
2488
2489 /*
2490 * Program the multicast filter, if necessary.
2491 */
2492 if (sc->xl_type == XL_TYPE_905B)
2493 xl_setmulti_hash(sc);
2494 else
2495 xl_setmulti(sc);
2496
2497 /*
2498 * Load the address of the RX list. We have to
2499 * stall the upload engine before we can manipulate
2500 * the uplist pointer register, then unstall it when
2501 * we're finished. We also have to wait for the
2502 * stall command to complete before proceeding.
2503 * Note that we have to do this after any RX resets
2504 * have completed since the uplist register is cleared
2505 * by a reset.
2506 */
2507 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2508 xl_wait(sc);
2509 CSR_WRITE_4(sc, XL_UPLIST_PTR, vtophys(&sc->xl_ldata->xl_rx_list[0]));
2510 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2511 xl_wait(sc);
2512
2513
2514 if (sc->xl_type == XL_TYPE_905B) {
2515 /* Set polling interval */
2516 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2517 /* Load the address of the TX list */
2518 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2519 xl_wait(sc);
2520 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2521 vtophys(&sc->xl_ldata->xl_tx_list[0]));
2522 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2523 xl_wait(sc);
2524 }
2525
2526 /*
2527 * If the coax transceiver is on, make sure to enable
2528 * the DC-DC converter.
2529 */
2530 XL_SEL_WIN(3);
2531 if (sc->xl_xcvr == XL_XCVR_COAX)
2532 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2533 else
2534 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2535
2536 /* Clear out the stats counters. */
2537 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2538 sc->xl_stats_no_timeout = 1;
2539 xl_stats_update(sc);
2540 sc->xl_stats_no_timeout = 0;
2541 XL_SEL_WIN(4);
2542 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2543 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2544
2545 /*
2546 * Enable interrupts.
2547 */
2548 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2549 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2550 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2551
2552 /* Set the RX early threshold */
2553 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2554 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2555
2556 /* Enable receiver and transmitter. */
2557 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2558 xl_wait(sc);
2559 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2560 xl_wait(sc);
2561
2562 if (mii != NULL)
2563 mii_mediachg(mii);
2564
2565 /* Select window 7 for normal operations. */
2566 XL_SEL_WIN(7);
2567
2568 ifp->if_flags |= IFF_RUNNING;
2569 ifp->if_flags &= ~IFF_OACTIVE;
2570
2571 (void)splx(s);
2572
2573 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2574
2575 return;
2576}
2577
2578/*
2579 * Set media options.
2580 */
2581static int xl_ifmedia_upd(ifp)
2582 struct ifnet *ifp;
2583{
2584 struct xl_softc *sc;
2585 struct ifmedia *ifm = NULL;
2586 struct mii_data *mii = NULL;
2587
2588 sc = ifp->if_softc;
2589 if (sc->xl_miibus != NULL)
2590 mii = device_get_softc(sc->xl_miibus);
2591 if (mii == NULL)
2592 ifm = &sc->ifmedia;
2593 else
2594 ifm = &mii->mii_media;
2595
2596 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2597 case IFM_100_FX:
2598 case IFM_10_FL:
2599 case IFM_10_2:
2600 case IFM_10_5:
2601 xl_setmode(sc, ifm->ifm_media);
2602 return(0);
2603 break;
2604 default:
2605 break;
2606 }
2607
2608 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
2609 || sc->xl_media & XL_MEDIAOPT_BT4) {
2610 xl_init(sc);
2611 } else {
2612 xl_setmode(sc, ifm->ifm_media);
2613 }
2614
2615 return(0);
2616}
2617
2618/*
2619 * Report current media status.
2620 */
2621static void xl_ifmedia_sts(ifp, ifmr)
2622 struct ifnet *ifp;
2623 struct ifmediareq *ifmr;
2624{
2625 struct xl_softc *sc;
2626 u_int32_t icfg;
2627 struct mii_data *mii = NULL;
2628
2629 sc = ifp->if_softc;
2630 if (sc->xl_miibus != NULL)
2631 mii = device_get_softc(sc->xl_miibus);
2632
2633 XL_SEL_WIN(3);
2634 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2635 icfg >>= XL_ICFG_CONNECTOR_BITS;
2636
2637 ifmr->ifm_active = IFM_ETHER;
2638
2639 switch(icfg) {
2640 case XL_XCVR_10BT:
2641 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2642 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2643 ifmr->ifm_active |= IFM_FDX;
2644 else
2645 ifmr->ifm_active |= IFM_HDX;
2646 break;
2647 case XL_XCVR_AUI:
2648 if (sc->xl_type == XL_TYPE_905B &&
2649 sc->xl_media == XL_MEDIAOPT_10FL) {
2650 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
2651 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2652 ifmr->ifm_active |= IFM_FDX;
2653 else
2654 ifmr->ifm_active |= IFM_HDX;
2655 } else
2656 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2657 break;
2658 case XL_XCVR_COAX:
2659 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
2660 break;
2661 /*
2662 * XXX MII and BTX/AUTO should be separate cases.
2663 */
2664
2665 case XL_XCVR_100BTX:
2666 case XL_XCVR_AUTO:
2667 case XL_XCVR_MII:
2668 if (mii != NULL) {
2669 mii_pollstat(mii);
2670 ifmr->ifm_active = mii->mii_media_active;
2671 ifmr->ifm_status = mii->mii_media_status;
2672 }
2673 break;
2674 case XL_XCVR_100BFX:
2675 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
2676 break;
2677 default:
2678 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, icfg);
2679 break;
2680 }
2681
2682 return;
2683}
2684
2685static int xl_ioctl(ifp, command, data)
2686 struct ifnet *ifp;
2687 u_long command;
2688 caddr_t data;
2689{
2690 struct xl_softc *sc = ifp->if_softc;
2691 struct ifreq *ifr = (struct ifreq *) data;
2692 int s, error = 0;
2693 struct mii_data *mii = NULL;
2694 u_int8_t rxfilt;
2695
2696 s = splimp();
2697
2698 switch(command) {
2699 case SIOCSIFADDR:
2700 case SIOCGIFADDR:
2701 case SIOCSIFMTU:
2702 error = ether_ioctl(ifp, command, data);
2703 break;
2704 case SIOCSIFFLAGS:
2705 XL_SEL_WIN(5);
2706 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2707 if (ifp->if_flags & IFF_UP) {
2708 if (ifp->if_flags & IFF_RUNNING &&
2709 ifp->if_flags & IFF_PROMISC &&
2710 !(sc->xl_if_flags & IFF_PROMISC)) {
2711 rxfilt |= XL_RXFILTER_ALLFRAMES;
2712 CSR_WRITE_2(sc, XL_COMMAND,
2713 XL_CMD_RX_SET_FILT|rxfilt);
2714 XL_SEL_WIN(7);
2715 } else if (ifp->if_flags & IFF_RUNNING &&
2716 !(ifp->if_flags & IFF_PROMISC) &&
2717 sc->xl_if_flags & IFF_PROMISC) {
2718 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2719 CSR_WRITE_2(sc, XL_COMMAND,
2720 XL_CMD_RX_SET_FILT|rxfilt);
2721 XL_SEL_WIN(7);
2722 } else
2723 xl_init(sc);
2724 } else {
2725 if (ifp->if_flags & IFF_RUNNING)
2726 xl_stop(sc);
2727 }
2728 sc->xl_if_flags = ifp->if_flags;
2729 error = 0;
2730 break;
2731 case SIOCADDMULTI:
2732 case SIOCDELMULTI:
2733 if (sc->xl_type == XL_TYPE_905B)
2734 xl_setmulti_hash(sc);
2735 else
2736 xl_setmulti(sc);
2737 error = 0;
2738 break;
2739 case SIOCGIFMEDIA:
2740 case SIOCSIFMEDIA:
2741 if (sc->xl_miibus != NULL)
2742 mii = device_get_softc(sc->xl_miibus);
2743 if (mii == NULL)
2744 error = ifmedia_ioctl(ifp, ifr,
2745 &sc->ifmedia, command);
2746 else
2747 error = ifmedia_ioctl(ifp, ifr,
2748 &mii->mii_media, command);
2749 break;
2750 default:
2751 error = EINVAL;
2752 break;
2753 }
2754
2755 (void)splx(s);
2756
2757 return(error);
2758}
2759
2760static void xl_watchdog(ifp)
2761 struct ifnet *ifp;
2762{
2763 struct xl_softc *sc;
2764 u_int16_t status = 0;
2765
2766 sc = ifp->if_softc;
2767
2768 ifp->if_oerrors++;
2769 XL_SEL_WIN(4);
2770 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2771 printf("xl%d: watchdog timeout\n", sc->xl_unit);
2772
2773 if (status & XL_MEDIASTAT_CARRIER)
2774 printf("xl%d: no carrier - transceiver cable problem?\n",
2775 sc->xl_unit);
2776 xl_txeoc(sc);
2777 xl_txeof(sc);
2778 xl_rxeof(sc);
2779 xl_reset(sc);
2780 xl_init(sc);
2781
2782 if (ifp->if_snd.ifq_head != NULL)
2783 (*ifp->if_start)(ifp);
2784
2785 return;
2786}
2787
2788/*
2789 * Stop the adapter and free any mbufs allocated to the
2790 * RX and TX lists.
2791 */
2792static void xl_stop(sc)
2793 struct xl_softc *sc;
2794{
2795 register int i;
2796 struct ifnet *ifp;
2797
2798 ifp = &sc->arpcom.ac_if;
2799 ifp->if_timer = 0;
2800
2801 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
2802 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2803 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
2804 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
2805 xl_wait(sc);
2806 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
2807 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2808 DELAY(800);
2809
2810#ifdef foo
2811 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2812 xl_wait(sc);
2813 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2814 xl_wait(sc);
2815#endif
2816
2817 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
2818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
2819 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2820
2821 /* Stop the stats updater. */
2822 untimeout(xl_stats_update, sc, sc->xl_stat_ch);
2823
2824 /*
2825 * Free data in the RX lists.
2826 */
2827 for (i = 0; i < XL_RX_LIST_CNT; i++) {
2828 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
2829 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
2830 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
2831 }
2832 }
2833 bzero((char *)&sc->xl_ldata->xl_rx_list,
2834 sizeof(sc->xl_ldata->xl_rx_list));
2835 /*
2836 * Free the TX list buffers.
2837 */
2838 for (i = 0; i < XL_TX_LIST_CNT; i++) {
2839 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
2840 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
2841 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
2842 }
2843 }
2844 bzero((char *)&sc->xl_ldata->xl_tx_list,
2845 sizeof(sc->xl_ldata->xl_tx_list));
2846
2847 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2848
2849 return;
2850}
2851
2852/*
2853 * Stop all chip I/O so that the kernel's probe routines don't
2854 * get confused by errant DMAs when rebooting.
2855 */
2856static void xl_shutdown(dev)
2857 device_t dev;
2858{
2859 struct xl_softc *sc;
2860
2861 sc = device_get_softc(dev);
2862
2863 xl_reset(sc);
2864 xl_stop(sc);
2865
2866 return;
2867}
| 1518
1519 /* Delete any miibus and phy devices attached to this interface */
1520 if (sc->xl_miibus != NULL) {
1521 bus_generic_detach(dev);
1522 device_delete_child(dev, sc->xl_miibus);
1523 }
1524
1525 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1526 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1527 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1528
1529 ifmedia_removeall(&sc->ifmedia);
1530 contigfree(sc->xl_ldata, sizeof(struct xl_list_data), M_DEVBUF);
1531
1532 splx(s);
1533
1534 return(0);
1535}
1536
1537/*
1538 * Initialize the transmit descriptors.
1539 */
1540static int xl_list_tx_init(sc)
1541 struct xl_softc *sc;
1542{
1543 struct xl_chain_data *cd;
1544 struct xl_list_data *ld;
1545 int i;
1546
1547 cd = &sc->xl_cdata;
1548 ld = sc->xl_ldata;
1549 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1550 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1551 if (i == (XL_TX_LIST_CNT - 1))
1552 cd->xl_tx_chain[i].xl_next = NULL;
1553 else
1554 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1555 }
1556
1557 cd->xl_tx_free = &cd->xl_tx_chain[0];
1558 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1559
1560 return(0);
1561}
1562
1563/*
1564 * Initialize the transmit descriptors.
1565 */
1566static int xl_list_tx_init_90xB(sc)
1567 struct xl_softc *sc;
1568{
1569 struct xl_chain_data *cd;
1570 struct xl_list_data *ld;
1571 int i;
1572
1573 cd = &sc->xl_cdata;
1574 ld = sc->xl_ldata;
1575 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1576 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1577 cd->xl_tx_chain[i].xl_phys = vtophys(&ld->xl_tx_list[i]);
1578 if (i == (XL_TX_LIST_CNT - 1))
1579 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1580 else
1581 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1582 if (i == 0)
1583 cd->xl_tx_chain[i].xl_prev =
1584 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1585 else
1586 cd->xl_tx_chain[i].xl_prev =
1587 &cd->xl_tx_chain[i - 1];
1588 }
1589
1590 bzero((char *)ld->xl_tx_list,
1591 sizeof(struct xl_list) * XL_TX_LIST_CNT);
1592 ld->xl_tx_list[0].xl_status = XL_TXSTAT_EMPTY;
1593
1594 cd->xl_tx_prod = 1;
1595 cd->xl_tx_cons = 1;
1596 cd->xl_tx_cnt = 0;
1597
1598 return(0);
1599}
1600
1601/*
1602 * Initialize the RX descriptors and allocate mbufs for them. Note that
1603 * we arrange the descriptors in a closed ring, so that the last descriptor
1604 * points back to the first.
1605 */
1606static int xl_list_rx_init(sc)
1607 struct xl_softc *sc;
1608{
1609 struct xl_chain_data *cd;
1610 struct xl_list_data *ld;
1611 int i;
1612
1613 cd = &sc->xl_cdata;
1614 ld = sc->xl_ldata;
1615
1616 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1617 cd->xl_rx_chain[i].xl_ptr =
1618 (struct xl_list_onefrag *)&ld->xl_rx_list[i];
1619 if (xl_newbuf(sc, &cd->xl_rx_chain[i]) == ENOBUFS)
1620 return(ENOBUFS);
1621 if (i == (XL_RX_LIST_CNT - 1)) {
1622 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[0];
1623 ld->xl_rx_list[i].xl_next =
1624 vtophys(&ld->xl_rx_list[0]);
1625 } else {
1626 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[i + 1];
1627 ld->xl_rx_list[i].xl_next =
1628 vtophys(&ld->xl_rx_list[i + 1]);
1629 }
1630 }
1631
1632 cd->xl_rx_head = &cd->xl_rx_chain[0];
1633
1634 return(0);
1635}
1636
1637/*
1638 * Initialize an RX descriptor and attach an MBUF cluster.
1639 */
1640static int xl_newbuf(sc, c)
1641 struct xl_softc *sc;
1642 struct xl_chain_onefrag *c;
1643{
1644 struct mbuf *m_new = NULL;
1645
1646 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1647 if (m_new == NULL) {
1648 printf("xl%d: no memory for rx list -- "
1649 "packet dropped!\n", sc->xl_unit);
1650 return(ENOBUFS);
1651 }
1652
1653 MCLGET(m_new, M_DONTWAIT);
1654 if (!(m_new->m_flags & M_EXT)) {
1655 printf("xl%d: no memory for rx list -- "
1656 "packet dropped!\n", sc->xl_unit);
1657 m_freem(m_new);
1658 return(ENOBUFS);
1659 }
1660
1661 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1662
1663 /* Force longword alignment for packet payload. */
1664 m_adj(m_new, ETHER_ALIGN);
1665
1666 c->xl_mbuf = m_new;
1667 c->xl_ptr->xl_frag.xl_addr = vtophys(mtod(m_new, caddr_t));
1668 c->xl_ptr->xl_frag.xl_len = MCLBYTES | XL_LAST_FRAG;
1669 c->xl_ptr->xl_status = 0;
1670
1671 return(0);
1672}
1673
1674static int xl_rx_resync(sc)
1675 struct xl_softc *sc;
1676{
1677 struct xl_chain_onefrag *pos;
1678 int i;
1679
1680 pos = sc->xl_cdata.xl_rx_head;
1681
1682 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1683 if (pos->xl_ptr->xl_status)
1684 break;
1685 pos = pos->xl_next;
1686 }
1687
1688 if (i == XL_RX_LIST_CNT)
1689 return(0);
1690
1691 sc->xl_cdata.xl_rx_head = pos;
1692
1693 return(EAGAIN);
1694}
1695
1696/*
1697 * A frame has been uploaded: pass the resulting mbuf chain up to
1698 * the higher level protocols.
1699 */
1700static void xl_rxeof(sc)
1701 struct xl_softc *sc;
1702{
1703 struct ether_header *eh;
1704 struct mbuf *m;
1705 struct ifnet *ifp;
1706 struct xl_chain_onefrag *cur_rx;
1707 int total_len = 0;
1708 u_int16_t rxstat;
1709
1710 ifp = &sc->arpcom.ac_if;
1711
1712again:
1713
1714 while((rxstat = sc->xl_cdata.xl_rx_head->xl_ptr->xl_status)) {
1715 cur_rx = sc->xl_cdata.xl_rx_head;
1716 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1717
1718 /*
1719 * If an error occurs, update stats, clear the
1720 * status word and leave the mbuf cluster in place:
1721 * it should simply get re-used next time this descriptor
1722 * comes up in the ring.
1723 */
1724 if (rxstat & XL_RXSTAT_UP_ERROR) {
1725 ifp->if_ierrors++;
1726 cur_rx->xl_ptr->xl_status = 0;
1727 continue;
1728 }
1729
1730 /*
1731 * If there error bit was not set, the upload complete
1732 * bit should be set which means we have a valid packet.
1733 * If not, something truly strange has happened.
1734 */
1735 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1736 printf("xl%d: bad receive status -- "
1737 "packet dropped", sc->xl_unit);
1738 ifp->if_ierrors++;
1739 cur_rx->xl_ptr->xl_status = 0;
1740 continue;
1741 }
1742
1743 /* No errors; receive the packet. */
1744 m = cur_rx->xl_mbuf;
1745 total_len = cur_rx->xl_ptr->xl_status & XL_RXSTAT_LENMASK;
1746
1747 /*
1748 * Try to conjure up a new mbuf cluster. If that
1749 * fails, it means we have an out of memory condition and
1750 * should leave the buffer in place and continue. This will
1751 * result in a lost packet, but there's little else we
1752 * can do in this situation.
1753 */
1754 if (xl_newbuf(sc, cur_rx) == ENOBUFS) {
1755 ifp->if_ierrors++;
1756 cur_rx->xl_ptr->xl_status = 0;
1757 continue;
1758 }
1759
1760 ifp->if_ipackets++;
1761 eh = mtod(m, struct ether_header *);
1762 m->m_pkthdr.rcvif = ifp;
1763 m->m_pkthdr.len = m->m_len = total_len;
1764
1765 /* Remove header from mbuf and pass it on. */
1766 m_adj(m, sizeof(struct ether_header));
1767 ether_input(ifp, eh, m);
1768 }
1769
1770 /*
1771 * Handle the 'end of channel' condition. When the upload
1772 * engine hits the end of the RX ring, it will stall. This
1773 * is our cue to flush the RX ring, reload the uplist pointer
1774 * register and unstall the engine.
1775 * XXX This is actually a little goofy. With the ThunderLAN
1776 * chip, you get an interrupt when the receiver hits the end
1777 * of the receive ring, which tells you exactly when you
1778 * you need to reload the ring pointer. Here we have to
1779 * fake it. I'm mad at myself for not being clever enough
1780 * to avoid the use of a goto here.
1781 */
1782 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
1783 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
1784 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1785 xl_wait(sc);
1786 CSR_WRITE_4(sc, XL_UPLIST_PTR,
1787 vtophys(&sc->xl_ldata->xl_rx_list[0]));
1788 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
1789 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1790 goto again;
1791 }
1792
1793 return;
1794}
1795
1796/*
1797 * A frame was downloaded to the chip. It's safe for us to clean up
1798 * the list buffers.
1799 */
1800static void xl_txeof(sc)
1801 struct xl_softc *sc;
1802{
1803 struct xl_chain *cur_tx;
1804 struct ifnet *ifp;
1805
1806 ifp = &sc->arpcom.ac_if;
1807
1808 /* Clear the timeout timer. */
1809 ifp->if_timer = 0;
1810
1811 /*
1812 * Go through our tx list and free mbufs for those
1813 * frames that have been uploaded. Note: the 3c905B
1814 * sets a special bit in the status word to let us
1815 * know that a frame has been downloaded, but the
1816 * original 3c900/3c905 adapters don't do that.
1817 * Consequently, we have to use a different test if
1818 * xl_type != XL_TYPE_905B.
1819 */
1820 while(sc->xl_cdata.xl_tx_head != NULL) {
1821 cur_tx = sc->xl_cdata.xl_tx_head;
1822
1823 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
1824 break;
1825
1826 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
1827 m_freem(cur_tx->xl_mbuf);
1828 cur_tx->xl_mbuf = NULL;
1829 ifp->if_opackets++;
1830
1831 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
1832 sc->xl_cdata.xl_tx_free = cur_tx;
1833 }
1834
1835 if (sc->xl_cdata.xl_tx_head == NULL) {
1836 ifp->if_flags &= ~IFF_OACTIVE;
1837 sc->xl_cdata.xl_tx_tail = NULL;
1838 } else {
1839 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
1840 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
1841 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
1842 vtophys(sc->xl_cdata.xl_tx_head->xl_ptr));
1843 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
1844 }
1845 }
1846
1847 return;
1848}
1849
1850static void xl_txeof_90xB(sc)
1851 struct xl_softc *sc;
1852{
1853 struct xl_chain *cur_tx = NULL;
1854 struct ifnet *ifp;
1855 int idx;
1856
1857 ifp = &sc->arpcom.ac_if;
1858
1859 idx = sc->xl_cdata.xl_tx_cons;
1860 while(idx != sc->xl_cdata.xl_tx_prod) {
1861
1862 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
1863
1864 if (!(cur_tx->xl_ptr->xl_status & XL_TXSTAT_DL_COMPLETE))
1865 break;
1866
1867 if (cur_tx->xl_mbuf != NULL) {
1868 m_freem(cur_tx->xl_mbuf);
1869 cur_tx->xl_mbuf = NULL;
1870 }
1871
1872 ifp->if_opackets++;
1873
1874 sc->xl_cdata.xl_tx_cnt--;
1875 XL_INC(idx, XL_TX_LIST_CNT);
1876 ifp->if_timer = 0;
1877 }
1878
1879 sc->xl_cdata.xl_tx_cons = idx;
1880
1881 if (cur_tx != NULL)
1882 ifp->if_flags &= ~IFF_OACTIVE;
1883
1884 return;
1885}
1886
1887/*
1888 * TX 'end of channel' interrupt handler. Actually, we should
1889 * only get a 'TX complete' interrupt if there's a transmit error,
1890 * so this is really TX error handler.
1891 */
1892static void xl_txeoc(sc)
1893 struct xl_softc *sc;
1894{
1895 u_int8_t txstat;
1896
1897 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
1898 if (txstat & XL_TXSTATUS_UNDERRUN ||
1899 txstat & XL_TXSTATUS_JABBER ||
1900 txstat & XL_TXSTATUS_RECLAIM) {
1901 printf("xl%d: transmission error: %x\n",
1902 sc->xl_unit, txstat);
1903 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1904 xl_wait(sc);
1905 if (sc->xl_type == XL_TYPE_905B) {
1906 if (sc->xl_cdata.xl_tx_cnt) {
1907 int i;
1908 struct xl_chain *c;
1909 i = sc->xl_cdata.xl_tx_cons;
1910 c = &sc->xl_cdata.xl_tx_chain[i];
1911 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
1912 c->xl_phys);
1913 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
1914 }
1915 } else {
1916 if (sc->xl_cdata.xl_tx_head != NULL)
1917 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
1918 vtophys(sc->xl_cdata.xl_tx_head->xl_ptr));
1919 }
1920 /*
1921 * Remember to set this for the
1922 * first generation 3c90X chips.
1923 */
1924 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
1925 if (txstat & XL_TXSTATUS_UNDERRUN &&
1926 sc->xl_tx_thresh < XL_PACKET_SIZE) {
1927 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
1928 printf("xl%d: tx underrun, increasing tx start"
1929 " threshold to %d bytes\n", sc->xl_unit,
1930 sc->xl_tx_thresh);
1931 }
1932 CSR_WRITE_2(sc, XL_COMMAND,
1933 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
1934 if (sc->xl_type == XL_TYPE_905B) {
1935 CSR_WRITE_2(sc, XL_COMMAND,
1936 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
1937 }
1938 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
1939 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
1940 } else {
1941 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
1942 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
1943 }
1944 /*
1945 * Write an arbitrary byte to the TX_STATUS register
1946 * to clear this interrupt/error and advance to the next.
1947 */
1948 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
1949 }
1950
1951 return;
1952}
1953
1954static void xl_intr(arg)
1955 void *arg;
1956{
1957 struct xl_softc *sc;
1958 struct ifnet *ifp;
1959 u_int16_t status;
1960
1961 sc = arg;
1962 ifp = &sc->arpcom.ac_if;
1963
1964 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) {
1965
1966 CSR_WRITE_2(sc, XL_COMMAND,
1967 XL_CMD_INTR_ACK|(status & XL_INTRS));
1968
1969 if (status & XL_STAT_UP_COMPLETE) {
1970 int curpkts;
1971
1972 curpkts = ifp->if_ipackets;
1973 xl_rxeof(sc);
1974 if (curpkts == ifp->if_ipackets) {
1975 while (xl_rx_resync(sc))
1976 xl_rxeof(sc);
1977 }
1978 }
1979
1980 if (status & XL_STAT_DOWN_COMPLETE) {
1981 if (sc->xl_type == XL_TYPE_905B)
1982 xl_txeof_90xB(sc);
1983 else
1984 xl_txeof(sc);
1985 }
1986
1987 if (status & XL_STAT_TX_COMPLETE) {
1988 ifp->if_oerrors++;
1989 xl_txeoc(sc);
1990 }
1991
1992 if (status & XL_STAT_ADFAIL) {
1993 xl_reset(sc);
1994 xl_init(sc);
1995 }
1996
1997 if (status & XL_STAT_STATSOFLOW) {
1998 sc->xl_stats_no_timeout = 1;
1999 xl_stats_update(sc);
2000 sc->xl_stats_no_timeout = 0;
2001 }
2002 }
2003
2004 if (ifp->if_snd.ifq_head != NULL)
2005 (*ifp->if_start)(ifp);
2006
2007 return;
2008}
2009
2010static void xl_stats_update(xsc)
2011 void *xsc;
2012{
2013 struct xl_softc *sc;
2014 struct ifnet *ifp;
2015 struct xl_stats xl_stats;
2016 u_int8_t *p;
2017 int i;
2018 struct mii_data *mii = NULL;
2019
2020 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2021
2022 sc = xsc;
2023 ifp = &sc->arpcom.ac_if;
2024 if (sc->xl_miibus != NULL)
2025 mii = device_get_softc(sc->xl_miibus);
2026
2027 p = (u_int8_t *)&xl_stats;
2028
2029 /* Read all the stats registers. */
2030 XL_SEL_WIN(6);
2031
2032 for (i = 0; i < 16; i++)
2033 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2034
2035 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2036
2037 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2038 xl_stats.xl_tx_single_collision +
2039 xl_stats.xl_tx_late_collision;
2040
2041 /*
2042 * Boomerang and cyclone chips have an extra stats counter
2043 * in window 4 (BadSSD). We have to read this too in order
2044 * to clear out all the stats registers and avoid a statsoflow
2045 * interrupt.
2046 */
2047 XL_SEL_WIN(4);
2048 CSR_READ_1(sc, XL_W4_BADSSD);
2049
2050 if (mii != NULL)
2051 mii_tick(mii);
2052
2053 XL_SEL_WIN(7);
2054
2055 if (!sc->xl_stats_no_timeout)
2056 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2057
2058 return;
2059}
2060
2061/*
2062 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2063 * pointers to the fragment pointers.
2064 */
2065static int xl_encap(sc, c, m_head)
2066 struct xl_softc *sc;
2067 struct xl_chain *c;
2068 struct mbuf *m_head;
2069{
2070 int frag = 0;
2071 struct xl_frag *f = NULL;
2072 int total_len;
2073 struct mbuf *m;
2074
2075 /*
2076 * Start packing the mbufs in this chain into
2077 * the fragment pointers. Stop when we run out
2078 * of fragments or hit the end of the mbuf chain.
2079 */
2080 m = m_head;
2081 total_len = 0;
2082
2083 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
2084 if (m->m_len != 0) {
2085 if (frag == XL_MAXFRAGS)
2086 break;
2087 total_len+= m->m_len;
2088 c->xl_ptr->xl_frag[frag].xl_addr =
2089 vtophys(mtod(m, vm_offset_t));
2090 c->xl_ptr->xl_frag[frag].xl_len = m->m_len;
2091 frag++;
2092 }
2093 }
2094
2095 /*
2096 * Handle special case: we used up all 63 fragments,
2097 * but we have more mbufs left in the chain. Copy the
2098 * data into an mbuf cluster. Note that we don't
2099 * bother clearing the values in the other fragment
2100 * pointers/counters; it wouldn't gain us anything,
2101 * and would waste cycles.
2102 */
2103 if (m != NULL) {
2104 struct mbuf *m_new = NULL;
2105
2106 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
2107 if (m_new == NULL) {
2108 printf("xl%d: no memory for tx list", sc->xl_unit);
2109 return(1);
2110 }
2111 if (m_head->m_pkthdr.len > MHLEN) {
2112 MCLGET(m_new, M_DONTWAIT);
2113 if (!(m_new->m_flags & M_EXT)) {
2114 m_freem(m_new);
2115 printf("xl%d: no memory for tx list",
2116 sc->xl_unit);
2117 return(1);
2118 }
2119 }
2120 m_copydata(m_head, 0, m_head->m_pkthdr.len,
2121 mtod(m_new, caddr_t));
2122 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
2123 m_freem(m_head);
2124 m_head = m_new;
2125 f = &c->xl_ptr->xl_frag[0];
2126 f->xl_addr = vtophys(mtod(m_new, caddr_t));
2127 f->xl_len = total_len = m_new->m_len;
2128 frag = 1;
2129 }
2130
2131 c->xl_mbuf = m_head;
2132 c->xl_ptr->xl_frag[frag - 1].xl_len |= XL_LAST_FRAG;
2133 c->xl_ptr->xl_status = total_len;
2134 c->xl_ptr->xl_next = 0;
2135
2136 return(0);
2137}
2138
2139/*
2140 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2141 * to the mbuf data regions directly in the transmit lists. We also save a
2142 * copy of the pointers since the transmit list fragment pointers are
2143 * physical addresses.
2144 */
2145static void xl_start(ifp)
2146 struct ifnet *ifp;
2147{
2148 struct xl_softc *sc;
2149 struct mbuf *m_head = NULL;
2150 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2151
2152 sc = ifp->if_softc;
2153
2154 /*
2155 * Check for an available queue slot. If there are none,
2156 * punt.
2157 */
2158 if (sc->xl_cdata.xl_tx_free == NULL) {
2159 xl_txeoc(sc);
2160 xl_txeof(sc);
2161 if (sc->xl_cdata.xl_tx_free == NULL) {
2162 ifp->if_flags |= IFF_OACTIVE;
2163 return;
2164 }
2165 }
2166
2167 start_tx = sc->xl_cdata.xl_tx_free;
2168
2169 while(sc->xl_cdata.xl_tx_free != NULL) {
2170 IF_DEQUEUE(&ifp->if_snd, m_head);
2171 if (m_head == NULL)
2172 break;
2173
2174 /* Pick a descriptor off the free list. */
2175 cur_tx = sc->xl_cdata.xl_tx_free;
2176 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2177
2178 cur_tx->xl_next = NULL;
2179
2180 /* Pack the data into the descriptor. */
2181 xl_encap(sc, cur_tx, m_head);
2182
2183 /* Chain it together. */
2184 if (prev != NULL) {
2185 prev->xl_next = cur_tx;
2186 prev->xl_ptr->xl_next = vtophys(cur_tx->xl_ptr);
2187 }
2188 prev = cur_tx;
2189
2190 /*
2191 * If there's a BPF listener, bounce a copy of this frame
2192 * to him.
2193 */
2194 if (ifp->if_bpf)
2195 bpf_mtap(ifp, cur_tx->xl_mbuf);
2196 }
2197
2198 /*
2199 * If there are no packets queued, bail.
2200 */
2201 if (cur_tx == NULL)
2202 return;
2203
2204 /*
2205 * Place the request for the upload interrupt
2206 * in the last descriptor in the chain. This way, if
2207 * we're chaining several packets at once, we'll only
2208 * get an interupt once for the whole chain rather than
2209 * once for each packet.
2210 */
2211 cur_tx->xl_ptr->xl_status |= XL_TXSTAT_DL_INTR;
2212
2213 /*
2214 * Queue the packets. If the TX channel is clear, update
2215 * the downlist pointer register.
2216 */
2217 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2218 xl_wait(sc);
2219
2220 if (sc->xl_cdata.xl_tx_head != NULL) {
2221 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2222 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2223 vtophys(start_tx->xl_ptr);
2224 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
2225 ~XL_TXSTAT_DL_INTR;
2226 sc->xl_cdata.xl_tx_tail = cur_tx;
2227 } else {
2228 sc->xl_cdata.xl_tx_head = start_tx;
2229 sc->xl_cdata.xl_tx_tail = cur_tx;
2230 }
2231 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2232 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, vtophys(start_tx->xl_ptr));
2233
2234 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2235
2236 XL_SEL_WIN(7);
2237
2238 /*
2239 * Set a timeout in case the chip goes out to lunch.
2240 */
2241 ifp->if_timer = 5;
2242
2243 /*
2244 * XXX Under certain conditions, usually on slower machines
2245 * where interrupts may be dropped, it's possible for the
2246 * adapter to chew up all the buffers in the receive ring
2247 * and stall, without us being able to do anything about it.
2248 * To guard against this, we need to make a pass over the
2249 * RX queue to make sure there aren't any packets pending.
2250 * Doing it here means we can flush the receive ring at the
2251 * same time the chip is DMAing the transmit descriptors we
2252 * just gave it.
2253 *
2254 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2255 * nature of their chips in all their marketing literature;
2256 * we may as well take advantage of it. :)
2257 */
2258 xl_rxeof(sc);
2259
2260 return;
2261}
2262
2263static int xl_encap_90xB(sc, c, m_head)
2264 struct xl_softc *sc;
2265 struct xl_chain *c;
2266 struct mbuf *m_head;
2267{
2268 int frag = 0;
2269 struct xl_frag *f = NULL;
2270 struct mbuf *m;
2271 struct xl_list *d;
2272
2273 /*
2274 * Start packing the mbufs in this chain into
2275 * the fragment pointers. Stop when we run out
2276 * of fragments or hit the end of the mbuf chain.
2277 */
2278 d = c->xl_ptr;
2279 d->xl_status = 0;
2280 d->xl_next = 0;
2281
2282 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
2283 if (m->m_len != 0) {
2284 if (frag == XL_MAXFRAGS)
2285 break;
2286 f = &d->xl_frag[frag];
2287 f->xl_addr = vtophys(mtod(m, vm_offset_t));
2288 f->xl_len = m->m_len;
2289 frag++;
2290 }
2291 }
2292
2293 c->xl_mbuf = m_head;
2294 c->xl_ptr->xl_frag[frag - 1].xl_len |= XL_LAST_FRAG;
2295 c->xl_ptr->xl_status = XL_TXSTAT_RND_DEFEAT;
2296
2297 return(0);
2298}
2299
2300static void xl_start_90xB(ifp)
2301 struct ifnet *ifp;
2302{
2303 struct xl_softc *sc;
2304 struct mbuf *m_head = NULL;
2305 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2306 int idx;
2307
2308 sc = ifp->if_softc;
2309
2310 if (ifp->if_flags & IFF_OACTIVE)
2311 return;
2312
2313 idx = sc->xl_cdata.xl_tx_prod;
2314 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2315
2316 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2317
2318 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2319 ifp->if_flags |= IFF_OACTIVE;
2320 break;
2321 }
2322
2323 IF_DEQUEUE(&ifp->if_snd, m_head);
2324 if (m_head == NULL)
2325 break;
2326
2327 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2328
2329 /* Pack the data into the descriptor. */
2330 xl_encap_90xB(sc, cur_tx, m_head);
2331
2332 /* Chain it together. */
2333 if (prev != NULL)
2334 prev->xl_ptr->xl_next = cur_tx->xl_phys;
2335 prev = cur_tx;
2336
2337 /*
2338 * If there's a BPF listener, bounce a copy of this frame
2339 * to him.
2340 */
2341 if (ifp->if_bpf)
2342 bpf_mtap(ifp, cur_tx->xl_mbuf);
2343
2344 XL_INC(idx, XL_TX_LIST_CNT);
2345 sc->xl_cdata.xl_tx_cnt++;
2346 }
2347
2348 /*
2349 * If there are no packets queued, bail.
2350 */
2351 if (cur_tx == NULL)
2352 return;
2353
2354 /*
2355 * Place the request for the upload interrupt
2356 * in the last descriptor in the chain. This way, if
2357 * we're chaining several packets at once, we'll only
2358 * get an interupt once for the whole chain rather than
2359 * once for each packet.
2360 */
2361 cur_tx->xl_ptr->xl_status |= XL_TXSTAT_DL_INTR;
2362
2363 /* Start transmission */
2364 sc->xl_cdata.xl_tx_prod = idx;
2365 start_tx->xl_prev->xl_ptr->xl_next = start_tx->xl_phys;
2366
2367 /*
2368 * Set a timeout in case the chip goes out to lunch.
2369 */
2370 ifp->if_timer = 5;
2371
2372 return;
2373}
2374
2375static void xl_init(xsc)
2376 void *xsc;
2377{
2378 struct xl_softc *sc = xsc;
2379 struct ifnet *ifp = &sc->arpcom.ac_if;
2380 int s, i;
2381 u_int16_t rxfilt = 0;
2382 struct mii_data *mii = NULL;
2383
2384 s = splimp();
2385
2386 /*
2387 * Cancel pending I/O and free all RX/TX buffers.
2388 */
2389 xl_stop(sc);
2390
2391 if (sc->xl_miibus == NULL) {
2392 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2393 xl_wait(sc);
2394 }
2395 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2396 xl_wait(sc);
2397 DELAY(10000);
2398
2399 if (sc->xl_miibus != NULL)
2400 mii = device_get_softc(sc->xl_miibus);
2401
2402 /* Init our MAC address */
2403 XL_SEL_WIN(2);
2404 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2405 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2406 sc->arpcom.ac_enaddr[i]);
2407 }
2408
2409 /* Clear the station mask. */
2410 for (i = 0; i < 3; i++)
2411 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2412#ifdef notdef
2413 /* Reset TX and RX. */
2414 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2415 xl_wait(sc);
2416 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2417 xl_wait(sc);
2418#endif
2419 /* Init circular RX list. */
2420 if (xl_list_rx_init(sc) == ENOBUFS) {
2421 printf("xl%d: initialization failed: no "
2422 "memory for rx buffers\n", sc->xl_unit);
2423 xl_stop(sc);
2424 return;
2425 }
2426
2427 /* Init TX descriptors. */
2428 if (sc->xl_type == XL_TYPE_905B)
2429 xl_list_tx_init_90xB(sc);
2430 else
2431 xl_list_tx_init(sc);
2432
2433 /*
2434 * Set the TX freethresh value.
2435 * Note that this has no effect on 3c905B "cyclone"
2436 * cards but is required for 3c900/3c905 "boomerang"
2437 * cards in order to enable the download engine.
2438 */
2439 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2440
2441 /* Set the TX start threshold for best performance. */
2442 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2443 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2444
2445 /*
2446 * If this is a 3c905B, also set the tx reclaim threshold.
2447 * This helps cut down on the number of tx reclaim errors
2448 * that could happen on a busy network. The chip multiplies
2449 * the register value by 16 to obtain the actual threshold
2450 * in bytes, so we divide by 16 when setting the value here.
2451 * The existing threshold value can be examined by reading
2452 * the register at offset 9 in window 5.
2453 */
2454 if (sc->xl_type == XL_TYPE_905B) {
2455 CSR_WRITE_2(sc, XL_COMMAND,
2456 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2457 }
2458
2459 /* Set RX filter bits. */
2460 XL_SEL_WIN(5);
2461 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2462
2463 /* Set the individual bit to receive frames for this host only. */
2464 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2465
2466 /* If we want promiscuous mode, set the allframes bit. */
2467 if (ifp->if_flags & IFF_PROMISC) {
2468 rxfilt |= XL_RXFILTER_ALLFRAMES;
2469 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2470 } else {
2471 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2472 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2473 }
2474
2475 /*
2476 * Set capture broadcast bit to capture broadcast frames.
2477 */
2478 if (ifp->if_flags & IFF_BROADCAST) {
2479 rxfilt |= XL_RXFILTER_BROADCAST;
2480 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2481 } else {
2482 rxfilt &= ~XL_RXFILTER_BROADCAST;
2483 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2484 }
2485
2486 /*
2487 * Program the multicast filter, if necessary.
2488 */
2489 if (sc->xl_type == XL_TYPE_905B)
2490 xl_setmulti_hash(sc);
2491 else
2492 xl_setmulti(sc);
2493
2494 /*
2495 * Load the address of the RX list. We have to
2496 * stall the upload engine before we can manipulate
2497 * the uplist pointer register, then unstall it when
2498 * we're finished. We also have to wait for the
2499 * stall command to complete before proceeding.
2500 * Note that we have to do this after any RX resets
2501 * have completed since the uplist register is cleared
2502 * by a reset.
2503 */
2504 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2505 xl_wait(sc);
2506 CSR_WRITE_4(sc, XL_UPLIST_PTR, vtophys(&sc->xl_ldata->xl_rx_list[0]));
2507 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2508 xl_wait(sc);
2509
2510
2511 if (sc->xl_type == XL_TYPE_905B) {
2512 /* Set polling interval */
2513 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2514 /* Load the address of the TX list */
2515 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2516 xl_wait(sc);
2517 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2518 vtophys(&sc->xl_ldata->xl_tx_list[0]));
2519 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2520 xl_wait(sc);
2521 }
2522
2523 /*
2524 * If the coax transceiver is on, make sure to enable
2525 * the DC-DC converter.
2526 */
2527 XL_SEL_WIN(3);
2528 if (sc->xl_xcvr == XL_XCVR_COAX)
2529 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2530 else
2531 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2532
2533 /* Clear out the stats counters. */
2534 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2535 sc->xl_stats_no_timeout = 1;
2536 xl_stats_update(sc);
2537 sc->xl_stats_no_timeout = 0;
2538 XL_SEL_WIN(4);
2539 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2540 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2541
2542 /*
2543 * Enable interrupts.
2544 */
2545 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2546 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2547 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2548
2549 /* Set the RX early threshold */
2550 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2551 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2552
2553 /* Enable receiver and transmitter. */
2554 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2555 xl_wait(sc);
2556 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2557 xl_wait(sc);
2558
2559 if (mii != NULL)
2560 mii_mediachg(mii);
2561
2562 /* Select window 7 for normal operations. */
2563 XL_SEL_WIN(7);
2564
2565 ifp->if_flags |= IFF_RUNNING;
2566 ifp->if_flags &= ~IFF_OACTIVE;
2567
2568 (void)splx(s);
2569
2570 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2571
2572 return;
2573}
2574
2575/*
2576 * Set media options.
2577 */
2578static int xl_ifmedia_upd(ifp)
2579 struct ifnet *ifp;
2580{
2581 struct xl_softc *sc;
2582 struct ifmedia *ifm = NULL;
2583 struct mii_data *mii = NULL;
2584
2585 sc = ifp->if_softc;
2586 if (sc->xl_miibus != NULL)
2587 mii = device_get_softc(sc->xl_miibus);
2588 if (mii == NULL)
2589 ifm = &sc->ifmedia;
2590 else
2591 ifm = &mii->mii_media;
2592
2593 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2594 case IFM_100_FX:
2595 case IFM_10_FL:
2596 case IFM_10_2:
2597 case IFM_10_5:
2598 xl_setmode(sc, ifm->ifm_media);
2599 return(0);
2600 break;
2601 default:
2602 break;
2603 }
2604
2605 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
2606 || sc->xl_media & XL_MEDIAOPT_BT4) {
2607 xl_init(sc);
2608 } else {
2609 xl_setmode(sc, ifm->ifm_media);
2610 }
2611
2612 return(0);
2613}
2614
2615/*
2616 * Report current media status.
2617 */
2618static void xl_ifmedia_sts(ifp, ifmr)
2619 struct ifnet *ifp;
2620 struct ifmediareq *ifmr;
2621{
2622 struct xl_softc *sc;
2623 u_int32_t icfg;
2624 struct mii_data *mii = NULL;
2625
2626 sc = ifp->if_softc;
2627 if (sc->xl_miibus != NULL)
2628 mii = device_get_softc(sc->xl_miibus);
2629
2630 XL_SEL_WIN(3);
2631 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2632 icfg >>= XL_ICFG_CONNECTOR_BITS;
2633
2634 ifmr->ifm_active = IFM_ETHER;
2635
2636 switch(icfg) {
2637 case XL_XCVR_10BT:
2638 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2639 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2640 ifmr->ifm_active |= IFM_FDX;
2641 else
2642 ifmr->ifm_active |= IFM_HDX;
2643 break;
2644 case XL_XCVR_AUI:
2645 if (sc->xl_type == XL_TYPE_905B &&
2646 sc->xl_media == XL_MEDIAOPT_10FL) {
2647 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
2648 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2649 ifmr->ifm_active |= IFM_FDX;
2650 else
2651 ifmr->ifm_active |= IFM_HDX;
2652 } else
2653 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2654 break;
2655 case XL_XCVR_COAX:
2656 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
2657 break;
2658 /*
2659 * XXX MII and BTX/AUTO should be separate cases.
2660 */
2661
2662 case XL_XCVR_100BTX:
2663 case XL_XCVR_AUTO:
2664 case XL_XCVR_MII:
2665 if (mii != NULL) {
2666 mii_pollstat(mii);
2667 ifmr->ifm_active = mii->mii_media_active;
2668 ifmr->ifm_status = mii->mii_media_status;
2669 }
2670 break;
2671 case XL_XCVR_100BFX:
2672 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
2673 break;
2674 default:
2675 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, icfg);
2676 break;
2677 }
2678
2679 return;
2680}
2681
2682static int xl_ioctl(ifp, command, data)
2683 struct ifnet *ifp;
2684 u_long command;
2685 caddr_t data;
2686{
2687 struct xl_softc *sc = ifp->if_softc;
2688 struct ifreq *ifr = (struct ifreq *) data;
2689 int s, error = 0;
2690 struct mii_data *mii = NULL;
2691 u_int8_t rxfilt;
2692
2693 s = splimp();
2694
2695 switch(command) {
2696 case SIOCSIFADDR:
2697 case SIOCGIFADDR:
2698 case SIOCSIFMTU:
2699 error = ether_ioctl(ifp, command, data);
2700 break;
2701 case SIOCSIFFLAGS:
2702 XL_SEL_WIN(5);
2703 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2704 if (ifp->if_flags & IFF_UP) {
2705 if (ifp->if_flags & IFF_RUNNING &&
2706 ifp->if_flags & IFF_PROMISC &&
2707 !(sc->xl_if_flags & IFF_PROMISC)) {
2708 rxfilt |= XL_RXFILTER_ALLFRAMES;
2709 CSR_WRITE_2(sc, XL_COMMAND,
2710 XL_CMD_RX_SET_FILT|rxfilt);
2711 XL_SEL_WIN(7);
2712 } else if (ifp->if_flags & IFF_RUNNING &&
2713 !(ifp->if_flags & IFF_PROMISC) &&
2714 sc->xl_if_flags & IFF_PROMISC) {
2715 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2716 CSR_WRITE_2(sc, XL_COMMAND,
2717 XL_CMD_RX_SET_FILT|rxfilt);
2718 XL_SEL_WIN(7);
2719 } else
2720 xl_init(sc);
2721 } else {
2722 if (ifp->if_flags & IFF_RUNNING)
2723 xl_stop(sc);
2724 }
2725 sc->xl_if_flags = ifp->if_flags;
2726 error = 0;
2727 break;
2728 case SIOCADDMULTI:
2729 case SIOCDELMULTI:
2730 if (sc->xl_type == XL_TYPE_905B)
2731 xl_setmulti_hash(sc);
2732 else
2733 xl_setmulti(sc);
2734 error = 0;
2735 break;
2736 case SIOCGIFMEDIA:
2737 case SIOCSIFMEDIA:
2738 if (sc->xl_miibus != NULL)
2739 mii = device_get_softc(sc->xl_miibus);
2740 if (mii == NULL)
2741 error = ifmedia_ioctl(ifp, ifr,
2742 &sc->ifmedia, command);
2743 else
2744 error = ifmedia_ioctl(ifp, ifr,
2745 &mii->mii_media, command);
2746 break;
2747 default:
2748 error = EINVAL;
2749 break;
2750 }
2751
2752 (void)splx(s);
2753
2754 return(error);
2755}
2756
2757static void xl_watchdog(ifp)
2758 struct ifnet *ifp;
2759{
2760 struct xl_softc *sc;
2761 u_int16_t status = 0;
2762
2763 sc = ifp->if_softc;
2764
2765 ifp->if_oerrors++;
2766 XL_SEL_WIN(4);
2767 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2768 printf("xl%d: watchdog timeout\n", sc->xl_unit);
2769
2770 if (status & XL_MEDIASTAT_CARRIER)
2771 printf("xl%d: no carrier - transceiver cable problem?\n",
2772 sc->xl_unit);
2773 xl_txeoc(sc);
2774 xl_txeof(sc);
2775 xl_rxeof(sc);
2776 xl_reset(sc);
2777 xl_init(sc);
2778
2779 if (ifp->if_snd.ifq_head != NULL)
2780 (*ifp->if_start)(ifp);
2781
2782 return;
2783}
2784
2785/*
2786 * Stop the adapter and free any mbufs allocated to the
2787 * RX and TX lists.
2788 */
2789static void xl_stop(sc)
2790 struct xl_softc *sc;
2791{
2792 register int i;
2793 struct ifnet *ifp;
2794
2795 ifp = &sc->arpcom.ac_if;
2796 ifp->if_timer = 0;
2797
2798 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
2799 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2800 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
2801 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
2802 xl_wait(sc);
2803 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
2804 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2805 DELAY(800);
2806
2807#ifdef foo
2808 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2809 xl_wait(sc);
2810 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2811 xl_wait(sc);
2812#endif
2813
2814 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
2815 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
2816 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2817
2818 /* Stop the stats updater. */
2819 untimeout(xl_stats_update, sc, sc->xl_stat_ch);
2820
2821 /*
2822 * Free data in the RX lists.
2823 */
2824 for (i = 0; i < XL_RX_LIST_CNT; i++) {
2825 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
2826 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
2827 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
2828 }
2829 }
2830 bzero((char *)&sc->xl_ldata->xl_rx_list,
2831 sizeof(sc->xl_ldata->xl_rx_list));
2832 /*
2833 * Free the TX list buffers.
2834 */
2835 for (i = 0; i < XL_TX_LIST_CNT; i++) {
2836 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
2837 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
2838 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
2839 }
2840 }
2841 bzero((char *)&sc->xl_ldata->xl_tx_list,
2842 sizeof(sc->xl_ldata->xl_tx_list));
2843
2844 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2845
2846 return;
2847}
2848
2849/*
2850 * Stop all chip I/O so that the kernel's probe routines don't
2851 * get confused by errant DMAs when rebooting.
2852 */
2853static void xl_shutdown(dev)
2854 device_t dev;
2855{
2856 struct xl_softc *sc;
2857
2858 sc = device_get_softc(dev);
2859
2860 xl_reset(sc);
2861 xl_stop(sc);
2862
2863 return;
2864}
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