Cross Reference: /freebsd-11-stable/sys/dev/xl/if

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if_xl.c (112872)	if_xl.c (112880)
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 / 33 34/ 35 * 3Com 3c90x Etherlink XL PCI NIC driver 36 * 37 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 38 * bus-master chips (3c90x cards and embedded controllers) including 39 * the following: 40 * 41 * 3Com 3c900-TPO 10Mbps/RJ-45 42 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 43 * 3Com 3c905-TX 10/100Mbps/RJ-45 44 * 3Com 3c905-T4 10/100Mbps/RJ-45 45 * 3Com 3c900B-TPO 10Mbps/RJ-45 46 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 47 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 48 * 3Com 3c900B-FL 10Mbps/Fiber-optic 49 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 50 * 3Com 3c905B-TX 10/100Mbps/RJ-45 51 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 52 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 53 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 54 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 55 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 56 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 57 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 58 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 59 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 60 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 61 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 62 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 66 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 67 * Dell on-board 3c920 10/100Mbps/RJ-45 68 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 69 * Dell Latitude laptop docking station embedded 3c905-TX 70 * 71 * Written by Bill Paul <wpaul@ctr.columbia.edu> 72 * Electrical Engineering Department 73 * Columbia University, New York City 74 / 75 76/ 77 * The 3c90x series chips use a bus-master DMA interface for transfering 78 * packets to and from the controller chip. Some of the "vortex" cards 79 * (3c59x) also supported a bus master mode, however for those chips 80 * you could only DMA packets to/from a contiguous memory buffer. For 81 * transmission this would mean copying the contents of the queued mbuf 82 * chain into an mbuf cluster and then DMAing the cluster. This extra 83 * copy would sort of defeat the purpose of the bus master support for 84 * any packet that doesn't fit into a single mbuf. 85 * 86 * By contrast, the 3c90x cards support a fragment-based bus master 87 * mode where mbuf chains can be encapsulated using TX descriptors. 88 * This is similar to other PCI chips such as the Texas Instruments 89 * ThunderLAN and the Intel 82557/82558. 90 * 91 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 92 * bus master chips because they maintain the old PIO interface for 93 * backwards compatibility, but starting with the 3c905B and the 94 * "cyclone" chips, the compatibility interface has been dropped. 95 * Since using bus master DMA is a big win, we use this driver to 96 * support the PCI "boomerang" chips even though they work with the 97 * "vortex" driver in order to obtain better performance. 98 * 99 * This driver is in the /sys/pci directory because it only supports 100 * PCI-based NICs. 101 / 102* 103#include <sys/cdefs.h>	1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 / 33 34/ 35 * 3Com 3c90x Etherlink XL PCI NIC driver 36 * 37 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 38 * bus-master chips (3c90x cards and embedded controllers) including 39 * the following: 40 * 41 * 3Com 3c900-TPO 10Mbps/RJ-45 42 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 43 * 3Com 3c905-TX 10/100Mbps/RJ-45 44 * 3Com 3c905-T4 10/100Mbps/RJ-45 45 * 3Com 3c900B-TPO 10Mbps/RJ-45 46 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 47 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 48 * 3Com 3c900B-FL 10Mbps/Fiber-optic 49 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 50 * 3Com 3c905B-TX 10/100Mbps/RJ-45 51 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 52 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 53 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 54 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 55 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 56 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 57 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 58 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 59 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 60 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 61 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 62 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 66 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 67 * Dell on-board 3c920 10/100Mbps/RJ-45 68 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 69 * Dell Latitude laptop docking station embedded 3c905-TX 70 * 71 * Written by Bill Paul <wpaul@ctr.columbia.edu> 72 * Electrical Engineering Department 73 * Columbia University, New York City 74 / 75 76/ 77 * The 3c90x series chips use a bus-master DMA interface for transfering 78 * packets to and from the controller chip. Some of the "vortex" cards 79 * (3c59x) also supported a bus master mode, however for those chips 80 * you could only DMA packets to/from a contiguous memory buffer. For 81 * transmission this would mean copying the contents of the queued mbuf 82 * chain into an mbuf cluster and then DMAing the cluster. This extra 83 * copy would sort of defeat the purpose of the bus master support for 84 * any packet that doesn't fit into a single mbuf. 85 * 86 * By contrast, the 3c90x cards support a fragment-based bus master 87 * mode where mbuf chains can be encapsulated using TX descriptors. 88 * This is similar to other PCI chips such as the Texas Instruments 89 * ThunderLAN and the Intel 82557/82558. 90 * 91 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 92 * bus master chips because they maintain the old PIO interface for 93 * backwards compatibility, but starting with the 3c905B and the 94 * "cyclone" chips, the compatibility interface has been dropped. 95 * Since using bus master DMA is a big win, we use this driver to 96 * support the PCI "boomerang" chips even though they work with the 97 * "vortex" driver in order to obtain better performance. 98 * 99 * This driver is in the /sys/pci directory because it only supports 100 * PCI-based NICs. 101 / 102* 103#include <sys/cdefs.h>
104__FBSDID("$FreeBSD: head/sys/pci/if_xl.c 112872 2003-03-31 17:29:43Z njl $");	104__FBSDID("$FreeBSD: head/sys/pci/if_xl.c 112880 2003-03-31 20:22:00Z jhb $");
105 106#include <sys/param.h> 107#include <sys/systm.h> 108#include <sys/sockio.h> 109#include <sys/endian.h> 110#include <sys/mbuf.h> 111#include <sys/kernel.h> 112#include <sys/socket.h> 113 114#include <net/if.h> 115#include <net/if_arp.h> 116#include <net/ethernet.h> 117#include <net/if_dl.h> 118#include <net/if_media.h> 119 120#include <net/bpf.h> 121 122#include <machine/bus_memio.h> 123#include <machine/bus_pio.h> 124#include <machine/bus.h> 125#include <machine/resource.h> 126#include <sys/bus.h> 127#include <sys/rman.h> 128 129#include <dev/mii/mii.h> 130#include <dev/mii/miivar.h> 131 132#include <pci/pcireg.h> 133#include <pci/pcivar.h> 134 135MODULE_DEPEND(xl, miibus, 1, 1, 1); 136 137/* "controller miibus0" required. See GENERIC if you get errors here. / 138#include "miibus_if.h" 139* 140#include <pci/if_xlreg.h> 141 142#define XL905B_CSUM_FEATURES (CSUM_IP \| CSUM_TCP \| CSUM_UDP) 143 144/* 145 * Various supported device vendors/types and their names. 146 / 147static struct xl_type xl_devs[] = { 148* { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 149 "3Com 3c900-TPO Etherlink XL" }, 150 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 151 "3Com 3c900-COMBO Etherlink XL" }, 152 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 153 "3Com 3c905-TX Fast Etherlink XL" }, 154 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 155 "3Com 3c905-T4 Fast Etherlink XL" }, 156 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 157 "3Com 3c900B-TPO Etherlink XL" }, 158 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 159 "3Com 3c900B-COMBO Etherlink XL" }, 160 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 161 "3Com 3c900B-TPC Etherlink XL" }, 162 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 163 "3Com 3c900B-FL Etherlink XL" }, 164 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 165 "3Com 3c905B-TX Fast Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 167 "3Com 3c905B-T4 Fast Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 169 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 171 "3Com 3c905B-COMBO Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 173 "3Com 3c905C-TX Fast Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 175 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 177 "3Com 3c980 Fast Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 179 "3Com 3c980C Fast Etherlink XL" }, 180 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 181 "3Com 3cSOHO100-TX OfficeConnect" }, 182 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 183 "3Com 3c450-TX HomeConnect" }, 184 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 185 "3Com 3c555 Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 187 "3Com 3c556 Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 189 "3Com 3c556B Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 191 "3Com 3c575TX Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 193 "3Com 3c575B Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 195 "3Com 3c575C Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 197 "3Com 3c656 Fast Etherlink XL" }, 198 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 199 "3Com 3c656B Fast Etherlink XL" }, 200 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 201 "3Com 3c656C Fast Etherlink XL" }, 202 { 0, 0, NULL } 203}; 204 205static int xl_probe (device_t); 206static int xl_attach (device_t); 207static int xl_detach (device_t); 208 209static int xl_newbuf (struct xl_softc , struct xl_chain_onefrag ); 210static void xl_stats_update (void ); 211static int xl_encap (struct xl_softc , struct xl_chain , 212* struct mbuf ); 213static void xl_rxeof (struct xl_softc ); 214static int xl_rx_resync (struct xl_softc ); 215static void xl_txeof (struct xl_softc ); 216static void xl_txeof_90xB (struct xl_softc ); 217static void xl_txeoc (struct xl_softc ); 218static void xl_intr (void ); 219static void xl_start (struct ifnet ); 220static void xl_start_90xB (struct ifnet ); 221static int xl_ioctl (struct ifnet , u_long, caddr_t); 222static void xl_init (void ); 223static void xl_stop (struct xl_softc ); 224static void xl_watchdog (struct ifnet ); 225static void xl_shutdown (device_t); 226static int xl_suspend (device_t); 227static int xl_resume (device_t); 228* 229static int xl_ifmedia_upd (struct ifnet ); 230static void xl_ifmedia_sts (struct ifnet , struct ifmediareq ); 231* 232static int xl_eeprom_wait (struct xl_softc ); 233static int xl_read_eeprom (struct xl_softc , caddr_t, int, int, int); 234static void xl_mii_sync (struct xl_softc ); 235static void xl_mii_send (struct xl_softc , u_int32_t, int); 236static int xl_mii_readreg (struct xl_softc , struct xl_mii_frame ); 237static int xl_mii_writereg (struct xl_softc , struct xl_mii_frame ); 238 239static void xl_setcfg (struct xl_softc ); 240static void xl_setmode (struct xl_softc , int); 241static u_int8_t xl_calchash (caddr_t); 242static void xl_setmulti (struct xl_softc ); 243static void xl_setmulti_hash (struct xl_softc ); 244static void xl_reset (struct xl_softc ); 245static int xl_list_rx_init (struct xl_softc ); 246static int xl_list_tx_init (struct xl_softc ); 247static int xl_list_tx_init_90xB (struct xl_softc ); 248static void xl_wait (struct xl_softc ); 249static void xl_mediacheck (struct xl_softc ); 250static void xl_choose_xcvr (struct xl_softc , int); 251static void xl_dma_map_addr (void , bus_dma_segment_t , int, int); 252static void xl_dma_map_txbuf (void , bus_dma_segment_t , int, bus_size_t, 253* int); 254#ifdef notdef 255static void xl_testpacket (struct xl_softc ); 256#endif 257* 258static int xl_miibus_readreg (device_t, int, int); 259static int xl_miibus_writereg (device_t, int, int, int); 260static void xl_miibus_statchg (device_t); 261static void xl_miibus_mediainit (device_t); 262 263static device_method_t xl_methods[] = { 264 /* Device interface / 265* DEVMETHOD(device_probe, xl_probe), 266 DEVMETHOD(device_attach, xl_attach), 267 DEVMETHOD(device_detach, xl_detach), 268 DEVMETHOD(device_shutdown, xl_shutdown), 269 DEVMETHOD(device_suspend, xl_suspend), 270 DEVMETHOD(device_resume, xl_resume), 271 272 /* bus interface / 273* DEVMETHOD(bus_print_child, bus_generic_print_child), 274 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 275 276 /* MII interface / 277* DEVMETHOD(miibus_readreg, xl_miibus_readreg), 278 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 279 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 280 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 281 282 { 0, 0 } 283}; 284 285static driver_t xl_driver = { 286 "xl", 287 xl_methods, 288 sizeof(struct xl_softc) 289}; 290 291static devclass_t xl_devclass; 292 293DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0); 294DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0); 295DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 296 297static void 298xl_dma_map_addr(arg, segs, nseg, error) 299 void arg; 300* bus_dma_segment_t segs; 301* int nseg, error; 302{ 303 u_int32_t paddr; 304* 305 paddr = arg; 306 paddr = segs->ds_addr; 307} 308* 309static void 310xl_dma_map_txbuf(arg, segs, nseg, mapsize, error) 311 void arg; 312* bus_dma_segment_t segs; 313* int nseg; 314 bus_size_t mapsize; 315 int error; 316{ 317 struct xl_list l; 318* int i, total_len; 319 320 if (error) 321 return; 322 323 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments")); 324 325 total_len = 0; 326 l = arg; 327 for (i = 0; i < nseg; i++) { 328 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 329 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 330 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 331 total_len += segs[i].ds_len; 332 } 333 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len \| 334 XL_LAST_FRAG); 335 l->xl_status = htole32(total_len); 336 l->xl_next = 0; 337} 338 339/* 340 * Murphy's law says that it's possible the chip can wedge and 341 * the 'command in progress' bit may never clear. Hence, we wait 342 * only a finite amount of time to avoid getting caught in an 343 * infinite loop. Normally this delay routine would be a macro, 344 * but it isn't called during normal operation so we can afford 345 * to make it a function. 346 / 347static void 348xl_wait(sc) 349* struct xl_softc sc; 350{ 351* register int i; 352 353 for (i = 0; i < XL_TIMEOUT; i++) { 354 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 355 break; 356 } 357 358 if (i == XL_TIMEOUT) 359 printf("xl%d: command never completed!\n", sc->xl_unit); 360 361 return; 362} 363 364/* 365 * MII access routines are provided for adapters with external 366 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 367 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 368 * Note: if you don't perform the MDIO operations just right, 369 * it's possible to end up with code that works correctly with 370 * some chips/CPUs/processor speeds/bus speeds/etc but not 371 * with others. 372 / 373#define MII_SET(x) \ 374* CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 375 CSR_READ_2(sc, XL_W4_PHY_MGMT) \| (x)) 376 377#define MII_CLR(x) \ 378 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 379 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 380 381/* 382 * Sync the PHYs by setting data bit and strobing the clock 32 times. 383 / 384static void 385xl_mii_sync(sc) 386* struct xl_softc sc; 387{ 388* register int i; 389 390 XL_SEL_WIN(4); 391 MII_SET(XL_MII_DIR\|XL_MII_DATA); 392 393 for (i = 0; i < 32; i++) { 394 MII_SET(XL_MII_CLK); 395 MII_SET(XL_MII_DATA); 396 MII_CLR(XL_MII_CLK); 397 MII_SET(XL_MII_DATA); 398 } 399 400 return; 401} 402 403/* 404 * Clock a series of bits through the MII. 405 / 406static void 407xl_mii_send(sc, bits, cnt) 408* struct xl_softc sc; 409* u_int32_t bits; 410 int cnt; 411{ 412 int i; 413 414 XL_SEL_WIN(4); 415 MII_CLR(XL_MII_CLK); 416 417 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 418 if (bits & i) { 419 MII_SET(XL_MII_DATA); 420 } else { 421 MII_CLR(XL_MII_DATA); 422 } 423 MII_CLR(XL_MII_CLK); 424 MII_SET(XL_MII_CLK); 425 } 426} 427 428/* 429 * Read an PHY register through the MII. 430 / 431static int 432xl_mii_readreg(sc, frame) 433* struct xl_softc sc; 434* struct xl_mii_frame frame; 435* 436{ 437 int i, ack; 438 439 XL_LOCK(sc); 440 441 /* 442 * Set up frame for RX. 443 / 444* frame->mii_stdelim = XL_MII_STARTDELIM; 445 frame->mii_opcode = XL_MII_READOP; 446 frame->mii_turnaround = 0; 447 frame->mii_data = 0; 448 449 /* 450 * Select register window 4. 451 / 452* 453 XL_SEL_WIN(4); 454 455 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 456 /* 457 * Turn on data xmit. 458 / 459* MII_SET(XL_MII_DIR); 460 461 xl_mii_sync(sc); 462 463 /* 464 * Send command/address info. 465 / 466* xl_mii_send(sc, frame->mii_stdelim, 2); 467 xl_mii_send(sc, frame->mii_opcode, 2); 468 xl_mii_send(sc, frame->mii_phyaddr, 5); 469 xl_mii_send(sc, frame->mii_regaddr, 5); 470 471 /* Idle bit / 472* MII_CLR((XL_MII_CLK\|XL_MII_DATA)); 473 MII_SET(XL_MII_CLK); 474 475 /* Turn off xmit. / 476* MII_CLR(XL_MII_DIR); 477 478 /* Check for ack / 479* MII_CLR(XL_MII_CLK); 480 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 481 MII_SET(XL_MII_CLK); 482 483 /* 484 * Now try reading data bits. If the ack failed, we still 485 * need to clock through 16 cycles to keep the PHY(s) in sync. 486 / 487* if (ack) { 488 for(i = 0; i < 16; i++) { 489 MII_CLR(XL_MII_CLK); 490 MII_SET(XL_MII_CLK); 491 } 492 goto fail; 493 } 494 495 for (i = 0x8000; i; i >>= 1) { 496 MII_CLR(XL_MII_CLK); 497 if (!ack) { 498 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 499 frame->mii_data \|= i; 500 } 501 MII_SET(XL_MII_CLK); 502 } 503 504fail: 505 506 MII_CLR(XL_MII_CLK); 507 MII_SET(XL_MII_CLK); 508 509 XL_UNLOCK(sc); 510 511 if (ack) 512 return(1); 513 return(0); 514} 515 516/* 517 * Write to a PHY register through the MII. 518 / 519static int 520xl_mii_writereg(sc, frame) 521* struct xl_softc sc; 522* struct xl_mii_frame frame; 523* 524{ 525 XL_LOCK(sc); 526 527 /* 528 * Set up frame for TX. 529 / 530* 531 frame->mii_stdelim = XL_MII_STARTDELIM; 532 frame->mii_opcode = XL_MII_WRITEOP; 533 frame->mii_turnaround = XL_MII_TURNAROUND; 534 535 /* 536 * Select the window 4. 537 / 538* XL_SEL_WIN(4); 539 540 /* 541 * Turn on data output. 542 / 543* MII_SET(XL_MII_DIR); 544 545 xl_mii_sync(sc); 546 547 xl_mii_send(sc, frame->mii_stdelim, 2); 548 xl_mii_send(sc, frame->mii_opcode, 2); 549 xl_mii_send(sc, frame->mii_phyaddr, 5); 550 xl_mii_send(sc, frame->mii_regaddr, 5); 551 xl_mii_send(sc, frame->mii_turnaround, 2); 552 xl_mii_send(sc, frame->mii_data, 16); 553 554 /* Idle bit. / 555* MII_SET(XL_MII_CLK); 556 MII_CLR(XL_MII_CLK); 557 558 /* 559 * Turn off xmit. 560 / 561* MII_CLR(XL_MII_DIR); 562 563 XL_UNLOCK(sc); 564 565 return(0); 566} 567 568static int 569xl_miibus_readreg(dev, phy, reg) 570 device_t dev; 571 int phy, reg; 572{ 573 struct xl_softc sc; 574* struct xl_mii_frame frame; 575 576 sc = device_get_softc(dev); 577 578 /* 579 * Pretend that PHYs are only available at MII address 24. 580 * This is to guard against problems with certain 3Com ASIC 581 * revisions that incorrectly map the internal transceiver 582 * control registers at all MII addresses. This can cause 583 * the miibus code to attach the same PHY several times over. 584 / 585* if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 586 return(0); 587 588 bzero((char )&frame, sizeof(frame)); 589* 590 frame.mii_phyaddr = phy; 591 frame.mii_regaddr = reg; 592 xl_mii_readreg(sc, &frame); 593 594 return(frame.mii_data); 595} 596 597static int 598xl_miibus_writereg(dev, phy, reg, data) 599 device_t dev; 600 int phy, reg, data; 601{ 602 struct xl_softc sc; 603* struct xl_mii_frame frame; 604 605 sc = device_get_softc(dev); 606 607 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 608 return(0); 609 610 bzero((char )&frame, sizeof(frame)); 611* 612 frame.mii_phyaddr = phy; 613 frame.mii_regaddr = reg; 614 frame.mii_data = data; 615 616 xl_mii_writereg(sc, &frame); 617 618 return(0); 619} 620 621static void 622xl_miibus_statchg(dev) 623 device_t dev; 624{ 625 struct xl_softc sc; 626* struct mii_data mii; 627* 628 629 sc = device_get_softc(dev); 630 mii = device_get_softc(sc->xl_miibus); 631 632 XL_LOCK(sc); 633 634 xl_setcfg(sc); 635 636 /* Set ASIC's duplex mode to match the PHY. / 637* XL_SEL_WIN(3); 638 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 639 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 640 else 641 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 642 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 643 644 XL_UNLOCK(sc); 645 646 return; 647} 648 649/* 650 * Special support for the 3c905B-COMBO. This card has 10/100 support 651 * plus BNC and AUI ports. This means we will have both an miibus attached 652 * plus some non-MII media settings. In order to allow this, we have to 653 * add the extra media to the miibus's ifmedia struct, but we can't do 654 * that during xl_attach() because the miibus hasn't been attached yet. 655 * So instead, we wait until the miibus probe/attach is done, at which 656 * point we will get a callback telling is that it's safe to add our 657 * extra media. 658 / 659static void 660xl_miibus_mediainit(dev) 661* device_t dev; 662{ 663 struct xl_softc sc; 664* struct mii_data mii; 665* struct ifmedia ifm; 666* 667 sc = device_get_softc(dev); 668 mii = device_get_softc(sc->xl_miibus); 669 ifm = &mii->mii_media; 670 671 XL_LOCK(sc); 672 673 if (sc->xl_media & (XL_MEDIAOPT_AUI\|XL_MEDIAOPT_10FL)) { 674 /* 675 * Check for a 10baseFL board in disguise. 676 / 677* if (sc->xl_type == XL_TYPE_905B && 678 sc->xl_media == XL_MEDIAOPT_10FL) { 679 if (bootverbose) 680 printf("xl%d: found 10baseFL\n", sc->xl_unit); 681 ifmedia_add(ifm, IFM_ETHER\|IFM_10_FL, 0, NULL); 682 ifmedia_add(ifm, IFM_ETHER\|IFM_10_FL\|IFM_HDX, 0, NULL); 683 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 684 ifmedia_add(ifm, 685 IFM_ETHER\|IFM_10_FL\|IFM_FDX, 0, NULL); 686 } else { 687 if (bootverbose) 688 printf("xl%d: found AUI\n", sc->xl_unit); 689 ifmedia_add(ifm, IFM_ETHER\|IFM_10_5, 0, NULL); 690 } 691 } 692 693 if (sc->xl_media & XL_MEDIAOPT_BNC) { 694 if (bootverbose) 695 printf("xl%d: found BNC\n", sc->xl_unit); 696 ifmedia_add(ifm, IFM_ETHER\|IFM_10_2, 0, NULL); 697 } 698 699 XL_UNLOCK(sc); 700 701 return; 702} 703 704/* 705 * The EEPROM is slow: give it time to come ready after issuing 706 * it a command. 707 / 708static int 709xl_eeprom_wait(sc) 710* struct xl_softc sc; 711{ 712* int i; 713 714 for (i = 0; i < 100; i++) { 715 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 716 DELAY(162); 717 else 718 break; 719 } 720 721 if (i == 100) { 722 printf("xl%d: eeprom failed to come ready\n", sc->xl_unit); 723 return(1); 724 } 725 726 return(0); 727} 728 729/* 730 * Read a sequence of words from the EEPROM. Note that ethernet address 731 * data is stored in the EEPROM in network byte order. 732 / 733static int 734xl_read_eeprom(sc, dest, off, cnt, swap) 735* struct xl_softc sc; 736* caddr_t dest; 737 int off; 738 int cnt; 739 int swap; 740{ 741 int err = 0, i; 742 u_int16_t word = 0, ptr; 743#define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) \| ((A) & 0x003F)) 744#define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 745* /* WARNING! DANGER! 746 * It's easy to accidentally overwrite the rom content! 747 * Note: the 3c575 uses 8bit EEPROM offsets. 748 / 749* XL_SEL_WIN(0); 750 751 if (xl_eeprom_wait(sc)) 752 return(1); 753 754 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 755 off += 0x30; 756 757 for (i = 0; i < cnt; i++) { 758 if (sc->xl_flags & XL_FLAG_8BITROM) 759 CSR_WRITE_2(sc, XL_W0_EE_CMD, 760 XL_EE_8BIT_READ \| EEPROM_8BIT_OFFSET(off + i)); 761 else 762 CSR_WRITE_2(sc, XL_W0_EE_CMD, 763 XL_EE_READ \| EEPROM_5BIT_OFFSET(off + i)); 764 err = xl_eeprom_wait(sc); 765 if (err) 766 break; 767 word = CSR_READ_2(sc, XL_W0_EE_DATA); 768 ptr = (u_int16_t )(dest + (i 2)); 769 if (swap) 770 ptr = ntohs(word); 771* else 772 ptr = word; 773* } 774 775 return(err ? 1 : 0); 776} 777 778/* 779 * This routine is taken from the 3Com Etherlink XL manual, 780 * page 10-7. It calculates a CRC of the supplied multicast 781 * group address and returns the lower 8 bits, which are used 782 * as the multicast filter position. 783 * Note: the 3c905B currently only supports a 64-bit hash table, 784 * which means we really only need 6 bits, but the manual indicates 785 * that future chip revisions will have a 256-bit hash table, 786 * hence the routine is set up to calculate 8 bits of position 787 * info in case we need it some day. 788 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a 789 * 256 bit hash table. This means we have to use all 8 bits regardless. 790 * On older cards, the upper 2 bits will be ignored. Grrrr.... 791 / 792static u_int8_t xl_calchash(addr) 793* caddr_t addr; 794{ 795 u_int32_t crc, carry; 796 int i, j; 797 u_int8_t c; 798 799 /* Compute CRC for the address value. / 800* crc = 0xFFFFFFFF; /* initial value / 801* 802 for (i = 0; i < 6; i++) { 803 c = (addr + i); 804* for (j = 0; j < 8; j++) { 805 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 806 crc <<= 1; 807 c >>= 1; 808 if (carry) 809 crc = (crc ^ 0x04c11db6) \| carry; 810 } 811 } 812 813 /* return the filter bit position / 814* return(crc & 0x000000FF); 815} 816 817/* 818 * NICs older than the 3c905B have only one multicast option, which 819 * is to enable reception of all multicast frames. 820 / 821static void 822xl_setmulti(sc) 823* struct xl_softc sc; 824{ 825* struct ifnet ifp; 826* struct ifmultiaddr ifma; 827* u_int8_t rxfilt; 828 int mcnt = 0; 829 830 ifp = &sc->arpcom.ac_if; 831 832 XL_SEL_WIN(5); 833 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 834 835 if (ifp->if_flags & IFF_ALLMULTI) { 836 rxfilt \|= XL_RXFILTER_ALLMULTI; 837 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT\|rxfilt); 838 return; 839 } 840 841 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 842 mcnt++; 843 844 if (mcnt) 845 rxfilt \|= XL_RXFILTER_ALLMULTI; 846 else 847 rxfilt &= ~XL_RXFILTER_ALLMULTI; 848 849 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT\|rxfilt); 850 851 return; 852} 853 854/* 855 * 3c905B adapters have a hash filter that we can program. 856 / 857static void 858xl_setmulti_hash(sc) 859* struct xl_softc sc; 860{ 861* struct ifnet ifp; 862* int h = 0, i; 863 struct ifmultiaddr ifma; 864* u_int8_t rxfilt; 865 int mcnt = 0; 866 867 ifp = &sc->arpcom.ac_if; 868 869 XL_SEL_WIN(5); 870 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 871 872 if (ifp->if_flags & IFF_ALLMULTI) { 873 rxfilt \|= XL_RXFILTER_ALLMULTI; 874 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT\|rxfilt); 875 return; 876 } else 877 rxfilt &= ~XL_RXFILTER_ALLMULTI; 878 879 880 /* first, zot all the existing hash bits / 881* for (i = 0; i < XL_HASHFILT_SIZE; i++) 882 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH\|i); 883 884 /* now program new ones / 885* TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 886 if (ifma->ifma_addr->sa_family != AF_LINK) 887 continue; 888 h = xl_calchash(LLADDR((struct sockaddr_dl )ifma->ifma_addr)); 889* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH\|XL_HASH_SET\|h); 890 mcnt++; 891 } 892 893 if (mcnt) 894 rxfilt \|= XL_RXFILTER_MULTIHASH; 895 else 896 rxfilt &= ~XL_RXFILTER_MULTIHASH; 897 898 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT\|rxfilt); 899 900 return; 901} 902 903#ifdef notdef 904static void 905xl_testpacket(sc) 906 struct xl_softc sc; 907{ 908* struct mbuf m; 909* struct ifnet ifp; 910* 911 ifp = &sc->arpcom.ac_if; 912 913 MGETHDR(m, M_DONTWAIT, MT_DATA); 914 915 if (m == NULL) 916 return; 917 918 bcopy(&sc->arpcom.ac_enaddr, 919 mtod(m, struct ether_header )->ether_dhost, ETHER_ADDR_LEN); 920* bcopy(&sc->arpcom.ac_enaddr, 921 mtod(m, struct ether_header )->ether_shost, ETHER_ADDR_LEN); 922* mtod(m, struct ether_header )->ether_type = htons(3); 923* mtod(m, unsigned char )[14] = 0; 924* mtod(m, unsigned char )[15] = 0; 925* mtod(m, unsigned char )[16] = 0xE3; 926* m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 927 IF_ENQUEUE(&ifp->if_snd, m); 928 xl_start(ifp); 929 930 return; 931} 932#endif 933 934static void 935xl_setcfg(sc) 936 struct xl_softc sc; 937{ 938* u_int32_t icfg; 939 940 XL_SEL_WIN(3); 941 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 942 icfg &= ~XL_ICFG_CONNECTOR_MASK; 943 if (sc->xl_media & XL_MEDIAOPT_MII \|\| 944 sc->xl_media & XL_MEDIAOPT_BT4) 945 icfg \|= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 946 if (sc->xl_media & XL_MEDIAOPT_BTX) 947 icfg \|= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 948 949 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 950 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 951 952 return; 953} 954 955static void 956xl_setmode(sc, media) 957 struct xl_softc sc; 958* int media; 959{ 960 u_int32_t icfg; 961 u_int16_t mediastat; 962 963 printf("xl%d: selecting ", sc->xl_unit); 964 965 XL_SEL_WIN(4); 966 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 967 XL_SEL_WIN(3); 968 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 969 970 if (sc->xl_media & XL_MEDIAOPT_BT) { 971 if (IFM_SUBTYPE(media) == IFM_10_T) { 972 printf("10baseT transceiver, "); 973 sc->xl_xcvr = XL_XCVR_10BT; 974 icfg &= ~XL_ICFG_CONNECTOR_MASK; 975 icfg \|= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 976 mediastat \|= XL_MEDIASTAT_LINKBEAT\| 977 XL_MEDIASTAT_JABGUARD; 978 mediastat &= ~XL_MEDIASTAT_SQEENB; 979 } 980 } 981 982 if (sc->xl_media & XL_MEDIAOPT_BFX) { 983 if (IFM_SUBTYPE(media) == IFM_100_FX) { 984 printf("100baseFX port, "); 985 sc->xl_xcvr = XL_XCVR_100BFX; 986 icfg &= ~XL_ICFG_CONNECTOR_MASK; 987 icfg \|= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 988 mediastat \|= XL_MEDIASTAT_LINKBEAT; 989 mediastat &= ~XL_MEDIASTAT_SQEENB; 990 } 991 } 992 993 if (sc->xl_media & (XL_MEDIAOPT_AUI\|XL_MEDIAOPT_10FL)) { 994 if (IFM_SUBTYPE(media) == IFM_10_5) { 995 printf("AUI port, "); 996 sc->xl_xcvr = XL_XCVR_AUI; 997 icfg &= ~XL_ICFG_CONNECTOR_MASK; 998 icfg \|= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 999 mediastat &= ~(XL_MEDIASTAT_LINKBEAT\| 1000 XL_MEDIASTAT_JABGUARD); 1001 mediastat \|= ~XL_MEDIASTAT_SQEENB; 1002 } 1003 if (IFM_SUBTYPE(media) == IFM_10_FL) { 1004 printf("10baseFL transceiver, "); 1005 sc->xl_xcvr = XL_XCVR_AUI; 1006 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1007 icfg \|= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 1008 mediastat &= ~(XL_MEDIASTAT_LINKBEAT\| 1009 XL_MEDIASTAT_JABGUARD); 1010 mediastat \|= ~XL_MEDIASTAT_SQEENB; 1011 } 1012 } 1013 1014 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1015 if (IFM_SUBTYPE(media) == IFM_10_2) { 1016 printf("BNC port, "); 1017 sc->xl_xcvr = XL_XCVR_COAX; 1018 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1019 icfg \|= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 1020 mediastat &= ~(XL_MEDIASTAT_LINKBEAT\| 1021 XL_MEDIASTAT_JABGUARD\| 1022 XL_MEDIASTAT_SQEENB); 1023 } 1024 } 1025 1026 if ((media & IFM_GMASK) == IFM_FDX \|\| 1027 IFM_SUBTYPE(media) == IFM_100_FX) { 1028 printf("full duplex\n"); 1029 XL_SEL_WIN(3); 1030 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 1031 } else { 1032 printf("half duplex\n"); 1033 XL_SEL_WIN(3); 1034 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 1035 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 1036 } 1037 1038 if (IFM_SUBTYPE(media) == IFM_10_2) 1039 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 1040 else 1041 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 1042 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 1043 XL_SEL_WIN(4); 1044 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 1045 DELAY(800); 1046 XL_SEL_WIN(7); 1047 1048 return; 1049} 1050 1051static void 1052xl_reset(sc) 1053 struct xl_softc sc; 1054{ 1055* register int i; 1056 1057 XL_SEL_WIN(0); 1058 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET \| 1059 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1060 XL_RESETOPT_DISADVFD:0)); 1061 1062 for (i = 0; i < XL_TIMEOUT; i++) { 1063 DELAY(10); 1064 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1065 break; 1066 } 1067 1068 if (i == XL_TIMEOUT) 1069 printf("xl%d: reset didn't complete\n", sc->xl_unit); 1070 1071 /* Reset TX and RX. / 1072* /* Note: the RX reset takes an absurd amount of time 1073 * on newer versions of the Tornado chips such as those 1074 * on the 3c905CX and newer 3c908C cards. We wait an 1075 * extra amount of time so that xl_wait() doesn't complain 1076 * and annoy the users. 1077 / 1078* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1079 DELAY(100000); 1080 xl_wait(sc); 1081 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1082 xl_wait(sc); 1083 1084 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR \|\| 1085 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1086 XL_SEL_WIN(2); 1087 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1088 XL_W2_RESET_OPTIONS) 1089 \| ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1090 \| ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1091 ); 1092 } 1093 1094 /* Wait a little while for the chip to get its brains in order. / 1095* DELAY(100000); 1096 return; 1097} 1098 1099/* 1100 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1101 * IDs against our list and return a device name if we find a match. 1102 / 1103static int 1104xl_probe(dev) 1105* device_t dev; 1106{ 1107 struct xl_type t; 1108* 1109 t = xl_devs; 1110 1111 while(t->xl_name != NULL) { 1112 if ((pci_get_vendor(dev) == t->xl_vid) && 1113 (pci_get_device(dev) == t->xl_did)) { 1114 device_set_desc(dev, t->xl_name); 1115 return(0); 1116 } 1117 t++; 1118 } 1119 1120 return(ENXIO); 1121} 1122 1123/* 1124 * This routine is a kludge to work around possible hardware faults 1125 * or manufacturing defects that can cause the media options register 1126 * (or reset options register, as it's called for the first generation 1127 * 3c90x adapters) to return an incorrect result. I have encountered 1128 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1129 * which doesn't have any of the 'mediaopt' bits set. This screws up 1130 * the attach routine pretty badly because it doesn't know what media 1131 * to look for. If we find ourselves in this predicament, this routine 1132 * will try to guess the media options values and warn the user of a 1133 * possible manufacturing defect with his adapter/system/whatever. 1134 / 1135static void 1136xl_mediacheck(sc) 1137* struct xl_softc sc; 1138{ 1139* 1140 /* 1141 * If some of the media options bits are set, assume they are 1142 * correct. If not, try to figure it out down below. 1143 * XXX I should check for 10baseFL, but I don't have an adapter 1144 * to test with. 1145 / 1146* if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1147 /* 1148 * Check the XCVR value. If it's not in the normal range 1149 * of values, we need to fake it up here. 1150 / 1151* if (sc->xl_xcvr <= XL_XCVR_AUTO) 1152 return; 1153 else { 1154 printf("xl%d: bogus xcvr value " 1155 "in EEPROM (%x)\n", sc->xl_unit, sc->xl_xcvr); 1156 printf("xl%d: choosing new default based " 1157 "on card type\n", sc->xl_unit); 1158 } 1159 } else { 1160 if (sc->xl_type == XL_TYPE_905B && 1161 sc->xl_media & XL_MEDIAOPT_10FL) 1162 return; 1163 printf("xl%d: WARNING: no media options bits set in " 1164 "the media options register!!\n", sc->xl_unit); 1165 printf("xl%d: this could be a manufacturing defect in " 1166 "your adapter or system\n", sc->xl_unit); 1167 printf("xl%d: attempting to guess media type; you " 1168 "should probably consult your vendor\n", sc->xl_unit); 1169 } 1170 1171 xl_choose_xcvr(sc, 1); 1172 1173 return; 1174} 1175 1176static void 1177xl_choose_xcvr(sc, verbose) 1178 struct xl_softc sc; 1179* int verbose; 1180{ 1181 u_int16_t devid; 1182 1183 /* 1184 * Read the device ID from the EEPROM. 1185 * This is what's loaded into the PCI device ID register, so it has 1186 * to be correct otherwise we wouldn't have gotten this far. 1187 / 1188* xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1189 1190 switch(devid) { 1191 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO / 1192* case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO / 1193* sc->xl_media = XL_MEDIAOPT_BT; 1194 sc->xl_xcvr = XL_XCVR_10BT; 1195 if (verbose) 1196 printf("xl%d: guessing 10BaseT " 1197 "transceiver\n", sc->xl_unit); 1198 break; 1199 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO / 1200* case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO / 1201* sc->xl_media = XL_MEDIAOPT_BT\|XL_MEDIAOPT_BNC\|XL_MEDIAOPT_AUI; 1202 sc->xl_xcvr = XL_XCVR_10BT; 1203 if (verbose) 1204 printf("xl%d: guessing COMBO " 1205 "(AUI/BNC/TP)\n", sc->xl_unit); 1206 break; 1207 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC / 1208* sc->xl_media = XL_MEDIAOPT_BT\|XL_MEDIAOPT_BNC; 1209 sc->xl_xcvr = XL_XCVR_10BT; 1210 if (verbose) 1211 printf("xl%d: guessing TPC (BNC/TP)\n", sc->xl_unit); 1212 break; 1213 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL / 1214* sc->xl_media = XL_MEDIAOPT_10FL; 1215 sc->xl_xcvr = XL_XCVR_AUI; 1216 if (verbose) 1217 printf("xl%d: guessing 10baseFL\n", sc->xl_unit); 1218 break; 1219 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX / 1220* case TC_DEVICEID_HURRICANE_555: /* 3c555 / 1221* case TC_DEVICEID_HURRICANE_556: /* 3c556 / 1222* case TC_DEVICEID_HURRICANE_556B: /* 3c556B / 1223* case TC_DEVICEID_HURRICANE_575A: /* 3c575TX / 1224* case TC_DEVICEID_HURRICANE_575B: /* 3c575B / 1225* case TC_DEVICEID_HURRICANE_575C: /* 3c575C / 1226* case TC_DEVICEID_HURRICANE_656: /* 3c656 / 1227* case TC_DEVICEID_HURRICANE_656B: /* 3c656B / 1228* case TC_DEVICEID_TORNADO_656C: /* 3c656C / 1229* case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB / 1230* sc->xl_media = XL_MEDIAOPT_MII; 1231 sc->xl_xcvr = XL_XCVR_MII; 1232 if (verbose) 1233 printf("xl%d: guessing MII\n", sc->xl_unit); 1234 break; 1235 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 / 1236* case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 / 1237* sc->xl_media = XL_MEDIAOPT_BT4; 1238 sc->xl_xcvr = XL_XCVR_MII; 1239 if (verbose) 1240 printf("xl%d: guessing 100BaseT4/MII\n", sc->xl_unit); 1241 break; 1242 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX / 1243* case TC_DEVICEID_HURRICANE_10_100BT_SERV:/3c980-TX / 1244 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX / 1245* case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX / 1246* case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX / 1247* case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX / 1248* sc->xl_media = XL_MEDIAOPT_BTX; 1249 sc->xl_xcvr = XL_XCVR_AUTO; 1250 if (verbose) 1251 printf("xl%d: guessing 10/100 internal\n", sc->xl_unit); 1252 break; 1253 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO / 1254* sc->xl_media = XL_MEDIAOPT_BTX\|XL_MEDIAOPT_BNC\|XL_MEDIAOPT_AUI; 1255 sc->xl_xcvr = XL_XCVR_AUTO; 1256 if (verbose) 1257 printf("xl%d: guessing 10/100 " 1258 "plus BNC/AUI\n", sc->xl_unit); 1259 break; 1260 default: 1261 printf("xl%d: unknown device ID: %x -- " 1262 "defaulting to 10baseT\n", sc->xl_unit, devid); 1263 sc->xl_media = XL_MEDIAOPT_BT; 1264 break; 1265 } 1266 1267 return; 1268} 1269 1270/* 1271 * Attach the interface. Allocate softc structures, do ifmedia 1272 * setup and ethernet/BPF attach. 1273 / 1274static int 1275xl_attach(dev) 1276* device_t dev; 1277{ 1278 u_char eaddr[ETHER_ADDR_LEN]; 1279 u_int32_t command; 1280 u_int16_t xcvr[2]; 1281 struct xl_softc sc; 1282* struct ifnet ifp; 1283* int media = IFM_ETHER\|IFM_100_TX\|IFM_FDX; 1284 int unit, error = 0, rid, res; 1285 1286 sc = device_get_softc(dev); 1287 unit = device_get_unit(dev); 1288 1289 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1290 MTX_DEF \| MTX_RECURSE); 1291 1292 sc->xl_flags = 0; 1293 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555) 1294 sc->xl_flags \|= XL_FLAG_EEPROM_OFFSET_30 \| XL_FLAG_PHYOK; 1295 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 \|\| 1296 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1297 sc->xl_flags \|= XL_FLAG_FUNCREG \| XL_FLAG_PHYOK \| 1298 XL_FLAG_EEPROM_OFFSET_30 \| XL_FLAG_WEIRDRESET \| 1299 XL_FLAG_INVERT_LED_PWR \| XL_FLAG_INVERT_MII_PWR; 1300 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 \|\| 1301 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556) 1302 sc->xl_flags \|= XL_FLAG_8BITROM; 1303 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1304 sc->xl_flags \|= XL_FLAG_NO_XCVR_PWR; 1305 1306 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A \|\| 1307 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B \|\| 1308 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C \|\| 1309 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B \|\| 1310 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1311 sc->xl_flags \|= XL_FLAG_FUNCREG \| XL_FLAG_PHYOK \| 1312 XL_FLAG_EEPROM_OFFSET_30 \| XL_FLAG_8BITROM; 1313 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656) 1314 sc->xl_flags \|= XL_FLAG_FUNCREG \| XL_FLAG_PHYOK; 1315 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B) 1316 sc->xl_flags \|= XL_FLAG_INVERT_LED_PWR; 1317 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C) 1318 sc->xl_flags \|= XL_FLAG_INVERT_MII_PWR; 1319 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1320 sc->xl_flags \|= XL_FLAG_INVERT_MII_PWR; 1321 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 \|\| 1322 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B) 1323 sc->xl_flags \|= XL_FLAG_INVERT_MII_PWR \| 1324 XL_FLAG_INVERT_LED_PWR; 1325 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B) 1326 sc->xl_flags \|= XL_FLAG_PHYOK; 1327 1328 /* 1329 * If this is a 3c905B, we have to check one extra thing. 1330 * The 905B supports power management and may be placed in 1331 * a low-power mode (D3 mode), typically by certain operating 1332 * systems which shall not be named. The PCI BIOS is supposed 1333 * to reset the NIC and bring it out of low-power mode, but 1334 * some do not. Consequently, we have to see if this chip 1335 * supports power management, and if so, make sure it's not 1336 * in low-power mode. If power management is available, the 1337 * capid byte will be 0x01. 1338 * 1339 * I _think_ that what actually happens is that the chip 1340 * loses its PCI configuration during the transition from 1341 * D3 back to D0; this means that it should be possible for 1342 * us to save the PCI iobase, membase and IRQ, put the chip 1343 * back in the D0 state, then restore the PCI config ourselves. 1344 / 1345* 1346 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1347 u_int32_t iobase, membase, irq; 1348 1349 /* Save important PCI config data. / 1350* iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1351 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1352 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1353 1354 /* Reset the power state. / 1355* printf("xl%d: chip is in D%d power mode " 1356 "-- setting to D0\n", unit, 1357 pci_get_powerstate(dev)); 1358 1359 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1360 1361 /* Restore PCI config data. / 1362* pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1363 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1364 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1365 } 1366 1367 /* 1368 * Map control/status registers. 1369 / 1370* pci_enable_busmaster(dev); 1371 pci_enable_io(dev, SYS_RES_IOPORT); 1372 pci_enable_io(dev, SYS_RES_MEMORY); 1373 command = pci_read_config(dev, PCIR_COMMAND, 4); 1374 1375 if (!(command & PCIM_CMD_PORTEN) && !(command & PCIM_CMD_MEMEN)) { 1376 printf("xl%d: failed to enable I/O ports and memory mappings!\n", unit); 1377 error = ENXIO; 1378 goto fail; 1379 } 1380 1381 rid = XL_PCI_LOMEM; 1382 res = SYS_RES_MEMORY; 1383 1384 sc->xl_res = bus_alloc_resource(dev, res, &rid, 1385 0, ~0, 1, RF_ACTIVE); 1386 1387 if (sc->xl_res != NULL) { 1388 sc->xl_flags \|= XL_FLAG_USE_MMIO; 1389 if (bootverbose) 1390 printf("xl%d: using memory mapped I/O\n", unit); 1391 } else { 1392 rid = XL_PCI_LOIO; 1393 res = SYS_RES_IOPORT; 1394 sc->xl_res = bus_alloc_resource(dev, res, &rid, 1395 0, ~0, 1, RF_ACTIVE); 1396 if (sc->xl_res == NULL) { 1397 printf ("xl%d: couldn't map ports/memory\n", unit); 1398 error = ENXIO; 1399 goto fail; 1400 } 1401 if (bootverbose) 1402 printf("xl%d: using port I/O\n", unit); 1403 } 1404 1405 sc->xl_btag = rman_get_bustag(sc->xl_res); 1406 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1407 1408 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1409 rid = XL_PCI_FUNCMEM; 1410 sc->xl_fres = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1411 0, ~0, 1, RF_ACTIVE); 1412 1413 if (sc->xl_fres == NULL) { 1414 printf ("xl%d: couldn't map ports/memory\n", unit); 1415 error = ENXIO; 1416 goto fail; 1417 } 1418 1419 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1420 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1421 } 1422 1423 /* Allocate interrupt / 1424* rid = 0; 1425 sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1426 RF_SHAREABLE \| RF_ACTIVE); 1427 if (sc->xl_irq == NULL) { 1428 printf("xl%d: couldn't map interrupt\n", unit); 1429 error = ENXIO; 1430 goto fail; 1431 } 1432 1433 /* Reset the adapter. / 1434* xl_reset(sc); 1435 1436 /* 1437 * Get station address from the EEPROM. 1438 / 1439* if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1440 printf("xl%d: failed to read station address\n", sc->xl_unit); 1441 error = ENXIO; 1442 goto fail; 1443 } 1444 1445 /* 1446 * A 3Com chip was detected. Inform the world. 1447 / 1448* printf("xl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1449 1450 sc->xl_unit = unit; 1451 callout_handle_init(&sc->xl_stat_ch); 1452 bcopy(eaddr, (char )&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1453* 1454 /* 1455 * Now allocate a tag for the DMA descriptor lists and a chunk 1456 * of DMA-able memory based on the tag. Also obtain the DMA 1457 * addresses of the RX and TX ring, which we'll need later. 1458 * All of our lists are allocated as a contiguous block 1459 * of memory. 1460 / 1461* error = bus_dma_tag_create(NULL, 8, 0, 1462 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1463 XL_RX_LIST_SZ, 1, BUS_SPACE_MAXSIZE_32BIT, 0, 1464 &sc->xl_ldata.xl_rx_tag); 1465 if (error) { 1466 printf("xl%d: failed to allocate rx dma tag\n", unit); 1467 goto fail; 1468 } 1469 1470 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1471 (void *)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT, 1472* &sc->xl_ldata.xl_rx_dmamap); 1473 if (error) { 1474 printf("xl%d: no memory for rx list buffers!\n", unit); 1475 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1476 sc->xl_ldata.xl_rx_tag = NULL; 1477 goto fail; 1478 } 1479 1480 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1481 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1482 XL_RX_LIST_SZ, xl_dma_map_addr, 1483 &sc->xl_ldata.xl_rx_dmaaddr, 0); 1484 if (error) { 1485 printf("xl%d: cannot get dma address of the rx ring!\n", unit); 1486 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1487 sc->xl_ldata.xl_rx_dmamap); 1488 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1489 sc->xl_ldata.xl_rx_tag = NULL; 1490 goto fail; 1491 } 1492 1493 error = bus_dma_tag_create(NULL, 8, 0, 1494 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1495 XL_TX_LIST_SZ, 1, BUS_SPACE_MAXSIZE_32BIT, 0, 1496 &sc->xl_ldata.xl_tx_tag); 1497 if (error) { 1498 printf("xl%d: failed to allocate tx dma tag\n", unit); 1499 goto fail; 1500 } 1501 1502 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1503 (void *)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT, 1504* &sc->xl_ldata.xl_tx_dmamap); 1505 if (error) { 1506 printf("xl%d: no memory for list buffers!\n", unit); 1507 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1508 sc->xl_ldata.xl_tx_tag = NULL; 1509 goto fail; 1510 } 1511 1512 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1513 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1514 XL_TX_LIST_SZ, xl_dma_map_addr, 1515 &sc->xl_ldata.xl_tx_dmaaddr, 0); 1516 if (error) { 1517 printf("xl%d: cannot get dma address of the tx ring!\n", unit); 1518 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1519 sc->xl_ldata.xl_tx_dmamap); 1520 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1521 sc->xl_ldata.xl_tx_tag = NULL; 1522 goto fail; 1523 } 1524 1525 /* 1526 * Allocate a DMA tag for the mapping of mbufs. 1527 / 1528* error = bus_dma_tag_create(NULL, 1, 0, 1529 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1530 XL_MAXFRAGS, BUS_SPACE_MAXSIZE_32BIT, 0, &sc->xl_mtag); 1531 if (error) { 1532 printf("xl%d: failed to allocate mbuf dma tag\n", unit); 1533 goto fail; 1534 } 1535 1536 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 1537 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 1538 1539 /* We need a spare DMA map for the RX ring. / 1540* error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1541 if (error) 1542 goto fail; 1543 1544 /* 1545 * Figure out the card type. 3c905B adapters have the 1546 * 'supportsNoTxLength' bit set in the capabilities 1547 * word in the EEPROM. 1548 / 1549* xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1550 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH) 1551 sc->xl_type = XL_TYPE_905B; 1552 else 1553 sc->xl_type = XL_TYPE_90X; 1554 1555 ifp = &sc->arpcom.ac_if; 1556 ifp->if_softc = sc; 1557 ifp->if_unit = unit; 1558 ifp->if_name = "xl"; 1559 ifp->if_mtu = ETHERMTU; 1560 ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX \| IFF_MULTICAST; 1561 ifp->if_ioctl = xl_ioctl; 1562 ifp->if_output = ether_output; 1563 if (sc->xl_type == XL_TYPE_905B) { 1564 ifp->if_start = xl_start_90xB; 1565 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1566 ifp->if_capabilities = IFCAP_HWCSUM; 1567 } else 1568 ifp->if_start = xl_start; 1569 ifp->if_watchdog = xl_watchdog; 1570 ifp->if_init = xl_init; 1571 ifp->if_baudrate = 10000000; 1572 ifp->if_snd.ifq_maxlen = XL_TX_LIST_CNT - 1; 1573 ifp->if_capenable = ifp->if_capabilities; 1574 1575 /* 1576 * Now we have to see what sort of media we have. 1577 * This includes probing for an MII interace and a 1578 * possible PHY. 1579 / 1580* XL_SEL_WIN(3); 1581 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1582 if (bootverbose) 1583 printf("xl%d: media options word: %x\n", sc->xl_unit, 1584 sc->xl_media); 1585 1586 xl_read_eeprom(sc, (char )&xcvr, XL_EE_ICFG_0, 2, 0); 1587* sc->xl_xcvr = xcvr[0] \| xcvr[1] << 16; 1588 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1589 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1590 1591 xl_mediacheck(sc); 1592 1593 if (sc->xl_media & XL_MEDIAOPT_MII \|\| sc->xl_media & XL_MEDIAOPT_BTX 1594 \|\| sc->xl_media & XL_MEDIAOPT_BT4) { 1595 if (bootverbose) 1596 printf("xl%d: found MII/AUTO\n", sc->xl_unit); 1597 xl_setcfg(sc); 1598 if (mii_phy_probe(dev, &sc->xl_miibus, 1599 xl_ifmedia_upd, xl_ifmedia_sts)) { 1600 printf("xl%d: no PHY found!\n", sc->xl_unit); 1601 error = ENXIO; 1602 goto fail; 1603 } 1604 1605 goto done; 1606 } 1607 1608 /* 1609 * Sanity check. If the user has selected "auto" and this isn't 1610 * a 10/100 card of some kind, we need to force the transceiver 1611 * type to something sane. 1612 / 1613* if (sc->xl_xcvr == XL_XCVR_AUTO) 1614 xl_choose_xcvr(sc, bootverbose); 1615 1616 /* 1617 * Do ifmedia setup. 1618 / 1619* 1620 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1621 1622 if (sc->xl_media & XL_MEDIAOPT_BT) { 1623 if (bootverbose) 1624 printf("xl%d: found 10baseT\n", sc->xl_unit); 1625 ifmedia_add(&sc->ifmedia, IFM_ETHER\|IFM_10_T, 0, NULL); 1626 ifmedia_add(&sc->ifmedia, IFM_ETHER\|IFM_10_T\|IFM_HDX, 0, NULL); 1627 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1628 ifmedia_add(&sc->ifmedia, 1629 IFM_ETHER\|IFM_10_T\|IFM_FDX, 0, NULL); 1630 } 1631 1632 if (sc->xl_media & (XL_MEDIAOPT_AUI\|XL_MEDIAOPT_10FL)) { 1633 /* 1634 * Check for a 10baseFL board in disguise. 1635 / 1636* if (sc->xl_type == XL_TYPE_905B && 1637 sc->xl_media == XL_MEDIAOPT_10FL) { 1638 if (bootverbose) 1639 printf("xl%d: found 10baseFL\n", sc->xl_unit); 1640 ifmedia_add(&sc->ifmedia, IFM_ETHER\|IFM_10_FL, 0, NULL); 1641 ifmedia_add(&sc->ifmedia, IFM_ETHER\|IFM_10_FL\|IFM_HDX, 1642 0, NULL); 1643 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1644 ifmedia_add(&sc->ifmedia, 1645 IFM_ETHER\|IFM_10_FL\|IFM_FDX, 0, NULL); 1646 } else { 1647 if (bootverbose) 1648 printf("xl%d: found AUI\n", sc->xl_unit); 1649 ifmedia_add(&sc->ifmedia, IFM_ETHER\|IFM_10_5, 0, NULL); 1650 } 1651 } 1652 1653 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1654 if (bootverbose) 1655 printf("xl%d: found BNC\n", sc->xl_unit); 1656 ifmedia_add(&sc->ifmedia, IFM_ETHER\|IFM_10_2, 0, NULL); 1657 } 1658 1659 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1660 if (bootverbose) 1661 printf("xl%d: found 100baseFX\n", sc->xl_unit); 1662 ifp->if_baudrate = 100000000; 1663 ifmedia_add(&sc->ifmedia, IFM_ETHER\|IFM_100_FX, 0, NULL); 1664 } 1665 1666 /* Choose a default media. / 1667* switch(sc->xl_xcvr) { 1668 case XL_XCVR_10BT: 1669 media = IFM_ETHER\|IFM_10_T; 1670 xl_setmode(sc, media); 1671 break; 1672 case XL_XCVR_AUI: 1673 if (sc->xl_type == XL_TYPE_905B && 1674 sc->xl_media == XL_MEDIAOPT_10FL) { 1675 media = IFM_ETHER\|IFM_10_FL; 1676 xl_setmode(sc, media); 1677 } else { 1678 media = IFM_ETHER\|IFM_10_5; 1679 xl_setmode(sc, media); 1680 } 1681 break; 1682 case XL_XCVR_COAX: 1683 media = IFM_ETHER\|IFM_10_2; 1684 xl_setmode(sc, media); 1685 break; 1686 case XL_XCVR_AUTO: 1687 case XL_XCVR_100BTX: 1688 case XL_XCVR_MII: 1689 /* Chosen by miibus / 1690* break; 1691 case XL_XCVR_100BFX: 1692 media = IFM_ETHER\|IFM_100_FX; 1693 break; 1694 default: 1695 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, 1696 sc->xl_xcvr); 1697 /* 1698 * This will probably be wrong, but it prevents 1699 * the ifmedia code from panicking. 1700 / 1701* media = IFM_ETHER\|IFM_10_T; 1702 break; 1703 } 1704 1705 if (sc->xl_miibus == NULL) 1706 ifmedia_set(&sc->ifmedia, media); 1707 1708done: 1709 1710 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1711 XL_SEL_WIN(0); 1712 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1713 } 1714 1715 /* 1716 * Call MI attach routine. 1717 / 1718* ether_ifattach(ifp, eaddr); 1719 1720 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET, 1721 xl_intr, sc, &sc->xl_intrhand); 1722 if (error) { 1723 printf("xl%d: couldn't set up irq\n", unit); 1724 goto fail; 1725 } 1726 1727fail: 1728 if (error) 1729 xl_detach(dev); 1730 1731 return(error); 1732} 1733 1734static int 1735xl_detach(dev) 1736 device_t dev; 1737{ 1738 struct xl_softc sc; 1739* struct ifnet ifp; 1740* int rid, res; 1741 1742 sc = device_get_softc(dev);	105 106#include <sys/param.h> 107#include <sys/systm.h> 108#include <sys/sockio.h> 109#include <sys/endian.h> 110#include <sys/mbuf.h> 111#include <sys/kernel.h> 112#include <sys/socket.h> 113 114#include <net/if.h> 115#include <net/if_arp.h> 116#include <net/ethernet.h> 117#include <net/if_dl.h> 118#include <net/if_media.h> 119 120#include <net/bpf.h> 121 122#include <machine/bus_memio.h> 123#include <machine/bus_pio.h> 124#include <machine/bus.h> 125#include <machine/resource.h> 126#include <sys/bus.h> 127#include <sys/rman.h> 128 129#include <dev/mii/mii.h> 130#include <dev/mii/miivar.h> 131 132#include <pci/pcireg.h> 133#include <pci/pcivar.h> 134 135MODULE_DEPEND(xl, miibus, 1, 1, 1); 136 137/* "controller miibus0" required. See GENERIC if you get errors here. / 138#include "miibus_if.h" 139* 140#include <pci/if_xlreg.h> 141 142#define XL905B_CSUM_FEATURES (CSUM_IP \| CSUM_TCP \| CSUM_UDP) 143 144/* 145 * Various supported device vendors/types and their names. 146 / 147static struct xl_type xl_devs[] = { 148* { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 149 "3Com 3c900-TPO Etherlink XL" }, 150 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 151 "3Com 3c900-COMBO Etherlink XL" }, 152 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 153 "3Com 3c905-TX Fast Etherlink XL" }, 154 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 155 "3Com 3c905-T4 Fast Etherlink XL" }, 156 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 157 "3Com 3c900B-TPO Etherlink XL" }, 158 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 159 "3Com 3c900B-COMBO Etherlink XL" }, 160 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 161 "3Com 3c900B-TPC Etherlink XL" }, 162 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 163 "3Com 3c900B-FL Etherlink XL" }, 164 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 165 "3Com 3c905B-TX Fast Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 167 "3Com 3c905B-T4 Fast Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 169 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 171 "3Com 3c905B-COMBO Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 173 "3Com 3c905C-TX Fast Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 175 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 177 "3Com 3c980 Fast Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 179 "3Com 3c980C Fast Etherlink XL" }, 180 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 181 "3Com 3cSOHO100-TX OfficeConnect" }, 182 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 183 "3Com 3c450-TX HomeConnect" }, 184 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 185 "3Com 3c555 Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 187 "3Com 3c556 Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 189 "3Com 3c556B Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 191 "3Com 3c575TX Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 193 "3Com 3c575B Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 195 "3Com 3c575C Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 197 "3Com 3c656 Fast Etherlink XL" }, 198 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 199 "3Com 3c656B Fast Etherlink XL" }, 200 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 201 "3Com 3c656C Fast Etherlink XL" }, 202 { 0, 0, NULL } 203}; 204 205static int xl_probe (device_t); 206static int xl_attach (device_t); 207static int xl_detach (device_t); 208 209static int xl_newbuf (struct xl_softc , struct xl_chain_onefrag ); 210static void xl_stats_update (void ); 211static int xl_encap (struct xl_softc , struct xl_chain , 212* struct mbuf ); 213static void xl_rxeof (struct xl_softc ); 214static int xl_rx_resync (struct xl_softc ); 215static void xl_txeof (struct xl_softc ); 216static void xl_txeof_90xB (struct xl_softc ); 217static void xl_txeoc (struct xl_softc ); 218static void xl_intr (void ); 219static void xl_start (struct ifnet ); 220static void xl_start_90xB (struct ifnet ); 221static int xl_ioctl (struct ifnet , u_long, caddr_t); 222static void xl_init (void ); 223static void xl_stop (struct xl_softc ); 224static void xl_watchdog (struct ifnet ); 225static void xl_shutdown (device_t); 226static int xl_suspend (device_t); 227static int xl_resume (device_t); 228* 229static int xl_ifmedia_upd (struct ifnet ); 230static void xl_ifmedia_sts (struct ifnet , struct ifmediareq ); 231* 232static int xl_eeprom_wait (struct xl_softc ); 233static int xl_read_eeprom (struct xl_softc , caddr_t, int, int, int); 234static void xl_mii_sync (struct xl_softc ); 235static void xl_mii_send (struct xl_softc , u_int32_t, int); 236static int xl_mii_readreg (struct xl_softc , struct xl_mii_frame ); 237static int xl_mii_writereg (struct xl_softc , struct xl_mii_frame ); 238 239static void xl_setcfg (struct xl_softc ); 240static void xl_setmode (struct xl_softc , int); 241static u_int8_t xl_calchash (caddr_t); 242static void xl_setmulti (struct xl_softc ); 243static void xl_setmulti_hash (struct xl_softc ); 244static void xl_reset (struct xl_softc ); 245static int xl_list_rx_init (struct xl_softc ); 246static int xl_list_tx_init (struct xl_softc ); 247static int xl_list_tx_init_90xB (struct xl_softc ); 248static void xl_wait (struct xl_softc ); 249static void xl_mediacheck (struct xl_softc ); 250static void xl_choose_xcvr (struct xl_softc , int); 251static void xl_dma_map_addr (void , bus_dma_segment_t , int, int); 252static void xl_dma_map_txbuf (void , bus_dma_segment_t , int, bus_size_t, 253* int); 254#ifdef notdef 255static void xl_testpacket (struct xl_softc ); 256#endif 257* 258static int xl_miibus_readreg (device_t, int, int); 259static int xl_miibus_writereg (device_t, int, int, int); 260static void xl_miibus_statchg (device_t); 261static void xl_miibus_mediainit (device_t); 262 263static device_method_t xl_methods[] = { 264 /* Device interface / 265* DEVMETHOD(device_probe, xl_probe), 266 DEVMETHOD(device_attach, xl_attach), 267 DEVMETHOD(device_detach, xl_detach), 268 DEVMETHOD(device_shutdown, xl_shutdown), 269 DEVMETHOD(device_suspend, xl_suspend), 270 DEVMETHOD(device_resume, xl_resume), 271 272 /* bus interface / 273* DEVMETHOD(bus_print_child, bus_generic_print_child), 274 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 275 276 /* MII interface / 277* DEVMETHOD(miibus_readreg, xl_miibus_readreg), 278 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 279 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 280 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 281 282 { 0, 0 } 283}; 284 285static driver_t xl_driver = { 286 "xl", 287 xl_methods, 288 sizeof(struct xl_softc) 289}; 290 291static devclass_t xl_devclass; 292 293DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0); 294DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0); 295DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 296 297static void 298xl_dma_map_addr(arg, segs, nseg, error) 299 void arg; 300* bus_dma_segment_t segs; 301* int nseg, error; 302{ 303 u_int32_t paddr; 304* 305 paddr = arg; 306 paddr = segs->ds_addr; 307} 308* 309static void 310xl_dma_map_txbuf(arg, segs, nseg, mapsize, error) 311 void arg; 312* bus_dma_segment_t segs; 313* int nseg; 314 bus_size_t mapsize; 315 int error; 316{ 317 struct xl_list l; 318* int i, total_len; 319 320 if (error) 321 return; 322 323 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments")); 324 325 total_len = 0; 326 l = arg; 327 for (i = 0; i < nseg; i++) { 328 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 329 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 330 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 331 total_len += segs[i].ds_len; 332 } 333 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len \| 334 XL_LAST_FRAG); 335 l->xl_status = htole32(total_len); 336 l->xl_next = 0; 337} 338 339/* 340 * Murphy's law says that it's possible the chip can wedge and 341 * the 'command in progress' bit may never clear. Hence, we wait 342 * only a finite amount of time to avoid getting caught in an 343 * infinite loop. Normally this delay routine would be a macro, 344 * but it isn't called during normal operation so we can afford 345 * to make it a function. 346 / 347static void 348xl_wait(sc) 349* struct xl_softc sc; 350{ 351* register int i; 352 353 for (i = 0; i < XL_TIMEOUT; i++) { 354 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 355 break; 356 } 357 358 if (i == XL_TIMEOUT) 359 printf("xl%d: command never completed!\n", sc->xl_unit); 360 361 return; 362} 363 364/* 365 * MII access routines are provided for adapters with external 366 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 367 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 368 * Note: if you don't perform the MDIO operations just right, 369 * it's possible to end up with code that works correctly with 370 * some chips/CPUs/processor speeds/bus speeds/etc but not 371 * with others. 372 / 373#define MII_SET(x) \ 374* CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 375 CSR_READ_2(sc, XL_W4_PHY_MGMT) \| (x)) 376 377#define MII_CLR(x) \ 378 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 379 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 380 381/* 382 * Sync the PHYs by setting data bit and strobing the clock 32 times. 383 / 384static void 385xl_mii_sync(sc) 386* struct xl_softc sc; 387{ 388* register int i; 389 390 XL_SEL_WIN(4); 391 MII_SET(XL_MII_DIR\|XL_MII_DATA); 392 393 for (i = 0; i < 32; i++) { 394 MII_SET(XL_MII_CLK); 395 MII_SET(XL_MII_DATA); 396 MII_CLR(XL_MII_CLK); 397 MII_SET(XL_MII_DATA); 398 } 399 400 return; 401} 402 403/* 404 * Clock a series of bits through the MII. 405 / 406static void 407xl_mii_send(sc, bits, cnt) 408* struct xl_softc sc; 409* u_int32_t bits; 410 int cnt; 411{ 412 int i; 413 414 XL_SEL_WIN(4); 415 MII_CLR(XL_MII_CLK); 416 417 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 418 if (bits & i) { 419 MII_SET(XL_MII_DATA); 420 } else { 421 MII_CLR(XL_MII_DATA); 422 } 423 MII_CLR(XL_MII_CLK); 424 MII_SET(XL_MII_CLK); 425 } 426} 427 428/* 429 * Read an PHY register through the MII. 430 / 431static int 432xl_mii_readreg(sc, frame) 433* struct xl_softc sc; 434* struct xl_mii_frame frame; 435* 436{ 437 int i, ack; 438 439 XL_LOCK(sc); 440 441 /* 442 * Set up frame for RX. 443 / 444* frame->mii_stdelim = XL_MII_STARTDELIM; 445 frame->mii_opcode = XL_MII_READOP; 446 frame->mii_turnaround = 0; 447 frame->mii_data = 0; 448 449 /* 450 * Select register window 4. 451 / 452* 453 XL_SEL_WIN(4); 454 455 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 456 /* 457 * Turn on data xmit. 458 / 459* MII_SET(XL_MII_DIR); 460 461 xl_mii_sync(sc); 462 463 /* 464 * Send command/address info. 465 / 466* xl_mii_send(sc, frame->mii_stdelim, 2); 467 xl_mii_send(sc, frame->mii_opcode, 2); 468 xl_mii_send(sc, frame->mii_phyaddr, 5); 469 xl_mii_send(sc, frame->mii_regaddr, 5); 470 471 /* Idle bit / 472* MII_CLR((XL_MII_CLK\|XL_MII_DATA)); 473 MII_SET(XL_MII_CLK); 474 475 /* Turn off xmit. / 476* MII_CLR(XL_MII_DIR); 477 478 /* Check for ack / 479* MII_CLR(XL_MII_CLK); 480 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 481 MII_SET(XL_MII_CLK); 482 483 /* 484 * Now try reading data bits. If the ack failed, we still 485 * need to clock through 16 cycles to keep the PHY(s) in sync. 486 / 487* if (ack) { 488 for(i = 0; i < 16; i++) { 489 MII_CLR(XL_MII_CLK); 490 MII_SET(XL_MII_CLK); 491 } 492 goto fail; 493 } 494 495 for (i = 0x8000; i; i >>= 1) { 496 MII_CLR(XL_MII_CLK); 497 if (!ack) { 498 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 499 frame->mii_data \|= i; 500 } 501 MII_SET(XL_MII_CLK); 502 } 503 504fail: 505 506 MII_CLR(XL_MII_CLK); 507 MII_SET(XL_MII_CLK); 508 509 XL_UNLOCK(sc); 510 511 if (ack) 512 return(1); 513 return(0); 514} 515 516/* 517 * Write to a PHY register through the MII. 518 / 519static int 520xl_mii_writereg(sc, frame) 521* struct xl_softc sc; 522* struct xl_mii_frame frame; 523* 524{ 525 XL_LOCK(sc); 526 527 /* 528 * Set up frame for TX. 529 / 530* 531 frame->mii_stdelim = XL_MII_STARTDELIM; 532 frame->mii_opcode = XL_MII_WRITEOP; 533 frame->mii_turnaround = XL_MII_TURNAROUND; 534 535 /* 536 * Select the window 4. 537 / 538* XL_SEL_WIN(4); 539 540 /* 541 * Turn on data output. 542 / 543* MII_SET(XL_MII_DIR); 544 545 xl_mii_sync(sc); 546 547 xl_mii_send(sc, frame->mii_stdelim, 2); 548 xl_mii_send(sc, frame->mii_opcode, 2); 549 xl_mii_send(sc, frame->mii_phyaddr, 5); 550 xl_mii_send(sc, frame->mii_regaddr, 5); 551 xl_mii_send(sc, frame->mii_turnaround, 2); 552 xl_mii_send(sc, frame->mii_data, 16); 553 554 /* Idle bit. / 555* MII_SET(XL_MII_CLK); 556 MII_CLR(XL_MII_CLK); 557 558 /* 559 * Turn off xmit. 560 / 561* MII_CLR(XL_MII_DIR); 562 563 XL_UNLOCK(sc); 564 565 return(0); 566} 567 568static int 569xl_miibus_readreg(dev, phy, reg) 570 device_t dev; 571 int phy, reg; 572{ 573 struct xl_softc sc; 574* struct xl_mii_frame frame; 575 576 sc = device_get_softc(dev); 577 578 /* 579 * Pretend that PHYs are only available at MII address 24. 580 * This is to guard against problems with certain 3Com ASIC 581 * revisions that incorrectly map the internal transceiver 582 * control registers at all MII addresses. This can cause 583 * the miibus code to attach the same PHY several times over. 584 / 585* if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 586 return(0); 587 588 bzero((char )&frame, sizeof(frame)); 589* 590 frame.mii_phyaddr = phy; 591 frame.mii_regaddr = reg; 592 xl_mii_readreg(sc, &frame); 593 594 return(frame.mii_data); 595} 596 597static int 598xl_miibus_writereg(dev, phy, reg, data) 599 device_t dev; 600 int phy, reg, data; 601{ 602 struct xl_softc sc; 603* struct xl_mii_frame frame; 604 605 sc = device_get_softc(dev); 606 607 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 608 return(0); 609 610 bzero((char )&frame, sizeof(frame)); 611* 612 frame.mii_phyaddr = phy; 613 frame.mii_regaddr = reg; 614 frame.mii_data = data; 615 616 xl_mii_writereg(sc, &frame); 617 618 return(0); 619} 620 621static void 622xl_miibus_statchg(dev) 623 device_t dev; 624{ 625 struct xl_softc sc; 626* struct mii_data mii; 627* 628 629 sc = device_get_softc(dev); 630 mii = device_get_softc(sc->xl_miibus); 631 632 XL_LOCK(sc); 633 634 xl_setcfg(sc); 635 636 /* Set ASIC's duplex mode to match the PHY. / 637* XL_SEL_WIN(3); 638 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 639 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 640 else 641 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 642 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 643 644 XL_UNLOCK(sc); 645 646 return; 647} 648 649/* 650 * Special support for the 3c905B-COMBO. This card has 10/100 support 651 * plus BNC and AUI ports. This means we will have both an miibus attached 652 * plus some non-MII media settings. In order to allow this, we have to 653 * add the extra media to the miibus's ifmedia struct, but we can't do 654 * that during xl_attach() because the miibus hasn't been attached yet. 655 * So instead, we wait until the miibus probe/attach is done, at which 656 * point we will get a callback telling is that it's safe to add our 657 * extra media. 658 / 659static void 660xl_miibus_mediainit(dev) 661* device_t dev; 662{ 663 struct xl_softc sc; 664* struct mii_data mii; 665* struct ifmedia ifm; 666* 667 sc = device_get_softc(dev); 668 mii = device_get_softc(sc->xl_miibus); 669 ifm = &mii->mii_media; 670 671 XL_LOCK(sc); 672 673 if (sc->xl_media & (XL_MEDIAOPT_AUI\|XL_MEDIAOPT_10FL)) { 674 /* 675 * Check for a 10baseFL board in disguise. 676 / 677* if (sc->xl_type == XL_TYPE_905B && 678 sc->xl_media == XL_MEDIAOPT_10FL) { 679 if (bootverbose) 680 printf("xl%d: found 10baseFL\n", sc->xl_unit); 681 ifmedia_add(ifm, IFM_ETHER\|IFM_10_FL, 0, NULL); 682 ifmedia_add(ifm, IFM_ETHER\|IFM_10_FL\|IFM_HDX, 0, NULL); 683 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 684 ifmedia_add(ifm, 685 IFM_ETHER\|IFM_10_FL\|IFM_FDX, 0, NULL); 686 } else { 687 if (bootverbose) 688 printf("xl%d: found AUI\n", sc->xl_unit); 689 ifmedia_add(ifm, IFM_ETHER\|IFM_10_5, 0, NULL); 690 } 691 } 692 693 if (sc->xl_media & XL_MEDIAOPT_BNC) { 694 if (bootverbose) 695 printf("xl%d: found BNC\n", sc->xl_unit); 696 ifmedia_add(ifm, IFM_ETHER\|IFM_10_2, 0, NULL); 697 } 698 699 XL_UNLOCK(sc); 700 701 return; 702} 703 704/* 705 * The EEPROM is slow: give it time to come ready after issuing 706 * it a command. 707 / 708static int 709xl_eeprom_wait(sc) 710* struct xl_softc sc; 711{ 712* int i; 713 714 for (i = 0; i < 100; i++) { 715 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 716 DELAY(162); 717 else 718 break; 719 } 720 721 if (i == 100) { 722 printf("xl%d: eeprom failed to come ready\n", sc->xl_unit); 723 return(1); 724 } 725 726 return(0); 727} 728 729/* 730 * Read a sequence of words from the EEPROM. Note that ethernet address 731 * data is stored in the EEPROM in network byte order. 732 / 733static int 734xl_read_eeprom(sc, dest, off, cnt, swap) 735* struct xl_softc sc; 736* caddr_t dest; 737 int off; 738 int cnt; 739 int swap; 740{ 741 int err = 0, i; 742 u_int16_t word = 0, ptr; 743#define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) \| ((A) & 0x003F)) 744#define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 745* /* WARNING! DANGER! 746 * It's easy to accidentally overwrite the rom content! 747 * Note: the 3c575 uses 8bit EEPROM offsets. 748 / 749* XL_SEL_WIN(0); 750 751 if (xl_eeprom_wait(sc)) 752 return(1); 753 754 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 755 off += 0x30; 756 757 for (i = 0; i < cnt; i++) { 758 if (sc->xl_flags & XL_FLAG_8BITROM) 759 CSR_WRITE_2(sc, XL_W0_EE_CMD, 760 XL_EE_8BIT_READ \| EEPROM_8BIT_OFFSET(off + i)); 761 else 762 CSR_WRITE_2(sc, XL_W0_EE_CMD, 763 XL_EE_READ \| EEPROM_5BIT_OFFSET(off + i)); 764 err = xl_eeprom_wait(sc); 765 if (err) 766 break; 767 word = CSR_READ_2(sc, XL_W0_EE_DATA); 768 ptr = (u_int16_t )(dest + (i 2)); 769 if (swap) 770 ptr = ntohs(word); 771* else 772 ptr = word; 773* } 774 775 return(err ? 1 : 0); 776} 777 778/* 779 * This routine is taken from the 3Com Etherlink XL manual, 780 * page 10-7. It calculates a CRC of the supplied multicast 781 * group address and returns the lower 8 bits, which are used 782 * as the multicast filter position. 783 * Note: the 3c905B currently only supports a 64-bit hash table, 784 * which means we really only need 6 bits, but the manual indicates 785 * that future chip revisions will have a 256-bit hash table, 786 * hence the routine is set up to calculate 8 bits of position 787 * info in case we need it some day. 788 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a 789 * 256 bit hash table. This means we have to use all 8 bits regardless. 790 * On older cards, the upper 2 bits will be ignored. Grrrr.... 791 / 792static u_int8_t xl_calchash(addr) 793* caddr_t addr; 794{ 795 u_int32_t crc, carry; 796 int i, j; 797 u_int8_t c; 798 799 /* Compute CRC for the address value. / 800* crc = 0xFFFFFFFF; /* initial value / 801* 802 for (i = 0; i < 6; i++) { 803 c = (addr + i); 804* for (j = 0; j < 8; j++) { 805 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 806 crc <<= 1; 807 c >>= 1; 808 if (carry) 809 crc = (crc ^ 0x04c11db6) \| carry; 810 } 811 } 812 813 /* return the filter bit position / 814* return(crc & 0x000000FF); 815} 816 817/* 818 * NICs older than the 3c905B have only one multicast option, which 819 * is to enable reception of all multicast frames. 820 / 821static void 822xl_setmulti(sc) 823* struct xl_softc sc; 824{ 825* struct ifnet ifp; 826* struct ifmultiaddr ifma; 827* u_int8_t rxfilt; 828 int mcnt = 0; 829 830 ifp = &sc->arpcom.ac_if; 831 832 XL_SEL_WIN(5); 833 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 834 835 if (ifp->if_flags & IFF_ALLMULTI) { 836 rxfilt \|= XL_RXFILTER_ALLMULTI; 837 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT\|rxfilt); 838 return; 839 } 840 841 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 842 mcnt++; 843 844 if (mcnt) 845 rxfilt \|= XL_RXFILTER_ALLMULTI; 846 else 847 rxfilt &= ~XL_RXFILTER_ALLMULTI; 848 849 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT\|rxfilt); 850 851 return; 852} 853 854/* 855 * 3c905B adapters have a hash filter that we can program. 856 / 857static void 858xl_setmulti_hash(sc) 859* struct xl_softc sc; 860{ 861* struct ifnet ifp; 862* int h = 0, i; 863 struct ifmultiaddr ifma; 864* u_int8_t rxfilt; 865 int mcnt = 0; 866 867 ifp = &sc->arpcom.ac_if; 868 869 XL_SEL_WIN(5); 870 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 871 872 if (ifp->if_flags & IFF_ALLMULTI) { 873 rxfilt \|= XL_RXFILTER_ALLMULTI; 874 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT\|rxfilt); 875 return; 876 } else 877 rxfilt &= ~XL_RXFILTER_ALLMULTI; 878 879 880 /* first, zot all the existing hash bits / 881* for (i = 0; i < XL_HASHFILT_SIZE; i++) 882 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH\|i); 883 884 /* now program new ones / 885* TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 886 if (ifma->ifma_addr->sa_family != AF_LINK) 887 continue; 888 h = xl_calchash(LLADDR((struct sockaddr_dl )ifma->ifma_addr)); 889* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH\|XL_HASH_SET\|h); 890 mcnt++; 891 } 892 893 if (mcnt) 894 rxfilt \|= XL_RXFILTER_MULTIHASH; 895 else 896 rxfilt &= ~XL_RXFILTER_MULTIHASH; 897 898 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT\|rxfilt); 899 900 return; 901} 902 903#ifdef notdef 904static void 905xl_testpacket(sc) 906 struct xl_softc sc; 907{ 908* struct mbuf m; 909* struct ifnet ifp; 910* 911 ifp = &sc->arpcom.ac_if; 912 913 MGETHDR(m, M_DONTWAIT, MT_DATA); 914 915 if (m == NULL) 916 return; 917 918 bcopy(&sc->arpcom.ac_enaddr, 919 mtod(m, struct ether_header )->ether_dhost, ETHER_ADDR_LEN); 920* bcopy(&sc->arpcom.ac_enaddr, 921 mtod(m, struct ether_header )->ether_shost, ETHER_ADDR_LEN); 922* mtod(m, struct ether_header )->ether_type = htons(3); 923* mtod(m, unsigned char )[14] = 0; 924* mtod(m, unsigned char )[15] = 0; 925* mtod(m, unsigned char )[16] = 0xE3; 926* m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 927 IF_ENQUEUE(&ifp->if_snd, m); 928 xl_start(ifp); 929 930 return; 931} 932#endif 933 934static void 935xl_setcfg(sc) 936 struct xl_softc sc; 937{ 938* u_int32_t icfg; 939 940 XL_SEL_WIN(3); 941 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 942 icfg &= ~XL_ICFG_CONNECTOR_MASK; 943 if (sc->xl_media & XL_MEDIAOPT_MII \|\| 944 sc->xl_media & XL_MEDIAOPT_BT4) 945 icfg \|= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 946 if (sc->xl_media & XL_MEDIAOPT_BTX) 947 icfg \|= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 948 949 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 950 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 951 952 return; 953} 954 955static void 956xl_setmode(sc, media) 957 struct xl_softc sc; 958* int media; 959{ 960 u_int32_t icfg; 961 u_int16_t mediastat; 962 963 printf("xl%d: selecting ", sc->xl_unit); 964 965 XL_SEL_WIN(4); 966 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 967 XL_SEL_WIN(3); 968 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 969 970 if (sc->xl_media & XL_MEDIAOPT_BT) { 971 if (IFM_SUBTYPE(media) == IFM_10_T) { 972 printf("10baseT transceiver, "); 973 sc->xl_xcvr = XL_XCVR_10BT; 974 icfg &= ~XL_ICFG_CONNECTOR_MASK; 975 icfg \|= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 976 mediastat \|= XL_MEDIASTAT_LINKBEAT\| 977 XL_MEDIASTAT_JABGUARD; 978 mediastat &= ~XL_MEDIASTAT_SQEENB; 979 } 980 } 981 982 if (sc->xl_media & XL_MEDIAOPT_BFX) { 983 if (IFM_SUBTYPE(media) == IFM_100_FX) { 984 printf("100baseFX port, "); 985 sc->xl_xcvr = XL_XCVR_100BFX; 986 icfg &= ~XL_ICFG_CONNECTOR_MASK; 987 icfg \|= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 988 mediastat \|= XL_MEDIASTAT_LINKBEAT; 989 mediastat &= ~XL_MEDIASTAT_SQEENB; 990 } 991 } 992 993 if (sc->xl_media & (XL_MEDIAOPT_AUI\|XL_MEDIAOPT_10FL)) { 994 if (IFM_SUBTYPE(media) == IFM_10_5) { 995 printf("AUI port, "); 996 sc->xl_xcvr = XL_XCVR_AUI; 997 icfg &= ~XL_ICFG_CONNECTOR_MASK; 998 icfg \|= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 999 mediastat &= ~(XL_MEDIASTAT_LINKBEAT\| 1000 XL_MEDIASTAT_JABGUARD); 1001 mediastat \|= ~XL_MEDIASTAT_SQEENB; 1002 } 1003 if (IFM_SUBTYPE(media) == IFM_10_FL) { 1004 printf("10baseFL transceiver, "); 1005 sc->xl_xcvr = XL_XCVR_AUI; 1006 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1007 icfg \|= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 1008 mediastat &= ~(XL_MEDIASTAT_LINKBEAT\| 1009 XL_MEDIASTAT_JABGUARD); 1010 mediastat \|= ~XL_MEDIASTAT_SQEENB; 1011 } 1012 } 1013 1014 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1015 if (IFM_SUBTYPE(media) == IFM_10_2) { 1016 printf("BNC port, "); 1017 sc->xl_xcvr = XL_XCVR_COAX; 1018 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1019 icfg \|= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 1020 mediastat &= ~(XL_MEDIASTAT_LINKBEAT\| 1021 XL_MEDIASTAT_JABGUARD\| 1022 XL_MEDIASTAT_SQEENB); 1023 } 1024 } 1025 1026 if ((media & IFM_GMASK) == IFM_FDX \|\| 1027 IFM_SUBTYPE(media) == IFM_100_FX) { 1028 printf("full duplex\n"); 1029 XL_SEL_WIN(3); 1030 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 1031 } else { 1032 printf("half duplex\n"); 1033 XL_SEL_WIN(3); 1034 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 1035 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 1036 } 1037 1038 if (IFM_SUBTYPE(media) == IFM_10_2) 1039 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 1040 else 1041 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 1042 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 1043 XL_SEL_WIN(4); 1044 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 1045 DELAY(800); 1046 XL_SEL_WIN(7); 1047 1048 return; 1049} 1050 1051static void 1052xl_reset(sc) 1053 struct xl_softc sc; 1054{ 1055* register int i; 1056 1057 XL_SEL_WIN(0); 1058 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET \| 1059 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1060 XL_RESETOPT_DISADVFD:0)); 1061 1062 for (i = 0; i < XL_TIMEOUT; i++) { 1063 DELAY(10); 1064 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1065 break; 1066 } 1067 1068 if (i == XL_TIMEOUT) 1069 printf("xl%d: reset didn't complete\n", sc->xl_unit); 1070 1071 /* Reset TX and RX. / 1072* /* Note: the RX reset takes an absurd amount of time 1073 * on newer versions of the Tornado chips such as those 1074 * on the 3c905CX and newer 3c908C cards. We wait an 1075 * extra amount of time so that xl_wait() doesn't complain 1076 * and annoy the users. 1077 / 1078* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1079 DELAY(100000); 1080 xl_wait(sc); 1081 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1082 xl_wait(sc); 1083 1084 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR \|\| 1085 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1086 XL_SEL_WIN(2); 1087 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1088 XL_W2_RESET_OPTIONS) 1089 \| ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1090 \| ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1091 ); 1092 } 1093 1094 /* Wait a little while for the chip to get its brains in order. / 1095* DELAY(100000); 1096 return; 1097} 1098 1099/* 1100 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1101 * IDs against our list and return a device name if we find a match. 1102 / 1103static int 1104xl_probe(dev) 1105* device_t dev; 1106{ 1107 struct xl_type t; 1108* 1109 t = xl_devs; 1110 1111 while(t->xl_name != NULL) { 1112 if ((pci_get_vendor(dev) == t->xl_vid) && 1113 (pci_get_device(dev) == t->xl_did)) { 1114 device_set_desc(dev, t->xl_name); 1115 return(0); 1116 } 1117 t++; 1118 } 1119 1120 return(ENXIO); 1121} 1122 1123/* 1124 * This routine is a kludge to work around possible hardware faults 1125 * or manufacturing defects that can cause the media options register 1126 * (or reset options register, as it's called for the first generation 1127 * 3c90x adapters) to return an incorrect result. I have encountered 1128 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1129 * which doesn't have any of the 'mediaopt' bits set. This screws up 1130 * the attach routine pretty badly because it doesn't know what media 1131 * to look for. If we find ourselves in this predicament, this routine 1132 * will try to guess the media options values and warn the user of a 1133 * possible manufacturing defect with his adapter/system/whatever. 1134 / 1135static void 1136xl_mediacheck(sc) 1137* struct xl_softc sc; 1138{ 1139* 1140 /* 1141 * If some of the media options bits are set, assume they are 1142 * correct. If not, try to figure it out down below. 1143 * XXX I should check for 10baseFL, but I don't have an adapter 1144 * to test with. 1145 / 1146* if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1147 /* 1148 * Check the XCVR value. If it's not in the normal range 1149 * of values, we need to fake it up here. 1150 / 1151* if (sc->xl_xcvr <= XL_XCVR_AUTO) 1152 return; 1153 else { 1154 printf("xl%d: bogus xcvr value " 1155 "in EEPROM (%x)\n", sc->xl_unit, sc->xl_xcvr); 1156 printf("xl%d: choosing new default based " 1157 "on card type\n", sc->xl_unit); 1158 } 1159 } else { 1160 if (sc->xl_type == XL_TYPE_905B && 1161 sc->xl_media & XL_MEDIAOPT_10FL) 1162 return; 1163 printf("xl%d: WARNING: no media options bits set in " 1164 "the media options register!!\n", sc->xl_unit); 1165 printf("xl%d: this could be a manufacturing defect in " 1166 "your adapter or system\n", sc->xl_unit); 1167 printf("xl%d: attempting to guess media type; you " 1168 "should probably consult your vendor\n", sc->xl_unit); 1169 } 1170 1171 xl_choose_xcvr(sc, 1); 1172 1173 return; 1174} 1175 1176static void 1177xl_choose_xcvr(sc, verbose) 1178 struct xl_softc sc; 1179* int verbose; 1180{ 1181 u_int16_t devid; 1182 1183 /* 1184 * Read the device ID from the EEPROM. 1185 * This is what's loaded into the PCI device ID register, so it has 1186 * to be correct otherwise we wouldn't have gotten this far. 1187 / 1188* xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1189 1190 switch(devid) { 1191 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO / 1192* case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO / 1193* sc->xl_media = XL_MEDIAOPT_BT; 1194 sc->xl_xcvr = XL_XCVR_10BT; 1195 if (verbose) 1196 printf("xl%d: guessing 10BaseT " 1197 "transceiver\n", sc->xl_unit); 1198 break; 1199 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO / 1200* case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO / 1201* sc->xl_media = XL_MEDIAOPT_BT\|XL_MEDIAOPT_BNC\|XL_MEDIAOPT_AUI; 1202 sc->xl_xcvr = XL_XCVR_10BT; 1203 if (verbose) 1204 printf("xl%d: guessing COMBO " 1205 "(AUI/BNC/TP)\n", sc->xl_unit); 1206 break; 1207 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC / 1208* sc->xl_media = XL_MEDIAOPT_BT\|XL_MEDIAOPT_BNC; 1209 sc->xl_xcvr = XL_XCVR_10BT; 1210 if (verbose) 1211 printf("xl%d: guessing TPC (BNC/TP)\n", sc->xl_unit); 1212 break; 1213 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL / 1214* sc->xl_media = XL_MEDIAOPT_10FL; 1215 sc->xl_xcvr = XL_XCVR_AUI; 1216 if (verbose) 1217 printf("xl%d: guessing 10baseFL\n", sc->xl_unit); 1218 break; 1219 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX / 1220* case TC_DEVICEID_HURRICANE_555: /* 3c555 / 1221* case TC_DEVICEID_HURRICANE_556: /* 3c556 / 1222* case TC_DEVICEID_HURRICANE_556B: /* 3c556B / 1223* case TC_DEVICEID_HURRICANE_575A: /* 3c575TX / 1224* case TC_DEVICEID_HURRICANE_575B: /* 3c575B / 1225* case TC_DEVICEID_HURRICANE_575C: /* 3c575C / 1226* case TC_DEVICEID_HURRICANE_656: /* 3c656 / 1227* case TC_DEVICEID_HURRICANE_656B: /* 3c656B / 1228* case TC_DEVICEID_TORNADO_656C: /* 3c656C / 1229* case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB / 1230* sc->xl_media = XL_MEDIAOPT_MII; 1231 sc->xl_xcvr = XL_XCVR_MII; 1232 if (verbose) 1233 printf("xl%d: guessing MII\n", sc->xl_unit); 1234 break; 1235 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 / 1236* case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 / 1237* sc->xl_media = XL_MEDIAOPT_BT4; 1238 sc->xl_xcvr = XL_XCVR_MII; 1239 if (verbose) 1240 printf("xl%d: guessing 100BaseT4/MII\n", sc->xl_unit); 1241 break; 1242 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX / 1243* case TC_DEVICEID_HURRICANE_10_100BT_SERV:/3c980-TX / 1244 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX / 1245* case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX / 1246* case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX / 1247* case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX / 1248* sc->xl_media = XL_MEDIAOPT_BTX; 1249 sc->xl_xcvr = XL_XCVR_AUTO; 1250 if (verbose) 1251 printf("xl%d: guessing 10/100 internal\n", sc->xl_unit); 1252 break; 1253 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO / 1254* sc->xl_media = XL_MEDIAOPT_BTX\|XL_MEDIAOPT_BNC\|XL_MEDIAOPT_AUI; 1255 sc->xl_xcvr = XL_XCVR_AUTO; 1256 if (verbose) 1257 printf("xl%d: guessing 10/100 " 1258 "plus BNC/AUI\n", sc->xl_unit); 1259 break; 1260 default: 1261 printf("xl%d: unknown device ID: %x -- " 1262 "defaulting to 10baseT\n", sc->xl_unit, devid); 1263 sc->xl_media = XL_MEDIAOPT_BT; 1264 break; 1265 } 1266 1267 return; 1268} 1269 1270/* 1271 * Attach the interface. Allocate softc structures, do ifmedia 1272 * setup and ethernet/BPF attach. 1273 / 1274static int 1275xl_attach(dev) 1276* device_t dev; 1277{ 1278 u_char eaddr[ETHER_ADDR_LEN]; 1279 u_int32_t command; 1280 u_int16_t xcvr[2]; 1281 struct xl_softc sc; 1282* struct ifnet ifp; 1283* int media = IFM_ETHER\|IFM_100_TX\|IFM_FDX; 1284 int unit, error = 0, rid, res; 1285 1286 sc = device_get_softc(dev); 1287 unit = device_get_unit(dev); 1288 1289 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1290 MTX_DEF \| MTX_RECURSE); 1291 1292 sc->xl_flags = 0; 1293 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555) 1294 sc->xl_flags \|= XL_FLAG_EEPROM_OFFSET_30 \| XL_FLAG_PHYOK; 1295 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 \|\| 1296 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1297 sc->xl_flags \|= XL_FLAG_FUNCREG \| XL_FLAG_PHYOK \| 1298 XL_FLAG_EEPROM_OFFSET_30 \| XL_FLAG_WEIRDRESET \| 1299 XL_FLAG_INVERT_LED_PWR \| XL_FLAG_INVERT_MII_PWR; 1300 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 \|\| 1301 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556) 1302 sc->xl_flags \|= XL_FLAG_8BITROM; 1303 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1304 sc->xl_flags \|= XL_FLAG_NO_XCVR_PWR; 1305 1306 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A \|\| 1307 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B \|\| 1308 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C \|\| 1309 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B \|\| 1310 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1311 sc->xl_flags \|= XL_FLAG_FUNCREG \| XL_FLAG_PHYOK \| 1312 XL_FLAG_EEPROM_OFFSET_30 \| XL_FLAG_8BITROM; 1313 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656) 1314 sc->xl_flags \|= XL_FLAG_FUNCREG \| XL_FLAG_PHYOK; 1315 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B) 1316 sc->xl_flags \|= XL_FLAG_INVERT_LED_PWR; 1317 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C) 1318 sc->xl_flags \|= XL_FLAG_INVERT_MII_PWR; 1319 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1320 sc->xl_flags \|= XL_FLAG_INVERT_MII_PWR; 1321 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 \|\| 1322 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B) 1323 sc->xl_flags \|= XL_FLAG_INVERT_MII_PWR \| 1324 XL_FLAG_INVERT_LED_PWR; 1325 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B) 1326 sc->xl_flags \|= XL_FLAG_PHYOK; 1327 1328 /* 1329 * If this is a 3c905B, we have to check one extra thing. 1330 * The 905B supports power management and may be placed in 1331 * a low-power mode (D3 mode), typically by certain operating 1332 * systems which shall not be named. The PCI BIOS is supposed 1333 * to reset the NIC and bring it out of low-power mode, but 1334 * some do not. Consequently, we have to see if this chip 1335 * supports power management, and if so, make sure it's not 1336 * in low-power mode. If power management is available, the 1337 * capid byte will be 0x01. 1338 * 1339 * I _think_ that what actually happens is that the chip 1340 * loses its PCI configuration during the transition from 1341 * D3 back to D0; this means that it should be possible for 1342 * us to save the PCI iobase, membase and IRQ, put the chip 1343 * back in the D0 state, then restore the PCI config ourselves. 1344 / 1345* 1346 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1347 u_int32_t iobase, membase, irq; 1348 1349 /* Save important PCI config data. / 1350* iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1351 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1352 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1353 1354 /* Reset the power state. / 1355* printf("xl%d: chip is in D%d power mode " 1356 "-- setting to D0\n", unit, 1357 pci_get_powerstate(dev)); 1358 1359 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1360 1361 /* Restore PCI config data. / 1362* pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1363 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1364 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1365 } 1366 1367 /* 1368 * Map control/status registers. 1369 / 1370* pci_enable_busmaster(dev); 1371 pci_enable_io(dev, SYS_RES_IOPORT); 1372 pci_enable_io(dev, SYS_RES_MEMORY); 1373 command = pci_read_config(dev, PCIR_COMMAND, 4); 1374 1375 if (!(command & PCIM_CMD_PORTEN) && !(command & PCIM_CMD_MEMEN)) { 1376 printf("xl%d: failed to enable I/O ports and memory mappings!\n", unit); 1377 error = ENXIO; 1378 goto fail; 1379 } 1380 1381 rid = XL_PCI_LOMEM; 1382 res = SYS_RES_MEMORY; 1383 1384 sc->xl_res = bus_alloc_resource(dev, res, &rid, 1385 0, ~0, 1, RF_ACTIVE); 1386 1387 if (sc->xl_res != NULL) { 1388 sc->xl_flags \|= XL_FLAG_USE_MMIO; 1389 if (bootverbose) 1390 printf("xl%d: using memory mapped I/O\n", unit); 1391 } else { 1392 rid = XL_PCI_LOIO; 1393 res = SYS_RES_IOPORT; 1394 sc->xl_res = bus_alloc_resource(dev, res, &rid, 1395 0, ~0, 1, RF_ACTIVE); 1396 if (sc->xl_res == NULL) { 1397 printf ("xl%d: couldn't map ports/memory\n", unit); 1398 error = ENXIO; 1399 goto fail; 1400 } 1401 if (bootverbose) 1402 printf("xl%d: using port I/O\n", unit); 1403 } 1404 1405 sc->xl_btag = rman_get_bustag(sc->xl_res); 1406 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1407 1408 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1409 rid = XL_PCI_FUNCMEM; 1410 sc->xl_fres = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1411 0, ~0, 1, RF_ACTIVE); 1412 1413 if (sc->xl_fres == NULL) { 1414 printf ("xl%d: couldn't map ports/memory\n", unit); 1415 error = ENXIO; 1416 goto fail; 1417 } 1418 1419 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1420 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1421 } 1422 1423 /* Allocate interrupt / 1424* rid = 0; 1425 sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1426 RF_SHAREABLE \| RF_ACTIVE); 1427 if (sc->xl_irq == NULL) { 1428 printf("xl%d: couldn't map interrupt\n", unit); 1429 error = ENXIO; 1430 goto fail; 1431 } 1432 1433 /* Reset the adapter. / 1434* xl_reset(sc); 1435 1436 /* 1437 * Get station address from the EEPROM. 1438 / 1439* if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1440 printf("xl%d: failed to read station address\n", sc->xl_unit); 1441 error = ENXIO; 1442 goto fail; 1443 } 1444 1445 /* 1446 * A 3Com chip was detected. Inform the world. 1447 / 1448* printf("xl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1449 1450 sc->xl_unit = unit; 1451 callout_handle_init(&sc->xl_stat_ch); 1452 bcopy(eaddr, (char )&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1453* 1454 /* 1455 * Now allocate a tag for the DMA descriptor lists and a chunk 1456 * of DMA-able memory based on the tag. Also obtain the DMA 1457 * addresses of the RX and TX ring, which we'll need later. 1458 * All of our lists are allocated as a contiguous block 1459 * of memory. 1460 / 1461* error = bus_dma_tag_create(NULL, 8, 0, 1462 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1463 XL_RX_LIST_SZ, 1, BUS_SPACE_MAXSIZE_32BIT, 0, 1464 &sc->xl_ldata.xl_rx_tag); 1465 if (error) { 1466 printf("xl%d: failed to allocate rx dma tag\n", unit); 1467 goto fail; 1468 } 1469 1470 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1471 (void *)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT, 1472* &sc->xl_ldata.xl_rx_dmamap); 1473 if (error) { 1474 printf("xl%d: no memory for rx list buffers!\n", unit); 1475 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1476 sc->xl_ldata.xl_rx_tag = NULL; 1477 goto fail; 1478 } 1479 1480 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1481 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1482 XL_RX_LIST_SZ, xl_dma_map_addr, 1483 &sc->xl_ldata.xl_rx_dmaaddr, 0); 1484 if (error) { 1485 printf("xl%d: cannot get dma address of the rx ring!\n", unit); 1486 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1487 sc->xl_ldata.xl_rx_dmamap); 1488 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1489 sc->xl_ldata.xl_rx_tag = NULL; 1490 goto fail; 1491 } 1492 1493 error = bus_dma_tag_create(NULL, 8, 0, 1494 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1495 XL_TX_LIST_SZ, 1, BUS_SPACE_MAXSIZE_32BIT, 0, 1496 &sc->xl_ldata.xl_tx_tag); 1497 if (error) { 1498 printf("xl%d: failed to allocate tx dma tag\n", unit); 1499 goto fail; 1500 } 1501 1502 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1503 (void *)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT, 1504* &sc->xl_ldata.xl_tx_dmamap); 1505 if (error) { 1506 printf("xl%d: no memory for list buffers!\n", unit); 1507 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1508 sc->xl_ldata.xl_tx_tag = NULL; 1509 goto fail; 1510 } 1511 1512 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1513 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1514 XL_TX_LIST_SZ, xl_dma_map_addr, 1515 &sc->xl_ldata.xl_tx_dmaaddr, 0); 1516 if (error) { 1517 printf("xl%d: cannot get dma address of the tx ring!\n", unit); 1518 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1519 sc->xl_ldata.xl_tx_dmamap); 1520 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1521 sc->xl_ldata.xl_tx_tag = NULL; 1522 goto fail; 1523 } 1524 1525 /* 1526 * Allocate a DMA tag for the mapping of mbufs. 1527 / 1528* error = bus_dma_tag_create(NULL, 1, 0, 1529 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1530 XL_MAXFRAGS, BUS_SPACE_MAXSIZE_32BIT, 0, &sc->xl_mtag); 1531 if (error) { 1532 printf("xl%d: failed to allocate mbuf dma tag\n", unit); 1533 goto fail; 1534 } 1535 1536 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 1537 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 1538 1539 /* We need a spare DMA map for the RX ring. / 1540* error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1541 if (error) 1542 goto fail; 1543 1544 /* 1545 * Figure out the card type. 3c905B adapters have the 1546 * 'supportsNoTxLength' bit set in the capabilities 1547 * word in the EEPROM. 1548 / 1549* xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1550 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH) 1551 sc->xl_type = XL_TYPE_905B; 1552 else 1553 sc->xl_type = XL_TYPE_90X; 1554 1555 ifp = &sc->arpcom.ac_if; 1556 ifp->if_softc = sc; 1557 ifp->if_unit = unit; 1558 ifp->if_name = "xl"; 1559 ifp->if_mtu = ETHERMTU; 1560 ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX \| IFF_MULTICAST; 1561 ifp->if_ioctl = xl_ioctl; 1562 ifp->if_output = ether_output; 1563 if (sc->xl_type == XL_TYPE_905B) { 1564 ifp->if_start = xl_start_90xB; 1565 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1566 ifp->if_capabilities = IFCAP_HWCSUM; 1567 } else 1568 ifp->if_start = xl_start; 1569 ifp->if_watchdog = xl_watchdog; 1570 ifp->if_init = xl_init; 1571 ifp->if_baudrate = 10000000; 1572 ifp->if_snd.ifq_maxlen = XL_TX_LIST_CNT - 1; 1573 ifp->if_capenable = ifp->if_capabilities; 1574 1575 /* 1576 * Now we have to see what sort of media we have. 1577 * This includes probing for an MII interace and a 1578 * possible PHY. 1579 / 1580* XL_SEL_WIN(3); 1581 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1582 if (bootverbose) 1583 printf("xl%d: media options word: %x\n", sc->xl_unit, 1584 sc->xl_media); 1585 1586 xl_read_eeprom(sc, (char )&xcvr, XL_EE_ICFG_0, 2, 0); 1587* sc->xl_xcvr = xcvr[0] \| xcvr[1] << 16; 1588 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1589 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1590 1591 xl_mediacheck(sc); 1592 1593 if (sc->xl_media & XL_MEDIAOPT_MII \|\| sc->xl_media & XL_MEDIAOPT_BTX 1594 \|\| sc->xl_media & XL_MEDIAOPT_BT4) { 1595 if (bootverbose) 1596 printf("xl%d: found MII/AUTO\n", sc->xl_unit); 1597 xl_setcfg(sc); 1598 if (mii_phy_probe(dev, &sc->xl_miibus, 1599 xl_ifmedia_upd, xl_ifmedia_sts)) { 1600 printf("xl%d: no PHY found!\n", sc->xl_unit); 1601 error = ENXIO; 1602 goto fail; 1603 } 1604 1605 goto done; 1606 } 1607 1608 /* 1609 * Sanity check. If the user has selected "auto" and this isn't 1610 * a 10/100 card of some kind, we need to force the transceiver 1611 * type to something sane. 1612 / 1613* if (sc->xl_xcvr == XL_XCVR_AUTO) 1614 xl_choose_xcvr(sc, bootverbose); 1615 1616 /* 1617 * Do ifmedia setup. 1618 / 1619* 1620 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1621 1622 if (sc->xl_media & XL_MEDIAOPT_BT) { 1623 if (bootverbose) 1624 printf("xl%d: found 10baseT\n", sc->xl_unit); 1625 ifmedia_add(&sc->ifmedia, IFM_ETHER\|IFM_10_T, 0, NULL); 1626 ifmedia_add(&sc->ifmedia, IFM_ETHER\|IFM_10_T\|IFM_HDX, 0, NULL); 1627 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1628 ifmedia_add(&sc->ifmedia, 1629 IFM_ETHER\|IFM_10_T\|IFM_FDX, 0, NULL); 1630 } 1631 1632 if (sc->xl_media & (XL_MEDIAOPT_AUI\|XL_MEDIAOPT_10FL)) { 1633 /* 1634 * Check for a 10baseFL board in disguise. 1635 / 1636* if (sc->xl_type == XL_TYPE_905B && 1637 sc->xl_media == XL_MEDIAOPT_10FL) { 1638 if (bootverbose) 1639 printf("xl%d: found 10baseFL\n", sc->xl_unit); 1640 ifmedia_add(&sc->ifmedia, IFM_ETHER\|IFM_10_FL, 0, NULL); 1641 ifmedia_add(&sc->ifmedia, IFM_ETHER\|IFM_10_FL\|IFM_HDX, 1642 0, NULL); 1643 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1644 ifmedia_add(&sc->ifmedia, 1645 IFM_ETHER\|IFM_10_FL\|IFM_FDX, 0, NULL); 1646 } else { 1647 if (bootverbose) 1648 printf("xl%d: found AUI\n", sc->xl_unit); 1649 ifmedia_add(&sc->ifmedia, IFM_ETHER\|IFM_10_5, 0, NULL); 1650 } 1651 } 1652 1653 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1654 if (bootverbose) 1655 printf("xl%d: found BNC\n", sc->xl_unit); 1656 ifmedia_add(&sc->ifmedia, IFM_ETHER\|IFM_10_2, 0, NULL); 1657 } 1658 1659 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1660 if (bootverbose) 1661 printf("xl%d: found 100baseFX\n", sc->xl_unit); 1662 ifp->if_baudrate = 100000000; 1663 ifmedia_add(&sc->ifmedia, IFM_ETHER\|IFM_100_FX, 0, NULL); 1664 } 1665 1666 /* Choose a default media. / 1667* switch(sc->xl_xcvr) { 1668 case XL_XCVR_10BT: 1669 media = IFM_ETHER\|IFM_10_T; 1670 xl_setmode(sc, media); 1671 break; 1672 case XL_XCVR_AUI: 1673 if (sc->xl_type == XL_TYPE_905B && 1674 sc->xl_media == XL_MEDIAOPT_10FL) { 1675 media = IFM_ETHER\|IFM_10_FL; 1676 xl_setmode(sc, media); 1677 } else { 1678 media = IFM_ETHER\|IFM_10_5; 1679 xl_setmode(sc, media); 1680 } 1681 break; 1682 case XL_XCVR_COAX: 1683 media = IFM_ETHER\|IFM_10_2; 1684 xl_setmode(sc, media); 1685 break; 1686 case XL_XCVR_AUTO: 1687 case XL_XCVR_100BTX: 1688 case XL_XCVR_MII: 1689 /* Chosen by miibus / 1690* break; 1691 case XL_XCVR_100BFX: 1692 media = IFM_ETHER\|IFM_100_FX; 1693 break; 1694 default: 1695 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, 1696 sc->xl_xcvr); 1697 /* 1698 * This will probably be wrong, but it prevents 1699 * the ifmedia code from panicking. 1700 / 1701* media = IFM_ETHER\|IFM_10_T; 1702 break; 1703 } 1704 1705 if (sc->xl_miibus == NULL) 1706 ifmedia_set(&sc->ifmedia, media); 1707 1708done: 1709 1710 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1711 XL_SEL_WIN(0); 1712 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1713 } 1714 1715 /* 1716 * Call MI attach routine. 1717 / 1718* ether_ifattach(ifp, eaddr); 1719 1720 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET, 1721 xl_intr, sc, &sc->xl_intrhand); 1722 if (error) { 1723 printf("xl%d: couldn't set up irq\n", unit); 1724 goto fail; 1725 } 1726 1727fail: 1728 if (error) 1729 xl_detach(dev); 1730 1731 return(error); 1732} 1733 1734static int 1735xl_detach(dev) 1736 device_t dev; 1737{ 1738 struct xl_softc sc; 1739* struct ifnet ifp; 1740* int rid, res; 1741 1742 sc = device_get_softc(dev);
1743 KASSERT(mtx_initialized(&sc->xl_mtx), "xl mutex not initialized");	1743 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1744 XL_LOCK(sc); 1745 ifp = &sc->arpcom.ac_if; 1746 1747 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1748 rid = XL_PCI_LOMEM; 1749 res = SYS_RES_MEMORY; 1750 } else { 1751 rid = XL_PCI_LOIO; 1752 res = SYS_RES_IOPORT; 1753 } 1754 1755 if (device_is_alive(dev)) { 1756 if (bus_child_present(dev)) { 1757 xl_reset(sc); 1758 xl_stop(sc); 1759 } 1760 ether_ifdetach(ifp); 1761 device_delete_child(dev, sc->xl_miibus); 1762 bus_generic_detach(dev); 1763 ifmedia_removeall(&sc->ifmedia); 1764 } 1765 1766 if (sc->xl_intrhand) 1767 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1768 if (sc->xl_irq) 1769 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1770 if (sc->xl_fres != NULL) 1771 bus_release_resource(dev, SYS_RES_MEMORY, 1772 XL_PCI_FUNCMEM, sc->xl_fres); 1773 if (sc->xl_res) 1774 bus_release_resource(dev, res, rid, sc->xl_res); 1775 1776 if (sc->xl_mtag) { 1777 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1778 bus_dma_tag_destroy(sc->xl_mtag); 1779 } 1780 if (sc->xl_ldata.xl_rx_tag) { 1781 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1782 sc->xl_ldata.xl_rx_dmamap); 1783 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1784 sc->xl_ldata.xl_rx_dmamap); 1785 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1786 } 1787 if (sc->xl_ldata.xl_tx_tag) { 1788 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1789 sc->xl_ldata.xl_tx_dmamap); 1790 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1791 sc->xl_ldata.xl_tx_dmamap); 1792 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1793 } 1794 1795 XL_UNLOCK(sc); 1796 mtx_destroy(&sc->xl_mtx); 1797 1798 return(0); 1799} 1800 1801/* 1802 * Initialize the transmit descriptors. 1803 / 1804static int 1805xl_list_tx_init(sc) 1806* struct xl_softc sc; 1807{ 1808* struct xl_chain_data cd; 1809* struct xl_list_data ld; 1810* int error, i; 1811 1812 cd = &sc->xl_cdata; 1813 ld = &sc->xl_ldata; 1814 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1815 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1816 error = bus_dmamap_create(sc->xl_mtag, 0, 1817 &cd->xl_tx_chain[i].xl_map); 1818 if (error) 1819 return(error); 1820 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1821 i * sizeof(struct xl_list); 1822 if (i == (XL_TX_LIST_CNT - 1)) 1823 cd->xl_tx_chain[i].xl_next = NULL; 1824 else 1825 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1826 } 1827 1828 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1829 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1830 1831 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1832 return(0); 1833} 1834 1835/* 1836 * Initialize the transmit descriptors. 1837 / 1838static int 1839xl_list_tx_init_90xB(sc) 1840* struct xl_softc sc; 1841{ 1842* struct xl_chain_data cd; 1843* struct xl_list_data ld; 1844* int error, i; 1845 1846 cd = &sc->xl_cdata; 1847 ld = &sc->xl_ldata; 1848 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1849 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1850 error = bus_dmamap_create(sc->xl_mtag, 0, 1851 &cd->xl_tx_chain[i].xl_map); 1852 if (error) 1853 return(error); 1854 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1855 i * sizeof(struct xl_list); 1856 if (i == (XL_TX_LIST_CNT - 1)) 1857 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1858 else 1859 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1860 if (i == 0) 1861 cd->xl_tx_chain[i].xl_prev = 1862 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1863 else 1864 cd->xl_tx_chain[i].xl_prev = 1865 &cd->xl_tx_chain[i - 1]; 1866 } 1867 1868 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1869 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1870 1871 cd->xl_tx_prod = 1; 1872 cd->xl_tx_cons = 1; 1873 cd->xl_tx_cnt = 0; 1874 1875 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1876 return(0); 1877} 1878 1879/* 1880 * Initialize the RX descriptors and allocate mbufs for them. Note that 1881 * we arrange the descriptors in a closed ring, so that the last descriptor 1882 * points back to the first. 1883 / 1884static int 1885xl_list_rx_init(sc) 1886* struct xl_softc sc; 1887{ 1888* struct xl_chain_data cd; 1889* struct xl_list_data ld; 1890* int error, i, next; 1891 u_int32_t nextptr; 1892 1893 cd = &sc->xl_cdata; 1894 ld = &sc->xl_ldata; 1895 1896 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1897 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1898 error = bus_dmamap_create(sc->xl_mtag, 0, 1899 &cd->xl_rx_chain[i].xl_map); 1900 if (error) 1901 return(error); 1902 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1903 if (error) 1904 return(error); 1905 if (i == (XL_RX_LIST_CNT - 1)) 1906 next = 0; 1907 else 1908 next = i + 1; 1909 nextptr = ld->xl_rx_dmaaddr + 1910 next * sizeof(struct xl_list_onefrag); 1911 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1912 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1913 } 1914 1915 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1916 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1917 1918 return(0); 1919} 1920 1921/* 1922 * Initialize an RX descriptor and attach an MBUF cluster. 1923 * If we fail to do so, we need to leave the old mbuf and 1924 * the old DMA map untouched so that it can be reused. 1925 / 1926static int 1927xl_newbuf(sc, c) 1928* struct xl_softc sc; 1929* struct xl_chain_onefrag c; 1930{ 1931* struct mbuf m_new = NULL; 1932* bus_dmamap_t map; 1933 int error; 1934 u_int32_t baddr; 1935 1936 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1937 if (m_new == NULL) 1938 return(ENOBUFS); 1939 1940 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1941 1942 /* Force longword alignment for packet payload. / 1943* m_adj(m_new, ETHER_ALIGN); 1944 1945 error = bus_dmamap_load(sc->xl_mtag, sc->xl_tmpmap, mtod(m_new, void ), 1946* MCLBYTES, xl_dma_map_addr, &baddr, 0); 1947 if (error) { 1948 m_freem(m_new); 1949 printf("xl%d: can't map mbuf (error %d)\n", sc->xl_unit, error); 1950 return(error); 1951 } 1952 1953 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1954 map = c->xl_map; 1955 c->xl_map = sc->xl_tmpmap; 1956 sc->xl_tmpmap = map; 1957 c->xl_mbuf = m_new; 1958 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len \| XL_LAST_FRAG); 1959 c->xl_ptr->xl_status = 0; 1960 c->xl_ptr->xl_frag.xl_addr = htole32(baddr); 1961 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1962 return(0); 1963} 1964 1965static int 1966xl_rx_resync(sc) 1967 struct xl_softc sc; 1968{ 1969* struct xl_chain_onefrag pos; 1970* int i; 1971 1972 pos = sc->xl_cdata.xl_rx_head; 1973 1974 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1975 if (pos->xl_ptr->xl_status) 1976 break; 1977 pos = pos->xl_next; 1978 } 1979 1980 if (i == XL_RX_LIST_CNT) 1981 return(0); 1982 1983 sc->xl_cdata.xl_rx_head = pos; 1984 1985 return(EAGAIN); 1986} 1987 1988/* 1989 * A frame has been uploaded: pass the resulting mbuf chain up to 1990 * the higher level protocols. 1991 / 1992static void 1993xl_rxeof(sc) 1994* struct xl_softc sc; 1995{ 1996* struct mbuf m; 1997* struct ifnet ifp; 1998* struct xl_chain_onefrag cur_rx; 1999* int total_len = 0; 2000 u_int32_t rxstat; 2001 2002 ifp = &sc->arpcom.ac_if; 2003 2004again: 2005 2006 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 2007 BUS_DMASYNC_POSTREAD); 2008 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 2009 cur_rx = sc->xl_cdata.xl_rx_head; 2010 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 2011 2012 /* 2013 * If an error occurs, update stats, clear the 2014 * status word and leave the mbuf cluster in place: 2015 * it should simply get re-used next time this descriptor 2016 * comes up in the ring. 2017 / 2018* if (rxstat & XL_RXSTAT_UP_ERROR) { 2019 ifp->if_ierrors++; 2020 cur_rx->xl_ptr->xl_status = 0; 2021 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2022 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2023 continue; 2024 } 2025 2026 /* 2027 * If there error bit was not set, the upload complete 2028 * bit should be set which means we have a valid packet. 2029 * If not, something truly strange has happened. 2030 / 2031* if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2032 printf("xl%d: bad receive status -- " 2033 "packet dropped\n", sc->xl_unit); 2034 ifp->if_ierrors++; 2035 cur_rx->xl_ptr->xl_status = 0; 2036 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2037 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2038 continue; 2039 } 2040 2041 /* No errors; receive the packet. / 2042* bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 2043 BUS_DMASYNC_POSTREAD); 2044 m = cur_rx->xl_mbuf; 2045 total_len = le32toh(cur_rx->xl_ptr->xl_status) & 2046 XL_RXSTAT_LENMASK; 2047 2048 /* 2049 * Try to conjure up a new mbuf cluster. If that 2050 * fails, it means we have an out of memory condition and 2051 * should leave the buffer in place and continue. This will 2052 * result in a lost packet, but there's little else we 2053 * can do in this situation. 2054 / 2055* if (xl_newbuf(sc, cur_rx)) { 2056 ifp->if_ierrors++; 2057 cur_rx->xl_ptr->xl_status = 0; 2058 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2059 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2060 continue; 2061 } 2062 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2063 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2064 2065 ifp->if_ipackets++; 2066 m->m_pkthdr.rcvif = ifp; 2067 m->m_pkthdr.len = m->m_len = total_len; 2068 2069 if (sc->xl_type == XL_TYPE_905B) { 2070 /* Do IP checksum checking. / 2071* if (rxstat & XL_RXSTAT_IPCKOK) 2072 m->m_pkthdr.csum_flags \|= CSUM_IP_CHECKED; 2073 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2074 m->m_pkthdr.csum_flags \|= CSUM_IP_VALID; 2075 if ((rxstat & XL_RXSTAT_TCPCOK && 2076 !(rxstat & XL_RXSTAT_TCPCKERR)) \|\| 2077 (rxstat & XL_RXSTAT_UDPCKOK && 2078 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2079 m->m_pkthdr.csum_flags \|= 2080 CSUM_DATA_VALID\|CSUM_PSEUDO_HDR; 2081 m->m_pkthdr.csum_data = 0xffff; 2082 } 2083 } 2084 2085 (ifp->if_input)(ifp, m); 2086* } 2087 2088 /* 2089 * Handle the 'end of channel' condition. When the upload 2090 * engine hits the end of the RX ring, it will stall. This 2091 * is our cue to flush the RX ring, reload the uplist pointer 2092 * register and unstall the engine. 2093 * XXX This is actually a little goofy. With the ThunderLAN 2094 * chip, you get an interrupt when the receiver hits the end 2095 * of the receive ring, which tells you exactly when you 2096 * you need to reload the ring pointer. Here we have to 2097 * fake it. I'm mad at myself for not being clever enough 2098 * to avoid the use of a goto here. 2099 / 2100* if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 \|\| 2101 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2102 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2103 xl_wait(sc); 2104 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2105 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2106 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2107 goto again; 2108 } 2109 2110 return; 2111} 2112 2113/* 2114 * A frame was downloaded to the chip. It's safe for us to clean up 2115 * the list buffers. 2116 / 2117static void 2118xl_txeof(sc) 2119* struct xl_softc sc; 2120{ 2121* struct xl_chain cur_tx; 2122* struct ifnet ifp; 2123* 2124 ifp = &sc->arpcom.ac_if; 2125 2126 /* Clear the timeout timer. / 2127* ifp->if_timer = 0; 2128 2129 /* 2130 * Go through our tx list and free mbufs for those 2131 * frames that have been uploaded. Note: the 3c905B 2132 * sets a special bit in the status word to let us 2133 * know that a frame has been downloaded, but the 2134 * original 3c900/3c905 adapters don't do that. 2135 * Consequently, we have to use a different test if 2136 * xl_type != XL_TYPE_905B. 2137 / 2138* while(sc->xl_cdata.xl_tx_head != NULL) { 2139 cur_tx = sc->xl_cdata.xl_tx_head; 2140 2141 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2142 break; 2143 2144 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2145 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2146 BUS_DMASYNC_POSTWRITE); 2147 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2148 m_freem(cur_tx->xl_mbuf); 2149 cur_tx->xl_mbuf = NULL; 2150 ifp->if_opackets++; 2151 2152 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2153 sc->xl_cdata.xl_tx_free = cur_tx; 2154 } 2155 2156 if (sc->xl_cdata.xl_tx_head == NULL) { 2157 ifp->if_flags &= ~IFF_OACTIVE; 2158 sc->xl_cdata.xl_tx_tail = NULL; 2159 } else { 2160 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED \|\| 2161 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2162 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2163 sc->xl_cdata.xl_tx_head->xl_phys); 2164 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2165 } 2166 } 2167 2168 return; 2169} 2170 2171static void 2172xl_txeof_90xB(sc) 2173 struct xl_softc sc; 2174{ 2175* struct xl_chain cur_tx = NULL; 2176* struct ifnet ifp; 2177* int idx; 2178 2179 ifp = &sc->arpcom.ac_if; 2180 2181 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2182 BUS_DMASYNC_POSTREAD); 2183 idx = sc->xl_cdata.xl_tx_cons; 2184 while(idx != sc->xl_cdata.xl_tx_prod) { 2185 2186 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2187 2188 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2189 XL_TXSTAT_DL_COMPLETE)) 2190 break; 2191 2192 if (cur_tx->xl_mbuf != NULL) { 2193 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2194 BUS_DMASYNC_POSTWRITE); 2195 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2196 m_freem(cur_tx->xl_mbuf); 2197 cur_tx->xl_mbuf = NULL; 2198 } 2199 2200 ifp->if_opackets++; 2201 2202 sc->xl_cdata.xl_tx_cnt--; 2203 XL_INC(idx, XL_TX_LIST_CNT); 2204 ifp->if_timer = 0; 2205 } 2206 2207 sc->xl_cdata.xl_tx_cons = idx; 2208 2209 if (cur_tx != NULL) 2210 ifp->if_flags &= ~IFF_OACTIVE; 2211 2212 return; 2213} 2214 2215/* 2216 * TX 'end of channel' interrupt handler. Actually, we should 2217 * only get a 'TX complete' interrupt if there's a transmit error, 2218 * so this is really TX error handler. 2219 / 2220static void 2221xl_txeoc(sc) 2222* struct xl_softc sc; 2223{ 2224* u_int8_t txstat; 2225 2226 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2227 if (txstat & XL_TXSTATUS_UNDERRUN \|\| 2228 txstat & XL_TXSTATUS_JABBER \|\| 2229 txstat & XL_TXSTATUS_RECLAIM) { 2230 printf("xl%d: transmission error: %x\n", 2231 sc->xl_unit, txstat); 2232 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2233 xl_wait(sc); 2234 if (sc->xl_type == XL_TYPE_905B) { 2235 if (sc->xl_cdata.xl_tx_cnt) { 2236 int i; 2237 struct xl_chain c; 2238* i = sc->xl_cdata.xl_tx_cons; 2239 c = &sc->xl_cdata.xl_tx_chain[i]; 2240 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2241 c->xl_phys); 2242 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2243 } 2244 } else { 2245 if (sc->xl_cdata.xl_tx_head != NULL) 2246 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2247 sc->xl_cdata.xl_tx_head->xl_phys); 2248 } 2249 /* 2250 * Remember to set this for the 2251 * first generation 3c90X chips. 2252 / 2253* CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2254 if (txstat & XL_TXSTATUS_UNDERRUN && 2255 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2256 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2257 printf("xl%d: tx underrun, increasing tx start" 2258 " threshold to %d bytes\n", sc->xl_unit, 2259 sc->xl_tx_thresh); 2260 } 2261 CSR_WRITE_2(sc, XL_COMMAND, 2262 XL_CMD_TX_SET_START\|sc->xl_tx_thresh); 2263 if (sc->xl_type == XL_TYPE_905B) { 2264 CSR_WRITE_2(sc, XL_COMMAND, 2265 XL_CMD_SET_TX_RECLAIM\|(XL_PACKET_SIZE >> 4)); 2266 } 2267 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2268 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2269 } else { 2270 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2271 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2272 } 2273 /* 2274 * Write an arbitrary byte to the TX_STATUS register 2275 * to clear this interrupt/error and advance to the next. 2276 / 2277* CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2278 } 2279 2280 return; 2281} 2282 2283static void 2284xl_intr(arg) 2285 void arg; 2286{ 2287* struct xl_softc sc; 2288* struct ifnet ifp; 2289* u_int16_t status; 2290 2291 sc = arg; 2292 XL_LOCK(sc); 2293 ifp = &sc->arpcom.ac_if; 2294 2295 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) { 2296 2297 CSR_WRITE_2(sc, XL_COMMAND, 2298 XL_CMD_INTR_ACK\|(status & XL_INTRS)); 2299 2300 if (status & XL_STAT_UP_COMPLETE) { 2301 int curpkts; 2302 2303 curpkts = ifp->if_ipackets; 2304 xl_rxeof(sc); 2305 if (curpkts == ifp->if_ipackets) { 2306 while (xl_rx_resync(sc)) 2307 xl_rxeof(sc); 2308 } 2309 } 2310 2311 if (status & XL_STAT_DOWN_COMPLETE) { 2312 if (sc->xl_type == XL_TYPE_905B) 2313 xl_txeof_90xB(sc); 2314 else 2315 xl_txeof(sc); 2316 } 2317 2318 if (status & XL_STAT_TX_COMPLETE) { 2319 ifp->if_oerrors++; 2320 xl_txeoc(sc); 2321 } 2322 2323 if (status & XL_STAT_ADFAIL) { 2324 xl_reset(sc); 2325 xl_init(sc); 2326 } 2327 2328 if (status & XL_STAT_STATSOFLOW) { 2329 sc->xl_stats_no_timeout = 1; 2330 xl_stats_update(sc); 2331 sc->xl_stats_no_timeout = 0; 2332 } 2333 } 2334 2335 if (ifp->if_snd.ifq_head != NULL) 2336 (ifp->if_start)(ifp); 2337* 2338 XL_UNLOCK(sc); 2339 2340 return; 2341} 2342 2343static void 2344xl_stats_update(xsc) 2345 void xsc; 2346{ 2347* struct xl_softc sc; 2348* struct ifnet ifp; 2349* struct xl_stats xl_stats; 2350 u_int8_t p; 2351* int i; 2352 struct mii_data mii = NULL; 2353* 2354 bzero((char )&xl_stats, sizeof(struct xl_stats)); 2355* 2356 sc = xsc; 2357 ifp = &sc->arpcom.ac_if; 2358 if (sc->xl_miibus != NULL) 2359 mii = device_get_softc(sc->xl_miibus); 2360 2361 p = (u_int8_t )&xl_stats; 2362* 2363 /* Read all the stats registers. / 2364* XL_SEL_WIN(6); 2365 2366 for (i = 0; i < 16; i++) 2367 p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2368* 2369 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2370 2371 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2372 xl_stats.xl_tx_single_collision + 2373 xl_stats.xl_tx_late_collision; 2374 2375 /* 2376 * Boomerang and cyclone chips have an extra stats counter 2377 * in window 4 (BadSSD). We have to read this too in order 2378 * to clear out all the stats registers and avoid a statsoflow 2379 * interrupt. 2380 / 2381* XL_SEL_WIN(4); 2382 CSR_READ_1(sc, XL_W4_BADSSD); 2383 2384 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2385 mii_tick(mii); 2386 2387 XL_SEL_WIN(7); 2388 2389 if (!sc->xl_stats_no_timeout) 2390 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz); 2391 2392 return; 2393} 2394 2395/* 2396 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2397 * pointers to the fragment pointers. 2398 / 2399static int 2400xl_encap(sc, c, m_head) 2401* struct xl_softc sc; 2402* struct xl_chain c; 2403* struct mbuf m_head; 2404{ 2405* int error; 2406 u_int32_t status; 2407 2408 /* 2409 * Start packing the mbufs in this chain into 2410 * the fragment pointers. Stop when we run out 2411 * of fragments or hit the end of the mbuf chain. 2412 / 2413* error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head, 2414 xl_dma_map_txbuf, c->xl_ptr, 0); 2415 2416 if (error && error != EFBIG) { 2417 m_freem(m_head); 2418 printf("xl%d: can't map mbuf (error %d)\n", sc->xl_unit, error); 2419 return(1); 2420 } 2421 2422 /* 2423 * Handle special case: we used up all 63 fragments, 2424 * but we have more mbufs left in the chain. Copy the 2425 * data into an mbuf cluster. Note that we don't 2426 * bother clearing the values in the other fragment 2427 * pointers/counters; it wouldn't gain us anything, 2428 * and would waste cycles. 2429 / 2430* if (error) { 2431 struct mbuf m_new; 2432* 2433 m_new = m_defrag(m_head, M_DONTWAIT); 2434 if (m_new == NULL) { 2435 m_freem(m_head); 2436 printf("xl%d: no memory for tx list\n", sc->xl_unit); 2437 return(1); 2438 } else { 2439 m_head = m_new; 2440 } 2441 2442 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, 2443 m_head, xl_dma_map_txbuf, c->xl_ptr, 0); 2444 if (error) { 2445 m_freem(m_head); 2446 printf("xl%d: can't map mbuf (error %d)\n", 2447 sc->xl_unit, error); 2448 return(1); 2449 } 2450 } 2451 2452 if (sc->xl_type == XL_TYPE_905B) { 2453 status = XL_TXSTAT_RND_DEFEAT; 2454 2455 if (m_head->m_pkthdr.csum_flags) { 2456 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2457 status \|= XL_TXSTAT_IPCKSUM; 2458 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2459 status \|= XL_TXSTAT_TCPCKSUM; 2460 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2461 status \|= XL_TXSTAT_UDPCKSUM; 2462 } 2463 c->xl_ptr->xl_status = htole32(status); 2464 } 2465 2466 c->xl_mbuf = m_head; 2467 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2468 return(0); 2469} 2470 2471/* 2472 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2473 * to the mbuf data regions directly in the transmit lists. We also save a 2474 * copy of the pointers since the transmit list fragment pointers are 2475 * physical addresses. 2476 / 2477static void 2478xl_start(ifp) 2479* struct ifnet ifp; 2480{ 2481* struct xl_softc sc; 2482* struct mbuf m_head = NULL; 2483* struct xl_chain prev = NULL, cur_tx = NULL, start_tx; 2484* u_int32_t status; 2485 int error; 2486 2487 sc = ifp->if_softc; 2488 XL_LOCK(sc); 2489 /* 2490 * Check for an available queue slot. If there are none, 2491 * punt. 2492 / 2493* if (sc->xl_cdata.xl_tx_free == NULL) { 2494 xl_txeoc(sc); 2495 xl_txeof(sc); 2496 if (sc->xl_cdata.xl_tx_free == NULL) { 2497 ifp->if_flags \|= IFF_OACTIVE; 2498 XL_UNLOCK(sc); 2499 return; 2500 } 2501 } 2502 2503 start_tx = sc->xl_cdata.xl_tx_free; 2504 2505 while(sc->xl_cdata.xl_tx_free != NULL) { 2506 IF_DEQUEUE(&ifp->if_snd, m_head); 2507 if (m_head == NULL) 2508 break; 2509 2510 /* Pick a descriptor off the free list. / 2511* cur_tx = sc->xl_cdata.xl_tx_free; 2512 2513 /* Pack the data into the descriptor. / 2514* error = xl_encap(sc, cur_tx, m_head); 2515 if (error) 2516 continue; 2517 2518 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2519 cur_tx->xl_next = NULL; 2520 2521 /* Chain it together. / 2522* if (prev != NULL) { 2523 prev->xl_next = cur_tx; 2524 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2525 } 2526 prev = cur_tx; 2527 2528 /* 2529 * If there's a BPF listener, bounce a copy of this frame 2530 * to him. 2531 / 2532* BPF_MTAP(ifp, cur_tx->xl_mbuf); 2533 } 2534 2535 /* 2536 * If there are no packets queued, bail. 2537 / 2538* if (cur_tx == NULL) { 2539 XL_UNLOCK(sc); 2540 return; 2541 } 2542 2543 /* 2544 * Place the request for the upload interrupt 2545 * in the last descriptor in the chain. This way, if 2546 * we're chaining several packets at once, we'll only 2547 * get an interupt once for the whole chain rather than 2548 * once for each packet. 2549 / 2550* cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) \| 2551 XL_TXSTAT_DL_INTR); 2552 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2553 BUS_DMASYNC_PREWRITE); 2554 2555 /* 2556 * Queue the packets. If the TX channel is clear, update 2557 * the downlist pointer register. 2558 / 2559* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2560 xl_wait(sc); 2561 2562 if (sc->xl_cdata.xl_tx_head != NULL) { 2563 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2564 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2565 htole32(start_tx->xl_phys); 2566 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2567 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2568 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2569 sc->xl_cdata.xl_tx_tail = cur_tx; 2570 } else { 2571 sc->xl_cdata.xl_tx_head = start_tx; 2572 sc->xl_cdata.xl_tx_tail = cur_tx; 2573 } 2574 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2575 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2576 2577 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2578 2579 XL_SEL_WIN(7); 2580 2581 /* 2582 * Set a timeout in case the chip goes out to lunch. 2583 / 2584* ifp->if_timer = 5; 2585 2586 /* 2587 * XXX Under certain conditions, usually on slower machines 2588 * where interrupts may be dropped, it's possible for the 2589 * adapter to chew up all the buffers in the receive ring 2590 * and stall, without us being able to do anything about it. 2591 * To guard against this, we need to make a pass over the 2592 * RX queue to make sure there aren't any packets pending. 2593 * Doing it here means we can flush the receive ring at the 2594 * same time the chip is DMAing the transmit descriptors we 2595 * just gave it. 2596 * 2597 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2598 * nature of their chips in all their marketing literature; 2599 * we may as well take advantage of it. :) 2600 / 2601* xl_rxeof(sc); 2602 2603 XL_UNLOCK(sc); 2604 2605 return; 2606} 2607 2608static void 2609xl_start_90xB(ifp) 2610 struct ifnet ifp; 2611{ 2612* struct xl_softc sc; 2613* struct mbuf m_head = NULL; 2614* struct xl_chain prev = NULL, cur_tx = NULL, start_tx; 2615* int error, idx; 2616 2617 sc = ifp->if_softc; 2618 XL_LOCK(sc); 2619 2620 if (ifp->if_flags & IFF_OACTIVE) { 2621 XL_UNLOCK(sc); 2622 return; 2623 } 2624 2625 idx = sc->xl_cdata.xl_tx_prod; 2626 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2627 2628 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2629 2630 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2631 ifp->if_flags \|= IFF_OACTIVE; 2632 break; 2633 } 2634 2635 IF_DEQUEUE(&ifp->if_snd, m_head); 2636 if (m_head == NULL) 2637 break; 2638 2639 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2640 2641 /* Pack the data into the descriptor. / 2642* error = xl_encap(sc, cur_tx, m_head); 2643 if (error) 2644 continue; 2645 2646 /* Chain it together. / 2647* if (prev != NULL) 2648 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2649 prev = cur_tx; 2650 2651 /* 2652 * If there's a BPF listener, bounce a copy of this frame 2653 * to him. 2654 / 2655* BPF_MTAP(ifp, cur_tx->xl_mbuf); 2656 2657 XL_INC(idx, XL_TX_LIST_CNT); 2658 sc->xl_cdata.xl_tx_cnt++; 2659 } 2660 2661 /* 2662 * If there are no packets queued, bail. 2663 / 2664* if (cur_tx == NULL) { 2665 XL_UNLOCK(sc); 2666 return; 2667 } 2668 2669 /* 2670 * Place the request for the upload interrupt 2671 * in the last descriptor in the chain. This way, if 2672 * we're chaining several packets at once, we'll only 2673 * get an interupt once for the whole chain rather than 2674 * once for each packet. 2675 / 2676* cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) \| 2677 XL_TXSTAT_DL_INTR); 2678 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2679 BUS_DMASYNC_PREWRITE); 2680 2681 /* Start transmission / 2682* sc->xl_cdata.xl_tx_prod = idx; 2683 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2684 2685 /* 2686 * Set a timeout in case the chip goes out to lunch. 2687 / 2688* ifp->if_timer = 5; 2689 2690 XL_UNLOCK(sc); 2691 2692 return; 2693} 2694 2695static void 2696xl_init(xsc) 2697 void xsc; 2698{ 2699* struct xl_softc sc = xsc; 2700* struct ifnet ifp = &sc->arpcom.ac_if; 2701* int error, i; 2702 u_int16_t rxfilt = 0; 2703 struct mii_data mii = NULL; 2704* 2705 XL_LOCK(sc); 2706 2707 /* 2708 * Cancel pending I/O and free all RX/TX buffers. 2709 / 2710* xl_stop(sc); 2711 2712 if (sc->xl_miibus == NULL) { 2713 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2714 xl_wait(sc); 2715 } 2716 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2717 xl_wait(sc); 2718 DELAY(10000); 2719 2720 if (sc->xl_miibus != NULL) 2721 mii = device_get_softc(sc->xl_miibus); 2722 2723 /* Init our MAC address / 2724* XL_SEL_WIN(2); 2725 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2726 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2727 sc->arpcom.ac_enaddr[i]); 2728 } 2729 2730 /* Clear the station mask. / 2731* for (i = 0; i < 3; i++) 2732 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2733#ifdef notdef 2734 /* Reset TX and RX. / 2735* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2736 xl_wait(sc); 2737 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2738 xl_wait(sc); 2739#endif 2740 /* Init circular RX list. / 2741* error = xl_list_rx_init(sc); 2742 if (error) { 2743 printf("xl%d: initialization of the rx ring failed (%d)\n", 2744 sc->xl_unit, error); 2745 xl_stop(sc); 2746 XL_UNLOCK(sc); 2747 return; 2748 } 2749 2750 /* Init TX descriptors. / 2751* if (sc->xl_type == XL_TYPE_905B) 2752 error = xl_list_tx_init_90xB(sc); 2753 else 2754 error = xl_list_tx_init(sc); 2755 if (error) { 2756 printf("xl%d: initialization of the tx ring failed (%d)\n", 2757 sc->xl_unit, error); 2758 xl_stop(sc); 2759 XL_UNLOCK(sc); 2760 } 2761 2762 /* 2763 * Set the TX freethresh value. 2764 * Note that this has no effect on 3c905B "cyclone" 2765 * cards but is required for 3c900/3c905 "boomerang" 2766 * cards in order to enable the download engine. 2767 / 2768* CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2769 2770 /* Set the TX start threshold for best performance. / 2771* sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2772 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START\|sc->xl_tx_thresh); 2773 2774 /* 2775 * If this is a 3c905B, also set the tx reclaim threshold. 2776 * This helps cut down on the number of tx reclaim errors 2777 * that could happen on a busy network. The chip multiplies 2778 * the register value by 16 to obtain the actual threshold 2779 * in bytes, so we divide by 16 when setting the value here. 2780 * The existing threshold value can be examined by reading 2781 * the register at offset 9 in window 5. 2782 / 2783* if (sc->xl_type == XL_TYPE_905B) { 2784 CSR_WRITE_2(sc, XL_COMMAND, 2785 XL_CMD_SET_TX_RECLAIM\|(XL_PACKET_SIZE >> 4)); 2786 } 2787 2788 /* Set RX filter bits. / 2789* XL_SEL_WIN(5); 2790 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2791 2792 /* Set the individual bit to receive frames for this host only. / 2793* rxfilt \|= XL_RXFILTER_INDIVIDUAL; 2794 2795 /* If we want promiscuous mode, set the allframes bit. / 2796* if (ifp->if_flags & IFF_PROMISC) { 2797 rxfilt \|= XL_RXFILTER_ALLFRAMES; 2798 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT\|rxfilt); 2799 } else { 2800 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2801 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT\|rxfilt); 2802 } 2803 2804 /* 2805 * Set capture broadcast bit to capture broadcast frames. 2806 / 2807* if (ifp->if_flags & IFF_BROADCAST) { 2808 rxfilt \|= XL_RXFILTER_BROADCAST; 2809 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT\|rxfilt); 2810 } else { 2811 rxfilt &= ~XL_RXFILTER_BROADCAST; 2812 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT\|rxfilt); 2813 } 2814 2815 /* 2816 * Program the multicast filter, if necessary. 2817 / 2818* if (sc->xl_type == XL_TYPE_905B) 2819 xl_setmulti_hash(sc); 2820 else 2821 xl_setmulti(sc); 2822 2823 /* 2824 * Load the address of the RX list. We have to 2825 * stall the upload engine before we can manipulate 2826 * the uplist pointer register, then unstall it when 2827 * we're finished. We also have to wait for the 2828 * stall command to complete before proceeding. 2829 * Note that we have to do this after any RX resets 2830 * have completed since the uplist register is cleared 2831 * by a reset. 2832 / 2833* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2834 xl_wait(sc); 2835 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2836 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2837 xl_wait(sc); 2838 2839 2840 if (sc->xl_type == XL_TYPE_905B) { 2841 /* Set polling interval / 2842* CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2843 /* Load the address of the TX list / 2844* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2845 xl_wait(sc); 2846 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2847 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2848 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2849 xl_wait(sc); 2850 } 2851 2852 /* 2853 * If the coax transceiver is on, make sure to enable 2854 * the DC-DC converter. 2855 / 2856* XL_SEL_WIN(3); 2857 if (sc->xl_xcvr == XL_XCVR_COAX) 2858 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2859 else 2860 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2861 2862 /* increase packet size to allow reception of 802.1q or ISL packets / 2863* if (sc->xl_type == XL_TYPE_905B) 2864 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2865 /* Clear out the stats counters. / 2866* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2867 sc->xl_stats_no_timeout = 1; 2868 xl_stats_update(sc); 2869 sc->xl_stats_no_timeout = 0; 2870 XL_SEL_WIN(4); 2871 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2872 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2873 2874 /* 2875 * Enable interrupts. 2876 / 2877* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK\|0xFF); 2878 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB\|XL_INTRS); 2879 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB\|XL_INTRS); 2880 if (sc->xl_flags & XL_FLAG_FUNCREG) 2881 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2882 2883 /* Set the RX early threshold / 2884* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH\|(XL_PACKET_SIZE >>2)); 2885 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2886 2887 /* Enable receiver and transmitter. / 2888* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2889 xl_wait(sc); 2890 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2891 xl_wait(sc); 2892 2893 if (mii != NULL) 2894 mii_mediachg(mii); 2895 2896 /* Select window 7 for normal operations. / 2897* XL_SEL_WIN(7); 2898 2899 ifp->if_flags \|= IFF_RUNNING; 2900 ifp->if_flags &= ~IFF_OACTIVE; 2901 2902 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz); 2903 2904 XL_UNLOCK(sc); 2905 2906 return; 2907} 2908 2909/* 2910 * Set media options. 2911 / 2912static int 2913xl_ifmedia_upd(ifp) 2914* struct ifnet ifp; 2915{ 2916* struct xl_softc sc; 2917* struct ifmedia ifm = NULL; 2918* struct mii_data mii = NULL; 2919* 2920 sc = ifp->if_softc; 2921 if (sc->xl_miibus != NULL) 2922 mii = device_get_softc(sc->xl_miibus); 2923 if (mii == NULL) 2924 ifm = &sc->ifmedia; 2925 else 2926 ifm = &mii->mii_media; 2927 2928 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2929 case IFM_100_FX: 2930 case IFM_10_FL: 2931 case IFM_10_2: 2932 case IFM_10_5: 2933 xl_setmode(sc, ifm->ifm_media); 2934 return(0); 2935 break; 2936 default: 2937 break; 2938 } 2939 2940 if (sc->xl_media & XL_MEDIAOPT_MII \|\| sc->xl_media & XL_MEDIAOPT_BTX 2941 \|\| sc->xl_media & XL_MEDIAOPT_BT4) { 2942 xl_init(sc); 2943 } else { 2944 xl_setmode(sc, ifm->ifm_media); 2945 } 2946 2947 return(0); 2948} 2949 2950/* 2951 * Report current media status. 2952 / 2953static void 2954xl_ifmedia_sts(ifp, ifmr) 2955* struct ifnet ifp; 2956* struct ifmediareq ifmr; 2957{ 2958* struct xl_softc sc; 2959* u_int32_t icfg; 2960 struct mii_data mii = NULL; 2961* 2962 sc = ifp->if_softc; 2963 if (sc->xl_miibus != NULL) 2964 mii = device_get_softc(sc->xl_miibus); 2965 2966 XL_SEL_WIN(3); 2967 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2968 icfg >>= XL_ICFG_CONNECTOR_BITS; 2969 2970 ifmr->ifm_active = IFM_ETHER; 2971 2972 switch(icfg) { 2973 case XL_XCVR_10BT: 2974 ifmr->ifm_active = IFM_ETHER\|IFM_10_T; 2975 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2976 ifmr->ifm_active \|= IFM_FDX; 2977 else 2978 ifmr->ifm_active \|= IFM_HDX; 2979 break; 2980 case XL_XCVR_AUI: 2981 if (sc->xl_type == XL_TYPE_905B && 2982 sc->xl_media == XL_MEDIAOPT_10FL) { 2983 ifmr->ifm_active = IFM_ETHER\|IFM_10_FL; 2984 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2985 ifmr->ifm_active \|= IFM_FDX; 2986 else 2987 ifmr->ifm_active \|= IFM_HDX; 2988 } else 2989 ifmr->ifm_active = IFM_ETHER\|IFM_10_5; 2990 break; 2991 case XL_XCVR_COAX: 2992 ifmr->ifm_active = IFM_ETHER\|IFM_10_2; 2993 break; 2994 /* 2995 * XXX MII and BTX/AUTO should be separate cases. 2996 / 2997* 2998 case XL_XCVR_100BTX: 2999 case XL_XCVR_AUTO: 3000 case XL_XCVR_MII: 3001 if (mii != NULL) { 3002 mii_pollstat(mii); 3003 ifmr->ifm_active = mii->mii_media_active; 3004 ifmr->ifm_status = mii->mii_media_status; 3005 } 3006 break; 3007 case XL_XCVR_100BFX: 3008 ifmr->ifm_active = IFM_ETHER\|IFM_100_FX; 3009 break; 3010 default: 3011 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, icfg); 3012 break; 3013 } 3014 3015 return; 3016} 3017 3018static int 3019xl_ioctl(ifp, command, data) 3020 struct ifnet ifp; 3021* u_long command; 3022 caddr_t data; 3023{ 3024 struct xl_softc sc = ifp->if_softc; 3025* struct ifreq ifr = (struct ifreq ) data; 3026 int error = 0; 3027 struct mii_data mii = NULL; 3028* u_int8_t rxfilt; 3029 3030 XL_LOCK(sc); 3031 3032 switch(command) { 3033 case SIOCSIFFLAGS: 3034 XL_SEL_WIN(5); 3035 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3036 if (ifp->if_flags & IFF_UP) { 3037 if (ifp->if_flags & IFF_RUNNING && 3038 ifp->if_flags & IFF_PROMISC && 3039 !(sc->xl_if_flags & IFF_PROMISC)) { 3040 rxfilt \|= XL_RXFILTER_ALLFRAMES; 3041 CSR_WRITE_2(sc, XL_COMMAND, 3042 XL_CMD_RX_SET_FILT\|rxfilt); 3043 XL_SEL_WIN(7); 3044 } else if (ifp->if_flags & IFF_RUNNING && 3045 !(ifp->if_flags & IFF_PROMISC) && 3046 sc->xl_if_flags & IFF_PROMISC) { 3047 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3048 CSR_WRITE_2(sc, XL_COMMAND, 3049 XL_CMD_RX_SET_FILT\|rxfilt); 3050 XL_SEL_WIN(7); 3051 } else 3052 xl_init(sc); 3053 } else { 3054 if (ifp->if_flags & IFF_RUNNING) 3055 xl_stop(sc); 3056 } 3057 sc->xl_if_flags = ifp->if_flags; 3058 error = 0; 3059 break; 3060 case SIOCADDMULTI: 3061 case SIOCDELMULTI: 3062 if (sc->xl_type == XL_TYPE_905B) 3063 xl_setmulti_hash(sc); 3064 else 3065 xl_setmulti(sc); 3066 error = 0; 3067 break; 3068 case SIOCGIFMEDIA: 3069 case SIOCSIFMEDIA: 3070 if (sc->xl_miibus != NULL) 3071 mii = device_get_softc(sc->xl_miibus); 3072 if (mii == NULL) 3073 error = ifmedia_ioctl(ifp, ifr, 3074 &sc->ifmedia, command); 3075 else 3076 error = ifmedia_ioctl(ifp, ifr, 3077 &mii->mii_media, command); 3078 break; 3079 default: 3080 error = ether_ioctl(ifp, command, data); 3081 break; 3082 } 3083 3084 XL_UNLOCK(sc); 3085 3086 return(error); 3087} 3088 3089static void 3090xl_watchdog(ifp) 3091 struct ifnet ifp; 3092{ 3093* struct xl_softc sc; 3094* u_int16_t status = 0; 3095 3096 sc = ifp->if_softc; 3097 3098 XL_LOCK(sc); 3099 3100 ifp->if_oerrors++; 3101 XL_SEL_WIN(4); 3102 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3103 printf("xl%d: watchdog timeout\n", sc->xl_unit); 3104 3105 if (status & XL_MEDIASTAT_CARRIER) 3106 printf("xl%d: no carrier - transceiver cable problem?\n", 3107 sc->xl_unit); 3108 xl_txeoc(sc); 3109 xl_txeof(sc); 3110 xl_rxeof(sc); 3111 xl_reset(sc); 3112 xl_init(sc); 3113 3114 if (ifp->if_snd.ifq_head != NULL) 3115 (ifp->if_start)(ifp); 3116* 3117 XL_UNLOCK(sc); 3118 3119 return; 3120} 3121 3122/* 3123 * Stop the adapter and free any mbufs allocated to the 3124 * RX and TX lists. 3125 / 3126static void 3127xl_stop(sc) 3128* struct xl_softc sc; 3129{ 3130* register int i; 3131 struct ifnet ifp; 3132* 3133 XL_LOCK(sc); 3134 3135 ifp = &sc->arpcom.ac_if; 3136 ifp->if_timer = 0; 3137 3138 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3139 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3140 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3141 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3142 xl_wait(sc); 3143 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3144 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3145 DELAY(800); 3146 3147#ifdef foo 3148 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3149 xl_wait(sc); 3150 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3151 xl_wait(sc); 3152#endif 3153 3154 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK\|XL_STAT_INTLATCH); 3155 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB\|0); 3156 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB\|0); 3157 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3158 3159 /* Stop the stats updater. / 3160* untimeout(xl_stats_update, sc, sc->xl_stat_ch); 3161 3162 /* 3163 * Free data in the RX lists. 3164 / 3165* for (i = 0; i < XL_RX_LIST_CNT; i++) { 3166 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3167 bus_dmamap_unload(sc->xl_mtag, 3168 sc->xl_cdata.xl_rx_chain[i].xl_map); 3169 bus_dmamap_destroy(sc->xl_mtag, 3170 sc->xl_cdata.xl_rx_chain[i].xl_map); 3171 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3172 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3173 } 3174 } 3175 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3176 /* 3177 * Free the TX list buffers. 3178 / 3179* for (i = 0; i < XL_TX_LIST_CNT; i++) { 3180 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3181 bus_dmamap_unload(sc->xl_mtag, 3182 sc->xl_cdata.xl_tx_chain[i].xl_map); 3183 bus_dmamap_destroy(sc->xl_mtag, 3184 sc->xl_cdata.xl_tx_chain[i].xl_map); 3185 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3186 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3187 } 3188 } 3189 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3190 3191 ifp->if_flags &= ~(IFF_RUNNING \| IFF_OACTIVE); 3192 3193 XL_UNLOCK(sc); 3194 3195 return; 3196} 3197 3198/* 3199 * Stop all chip I/O so that the kernel's probe routines don't 3200 * get confused by errant DMAs when rebooting. 3201 / 3202static void 3203xl_shutdown(dev) 3204* device_t dev; 3205{ 3206 struct xl_softc sc; 3207* 3208 sc = device_get_softc(dev); 3209 3210 XL_LOCK(sc); 3211 xl_reset(sc); 3212 xl_stop(sc); 3213 XL_UNLOCK(sc); 3214 3215 return; 3216} 3217 3218static int 3219xl_suspend(dev) 3220 device_t dev; 3221{ 3222 struct xl_softc sc; 3223* 3224 sc = device_get_softc(dev); 3225 3226 XL_LOCK(sc); 3227 xl_stop(sc); 3228 XL_UNLOCK(sc); 3229 3230 return(0); 3231} 3232 3233static int 3234xl_resume(dev) 3235 device_t dev; 3236{ 3237 struct xl_softc sc; 3238* struct ifnet ifp; 3239* 3240 sc = device_get_softc(dev); 3241 XL_LOCK(sc); 3242 ifp = &sc->arpcom.ac_if; 3243 3244 xl_reset(sc); 3245 if (ifp->if_flags & IFF_UP) 3246 xl_init(sc); 3247 3248 XL_UNLOCK(sc); 3249 return(0); 3250}	1744 XL_LOCK(sc); 1745 ifp = &sc->arpcom.ac_if; 1746 1747 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1748 rid = XL_PCI_LOMEM; 1749 res = SYS_RES_MEMORY; 1750 } else { 1751 rid = XL_PCI_LOIO; 1752 res = SYS_RES_IOPORT; 1753 } 1754 1755 if (device_is_alive(dev)) { 1756 if (bus_child_present(dev)) { 1757 xl_reset(sc); 1758 xl_stop(sc); 1759 } 1760 ether_ifdetach(ifp); 1761 device_delete_child(dev, sc->xl_miibus); 1762 bus_generic_detach(dev); 1763 ifmedia_removeall(&sc->ifmedia); 1764 } 1765 1766 if (sc->xl_intrhand) 1767 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1768 if (sc->xl_irq) 1769 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1770 if (sc->xl_fres != NULL) 1771 bus_release_resource(dev, SYS_RES_MEMORY, 1772 XL_PCI_FUNCMEM, sc->xl_fres); 1773 if (sc->xl_res) 1774 bus_release_resource(dev, res, rid, sc->xl_res); 1775 1776 if (sc->xl_mtag) { 1777 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1778 bus_dma_tag_destroy(sc->xl_mtag); 1779 } 1780 if (sc->xl_ldata.xl_rx_tag) { 1781 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1782 sc->xl_ldata.xl_rx_dmamap); 1783 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1784 sc->xl_ldata.xl_rx_dmamap); 1785 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1786 } 1787 if (sc->xl_ldata.xl_tx_tag) { 1788 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1789 sc->xl_ldata.xl_tx_dmamap); 1790 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1791 sc->xl_ldata.xl_tx_dmamap); 1792 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1793 } 1794 1795 XL_UNLOCK(sc); 1796 mtx_destroy(&sc->xl_mtx); 1797 1798 return(0); 1799} 1800 1801/* 1802 * Initialize the transmit descriptors. 1803 / 1804static int 1805xl_list_tx_init(sc) 1806* struct xl_softc sc; 1807{ 1808* struct xl_chain_data cd; 1809* struct xl_list_data ld; 1810* int error, i; 1811 1812 cd = &sc->xl_cdata; 1813 ld = &sc->xl_ldata; 1814 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1815 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1816 error = bus_dmamap_create(sc->xl_mtag, 0, 1817 &cd->xl_tx_chain[i].xl_map); 1818 if (error) 1819 return(error); 1820 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1821 i * sizeof(struct xl_list); 1822 if (i == (XL_TX_LIST_CNT - 1)) 1823 cd->xl_tx_chain[i].xl_next = NULL; 1824 else 1825 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1826 } 1827 1828 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1829 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1830 1831 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1832 return(0); 1833} 1834 1835/* 1836 * Initialize the transmit descriptors. 1837 / 1838static int 1839xl_list_tx_init_90xB(sc) 1840* struct xl_softc sc; 1841{ 1842* struct xl_chain_data cd; 1843* struct xl_list_data ld; 1844* int error, i; 1845 1846 cd = &sc->xl_cdata; 1847 ld = &sc->xl_ldata; 1848 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1849 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1850 error = bus_dmamap_create(sc->xl_mtag, 0, 1851 &cd->xl_tx_chain[i].xl_map); 1852 if (error) 1853 return(error); 1854 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1855 i * sizeof(struct xl_list); 1856 if (i == (XL_TX_LIST_CNT - 1)) 1857 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1858 else 1859 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1860 if (i == 0) 1861 cd->xl_tx_chain[i].xl_prev = 1862 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1863 else 1864 cd->xl_tx_chain[i].xl_prev = 1865 &cd->xl_tx_chain[i - 1]; 1866 } 1867 1868 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1869 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1870 1871 cd->xl_tx_prod = 1; 1872 cd->xl_tx_cons = 1; 1873 cd->xl_tx_cnt = 0; 1874 1875 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1876 return(0); 1877} 1878 1879/* 1880 * Initialize the RX descriptors and allocate mbufs for them. Note that 1881 * we arrange the descriptors in a closed ring, so that the last descriptor 1882 * points back to the first. 1883 / 1884static int 1885xl_list_rx_init(sc) 1886* struct xl_softc sc; 1887{ 1888* struct xl_chain_data cd; 1889* struct xl_list_data ld; 1890* int error, i, next; 1891 u_int32_t nextptr; 1892 1893 cd = &sc->xl_cdata; 1894 ld = &sc->xl_ldata; 1895 1896 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1897 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1898 error = bus_dmamap_create(sc->xl_mtag, 0, 1899 &cd->xl_rx_chain[i].xl_map); 1900 if (error) 1901 return(error); 1902 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1903 if (error) 1904 return(error); 1905 if (i == (XL_RX_LIST_CNT - 1)) 1906 next = 0; 1907 else 1908 next = i + 1; 1909 nextptr = ld->xl_rx_dmaaddr + 1910 next * sizeof(struct xl_list_onefrag); 1911 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1912 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1913 } 1914 1915 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1916 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1917 1918 return(0); 1919} 1920 1921/* 1922 * Initialize an RX descriptor and attach an MBUF cluster. 1923 * If we fail to do so, we need to leave the old mbuf and 1924 * the old DMA map untouched so that it can be reused. 1925 / 1926static int 1927xl_newbuf(sc, c) 1928* struct xl_softc sc; 1929* struct xl_chain_onefrag c; 1930{ 1931* struct mbuf m_new = NULL; 1932* bus_dmamap_t map; 1933 int error; 1934 u_int32_t baddr; 1935 1936 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1937 if (m_new == NULL) 1938 return(ENOBUFS); 1939 1940 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1941 1942 /* Force longword alignment for packet payload. / 1943* m_adj(m_new, ETHER_ALIGN); 1944 1945 error = bus_dmamap_load(sc->xl_mtag, sc->xl_tmpmap, mtod(m_new, void ), 1946* MCLBYTES, xl_dma_map_addr, &baddr, 0); 1947 if (error) { 1948 m_freem(m_new); 1949 printf("xl%d: can't map mbuf (error %d)\n", sc->xl_unit, error); 1950 return(error); 1951 } 1952 1953 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1954 map = c->xl_map; 1955 c->xl_map = sc->xl_tmpmap; 1956 sc->xl_tmpmap = map; 1957 c->xl_mbuf = m_new; 1958 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len \| XL_LAST_FRAG); 1959 c->xl_ptr->xl_status = 0; 1960 c->xl_ptr->xl_frag.xl_addr = htole32(baddr); 1961 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1962 return(0); 1963} 1964 1965static int 1966xl_rx_resync(sc) 1967 struct xl_softc sc; 1968{ 1969* struct xl_chain_onefrag pos; 1970* int i; 1971 1972 pos = sc->xl_cdata.xl_rx_head; 1973 1974 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1975 if (pos->xl_ptr->xl_status) 1976 break; 1977 pos = pos->xl_next; 1978 } 1979 1980 if (i == XL_RX_LIST_CNT) 1981 return(0); 1982 1983 sc->xl_cdata.xl_rx_head = pos; 1984 1985 return(EAGAIN); 1986} 1987 1988/* 1989 * A frame has been uploaded: pass the resulting mbuf chain up to 1990 * the higher level protocols. 1991 / 1992static void 1993xl_rxeof(sc) 1994* struct xl_softc sc; 1995{ 1996* struct mbuf m; 1997* struct ifnet ifp; 1998* struct xl_chain_onefrag cur_rx; 1999* int total_len = 0; 2000 u_int32_t rxstat; 2001 2002 ifp = &sc->arpcom.ac_if; 2003 2004again: 2005 2006 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 2007 BUS_DMASYNC_POSTREAD); 2008 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 2009 cur_rx = sc->xl_cdata.xl_rx_head; 2010 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 2011 2012 /* 2013 * If an error occurs, update stats, clear the 2014 * status word and leave the mbuf cluster in place: 2015 * it should simply get re-used next time this descriptor 2016 * comes up in the ring. 2017 / 2018* if (rxstat & XL_RXSTAT_UP_ERROR) { 2019 ifp->if_ierrors++; 2020 cur_rx->xl_ptr->xl_status = 0; 2021 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2022 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2023 continue; 2024 } 2025 2026 /* 2027 * If there error bit was not set, the upload complete 2028 * bit should be set which means we have a valid packet. 2029 * If not, something truly strange has happened. 2030 / 2031* if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2032 printf("xl%d: bad receive status -- " 2033 "packet dropped\n", sc->xl_unit); 2034 ifp->if_ierrors++; 2035 cur_rx->xl_ptr->xl_status = 0; 2036 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2037 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2038 continue; 2039 } 2040 2041 /* No errors; receive the packet. / 2042* bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 2043 BUS_DMASYNC_POSTREAD); 2044 m = cur_rx->xl_mbuf; 2045 total_len = le32toh(cur_rx->xl_ptr->xl_status) & 2046 XL_RXSTAT_LENMASK; 2047 2048 /* 2049 * Try to conjure up a new mbuf cluster. If that 2050 * fails, it means we have an out of memory condition and 2051 * should leave the buffer in place and continue. This will 2052 * result in a lost packet, but there's little else we 2053 * can do in this situation. 2054 / 2055* if (xl_newbuf(sc, cur_rx)) { 2056 ifp->if_ierrors++; 2057 cur_rx->xl_ptr->xl_status = 0; 2058 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2059 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2060 continue; 2061 } 2062 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2063 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2064 2065 ifp->if_ipackets++; 2066 m->m_pkthdr.rcvif = ifp; 2067 m->m_pkthdr.len = m->m_len = total_len; 2068 2069 if (sc->xl_type == XL_TYPE_905B) { 2070 /* Do IP checksum checking. / 2071* if (rxstat & XL_RXSTAT_IPCKOK) 2072 m->m_pkthdr.csum_flags \|= CSUM_IP_CHECKED; 2073 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2074 m->m_pkthdr.csum_flags \|= CSUM_IP_VALID; 2075 if ((rxstat & XL_RXSTAT_TCPCOK && 2076 !(rxstat & XL_RXSTAT_TCPCKERR)) \|\| 2077 (rxstat & XL_RXSTAT_UDPCKOK && 2078 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2079 m->m_pkthdr.csum_flags \|= 2080 CSUM_DATA_VALID\|CSUM_PSEUDO_HDR; 2081 m->m_pkthdr.csum_data = 0xffff; 2082 } 2083 } 2084 2085 (ifp->if_input)(ifp, m); 2086* } 2087 2088 /* 2089 * Handle the 'end of channel' condition. When the upload 2090 * engine hits the end of the RX ring, it will stall. This 2091 * is our cue to flush the RX ring, reload the uplist pointer 2092 * register and unstall the engine. 2093 * XXX This is actually a little goofy. With the ThunderLAN 2094 * chip, you get an interrupt when the receiver hits the end 2095 * of the receive ring, which tells you exactly when you 2096 * you need to reload the ring pointer. Here we have to 2097 * fake it. I'm mad at myself for not being clever enough 2098 * to avoid the use of a goto here. 2099 / 2100* if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 \|\| 2101 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2102 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2103 xl_wait(sc); 2104 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2105 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2106 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2107 goto again; 2108 } 2109 2110 return; 2111} 2112 2113/* 2114 * A frame was downloaded to the chip. It's safe for us to clean up 2115 * the list buffers. 2116 / 2117static void 2118xl_txeof(sc) 2119* struct xl_softc sc; 2120{ 2121* struct xl_chain cur_tx; 2122* struct ifnet ifp; 2123* 2124 ifp = &sc->arpcom.ac_if; 2125 2126 /* Clear the timeout timer. / 2127* ifp->if_timer = 0; 2128 2129 /* 2130 * Go through our tx list and free mbufs for those 2131 * frames that have been uploaded. Note: the 3c905B 2132 * sets a special bit in the status word to let us 2133 * know that a frame has been downloaded, but the 2134 * original 3c900/3c905 adapters don't do that. 2135 * Consequently, we have to use a different test if 2136 * xl_type != XL_TYPE_905B. 2137 / 2138* while(sc->xl_cdata.xl_tx_head != NULL) { 2139 cur_tx = sc->xl_cdata.xl_tx_head; 2140 2141 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2142 break; 2143 2144 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2145 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2146 BUS_DMASYNC_POSTWRITE); 2147 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2148 m_freem(cur_tx->xl_mbuf); 2149 cur_tx->xl_mbuf = NULL; 2150 ifp->if_opackets++; 2151 2152 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2153 sc->xl_cdata.xl_tx_free = cur_tx; 2154 } 2155 2156 if (sc->xl_cdata.xl_tx_head == NULL) { 2157 ifp->if_flags &= ~IFF_OACTIVE; 2158 sc->xl_cdata.xl_tx_tail = NULL; 2159 } else { 2160 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED \|\| 2161 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2162 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2163 sc->xl_cdata.xl_tx_head->xl_phys); 2164 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2165 } 2166 } 2167 2168 return; 2169} 2170 2171static void 2172xl_txeof_90xB(sc) 2173 struct xl_softc sc; 2174{ 2175* struct xl_chain cur_tx = NULL; 2176* struct ifnet ifp; 2177* int idx; 2178 2179 ifp = &sc->arpcom.ac_if; 2180 2181 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2182 BUS_DMASYNC_POSTREAD); 2183 idx = sc->xl_cdata.xl_tx_cons; 2184 while(idx != sc->xl_cdata.xl_tx_prod) { 2185 2186 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2187 2188 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2189 XL_TXSTAT_DL_COMPLETE)) 2190 break; 2191 2192 if (cur_tx->xl_mbuf != NULL) { 2193 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2194 BUS_DMASYNC_POSTWRITE); 2195 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2196 m_freem(cur_tx->xl_mbuf); 2197 cur_tx->xl_mbuf = NULL; 2198 } 2199 2200 ifp->if_opackets++; 2201 2202 sc->xl_cdata.xl_tx_cnt--; 2203 XL_INC(idx, XL_TX_LIST_CNT); 2204 ifp->if_timer = 0; 2205 } 2206 2207 sc->xl_cdata.xl_tx_cons = idx; 2208 2209 if (cur_tx != NULL) 2210 ifp->if_flags &= ~IFF_OACTIVE; 2211 2212 return; 2213} 2214 2215/* 2216 * TX 'end of channel' interrupt handler. Actually, we should 2217 * only get a 'TX complete' interrupt if there's a transmit error, 2218 * so this is really TX error handler. 2219 / 2220static void 2221xl_txeoc(sc) 2222* struct xl_softc sc; 2223{ 2224* u_int8_t txstat; 2225 2226 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2227 if (txstat & XL_TXSTATUS_UNDERRUN \|\| 2228 txstat & XL_TXSTATUS_JABBER \|\| 2229 txstat & XL_TXSTATUS_RECLAIM) { 2230 printf("xl%d: transmission error: %x\n", 2231 sc->xl_unit, txstat); 2232 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2233 xl_wait(sc); 2234 if (sc->xl_type == XL_TYPE_905B) { 2235 if (sc->xl_cdata.xl_tx_cnt) { 2236 int i; 2237 struct xl_chain c; 2238* i = sc->xl_cdata.xl_tx_cons; 2239 c = &sc->xl_cdata.xl_tx_chain[i]; 2240 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2241 c->xl_phys); 2242 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2243 } 2244 } else { 2245 if (sc->xl_cdata.xl_tx_head != NULL) 2246 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2247 sc->xl_cdata.xl_tx_head->xl_phys); 2248 } 2249 /* 2250 * Remember to set this for the 2251 * first generation 3c90X chips. 2252 / 2253* CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2254 if (txstat & XL_TXSTATUS_UNDERRUN && 2255 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2256 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2257 printf("xl%d: tx underrun, increasing tx start" 2258 " threshold to %d bytes\n", sc->xl_unit, 2259 sc->xl_tx_thresh); 2260 } 2261 CSR_WRITE_2(sc, XL_COMMAND, 2262 XL_CMD_TX_SET_START\|sc->xl_tx_thresh); 2263 if (sc->xl_type == XL_TYPE_905B) { 2264 CSR_WRITE_2(sc, XL_COMMAND, 2265 XL_CMD_SET_TX_RECLAIM\|(XL_PACKET_SIZE >> 4)); 2266 } 2267 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2268 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2269 } else { 2270 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2271 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2272 } 2273 /* 2274 * Write an arbitrary byte to the TX_STATUS register 2275 * to clear this interrupt/error and advance to the next. 2276 / 2277* CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2278 } 2279 2280 return; 2281} 2282 2283static void 2284xl_intr(arg) 2285 void arg; 2286{ 2287* struct xl_softc sc; 2288* struct ifnet ifp; 2289* u_int16_t status; 2290 2291 sc = arg; 2292 XL_LOCK(sc); 2293 ifp = &sc->arpcom.ac_if; 2294 2295 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) { 2296 2297 CSR_WRITE_2(sc, XL_COMMAND, 2298 XL_CMD_INTR_ACK\|(status & XL_INTRS)); 2299 2300 if (status & XL_STAT_UP_COMPLETE) { 2301 int curpkts; 2302 2303 curpkts = ifp->if_ipackets; 2304 xl_rxeof(sc); 2305 if (curpkts == ifp->if_ipackets) { 2306 while (xl_rx_resync(sc)) 2307 xl_rxeof(sc); 2308 } 2309 } 2310 2311 if (status & XL_STAT_DOWN_COMPLETE) { 2312 if (sc->xl_type == XL_TYPE_905B) 2313 xl_txeof_90xB(sc); 2314 else 2315 xl_txeof(sc); 2316 } 2317 2318 if (status & XL_STAT_TX_COMPLETE) { 2319 ifp->if_oerrors++; 2320 xl_txeoc(sc); 2321 } 2322 2323 if (status & XL_STAT_ADFAIL) { 2324 xl_reset(sc); 2325 xl_init(sc); 2326 } 2327 2328 if (status & XL_STAT_STATSOFLOW) { 2329 sc->xl_stats_no_timeout = 1; 2330 xl_stats_update(sc); 2331 sc->xl_stats_no_timeout = 0; 2332 } 2333 } 2334 2335 if (ifp->if_snd.ifq_head != NULL) 2336 (ifp->if_start)(ifp); 2337* 2338 XL_UNLOCK(sc); 2339 2340 return; 2341} 2342 2343static void 2344xl_stats_update(xsc) 2345 void xsc; 2346{ 2347* struct xl_softc sc; 2348* struct ifnet ifp; 2349* struct xl_stats xl_stats; 2350 u_int8_t p; 2351* int i; 2352 struct mii_data mii = NULL; 2353* 2354 bzero((char )&xl_stats, sizeof(struct xl_stats)); 2355* 2356 sc = xsc; 2357 ifp = &sc->arpcom.ac_if; 2358 if (sc->xl_miibus != NULL) 2359 mii = device_get_softc(sc->xl_miibus); 2360 2361 p = (u_int8_t )&xl_stats; 2362* 2363 /* Read all the stats registers. / 2364* XL_SEL_WIN(6); 2365 2366 for (i = 0; i < 16; i++) 2367 p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2368* 2369 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2370 2371 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2372 xl_stats.xl_tx_single_collision + 2373 xl_stats.xl_tx_late_collision; 2374 2375 /* 2376 * Boomerang and cyclone chips have an extra stats counter 2377 * in window 4 (BadSSD). We have to read this too in order 2378 * to clear out all the stats registers and avoid a statsoflow 2379 * interrupt. 2380 / 2381* XL_SEL_WIN(4); 2382 CSR_READ_1(sc, XL_W4_BADSSD); 2383 2384 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2385 mii_tick(mii); 2386 2387 XL_SEL_WIN(7); 2388 2389 if (!sc->xl_stats_no_timeout) 2390 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz); 2391 2392 return; 2393} 2394 2395/* 2396 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2397 * pointers to the fragment pointers. 2398 / 2399static int 2400xl_encap(sc, c, m_head) 2401* struct xl_softc sc; 2402* struct xl_chain c; 2403* struct mbuf m_head; 2404{ 2405* int error; 2406 u_int32_t status; 2407 2408 /* 2409 * Start packing the mbufs in this chain into 2410 * the fragment pointers. Stop when we run out 2411 * of fragments or hit the end of the mbuf chain. 2412 / 2413* error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head, 2414 xl_dma_map_txbuf, c->xl_ptr, 0); 2415 2416 if (error && error != EFBIG) { 2417 m_freem(m_head); 2418 printf("xl%d: can't map mbuf (error %d)\n", sc->xl_unit, error); 2419 return(1); 2420 } 2421 2422 /* 2423 * Handle special case: we used up all 63 fragments, 2424 * but we have more mbufs left in the chain. Copy the 2425 * data into an mbuf cluster. Note that we don't 2426 * bother clearing the values in the other fragment 2427 * pointers/counters; it wouldn't gain us anything, 2428 * and would waste cycles. 2429 / 2430* if (error) { 2431 struct mbuf m_new; 2432* 2433 m_new = m_defrag(m_head, M_DONTWAIT); 2434 if (m_new == NULL) { 2435 m_freem(m_head); 2436 printf("xl%d: no memory for tx list\n", sc->xl_unit); 2437 return(1); 2438 } else { 2439 m_head = m_new; 2440 } 2441 2442 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, 2443 m_head, xl_dma_map_txbuf, c->xl_ptr, 0); 2444 if (error) { 2445 m_freem(m_head); 2446 printf("xl%d: can't map mbuf (error %d)\n", 2447 sc->xl_unit, error); 2448 return(1); 2449 } 2450 } 2451 2452 if (sc->xl_type == XL_TYPE_905B) { 2453 status = XL_TXSTAT_RND_DEFEAT; 2454 2455 if (m_head->m_pkthdr.csum_flags) { 2456 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2457 status \|= XL_TXSTAT_IPCKSUM; 2458 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2459 status \|= XL_TXSTAT_TCPCKSUM; 2460 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2461 status \|= XL_TXSTAT_UDPCKSUM; 2462 } 2463 c->xl_ptr->xl_status = htole32(status); 2464 } 2465 2466 c->xl_mbuf = m_head; 2467 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2468 return(0); 2469} 2470 2471/* 2472 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2473 * to the mbuf data regions directly in the transmit lists. We also save a 2474 * copy of the pointers since the transmit list fragment pointers are 2475 * physical addresses. 2476 / 2477static void 2478xl_start(ifp) 2479* struct ifnet ifp; 2480{ 2481* struct xl_softc sc; 2482* struct mbuf m_head = NULL; 2483* struct xl_chain prev = NULL, cur_tx = NULL, start_tx; 2484* u_int32_t status; 2485 int error; 2486 2487 sc = ifp->if_softc; 2488 XL_LOCK(sc); 2489 /* 2490 * Check for an available queue slot. If there are none, 2491 * punt. 2492 / 2493* if (sc->xl_cdata.xl_tx_free == NULL) { 2494 xl_txeoc(sc); 2495 xl_txeof(sc); 2496 if (sc->xl_cdata.xl_tx_free == NULL) { 2497 ifp->if_flags \|= IFF_OACTIVE; 2498 XL_UNLOCK(sc); 2499 return; 2500 } 2501 } 2502 2503 start_tx = sc->xl_cdata.xl_tx_free; 2504 2505 while(sc->xl_cdata.xl_tx_free != NULL) { 2506 IF_DEQUEUE(&ifp->if_snd, m_head); 2507 if (m_head == NULL) 2508 break; 2509 2510 /* Pick a descriptor off the free list. / 2511* cur_tx = sc->xl_cdata.xl_tx_free; 2512 2513 /* Pack the data into the descriptor. / 2514* error = xl_encap(sc, cur_tx, m_head); 2515 if (error) 2516 continue; 2517 2518 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2519 cur_tx->xl_next = NULL; 2520 2521 /* Chain it together. / 2522* if (prev != NULL) { 2523 prev->xl_next = cur_tx; 2524 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2525 } 2526 prev = cur_tx; 2527 2528 /* 2529 * If there's a BPF listener, bounce a copy of this frame 2530 * to him. 2531 / 2532* BPF_MTAP(ifp, cur_tx->xl_mbuf); 2533 } 2534 2535 /* 2536 * If there are no packets queued, bail. 2537 / 2538* if (cur_tx == NULL) { 2539 XL_UNLOCK(sc); 2540 return; 2541 } 2542 2543 /* 2544 * Place the request for the upload interrupt 2545 * in the last descriptor in the chain. This way, if 2546 * we're chaining several packets at once, we'll only 2547 * get an interupt once for the whole chain rather than 2548 * once for each packet. 2549 / 2550* cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) \| 2551 XL_TXSTAT_DL_INTR); 2552 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2553 BUS_DMASYNC_PREWRITE); 2554 2555 /* 2556 * Queue the packets. If the TX channel is clear, update 2557 * the downlist pointer register. 2558 / 2559* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2560 xl_wait(sc); 2561 2562 if (sc->xl_cdata.xl_tx_head != NULL) { 2563 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2564 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2565 htole32(start_tx->xl_phys); 2566 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2567 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2568 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2569 sc->xl_cdata.xl_tx_tail = cur_tx; 2570 } else { 2571 sc->xl_cdata.xl_tx_head = start_tx; 2572 sc->xl_cdata.xl_tx_tail = cur_tx; 2573 } 2574 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2575 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2576 2577 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2578 2579 XL_SEL_WIN(7); 2580 2581 /* 2582 * Set a timeout in case the chip goes out to lunch. 2583 / 2584* ifp->if_timer = 5; 2585 2586 /* 2587 * XXX Under certain conditions, usually on slower machines 2588 * where interrupts may be dropped, it's possible for the 2589 * adapter to chew up all the buffers in the receive ring 2590 * and stall, without us being able to do anything about it. 2591 * To guard against this, we need to make a pass over the 2592 * RX queue to make sure there aren't any packets pending. 2593 * Doing it here means we can flush the receive ring at the 2594 * same time the chip is DMAing the transmit descriptors we 2595 * just gave it. 2596 * 2597 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2598 * nature of their chips in all their marketing literature; 2599 * we may as well take advantage of it. :) 2600 / 2601* xl_rxeof(sc); 2602 2603 XL_UNLOCK(sc); 2604 2605 return; 2606} 2607 2608static void 2609xl_start_90xB(ifp) 2610 struct ifnet ifp; 2611{ 2612* struct xl_softc sc; 2613* struct mbuf m_head = NULL; 2614* struct xl_chain prev = NULL, cur_tx = NULL, start_tx; 2615* int error, idx; 2616 2617 sc = ifp->if_softc; 2618 XL_LOCK(sc); 2619 2620 if (ifp->if_flags & IFF_OACTIVE) { 2621 XL_UNLOCK(sc); 2622 return; 2623 } 2624 2625 idx = sc->xl_cdata.xl_tx_prod; 2626 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2627 2628 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2629 2630 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2631 ifp->if_flags \|= IFF_OACTIVE; 2632 break; 2633 } 2634 2635 IF_DEQUEUE(&ifp->if_snd, m_head); 2636 if (m_head == NULL) 2637 break; 2638 2639 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2640 2641 /* Pack the data into the descriptor. / 2642* error = xl_encap(sc, cur_tx, m_head); 2643 if (error) 2644 continue; 2645 2646 /* Chain it together. / 2647* if (prev != NULL) 2648 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2649 prev = cur_tx; 2650 2651 /* 2652 * If there's a BPF listener, bounce a copy of this frame 2653 * to him. 2654 / 2655* BPF_MTAP(ifp, cur_tx->xl_mbuf); 2656 2657 XL_INC(idx, XL_TX_LIST_CNT); 2658 sc->xl_cdata.xl_tx_cnt++; 2659 } 2660 2661 /* 2662 * If there are no packets queued, bail. 2663 / 2664* if (cur_tx == NULL) { 2665 XL_UNLOCK(sc); 2666 return; 2667 } 2668 2669 /* 2670 * Place the request for the upload interrupt 2671 * in the last descriptor in the chain. This way, if 2672 * we're chaining several packets at once, we'll only 2673 * get an interupt once for the whole chain rather than 2674 * once for each packet. 2675 / 2676* cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) \| 2677 XL_TXSTAT_DL_INTR); 2678 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2679 BUS_DMASYNC_PREWRITE); 2680 2681 /* Start transmission / 2682* sc->xl_cdata.xl_tx_prod = idx; 2683 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2684 2685 /* 2686 * Set a timeout in case the chip goes out to lunch. 2687 / 2688* ifp->if_timer = 5; 2689 2690 XL_UNLOCK(sc); 2691 2692 return; 2693} 2694 2695static void 2696xl_init(xsc) 2697 void xsc; 2698{ 2699* struct xl_softc sc = xsc; 2700* struct ifnet ifp = &sc->arpcom.ac_if; 2701* int error, i; 2702 u_int16_t rxfilt = 0; 2703 struct mii_data mii = NULL; 2704* 2705 XL_LOCK(sc); 2706 2707 /* 2708 * Cancel pending I/O and free all RX/TX buffers. 2709 / 2710* xl_stop(sc); 2711 2712 if (sc->xl_miibus == NULL) { 2713 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2714 xl_wait(sc); 2715 } 2716 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2717 xl_wait(sc); 2718 DELAY(10000); 2719 2720 if (sc->xl_miibus != NULL) 2721 mii = device_get_softc(sc->xl_miibus); 2722 2723 /* Init our MAC address / 2724* XL_SEL_WIN(2); 2725 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2726 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2727 sc->arpcom.ac_enaddr[i]); 2728 } 2729 2730 /* Clear the station mask. / 2731* for (i = 0; i < 3; i++) 2732 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2733#ifdef notdef 2734 /* Reset TX and RX. / 2735* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2736 xl_wait(sc); 2737 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2738 xl_wait(sc); 2739#endif 2740 /* Init circular RX list. / 2741* error = xl_list_rx_init(sc); 2742 if (error) { 2743 printf("xl%d: initialization of the rx ring failed (%d)\n", 2744 sc->xl_unit, error); 2745 xl_stop(sc); 2746 XL_UNLOCK(sc); 2747 return; 2748 } 2749 2750 /* Init TX descriptors. / 2751* if (sc->xl_type == XL_TYPE_905B) 2752 error = xl_list_tx_init_90xB(sc); 2753 else 2754 error = xl_list_tx_init(sc); 2755 if (error) { 2756 printf("xl%d: initialization of the tx ring failed (%d)\n", 2757 sc->xl_unit, error); 2758 xl_stop(sc); 2759 XL_UNLOCK(sc); 2760 } 2761 2762 /* 2763 * Set the TX freethresh value. 2764 * Note that this has no effect on 3c905B "cyclone" 2765 * cards but is required for 3c900/3c905 "boomerang" 2766 * cards in order to enable the download engine. 2767 / 2768* CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2769 2770 /* Set the TX start threshold for best performance. / 2771* sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2772 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START\|sc->xl_tx_thresh); 2773 2774 /* 2775 * If this is a 3c905B, also set the tx reclaim threshold. 2776 * This helps cut down on the number of tx reclaim errors 2777 * that could happen on a busy network. The chip multiplies 2778 * the register value by 16 to obtain the actual threshold 2779 * in bytes, so we divide by 16 when setting the value here. 2780 * The existing threshold value can be examined by reading 2781 * the register at offset 9 in window 5. 2782 / 2783* if (sc->xl_type == XL_TYPE_905B) { 2784 CSR_WRITE_2(sc, XL_COMMAND, 2785 XL_CMD_SET_TX_RECLAIM\|(XL_PACKET_SIZE >> 4)); 2786 } 2787 2788 /* Set RX filter bits. / 2789* XL_SEL_WIN(5); 2790 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2791 2792 /* Set the individual bit to receive frames for this host only. / 2793* rxfilt \|= XL_RXFILTER_INDIVIDUAL; 2794 2795 /* If we want promiscuous mode, set the allframes bit. / 2796* if (ifp->if_flags & IFF_PROMISC) { 2797 rxfilt \|= XL_RXFILTER_ALLFRAMES; 2798 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT\|rxfilt); 2799 } else { 2800 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2801 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT\|rxfilt); 2802 } 2803 2804 /* 2805 * Set capture broadcast bit to capture broadcast frames. 2806 / 2807* if (ifp->if_flags & IFF_BROADCAST) { 2808 rxfilt \|= XL_RXFILTER_BROADCAST; 2809 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT\|rxfilt); 2810 } else { 2811 rxfilt &= ~XL_RXFILTER_BROADCAST; 2812 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT\|rxfilt); 2813 } 2814 2815 /* 2816 * Program the multicast filter, if necessary. 2817 / 2818* if (sc->xl_type == XL_TYPE_905B) 2819 xl_setmulti_hash(sc); 2820 else 2821 xl_setmulti(sc); 2822 2823 /* 2824 * Load the address of the RX list. We have to 2825 * stall the upload engine before we can manipulate 2826 * the uplist pointer register, then unstall it when 2827 * we're finished. We also have to wait for the 2828 * stall command to complete before proceeding. 2829 * Note that we have to do this after any RX resets 2830 * have completed since the uplist register is cleared 2831 * by a reset. 2832 / 2833* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2834 xl_wait(sc); 2835 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2836 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2837 xl_wait(sc); 2838 2839 2840 if (sc->xl_type == XL_TYPE_905B) { 2841 /* Set polling interval / 2842* CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2843 /* Load the address of the TX list / 2844* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2845 xl_wait(sc); 2846 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2847 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2848 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2849 xl_wait(sc); 2850 } 2851 2852 /* 2853 * If the coax transceiver is on, make sure to enable 2854 * the DC-DC converter. 2855 / 2856* XL_SEL_WIN(3); 2857 if (sc->xl_xcvr == XL_XCVR_COAX) 2858 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2859 else 2860 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2861 2862 /* increase packet size to allow reception of 802.1q or ISL packets / 2863* if (sc->xl_type == XL_TYPE_905B) 2864 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2865 /* Clear out the stats counters. / 2866* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2867 sc->xl_stats_no_timeout = 1; 2868 xl_stats_update(sc); 2869 sc->xl_stats_no_timeout = 0; 2870 XL_SEL_WIN(4); 2871 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2872 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2873 2874 /* 2875 * Enable interrupts. 2876 / 2877* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK\|0xFF); 2878 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB\|XL_INTRS); 2879 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB\|XL_INTRS); 2880 if (sc->xl_flags & XL_FLAG_FUNCREG) 2881 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2882 2883 /* Set the RX early threshold / 2884* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH\|(XL_PACKET_SIZE >>2)); 2885 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2886 2887 /* Enable receiver and transmitter. / 2888* CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2889 xl_wait(sc); 2890 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2891 xl_wait(sc); 2892 2893 if (mii != NULL) 2894 mii_mediachg(mii); 2895 2896 /* Select window 7 for normal operations. / 2897* XL_SEL_WIN(7); 2898 2899 ifp->if_flags \|= IFF_RUNNING; 2900 ifp->if_flags &= ~IFF_OACTIVE; 2901 2902 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz); 2903 2904 XL_UNLOCK(sc); 2905 2906 return; 2907} 2908 2909/* 2910 * Set media options. 2911 / 2912static int 2913xl_ifmedia_upd(ifp) 2914* struct ifnet ifp; 2915{ 2916* struct xl_softc sc; 2917* struct ifmedia ifm = NULL; 2918* struct mii_data mii = NULL; 2919* 2920 sc = ifp->if_softc; 2921 if (sc->xl_miibus != NULL) 2922 mii = device_get_softc(sc->xl_miibus); 2923 if (mii == NULL) 2924 ifm = &sc->ifmedia; 2925 else 2926 ifm = &mii->mii_media; 2927 2928 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2929 case IFM_100_FX: 2930 case IFM_10_FL: 2931 case IFM_10_2: 2932 case IFM_10_5: 2933 xl_setmode(sc, ifm->ifm_media); 2934 return(0); 2935 break; 2936 default: 2937 break; 2938 } 2939 2940 if (sc->xl_media & XL_MEDIAOPT_MII \|\| sc->xl_media & XL_MEDIAOPT_BTX 2941 \|\| sc->xl_media & XL_MEDIAOPT_BT4) { 2942 xl_init(sc); 2943 } else { 2944 xl_setmode(sc, ifm->ifm_media); 2945 } 2946 2947 return(0); 2948} 2949 2950/* 2951 * Report current media status. 2952 / 2953static void 2954xl_ifmedia_sts(ifp, ifmr) 2955* struct ifnet ifp; 2956* struct ifmediareq ifmr; 2957{ 2958* struct xl_softc sc; 2959* u_int32_t icfg; 2960 struct mii_data mii = NULL; 2961* 2962 sc = ifp->if_softc; 2963 if (sc->xl_miibus != NULL) 2964 mii = device_get_softc(sc->xl_miibus); 2965 2966 XL_SEL_WIN(3); 2967 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2968 icfg >>= XL_ICFG_CONNECTOR_BITS; 2969 2970 ifmr->ifm_active = IFM_ETHER; 2971 2972 switch(icfg) { 2973 case XL_XCVR_10BT: 2974 ifmr->ifm_active = IFM_ETHER\|IFM_10_T; 2975 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2976 ifmr->ifm_active \|= IFM_FDX; 2977 else 2978 ifmr->ifm_active \|= IFM_HDX; 2979 break; 2980 case XL_XCVR_AUI: 2981 if (sc->xl_type == XL_TYPE_905B && 2982 sc->xl_media == XL_MEDIAOPT_10FL) { 2983 ifmr->ifm_active = IFM_ETHER\|IFM_10_FL; 2984 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2985 ifmr->ifm_active \|= IFM_FDX; 2986 else 2987 ifmr->ifm_active \|= IFM_HDX; 2988 } else 2989 ifmr->ifm_active = IFM_ETHER\|IFM_10_5; 2990 break; 2991 case XL_XCVR_COAX: 2992 ifmr->ifm_active = IFM_ETHER\|IFM_10_2; 2993 break; 2994 /* 2995 * XXX MII and BTX/AUTO should be separate cases. 2996 / 2997* 2998 case XL_XCVR_100BTX: 2999 case XL_XCVR_AUTO: 3000 case XL_XCVR_MII: 3001 if (mii != NULL) { 3002 mii_pollstat(mii); 3003 ifmr->ifm_active = mii->mii_media_active; 3004 ifmr->ifm_status = mii->mii_media_status; 3005 } 3006 break; 3007 case XL_XCVR_100BFX: 3008 ifmr->ifm_active = IFM_ETHER\|IFM_100_FX; 3009 break; 3010 default: 3011 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, icfg); 3012 break; 3013 } 3014 3015 return; 3016} 3017 3018static int 3019xl_ioctl(ifp, command, data) 3020 struct ifnet ifp; 3021* u_long command; 3022 caddr_t data; 3023{ 3024 struct xl_softc sc = ifp->if_softc; 3025* struct ifreq ifr = (struct ifreq ) data; 3026 int error = 0; 3027 struct mii_data mii = NULL; 3028* u_int8_t rxfilt; 3029 3030 XL_LOCK(sc); 3031 3032 switch(command) { 3033 case SIOCSIFFLAGS: 3034 XL_SEL_WIN(5); 3035 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3036 if (ifp->if_flags & IFF_UP) { 3037 if (ifp->if_flags & IFF_RUNNING && 3038 ifp->if_flags & IFF_PROMISC && 3039 !(sc->xl_if_flags & IFF_PROMISC)) { 3040 rxfilt \|= XL_RXFILTER_ALLFRAMES; 3041 CSR_WRITE_2(sc, XL_COMMAND, 3042 XL_CMD_RX_SET_FILT\|rxfilt); 3043 XL_SEL_WIN(7); 3044 } else if (ifp->if_flags & IFF_RUNNING && 3045 !(ifp->if_flags & IFF_PROMISC) && 3046 sc->xl_if_flags & IFF_PROMISC) { 3047 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3048 CSR_WRITE_2(sc, XL_COMMAND, 3049 XL_CMD_RX_SET_FILT\|rxfilt); 3050 XL_SEL_WIN(7); 3051 } else 3052 xl_init(sc); 3053 } else { 3054 if (ifp->if_flags & IFF_RUNNING) 3055 xl_stop(sc); 3056 } 3057 sc->xl_if_flags = ifp->if_flags; 3058 error = 0; 3059 break; 3060 case SIOCADDMULTI: 3061 case SIOCDELMULTI: 3062 if (sc->xl_type == XL_TYPE_905B) 3063 xl_setmulti_hash(sc); 3064 else 3065 xl_setmulti(sc); 3066 error = 0; 3067 break; 3068 case SIOCGIFMEDIA: 3069 case SIOCSIFMEDIA: 3070 if (sc->xl_miibus != NULL) 3071 mii = device_get_softc(sc->xl_miibus); 3072 if (mii == NULL) 3073 error = ifmedia_ioctl(ifp, ifr, 3074 &sc->ifmedia, command); 3075 else 3076 error = ifmedia_ioctl(ifp, ifr, 3077 &mii->mii_media, command); 3078 break; 3079 default: 3080 error = ether_ioctl(ifp, command, data); 3081 break; 3082 } 3083 3084 XL_UNLOCK(sc); 3085 3086 return(error); 3087} 3088 3089static void 3090xl_watchdog(ifp) 3091 struct ifnet ifp; 3092{ 3093* struct xl_softc sc; 3094* u_int16_t status = 0; 3095 3096 sc = ifp->if_softc; 3097 3098 XL_LOCK(sc); 3099 3100 ifp->if_oerrors++; 3101 XL_SEL_WIN(4); 3102 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3103 printf("xl%d: watchdog timeout\n", sc->xl_unit); 3104 3105 if (status & XL_MEDIASTAT_CARRIER) 3106 printf("xl%d: no carrier - transceiver cable problem?\n", 3107 sc->xl_unit); 3108 xl_txeoc(sc); 3109 xl_txeof(sc); 3110 xl_rxeof(sc); 3111 xl_reset(sc); 3112 xl_init(sc); 3113 3114 if (ifp->if_snd.ifq_head != NULL) 3115 (ifp->if_start)(ifp); 3116* 3117 XL_UNLOCK(sc); 3118 3119 return; 3120} 3121 3122/* 3123 * Stop the adapter and free any mbufs allocated to the 3124 * RX and TX lists. 3125 / 3126static void 3127xl_stop(sc) 3128* struct xl_softc sc; 3129{ 3130* register int i; 3131 struct ifnet ifp; 3132* 3133 XL_LOCK(sc); 3134 3135 ifp = &sc->arpcom.ac_if; 3136 ifp->if_timer = 0; 3137 3138 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3139 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3140 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3141 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3142 xl_wait(sc); 3143 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3144 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3145 DELAY(800); 3146 3147#ifdef foo 3148 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3149 xl_wait(sc); 3150 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3151 xl_wait(sc); 3152#endif 3153 3154 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK\|XL_STAT_INTLATCH); 3155 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB\|0); 3156 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB\|0); 3157 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3158 3159 /* Stop the stats updater. / 3160* untimeout(xl_stats_update, sc, sc->xl_stat_ch); 3161 3162 /* 3163 * Free data in the RX lists. 3164 / 3165* for (i = 0; i < XL_RX_LIST_CNT; i++) { 3166 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3167 bus_dmamap_unload(sc->xl_mtag, 3168 sc->xl_cdata.xl_rx_chain[i].xl_map); 3169 bus_dmamap_destroy(sc->xl_mtag, 3170 sc->xl_cdata.xl_rx_chain[i].xl_map); 3171 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3172 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3173 } 3174 } 3175 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3176 /* 3177 * Free the TX list buffers. 3178 / 3179* for (i = 0; i < XL_TX_LIST_CNT; i++) { 3180 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3181 bus_dmamap_unload(sc->xl_mtag, 3182 sc->xl_cdata.xl_tx_chain[i].xl_map); 3183 bus_dmamap_destroy(sc->xl_mtag, 3184 sc->xl_cdata.xl_tx_chain[i].xl_map); 3185 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3186 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3187 } 3188 } 3189 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3190 3191 ifp->if_flags &= ~(IFF_RUNNING \| IFF_OACTIVE); 3192 3193 XL_UNLOCK(sc); 3194 3195 return; 3196} 3197 3198/* 3199 * Stop all chip I/O so that the kernel's probe routines don't 3200 * get confused by errant DMAs when rebooting. 3201 / 3202static void 3203xl_shutdown(dev) 3204* device_t dev; 3205{ 3206 struct xl_softc sc; 3207* 3208 sc = device_get_softc(dev); 3209 3210 XL_LOCK(sc); 3211 xl_reset(sc); 3212 xl_stop(sc); 3213 XL_UNLOCK(sc); 3214 3215 return; 3216} 3217 3218static int 3219xl_suspend(dev) 3220 device_t dev; 3221{ 3222 struct xl_softc sc; 3223* 3224 sc = device_get_softc(dev); 3225 3226 XL_LOCK(sc); 3227 xl_stop(sc); 3228 XL_UNLOCK(sc); 3229 3230 return(0); 3231} 3232 3233static int 3234xl_resume(dev) 3235 device_t dev; 3236{ 3237 struct xl_softc sc; 3238* struct ifnet ifp; 3239* 3240 sc = device_get_softc(dev); 3241 XL_LOCK(sc); 3242 ifp = &sc->arpcom.ac_if; 3243 3244 xl_reset(sc); 3245 if (ifp->if_flags & IFF_UP) 3246 xl_init(sc); 3247 3248 XL_UNLOCK(sc); 3249 return(0); 3250}