133#endif
134
135/*
136 * Various supported device vendors/types and their names.
137 */
138static struct wb_type wb_devs[] = {
139 { WB_VENDORID, WB_DEVICEID_840F,
140 "Winbond W89C840F 10/100BaseTX" },
141 { CP_VENDORID, CP_DEVICEID_RL100,
142 "Compex RL100-ATX 10/100baseTX" },
143 { 0, 0, NULL }
144};
145
146static int wb_probe __P((device_t));
147static int wb_attach __P((device_t));
148static int wb_detach __P((device_t));
149
150static void wb_bfree __P((caddr_t, u_int));
151static int wb_newbuf __P((struct wb_softc *,
152 struct wb_chain_onefrag *,
153 struct mbuf *));
154static int wb_encap __P((struct wb_softc *, struct wb_chain *,
155 struct mbuf *));
156
157static void wb_rxeof __P((struct wb_softc *));
158static void wb_rxeoc __P((struct wb_softc *));
159static void wb_txeof __P((struct wb_softc *));
160static void wb_txeoc __P((struct wb_softc *));
161static void wb_intr __P((void *));
162static void wb_tick __P((void *));
163static void wb_start __P((struct ifnet *));
164static int wb_ioctl __P((struct ifnet *, u_long, caddr_t));
165static void wb_init __P((void *));
166static void wb_stop __P((struct wb_softc *));
167static void wb_watchdog __P((struct ifnet *));
168static void wb_shutdown __P((device_t));
169static int wb_ifmedia_upd __P((struct ifnet *));
170static void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
171
172static void wb_eeprom_putbyte __P((struct wb_softc *, int));
173static void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *));
174static void wb_read_eeprom __P((struct wb_softc *, caddr_t, int,
175 int, int));
176static void wb_mii_sync __P((struct wb_softc *));
177static void wb_mii_send __P((struct wb_softc *, u_int32_t, int));
178static int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *));
179static int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *));
180
181static void wb_setcfg __P((struct wb_softc *, u_int32_t));
182static u_int8_t wb_calchash __P((caddr_t));
183static void wb_setmulti __P((struct wb_softc *));
184static void wb_reset __P((struct wb_softc *));
185static void wb_fixmedia __P((struct wb_softc *));
186static int wb_list_rx_init __P((struct wb_softc *));
187static int wb_list_tx_init __P((struct wb_softc *));
188
189static int wb_miibus_readreg __P((device_t, int, int));
190static int wb_miibus_writereg __P((device_t, int, int, int));
191static void wb_miibus_statchg __P((device_t));
192
193#ifdef WB_USEIOSPACE
194#define WB_RES SYS_RES_IOPORT
195#define WB_RID WB_PCI_LOIO
196#else
197#define WB_RES SYS_RES_MEMORY
198#define WB_RID WB_PCI_LOMEM
199#endif
200
201static device_method_t wb_methods[] = {
202 /* Device interface */
203 DEVMETHOD(device_probe, wb_probe),
204 DEVMETHOD(device_attach, wb_attach),
205 DEVMETHOD(device_detach, wb_detach),
206 DEVMETHOD(device_shutdown, wb_shutdown),
207
208 /* bus interface, for miibus */
209 DEVMETHOD(bus_print_child, bus_generic_print_child),
210 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
211
212 /* MII interface */
213 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
214 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
215 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
216 { 0, 0 }
217};
218
219static driver_t wb_driver = {
220 "wb",
221 wb_methods,
222 sizeof(struct wb_softc)
223};
224
225static devclass_t wb_devclass;
226
227DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0);
228DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
229
230#define WB_SETBIT(sc, reg, x) \
231 CSR_WRITE_4(sc, reg, \
232 CSR_READ_4(sc, reg) | x)
233
234#define WB_CLRBIT(sc, reg, x) \
235 CSR_WRITE_4(sc, reg, \
236 CSR_READ_4(sc, reg) & ~x)
237
238#define SIO_SET(x) \
239 CSR_WRITE_4(sc, WB_SIO, \
240 CSR_READ_4(sc, WB_SIO) | x)
241
242#define SIO_CLR(x) \
243 CSR_WRITE_4(sc, WB_SIO, \
244 CSR_READ_4(sc, WB_SIO) & ~x)
245
246/*
247 * Send a read command and address to the EEPROM, check for ACK.
248 */
249static void wb_eeprom_putbyte(sc, addr)
250 struct wb_softc *sc;
251 int addr;
252{
253 register int d, i;
254
255 d = addr | WB_EECMD_READ;
256
257 /*
258 * Feed in each bit and stobe the clock.
259 */
260 for (i = 0x400; i; i >>= 1) {
261 if (d & i) {
262 SIO_SET(WB_SIO_EE_DATAIN);
263 } else {
264 SIO_CLR(WB_SIO_EE_DATAIN);
265 }
266 DELAY(100);
267 SIO_SET(WB_SIO_EE_CLK);
268 DELAY(150);
269 SIO_CLR(WB_SIO_EE_CLK);
270 DELAY(100);
271 }
272
273 return;
274}
275
276/*
277 * Read a word of data stored in the EEPROM at address 'addr.'
278 */
279static void wb_eeprom_getword(sc, addr, dest)
280 struct wb_softc *sc;
281 int addr;
282 u_int16_t *dest;
283{
284 register int i;
285 u_int16_t word = 0;
286
287 /* Enter EEPROM access mode. */
288 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
289
290 /*
291 * Send address of word we want to read.
292 */
293 wb_eeprom_putbyte(sc, addr);
294
295 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
296
297 /*
298 * Start reading bits from EEPROM.
299 */
300 for (i = 0x8000; i; i >>= 1) {
301 SIO_SET(WB_SIO_EE_CLK);
302 DELAY(100);
303 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
304 word |= i;
305 SIO_CLR(WB_SIO_EE_CLK);
306 DELAY(100);
307 }
308
309 /* Turn off EEPROM access mode. */
310 CSR_WRITE_4(sc, WB_SIO, 0);
311
312 *dest = word;
313
314 return;
315}
316
317/*
318 * Read a sequence of words from the EEPROM.
319 */
320static void wb_read_eeprom(sc, dest, off, cnt, swap)
321 struct wb_softc *sc;
322 caddr_t dest;
323 int off;
324 int cnt;
325 int swap;
326{
327 int i;
328 u_int16_t word = 0, *ptr;
329
330 for (i = 0; i < cnt; i++) {
331 wb_eeprom_getword(sc, off + i, &word);
332 ptr = (u_int16_t *)(dest + (i * 2));
333 if (swap)
334 *ptr = ntohs(word);
335 else
336 *ptr = word;
337 }
338
339 return;
340}
341
342/*
343 * Sync the PHYs by setting data bit and strobing the clock 32 times.
344 */
345static void wb_mii_sync(sc)
346 struct wb_softc *sc;
347{
348 register int i;
349
350 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
351
352 for (i = 0; i < 32; i++) {
353 SIO_SET(WB_SIO_MII_CLK);
354 DELAY(1);
355 SIO_CLR(WB_SIO_MII_CLK);
356 DELAY(1);
357 }
358
359 return;
360}
361
362/*
363 * Clock a series of bits through the MII.
364 */
365static void wb_mii_send(sc, bits, cnt)
366 struct wb_softc *sc;
367 u_int32_t bits;
368 int cnt;
369{
370 int i;
371
372 SIO_CLR(WB_SIO_MII_CLK);
373
374 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
375 if (bits & i) {
376 SIO_SET(WB_SIO_MII_DATAIN);
377 } else {
378 SIO_CLR(WB_SIO_MII_DATAIN);
379 }
380 DELAY(1);
381 SIO_CLR(WB_SIO_MII_CLK);
382 DELAY(1);
383 SIO_SET(WB_SIO_MII_CLK);
384 }
385}
386
387/*
388 * Read an PHY register through the MII.
389 */
390static int wb_mii_readreg(sc, frame)
391 struct wb_softc *sc;
392 struct wb_mii_frame *frame;
393
394{
395 int i, ack, s;
396
397 s = splimp();
398
399 /*
400 * Set up frame for RX.
401 */
402 frame->mii_stdelim = WB_MII_STARTDELIM;
403 frame->mii_opcode = WB_MII_READOP;
404 frame->mii_turnaround = 0;
405 frame->mii_data = 0;
406
407 CSR_WRITE_4(sc, WB_SIO, 0);
408
409 /*
410 * Turn on data xmit.
411 */
412 SIO_SET(WB_SIO_MII_DIR);
413
414 wb_mii_sync(sc);
415
416 /*
417 * Send command/address info.
418 */
419 wb_mii_send(sc, frame->mii_stdelim, 2);
420 wb_mii_send(sc, frame->mii_opcode, 2);
421 wb_mii_send(sc, frame->mii_phyaddr, 5);
422 wb_mii_send(sc, frame->mii_regaddr, 5);
423
424 /* Idle bit */
425 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
426 DELAY(1);
427 SIO_SET(WB_SIO_MII_CLK);
428 DELAY(1);
429
430 /* Turn off xmit. */
431 SIO_CLR(WB_SIO_MII_DIR);
432 /* Check for ack */
433 SIO_CLR(WB_SIO_MII_CLK);
434 DELAY(1);
435 SIO_SET(WB_SIO_MII_CLK);
436 DELAY(1);
437 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
438 SIO_CLR(WB_SIO_MII_CLK);
439 DELAY(1);
440 SIO_SET(WB_SIO_MII_CLK);
441 DELAY(1);
442
443 /*
444 * Now try reading data bits. If the ack failed, we still
445 * need to clock through 16 cycles to keep the PHY(s) in sync.
446 */
447 if (ack) {
448 for(i = 0; i < 16; i++) {
449 SIO_CLR(WB_SIO_MII_CLK);
450 DELAY(1);
451 SIO_SET(WB_SIO_MII_CLK);
452 DELAY(1);
453 }
454 goto fail;
455 }
456
457 for (i = 0x8000; i; i >>= 1) {
458 SIO_CLR(WB_SIO_MII_CLK);
459 DELAY(1);
460 if (!ack) {
461 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
462 frame->mii_data |= i;
463 DELAY(1);
464 }
465 SIO_SET(WB_SIO_MII_CLK);
466 DELAY(1);
467 }
468
469fail:
470
471 SIO_CLR(WB_SIO_MII_CLK);
472 DELAY(1);
473 SIO_SET(WB_SIO_MII_CLK);
474 DELAY(1);
475
476 splx(s);
477
478 if (ack)
479 return(1);
480 return(0);
481}
482
483/*
484 * Write to a PHY register through the MII.
485 */
486static int wb_mii_writereg(sc, frame)
487 struct wb_softc *sc;
488 struct wb_mii_frame *frame;
489
490{
491 int s;
492
493 s = splimp();
494 /*
495 * Set up frame for TX.
496 */
497
498 frame->mii_stdelim = WB_MII_STARTDELIM;
499 frame->mii_opcode = WB_MII_WRITEOP;
500 frame->mii_turnaround = WB_MII_TURNAROUND;
501
502 /*
503 * Turn on data output.
504 */
505 SIO_SET(WB_SIO_MII_DIR);
506
507 wb_mii_sync(sc);
508
509 wb_mii_send(sc, frame->mii_stdelim, 2);
510 wb_mii_send(sc, frame->mii_opcode, 2);
511 wb_mii_send(sc, frame->mii_phyaddr, 5);
512 wb_mii_send(sc, frame->mii_regaddr, 5);
513 wb_mii_send(sc, frame->mii_turnaround, 2);
514 wb_mii_send(sc, frame->mii_data, 16);
515
516 /* Idle bit. */
517 SIO_SET(WB_SIO_MII_CLK);
518 DELAY(1);
519 SIO_CLR(WB_SIO_MII_CLK);
520 DELAY(1);
521
522 /*
523 * Turn off xmit.
524 */
525 SIO_CLR(WB_SIO_MII_DIR);
526
527 splx(s);
528
529 return(0);
530}
531
532static int wb_miibus_readreg(dev, phy, reg)
533 device_t dev;
534 int phy, reg;
535{
536 struct wb_softc *sc;
537 struct wb_mii_frame frame;
538
539 sc = device_get_softc(dev);
540
541 bzero((char *)&frame, sizeof(frame));
542
543 frame.mii_phyaddr = phy;
544 frame.mii_regaddr = reg;
545 wb_mii_readreg(sc, &frame);
546
547 return(frame.mii_data);
548}
549
550static int wb_miibus_writereg(dev, phy, reg, data)
551 device_t dev;
552 int phy, reg, data;
553{
554 struct wb_softc *sc;
555 struct wb_mii_frame frame;
556
557 sc = device_get_softc(dev);
558
559 bzero((char *)&frame, sizeof(frame));
560
561 frame.mii_phyaddr = phy;
562 frame.mii_regaddr = reg;
563 frame.mii_data = data;
564
565 wb_mii_writereg(sc, &frame);
566
567 return(0);
568}
569
570static void wb_miibus_statchg(dev)
571 device_t dev;
572{
573 struct wb_softc *sc;
574 struct mii_data *mii;
575
576 sc = device_get_softc(dev);
577 mii = device_get_softc(sc->wb_miibus);
578 wb_setcfg(sc, mii->mii_media_active);
579
580 return;
581}
582
583static u_int8_t wb_calchash(addr)
584 caddr_t addr;
585{
586 u_int32_t crc, carry;
587 int i, j;
588 u_int8_t c;
589
590 /* Compute CRC for the address value. */
591 crc = 0xFFFFFFFF; /* initial value */
592
593 for (i = 0; i < 6; i++) {
594 c = *(addr + i);
595 for (j = 0; j < 8; j++) {
596 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
597 crc <<= 1;
598 c >>= 1;
599 if (carry)
600 crc = (crc ^ 0x04c11db6) | carry;
601 }
602 }
603
604 /*
605 * return the filter bit position
606 * Note: I arrived at the following nonsense
607 * through experimentation. It's not the usual way to
608 * generate the bit position but it's the only thing
609 * I could come up with that works.
610 */
611 return(~(crc >> 26) & 0x0000003F);
612}
613
614/*
615 * Program the 64-bit multicast hash filter.
616 */
617static void wb_setmulti(sc)
618 struct wb_softc *sc;
619{
620 struct ifnet *ifp;
621 int h = 0;
622 u_int32_t hashes[2] = { 0, 0 };
623 struct ifmultiaddr *ifma;
624 u_int32_t rxfilt;
625 int mcnt = 0;
626
627 ifp = &sc->arpcom.ac_if;
628
629 rxfilt = CSR_READ_4(sc, WB_NETCFG);
630
631 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
632 rxfilt |= WB_NETCFG_RX_MULTI;
633 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
634 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
635 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
636 return;
637 }
638
639 /* first, zot all the existing hash bits */
640 CSR_WRITE_4(sc, WB_MAR0, 0);
641 CSR_WRITE_4(sc, WB_MAR1, 0);
642
643 /* now program new ones */
644 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
645 ifma = ifma->ifma_link.le_next) {
646 if (ifma->ifma_addr->sa_family != AF_LINK)
647 continue;
648 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
649 if (h < 32)
650 hashes[0] |= (1 << h);
651 else
652 hashes[1] |= (1 << (h - 32));
653 mcnt++;
654 }
655
656 if (mcnt)
657 rxfilt |= WB_NETCFG_RX_MULTI;
658 else
659 rxfilt &= ~WB_NETCFG_RX_MULTI;
660
661 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
662 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
663 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
664
665 return;
666}
667
668/*
669 * The Winbond manual states that in order to fiddle with the
670 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
671 * first have to put the transmit and/or receive logic in the idle state.
672 */
673static void wb_setcfg(sc, media)
674 struct wb_softc *sc;
675 u_int32_t media;
676{
677 int i, restart = 0;
678
679 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
680 restart = 1;
681 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
682
683 for (i = 0; i < WB_TIMEOUT; i++) {
684 DELAY(10);
685 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
686 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
687 break;
688 }
689
690 if (i == WB_TIMEOUT)
691 printf("wb%d: failed to force tx and "
692 "rx to idle state\n", sc->wb_unit);
693 }
694
695 if (IFM_SUBTYPE(media) == IFM_10_T)
696 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
697 else
698 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
699
700 if ((media & IFM_GMASK) == IFM_FDX)
701 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
702 else
703 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
704
705 if (restart)
706 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
707
708 return;
709}
710
711static void wb_reset(sc)
712 struct wb_softc *sc;
713{
714 register int i;
715 struct mii_data *mii;
716
717 CSR_WRITE_4(sc, WB_NETCFG, 0);
718 CSR_WRITE_4(sc, WB_BUSCTL, 0);
719 CSR_WRITE_4(sc, WB_TXADDR, 0);
720 CSR_WRITE_4(sc, WB_RXADDR, 0);
721
722 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
723 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
724
725 for (i = 0; i < WB_TIMEOUT; i++) {
726 DELAY(10);
727 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
728 break;
729 }
730 if (i == WB_TIMEOUT)
731 printf("wb%d: reset never completed!\n", sc->wb_unit);
732
733 /* Wait a little while for the chip to get its brains in order. */
734 DELAY(1000);
735
736 if (sc->wb_miibus == NULL)
737 return;
738
739 mii = device_get_softc(sc->wb_miibus);
740 if (mii == NULL)
741 return;
742
743 if (mii->mii_instance) {
744 struct mii_softc *miisc;
745 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
746 miisc = LIST_NEXT(miisc, mii_list))
747 mii_phy_reset(miisc);
748 }
749
750 return;
751}
752
753static void wb_fixmedia(sc)
754 struct wb_softc *sc;
755{
756 struct mii_data *mii = NULL;
757 struct ifnet *ifp;
758 u_int32_t media;
759
760 if (sc->wb_miibus == NULL)
761 return;
762
763 mii = device_get_softc(sc->wb_miibus);
764 ifp = &sc->arpcom.ac_if;
765
766 mii_pollstat(mii);
767 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
768 media = mii->mii_media_active & ~IFM_10_T;
769 media |= IFM_100_TX;
770 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
771 media = mii->mii_media_active & ~IFM_100_TX;
772 media |= IFM_10_T;
773 } else
774 return;
775
776 ifmedia_set(&mii->mii_media, media);
777
778 return;
779}
780
781/*
782 * Probe for a Winbond chip. Check the PCI vendor and device
783 * IDs against our list and return a device name if we find a match.
784 */
785static int wb_probe(dev)
786 device_t dev;
787{
788 struct wb_type *t;
789
790 t = wb_devs;
791
792 while(t->wb_name != NULL) {
793 if ((pci_get_vendor(dev) == t->wb_vid) &&
794 (pci_get_device(dev) == t->wb_did)) {
795 device_set_desc(dev, t->wb_name);
796 return(0);
797 }
798 t++;
799 }
800
801 return(ENXIO);
802}
803
804/*
805 * Attach the interface. Allocate softc structures, do ifmedia
806 * setup and ethernet/BPF attach.
807 */
808static int wb_attach(dev)
809 device_t dev;
810{
811 int s;
812 u_char eaddr[ETHER_ADDR_LEN];
813 u_int32_t command;
814 struct wb_softc *sc;
815 struct ifnet *ifp;
816 int unit, error = 0, rid;
817
818 s = splimp();
819
820 sc = device_get_softc(dev);
821 unit = device_get_unit(dev);
822
823 /*
824 * Handle power management nonsense.
825 */
826
827 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF;
828 if (command == 0x01) {
829
830 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4);
831 if (command & WB_PSTATE_MASK) {
832 u_int32_t iobase, membase, irq;
833
834 /* Save important PCI config data. */
835 iobase = pci_read_config(dev, WB_PCI_LOIO, 4);
836 membase = pci_read_config(dev, WB_PCI_LOMEM, 4);
837 irq = pci_read_config(dev, WB_PCI_INTLINE, 4);
838
839 /* Reset the power state. */
840 printf("wb%d: chip is in D%d power mode "
841 "-- setting to D0\n", unit, command & WB_PSTATE_MASK);
842 command &= 0xFFFFFFFC;
843 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4);
844
845 /* Restore PCI config data. */
846 pci_write_config(dev, WB_PCI_LOIO, iobase, 4);
847 pci_write_config(dev, WB_PCI_LOMEM, membase, 4);
848 pci_write_config(dev, WB_PCI_INTLINE, irq, 4);
849 }
850 }
851
852 /*
853 * Map control/status registers.
854 */
855 command = pci_read_config(dev, PCIR_COMMAND, 4);
856 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
857 pci_write_config(dev, PCIR_COMMAND, command, 4);
858 command = pci_read_config(dev, PCIR_COMMAND, 4);
859
860#ifdef WB_USEIOSPACE
861 if (!(command & PCIM_CMD_PORTEN)) {
862 printf("wb%d: failed to enable I/O ports!\n", unit);
863 error = ENXIO;
864 goto fail;
865 }
866#else
867 if (!(command & PCIM_CMD_MEMEN)) {
868 printf("wb%d: failed to enable memory mapping!\n", unit);
869 error = ENXIO;
870 goto fail;
871 }
872#endif
873
874 rid = WB_RID;
875 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid,
876 0, ~0, 1, RF_ACTIVE);
877
878 if (sc->wb_res == NULL) {
879 printf("wb%d: couldn't map ports/memory\n", unit);
880 error = ENXIO;
881 goto fail;
882 }
883
884 sc->wb_btag = rman_get_bustag(sc->wb_res);
885 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
886
887 /* Allocate interrupt */
888 rid = 0;
889 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
890 RF_SHAREABLE | RF_ACTIVE);
891
892 if (sc->wb_irq == NULL) {
893 printf("wb%d: couldn't map interrupt\n", unit);
894 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
895 error = ENXIO;
896 goto fail;
897 }
898
899 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET,
900 wb_intr, sc, &sc->wb_intrhand);
901
902 if (error) {
903 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
904 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
905 printf("wb%d: couldn't set up irq\n", unit);
906 goto fail;
907 }
908
909 /* Save the cache line size. */
910 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
911
912 /* Reset the adapter. */
913 wb_reset(sc);
914
915 /*
916 * Get station address from the EEPROM.
917 */
918 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
919
920 /*
921 * A Winbond chip was detected. Inform the world.
922 */
923 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":");
924
925 sc->wb_unit = unit;
926 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
927
928 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
929 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
930
931 if (sc->wb_ldata == NULL) {
932 printf("wb%d: no memory for list buffers!\n", unit);
933 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
934 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
935 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
936 error = ENXIO;
937 goto fail;
938 }
939
940 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
941
942 ifp = &sc->arpcom.ac_if;
943 ifp->if_softc = sc;
944 ifp->if_unit = unit;
945 ifp->if_name = "wb";
946 ifp->if_mtu = ETHERMTU;
947 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
948 ifp->if_ioctl = wb_ioctl;
949 ifp->if_output = ether_output;
950 ifp->if_start = wb_start;
951 ifp->if_watchdog = wb_watchdog;
952 ifp->if_init = wb_init;
953 ifp->if_baudrate = 10000000;
954 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
955
956 /*
957 * Do MII setup.
958 */
959 if (mii_phy_probe(dev, &sc->wb_miibus,
960 wb_ifmedia_upd, wb_ifmedia_sts)) {
961 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
962 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
963 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
964 free(sc->wb_ldata_ptr, M_DEVBUF);
965 error = ENXIO;
966 goto fail;
967 }
968
969 /*
| 133#endif
134
135/*
136 * Various supported device vendors/types and their names.
137 */
138static struct wb_type wb_devs[] = {
139 { WB_VENDORID, WB_DEVICEID_840F,
140 "Winbond W89C840F 10/100BaseTX" },
141 { CP_VENDORID, CP_DEVICEID_RL100,
142 "Compex RL100-ATX 10/100baseTX" },
143 { 0, 0, NULL }
144};
145
146static int wb_probe __P((device_t));
147static int wb_attach __P((device_t));
148static int wb_detach __P((device_t));
149
150static void wb_bfree __P((caddr_t, u_int));
151static int wb_newbuf __P((struct wb_softc *,
152 struct wb_chain_onefrag *,
153 struct mbuf *));
154static int wb_encap __P((struct wb_softc *, struct wb_chain *,
155 struct mbuf *));
156
157static void wb_rxeof __P((struct wb_softc *));
158static void wb_rxeoc __P((struct wb_softc *));
159static void wb_txeof __P((struct wb_softc *));
160static void wb_txeoc __P((struct wb_softc *));
161static void wb_intr __P((void *));
162static void wb_tick __P((void *));
163static void wb_start __P((struct ifnet *));
164static int wb_ioctl __P((struct ifnet *, u_long, caddr_t));
165static void wb_init __P((void *));
166static void wb_stop __P((struct wb_softc *));
167static void wb_watchdog __P((struct ifnet *));
168static void wb_shutdown __P((device_t));
169static int wb_ifmedia_upd __P((struct ifnet *));
170static void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
171
172static void wb_eeprom_putbyte __P((struct wb_softc *, int));
173static void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *));
174static void wb_read_eeprom __P((struct wb_softc *, caddr_t, int,
175 int, int));
176static void wb_mii_sync __P((struct wb_softc *));
177static void wb_mii_send __P((struct wb_softc *, u_int32_t, int));
178static int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *));
179static int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *));
180
181static void wb_setcfg __P((struct wb_softc *, u_int32_t));
182static u_int8_t wb_calchash __P((caddr_t));
183static void wb_setmulti __P((struct wb_softc *));
184static void wb_reset __P((struct wb_softc *));
185static void wb_fixmedia __P((struct wb_softc *));
186static int wb_list_rx_init __P((struct wb_softc *));
187static int wb_list_tx_init __P((struct wb_softc *));
188
189static int wb_miibus_readreg __P((device_t, int, int));
190static int wb_miibus_writereg __P((device_t, int, int, int));
191static void wb_miibus_statchg __P((device_t));
192
193#ifdef WB_USEIOSPACE
194#define WB_RES SYS_RES_IOPORT
195#define WB_RID WB_PCI_LOIO
196#else
197#define WB_RES SYS_RES_MEMORY
198#define WB_RID WB_PCI_LOMEM
199#endif
200
201static device_method_t wb_methods[] = {
202 /* Device interface */
203 DEVMETHOD(device_probe, wb_probe),
204 DEVMETHOD(device_attach, wb_attach),
205 DEVMETHOD(device_detach, wb_detach),
206 DEVMETHOD(device_shutdown, wb_shutdown),
207
208 /* bus interface, for miibus */
209 DEVMETHOD(bus_print_child, bus_generic_print_child),
210 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
211
212 /* MII interface */
213 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
214 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
215 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
216 { 0, 0 }
217};
218
219static driver_t wb_driver = {
220 "wb",
221 wb_methods,
222 sizeof(struct wb_softc)
223};
224
225static devclass_t wb_devclass;
226
227DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0);
228DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
229
230#define WB_SETBIT(sc, reg, x) \
231 CSR_WRITE_4(sc, reg, \
232 CSR_READ_4(sc, reg) | x)
233
234#define WB_CLRBIT(sc, reg, x) \
235 CSR_WRITE_4(sc, reg, \
236 CSR_READ_4(sc, reg) & ~x)
237
238#define SIO_SET(x) \
239 CSR_WRITE_4(sc, WB_SIO, \
240 CSR_READ_4(sc, WB_SIO) | x)
241
242#define SIO_CLR(x) \
243 CSR_WRITE_4(sc, WB_SIO, \
244 CSR_READ_4(sc, WB_SIO) & ~x)
245
246/*
247 * Send a read command and address to the EEPROM, check for ACK.
248 */
249static void wb_eeprom_putbyte(sc, addr)
250 struct wb_softc *sc;
251 int addr;
252{
253 register int d, i;
254
255 d = addr | WB_EECMD_READ;
256
257 /*
258 * Feed in each bit and stobe the clock.
259 */
260 for (i = 0x400; i; i >>= 1) {
261 if (d & i) {
262 SIO_SET(WB_SIO_EE_DATAIN);
263 } else {
264 SIO_CLR(WB_SIO_EE_DATAIN);
265 }
266 DELAY(100);
267 SIO_SET(WB_SIO_EE_CLK);
268 DELAY(150);
269 SIO_CLR(WB_SIO_EE_CLK);
270 DELAY(100);
271 }
272
273 return;
274}
275
276/*
277 * Read a word of data stored in the EEPROM at address 'addr.'
278 */
279static void wb_eeprom_getword(sc, addr, dest)
280 struct wb_softc *sc;
281 int addr;
282 u_int16_t *dest;
283{
284 register int i;
285 u_int16_t word = 0;
286
287 /* Enter EEPROM access mode. */
288 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
289
290 /*
291 * Send address of word we want to read.
292 */
293 wb_eeprom_putbyte(sc, addr);
294
295 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
296
297 /*
298 * Start reading bits from EEPROM.
299 */
300 for (i = 0x8000; i; i >>= 1) {
301 SIO_SET(WB_SIO_EE_CLK);
302 DELAY(100);
303 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
304 word |= i;
305 SIO_CLR(WB_SIO_EE_CLK);
306 DELAY(100);
307 }
308
309 /* Turn off EEPROM access mode. */
310 CSR_WRITE_4(sc, WB_SIO, 0);
311
312 *dest = word;
313
314 return;
315}
316
317/*
318 * Read a sequence of words from the EEPROM.
319 */
320static void wb_read_eeprom(sc, dest, off, cnt, swap)
321 struct wb_softc *sc;
322 caddr_t dest;
323 int off;
324 int cnt;
325 int swap;
326{
327 int i;
328 u_int16_t word = 0, *ptr;
329
330 for (i = 0; i < cnt; i++) {
331 wb_eeprom_getword(sc, off + i, &word);
332 ptr = (u_int16_t *)(dest + (i * 2));
333 if (swap)
334 *ptr = ntohs(word);
335 else
336 *ptr = word;
337 }
338
339 return;
340}
341
342/*
343 * Sync the PHYs by setting data bit and strobing the clock 32 times.
344 */
345static void wb_mii_sync(sc)
346 struct wb_softc *sc;
347{
348 register int i;
349
350 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
351
352 for (i = 0; i < 32; i++) {
353 SIO_SET(WB_SIO_MII_CLK);
354 DELAY(1);
355 SIO_CLR(WB_SIO_MII_CLK);
356 DELAY(1);
357 }
358
359 return;
360}
361
362/*
363 * Clock a series of bits through the MII.
364 */
365static void wb_mii_send(sc, bits, cnt)
366 struct wb_softc *sc;
367 u_int32_t bits;
368 int cnt;
369{
370 int i;
371
372 SIO_CLR(WB_SIO_MII_CLK);
373
374 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
375 if (bits & i) {
376 SIO_SET(WB_SIO_MII_DATAIN);
377 } else {
378 SIO_CLR(WB_SIO_MII_DATAIN);
379 }
380 DELAY(1);
381 SIO_CLR(WB_SIO_MII_CLK);
382 DELAY(1);
383 SIO_SET(WB_SIO_MII_CLK);
384 }
385}
386
387/*
388 * Read an PHY register through the MII.
389 */
390static int wb_mii_readreg(sc, frame)
391 struct wb_softc *sc;
392 struct wb_mii_frame *frame;
393
394{
395 int i, ack, s;
396
397 s = splimp();
398
399 /*
400 * Set up frame for RX.
401 */
402 frame->mii_stdelim = WB_MII_STARTDELIM;
403 frame->mii_opcode = WB_MII_READOP;
404 frame->mii_turnaround = 0;
405 frame->mii_data = 0;
406
407 CSR_WRITE_4(sc, WB_SIO, 0);
408
409 /*
410 * Turn on data xmit.
411 */
412 SIO_SET(WB_SIO_MII_DIR);
413
414 wb_mii_sync(sc);
415
416 /*
417 * Send command/address info.
418 */
419 wb_mii_send(sc, frame->mii_stdelim, 2);
420 wb_mii_send(sc, frame->mii_opcode, 2);
421 wb_mii_send(sc, frame->mii_phyaddr, 5);
422 wb_mii_send(sc, frame->mii_regaddr, 5);
423
424 /* Idle bit */
425 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
426 DELAY(1);
427 SIO_SET(WB_SIO_MII_CLK);
428 DELAY(1);
429
430 /* Turn off xmit. */
431 SIO_CLR(WB_SIO_MII_DIR);
432 /* Check for ack */
433 SIO_CLR(WB_SIO_MII_CLK);
434 DELAY(1);
435 SIO_SET(WB_SIO_MII_CLK);
436 DELAY(1);
437 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
438 SIO_CLR(WB_SIO_MII_CLK);
439 DELAY(1);
440 SIO_SET(WB_SIO_MII_CLK);
441 DELAY(1);
442
443 /*
444 * Now try reading data bits. If the ack failed, we still
445 * need to clock through 16 cycles to keep the PHY(s) in sync.
446 */
447 if (ack) {
448 for(i = 0; i < 16; i++) {
449 SIO_CLR(WB_SIO_MII_CLK);
450 DELAY(1);
451 SIO_SET(WB_SIO_MII_CLK);
452 DELAY(1);
453 }
454 goto fail;
455 }
456
457 for (i = 0x8000; i; i >>= 1) {
458 SIO_CLR(WB_SIO_MII_CLK);
459 DELAY(1);
460 if (!ack) {
461 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
462 frame->mii_data |= i;
463 DELAY(1);
464 }
465 SIO_SET(WB_SIO_MII_CLK);
466 DELAY(1);
467 }
468
469fail:
470
471 SIO_CLR(WB_SIO_MII_CLK);
472 DELAY(1);
473 SIO_SET(WB_SIO_MII_CLK);
474 DELAY(1);
475
476 splx(s);
477
478 if (ack)
479 return(1);
480 return(0);
481}
482
483/*
484 * Write to a PHY register through the MII.
485 */
486static int wb_mii_writereg(sc, frame)
487 struct wb_softc *sc;
488 struct wb_mii_frame *frame;
489
490{
491 int s;
492
493 s = splimp();
494 /*
495 * Set up frame for TX.
496 */
497
498 frame->mii_stdelim = WB_MII_STARTDELIM;
499 frame->mii_opcode = WB_MII_WRITEOP;
500 frame->mii_turnaround = WB_MII_TURNAROUND;
501
502 /*
503 * Turn on data output.
504 */
505 SIO_SET(WB_SIO_MII_DIR);
506
507 wb_mii_sync(sc);
508
509 wb_mii_send(sc, frame->mii_stdelim, 2);
510 wb_mii_send(sc, frame->mii_opcode, 2);
511 wb_mii_send(sc, frame->mii_phyaddr, 5);
512 wb_mii_send(sc, frame->mii_regaddr, 5);
513 wb_mii_send(sc, frame->mii_turnaround, 2);
514 wb_mii_send(sc, frame->mii_data, 16);
515
516 /* Idle bit. */
517 SIO_SET(WB_SIO_MII_CLK);
518 DELAY(1);
519 SIO_CLR(WB_SIO_MII_CLK);
520 DELAY(1);
521
522 /*
523 * Turn off xmit.
524 */
525 SIO_CLR(WB_SIO_MII_DIR);
526
527 splx(s);
528
529 return(0);
530}
531
532static int wb_miibus_readreg(dev, phy, reg)
533 device_t dev;
534 int phy, reg;
535{
536 struct wb_softc *sc;
537 struct wb_mii_frame frame;
538
539 sc = device_get_softc(dev);
540
541 bzero((char *)&frame, sizeof(frame));
542
543 frame.mii_phyaddr = phy;
544 frame.mii_regaddr = reg;
545 wb_mii_readreg(sc, &frame);
546
547 return(frame.mii_data);
548}
549
550static int wb_miibus_writereg(dev, phy, reg, data)
551 device_t dev;
552 int phy, reg, data;
553{
554 struct wb_softc *sc;
555 struct wb_mii_frame frame;
556
557 sc = device_get_softc(dev);
558
559 bzero((char *)&frame, sizeof(frame));
560
561 frame.mii_phyaddr = phy;
562 frame.mii_regaddr = reg;
563 frame.mii_data = data;
564
565 wb_mii_writereg(sc, &frame);
566
567 return(0);
568}
569
570static void wb_miibus_statchg(dev)
571 device_t dev;
572{
573 struct wb_softc *sc;
574 struct mii_data *mii;
575
576 sc = device_get_softc(dev);
577 mii = device_get_softc(sc->wb_miibus);
578 wb_setcfg(sc, mii->mii_media_active);
579
580 return;
581}
582
583static u_int8_t wb_calchash(addr)
584 caddr_t addr;
585{
586 u_int32_t crc, carry;
587 int i, j;
588 u_int8_t c;
589
590 /* Compute CRC for the address value. */
591 crc = 0xFFFFFFFF; /* initial value */
592
593 for (i = 0; i < 6; i++) {
594 c = *(addr + i);
595 for (j = 0; j < 8; j++) {
596 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
597 crc <<= 1;
598 c >>= 1;
599 if (carry)
600 crc = (crc ^ 0x04c11db6) | carry;
601 }
602 }
603
604 /*
605 * return the filter bit position
606 * Note: I arrived at the following nonsense
607 * through experimentation. It's not the usual way to
608 * generate the bit position but it's the only thing
609 * I could come up with that works.
610 */
611 return(~(crc >> 26) & 0x0000003F);
612}
613
614/*
615 * Program the 64-bit multicast hash filter.
616 */
617static void wb_setmulti(sc)
618 struct wb_softc *sc;
619{
620 struct ifnet *ifp;
621 int h = 0;
622 u_int32_t hashes[2] = { 0, 0 };
623 struct ifmultiaddr *ifma;
624 u_int32_t rxfilt;
625 int mcnt = 0;
626
627 ifp = &sc->arpcom.ac_if;
628
629 rxfilt = CSR_READ_4(sc, WB_NETCFG);
630
631 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
632 rxfilt |= WB_NETCFG_RX_MULTI;
633 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
634 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
635 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
636 return;
637 }
638
639 /* first, zot all the existing hash bits */
640 CSR_WRITE_4(sc, WB_MAR0, 0);
641 CSR_WRITE_4(sc, WB_MAR1, 0);
642
643 /* now program new ones */
644 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
645 ifma = ifma->ifma_link.le_next) {
646 if (ifma->ifma_addr->sa_family != AF_LINK)
647 continue;
648 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
649 if (h < 32)
650 hashes[0] |= (1 << h);
651 else
652 hashes[1] |= (1 << (h - 32));
653 mcnt++;
654 }
655
656 if (mcnt)
657 rxfilt |= WB_NETCFG_RX_MULTI;
658 else
659 rxfilt &= ~WB_NETCFG_RX_MULTI;
660
661 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
662 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
663 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
664
665 return;
666}
667
668/*
669 * The Winbond manual states that in order to fiddle with the
670 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
671 * first have to put the transmit and/or receive logic in the idle state.
672 */
673static void wb_setcfg(sc, media)
674 struct wb_softc *sc;
675 u_int32_t media;
676{
677 int i, restart = 0;
678
679 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
680 restart = 1;
681 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
682
683 for (i = 0; i < WB_TIMEOUT; i++) {
684 DELAY(10);
685 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
686 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
687 break;
688 }
689
690 if (i == WB_TIMEOUT)
691 printf("wb%d: failed to force tx and "
692 "rx to idle state\n", sc->wb_unit);
693 }
694
695 if (IFM_SUBTYPE(media) == IFM_10_T)
696 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
697 else
698 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
699
700 if ((media & IFM_GMASK) == IFM_FDX)
701 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
702 else
703 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
704
705 if (restart)
706 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
707
708 return;
709}
710
711static void wb_reset(sc)
712 struct wb_softc *sc;
713{
714 register int i;
715 struct mii_data *mii;
716
717 CSR_WRITE_4(sc, WB_NETCFG, 0);
718 CSR_WRITE_4(sc, WB_BUSCTL, 0);
719 CSR_WRITE_4(sc, WB_TXADDR, 0);
720 CSR_WRITE_4(sc, WB_RXADDR, 0);
721
722 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
723 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
724
725 for (i = 0; i < WB_TIMEOUT; i++) {
726 DELAY(10);
727 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
728 break;
729 }
730 if (i == WB_TIMEOUT)
731 printf("wb%d: reset never completed!\n", sc->wb_unit);
732
733 /* Wait a little while for the chip to get its brains in order. */
734 DELAY(1000);
735
736 if (sc->wb_miibus == NULL)
737 return;
738
739 mii = device_get_softc(sc->wb_miibus);
740 if (mii == NULL)
741 return;
742
743 if (mii->mii_instance) {
744 struct mii_softc *miisc;
745 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
746 miisc = LIST_NEXT(miisc, mii_list))
747 mii_phy_reset(miisc);
748 }
749
750 return;
751}
752
753static void wb_fixmedia(sc)
754 struct wb_softc *sc;
755{
756 struct mii_data *mii = NULL;
757 struct ifnet *ifp;
758 u_int32_t media;
759
760 if (sc->wb_miibus == NULL)
761 return;
762
763 mii = device_get_softc(sc->wb_miibus);
764 ifp = &sc->arpcom.ac_if;
765
766 mii_pollstat(mii);
767 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
768 media = mii->mii_media_active & ~IFM_10_T;
769 media |= IFM_100_TX;
770 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
771 media = mii->mii_media_active & ~IFM_100_TX;
772 media |= IFM_10_T;
773 } else
774 return;
775
776 ifmedia_set(&mii->mii_media, media);
777
778 return;
779}
780
781/*
782 * Probe for a Winbond chip. Check the PCI vendor and device
783 * IDs against our list and return a device name if we find a match.
784 */
785static int wb_probe(dev)
786 device_t dev;
787{
788 struct wb_type *t;
789
790 t = wb_devs;
791
792 while(t->wb_name != NULL) {
793 if ((pci_get_vendor(dev) == t->wb_vid) &&
794 (pci_get_device(dev) == t->wb_did)) {
795 device_set_desc(dev, t->wb_name);
796 return(0);
797 }
798 t++;
799 }
800
801 return(ENXIO);
802}
803
804/*
805 * Attach the interface. Allocate softc structures, do ifmedia
806 * setup and ethernet/BPF attach.
807 */
808static int wb_attach(dev)
809 device_t dev;
810{
811 int s;
812 u_char eaddr[ETHER_ADDR_LEN];
813 u_int32_t command;
814 struct wb_softc *sc;
815 struct ifnet *ifp;
816 int unit, error = 0, rid;
817
818 s = splimp();
819
820 sc = device_get_softc(dev);
821 unit = device_get_unit(dev);
822
823 /*
824 * Handle power management nonsense.
825 */
826
827 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF;
828 if (command == 0x01) {
829
830 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4);
831 if (command & WB_PSTATE_MASK) {
832 u_int32_t iobase, membase, irq;
833
834 /* Save important PCI config data. */
835 iobase = pci_read_config(dev, WB_PCI_LOIO, 4);
836 membase = pci_read_config(dev, WB_PCI_LOMEM, 4);
837 irq = pci_read_config(dev, WB_PCI_INTLINE, 4);
838
839 /* Reset the power state. */
840 printf("wb%d: chip is in D%d power mode "
841 "-- setting to D0\n", unit, command & WB_PSTATE_MASK);
842 command &= 0xFFFFFFFC;
843 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4);
844
845 /* Restore PCI config data. */
846 pci_write_config(dev, WB_PCI_LOIO, iobase, 4);
847 pci_write_config(dev, WB_PCI_LOMEM, membase, 4);
848 pci_write_config(dev, WB_PCI_INTLINE, irq, 4);
849 }
850 }
851
852 /*
853 * Map control/status registers.
854 */
855 command = pci_read_config(dev, PCIR_COMMAND, 4);
856 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
857 pci_write_config(dev, PCIR_COMMAND, command, 4);
858 command = pci_read_config(dev, PCIR_COMMAND, 4);
859
860#ifdef WB_USEIOSPACE
861 if (!(command & PCIM_CMD_PORTEN)) {
862 printf("wb%d: failed to enable I/O ports!\n", unit);
863 error = ENXIO;
864 goto fail;
865 }
866#else
867 if (!(command & PCIM_CMD_MEMEN)) {
868 printf("wb%d: failed to enable memory mapping!\n", unit);
869 error = ENXIO;
870 goto fail;
871 }
872#endif
873
874 rid = WB_RID;
875 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid,
876 0, ~0, 1, RF_ACTIVE);
877
878 if (sc->wb_res == NULL) {
879 printf("wb%d: couldn't map ports/memory\n", unit);
880 error = ENXIO;
881 goto fail;
882 }
883
884 sc->wb_btag = rman_get_bustag(sc->wb_res);
885 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
886
887 /* Allocate interrupt */
888 rid = 0;
889 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
890 RF_SHAREABLE | RF_ACTIVE);
891
892 if (sc->wb_irq == NULL) {
893 printf("wb%d: couldn't map interrupt\n", unit);
894 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
895 error = ENXIO;
896 goto fail;
897 }
898
899 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET,
900 wb_intr, sc, &sc->wb_intrhand);
901
902 if (error) {
903 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
904 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
905 printf("wb%d: couldn't set up irq\n", unit);
906 goto fail;
907 }
908
909 /* Save the cache line size. */
910 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
911
912 /* Reset the adapter. */
913 wb_reset(sc);
914
915 /*
916 * Get station address from the EEPROM.
917 */
918 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
919
920 /*
921 * A Winbond chip was detected. Inform the world.
922 */
923 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":");
924
925 sc->wb_unit = unit;
926 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
927
928 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
929 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
930
931 if (sc->wb_ldata == NULL) {
932 printf("wb%d: no memory for list buffers!\n", unit);
933 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
934 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
935 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
936 error = ENXIO;
937 goto fail;
938 }
939
940 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
941
942 ifp = &sc->arpcom.ac_if;
943 ifp->if_softc = sc;
944 ifp->if_unit = unit;
945 ifp->if_name = "wb";
946 ifp->if_mtu = ETHERMTU;
947 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
948 ifp->if_ioctl = wb_ioctl;
949 ifp->if_output = ether_output;
950 ifp->if_start = wb_start;
951 ifp->if_watchdog = wb_watchdog;
952 ifp->if_init = wb_init;
953 ifp->if_baudrate = 10000000;
954 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
955
956 /*
957 * Do MII setup.
958 */
959 if (mii_phy_probe(dev, &sc->wb_miibus,
960 wb_ifmedia_upd, wb_ifmedia_sts)) {
961 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
962 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
963 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
964 free(sc->wb_ldata_ptr, M_DEVBUF);
965 error = ENXIO;
966 goto fail;
967 }
968
969 /*
|
999
1000 /* Delete any miibus and phy devices attached to this interface */
1001 bus_generic_detach(dev);
1002 device_delete_child(dev, sc->wb_miibus);
1003
1004 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
1005 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
1006 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
1007
1008 free(sc->wb_ldata_ptr, M_DEVBUF);
1009
1010 splx(s);
1011
1012 return(0);
1013}
1014
1015/*
1016 * Initialize the transmit descriptors.
1017 */
1018static int wb_list_tx_init(sc)
1019 struct wb_softc *sc;
1020{
1021 struct wb_chain_data *cd;
1022 struct wb_list_data *ld;
1023 int i;
1024
1025 cd = &sc->wb_cdata;
1026 ld = sc->wb_ldata;
1027
1028 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1029 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
1030 if (i == (WB_TX_LIST_CNT - 1)) {
1031 cd->wb_tx_chain[i].wb_nextdesc =
1032 &cd->wb_tx_chain[0];
1033 } else {
1034 cd->wb_tx_chain[i].wb_nextdesc =
1035 &cd->wb_tx_chain[i + 1];
1036 }
1037 }
1038
1039 cd->wb_tx_free = &cd->wb_tx_chain[0];
1040 cd->wb_tx_tail = cd->wb_tx_head = NULL;
1041
1042 return(0);
1043}
1044
1045
1046/*
1047 * Initialize the RX descriptors and allocate mbufs for them. Note that
1048 * we arrange the descriptors in a closed ring, so that the last descriptor
1049 * points back to the first.
1050 */
1051static int wb_list_rx_init(sc)
1052 struct wb_softc *sc;
1053{
1054 struct wb_chain_data *cd;
1055 struct wb_list_data *ld;
1056 int i;
1057
1058 cd = &sc->wb_cdata;
1059 ld = sc->wb_ldata;
1060
1061 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1062 cd->wb_rx_chain[i].wb_ptr =
1063 (struct wb_desc *)&ld->wb_rx_list[i];
1064 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
1065 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
1066 return(ENOBUFS);
1067 if (i == (WB_RX_LIST_CNT - 1)) {
1068 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
1069 ld->wb_rx_list[i].wb_next =
1070 vtophys(&ld->wb_rx_list[0]);
1071 } else {
1072 cd->wb_rx_chain[i].wb_nextdesc =
1073 &cd->wb_rx_chain[i + 1];
1074 ld->wb_rx_list[i].wb_next =
1075 vtophys(&ld->wb_rx_list[i + 1]);
1076 }
1077 }
1078
1079 cd->wb_rx_head = &cd->wb_rx_chain[0];
1080
1081 return(0);
1082}
1083
1084static void wb_bfree(buf, size)
1085 caddr_t buf;
1086 u_int size;
1087{
1088 return;
1089}
1090
1091/*
1092 * Initialize an RX descriptor and attach an MBUF cluster.
1093 */
1094static int wb_newbuf(sc, c, m)
1095 struct wb_softc *sc;
1096 struct wb_chain_onefrag *c;
1097 struct mbuf *m;
1098{
1099 struct mbuf *m_new = NULL;
1100
1101 if (m == NULL) {
1102 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1103 if (m_new == NULL) {
1104 printf("wb%d: no memory for rx "
1105 "list -- packet dropped!\n", sc->wb_unit);
1106 return(ENOBUFS);
1107 }
1108
1109 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf;
1110 m_new->m_flags |= M_EXT;
1111 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
1112 m_new->m_len = WB_BUFBYTES;
1113 m_new->m_ext.ext_free = wb_bfree;
1114 m_new->m_ext.ext_ref = wb_bfree;
1115 } else {
1116 m_new = m;
1117 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
1118 m_new->m_data = m_new->m_ext.ext_buf;
1119 }
1120
1121 m_adj(m_new, sizeof(u_int64_t));
1122
1123 c->wb_mbuf = m_new;
1124 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
1125 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
1126 c->wb_ptr->wb_status = WB_RXSTAT;
1127
1128 return(0);
1129}
1130
1131/*
1132 * A frame has been uploaded: pass the resulting mbuf chain up to
1133 * the higher level protocols.
1134 */
1135static void wb_rxeof(sc)
1136 struct wb_softc *sc;
1137{
1138 struct ether_header *eh;
1139 struct mbuf *m = NULL;
1140 struct ifnet *ifp;
1141 struct wb_chain_onefrag *cur_rx;
1142 int total_len = 0;
1143 u_int32_t rxstat;
1144
1145 ifp = &sc->arpcom.ac_if;
1146
1147 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
1148 WB_RXSTAT_OWN)) {
1149 struct mbuf *m0 = NULL;
1150
1151 cur_rx = sc->wb_cdata.wb_rx_head;
1152 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
1153
1154 m = cur_rx->wb_mbuf;
1155
1156 if ((rxstat & WB_RXSTAT_MIIERR) ||
1157 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
1158 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
1159 !(rxstat & WB_RXSTAT_LASTFRAG) ||
1160 !(rxstat & WB_RXSTAT_RXCMP)) {
1161 ifp->if_ierrors++;
1162 wb_newbuf(sc, cur_rx, m);
1163 printf("wb%x: receiver babbling: possible chip "
1164 "bug, forcing reset\n", sc->wb_unit);
1165 wb_fixmedia(sc);
1166 wb_reset(sc);
1167 wb_init(sc);
1168 return;
1169 }
1170
1171 if (rxstat & WB_RXSTAT_RXERR) {
1172 ifp->if_ierrors++;
1173 wb_newbuf(sc, cur_rx, m);
1174 break;
1175 }
1176
1177 /* No errors; receive the packet. */
1178 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1179
1180 /*
1181 * XXX The Winbond chip includes the CRC with every
1182 * received frame, and there's no way to turn this
1183 * behavior off (at least, I can't find anything in
1184 * the manual that explains how to do it) so we have
1185 * to trim off the CRC manually.
1186 */
1187 total_len -= ETHER_CRC_LEN;
1188
1189 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1190 total_len + ETHER_ALIGN, 0, ifp, NULL);
1191 wb_newbuf(sc, cur_rx, m);
1192 if (m0 == NULL) {
1193 ifp->if_ierrors++;
1194 break;
1195 }
1196 m_adj(m0, ETHER_ALIGN);
1197 m = m0;
1198
1199 ifp->if_ipackets++;
1200 eh = mtod(m, struct ether_header *);
1201
1202 /* Remove header from mbuf and pass it on. */
1203 m_adj(m, sizeof(struct ether_header));
1204 ether_input(ifp, eh, m);
1205 }
1206}
1207
1208void wb_rxeoc(sc)
1209 struct wb_softc *sc;
1210{
1211 wb_rxeof(sc);
1212
1213 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1214 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1215 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1216 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1217 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1218
1219 return;
1220}
1221
1222/*
1223 * A frame was downloaded to the chip. It's safe for us to clean up
1224 * the list buffers.
1225 */
1226static void wb_txeof(sc)
1227 struct wb_softc *sc;
1228{
1229 struct wb_chain *cur_tx;
1230 struct ifnet *ifp;
1231
1232 ifp = &sc->arpcom.ac_if;
1233
1234 /* Clear the timeout timer. */
1235 ifp->if_timer = 0;
1236
1237 if (sc->wb_cdata.wb_tx_head == NULL)
1238 return;
1239
1240 /*
1241 * Go through our tx list and free mbufs for those
1242 * frames that have been transmitted.
1243 */
1244 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1245 u_int32_t txstat;
1246
1247 cur_tx = sc->wb_cdata.wb_tx_head;
1248 txstat = WB_TXSTATUS(cur_tx);
1249
1250 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1251 break;
1252
1253 if (txstat & WB_TXSTAT_TXERR) {
1254 ifp->if_oerrors++;
1255 if (txstat & WB_TXSTAT_ABORT)
1256 ifp->if_collisions++;
1257 if (txstat & WB_TXSTAT_LATECOLL)
1258 ifp->if_collisions++;
1259 }
1260
1261 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1262
1263 ifp->if_opackets++;
1264 m_freem(cur_tx->wb_mbuf);
1265 cur_tx->wb_mbuf = NULL;
1266
1267 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1268 sc->wb_cdata.wb_tx_head = NULL;
1269 sc->wb_cdata.wb_tx_tail = NULL;
1270 break;
1271 }
1272
1273 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1274 }
1275
1276 return;
1277}
1278
1279/*
1280 * TX 'end of channel' interrupt handler.
1281 */
1282static void wb_txeoc(sc)
1283 struct wb_softc *sc;
1284{
1285 struct ifnet *ifp;
1286
1287 ifp = &sc->arpcom.ac_if;
1288
1289 ifp->if_timer = 0;
1290
1291 if (sc->wb_cdata.wb_tx_head == NULL) {
1292 ifp->if_flags &= ~IFF_OACTIVE;
1293 sc->wb_cdata.wb_tx_tail = NULL;
1294 } else {
1295 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1296 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1297 ifp->if_timer = 5;
1298 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1299 }
1300 }
1301
1302 return;
1303}
1304
1305static void wb_intr(arg)
1306 void *arg;
1307{
1308 struct wb_softc *sc;
1309 struct ifnet *ifp;
1310 u_int32_t status;
1311
1312 sc = arg;
1313 ifp = &sc->arpcom.ac_if;
1314
1315 if (!(ifp->if_flags & IFF_UP))
1316 return;
1317
1318 /* Disable interrupts. */
1319 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1320
1321 for (;;) {
1322
1323 status = CSR_READ_4(sc, WB_ISR);
1324 if (status)
1325 CSR_WRITE_4(sc, WB_ISR, status);
1326
1327 if ((status & WB_INTRS) == 0)
1328 break;
1329
1330 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1331 ifp->if_ierrors++;
1332 wb_reset(sc);
1333 if (status & WB_ISR_RX_ERR)
1334 wb_fixmedia(sc);
1335 wb_init(sc);
1336 continue;
1337 }
1338
1339 if (status & WB_ISR_RX_OK)
1340 wb_rxeof(sc);
1341
1342 if (status & WB_ISR_RX_IDLE)
1343 wb_rxeoc(sc);
1344
1345 if (status & WB_ISR_TX_OK)
1346 wb_txeof(sc);
1347
1348 if (status & WB_ISR_TX_NOBUF)
1349 wb_txeoc(sc);
1350
1351 if (status & WB_ISR_TX_IDLE) {
1352 wb_txeof(sc);
1353 if (sc->wb_cdata.wb_tx_head != NULL) {
1354 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1355 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1356 }
1357 }
1358
1359 if (status & WB_ISR_TX_UNDERRUN) {
1360 ifp->if_oerrors++;
1361 wb_txeof(sc);
1362 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1363 /* Jack up TX threshold */
1364 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1365 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1366 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1367 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1368 }
1369
1370 if (status & WB_ISR_BUS_ERR) {
1371 wb_reset(sc);
1372 wb_init(sc);
1373 }
1374
1375 }
1376
1377 /* Re-enable interrupts. */
1378 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1379
1380 if (ifp->if_snd.ifq_head != NULL) {
1381 wb_start(ifp);
1382 }
1383
1384 return;
1385}
1386
1387static void wb_tick(xsc)
1388 void *xsc;
1389{
1390 struct wb_softc *sc;
1391 struct mii_data *mii;
1392 int s;
1393
1394 s = splimp();
1395
1396 sc = xsc;
1397 mii = device_get_softc(sc->wb_miibus);
1398
1399 mii_tick(mii);
1400
1401 sc->wb_stat_ch = timeout(wb_tick, sc, hz);
1402
1403 splx(s);
1404
1405 return;
1406}
1407
1408/*
1409 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1410 * pointers to the fragment pointers.
1411 */
1412static int wb_encap(sc, c, m_head)
1413 struct wb_softc *sc;
1414 struct wb_chain *c;
1415 struct mbuf *m_head;
1416{
1417 int frag = 0;
1418 struct wb_desc *f = NULL;
1419 int total_len;
1420 struct mbuf *m;
1421
1422 /*
1423 * Start packing the mbufs in this chain into
1424 * the fragment pointers. Stop when we run out
1425 * of fragments or hit the end of the mbuf chain.
1426 */
1427 m = m_head;
1428 total_len = 0;
1429
1430 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1431 if (m->m_len != 0) {
1432 if (frag == WB_MAXFRAGS)
1433 break;
1434 total_len += m->m_len;
1435 f = &c->wb_ptr->wb_frag[frag];
1436 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1437 if (frag == 0) {
1438 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1439 f->wb_status = 0;
1440 } else
1441 f->wb_status = WB_TXSTAT_OWN;
1442 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1443 f->wb_data = vtophys(mtod(m, vm_offset_t));
1444 frag++;
1445 }
1446 }
1447
1448 /*
1449 * Handle special case: we used up all 16 fragments,
1450 * but we have more mbufs left in the chain. Copy the
1451 * data into an mbuf cluster. Note that we don't
1452 * bother clearing the values in the other fragment
1453 * pointers/counters; it wouldn't gain us anything,
1454 * and would waste cycles.
1455 */
1456 if (m != NULL) {
1457 struct mbuf *m_new = NULL;
1458
1459 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1460 if (m_new == NULL) {
1461 printf("wb%d: no memory for tx list", sc->wb_unit);
1462 return(1);
1463 }
1464 if (m_head->m_pkthdr.len > MHLEN) {
1465 MCLGET(m_new, M_DONTWAIT);
1466 if (!(m_new->m_flags & M_EXT)) {
1467 m_freem(m_new);
1468 printf("wb%d: no memory for tx list",
1469 sc->wb_unit);
1470 return(1);
1471 }
1472 }
1473 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1474 mtod(m_new, caddr_t));
1475 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1476 m_freem(m_head);
1477 m_head = m_new;
1478 f = &c->wb_ptr->wb_frag[0];
1479 f->wb_status = 0;
1480 f->wb_data = vtophys(mtod(m_new, caddr_t));
1481 f->wb_ctl = total_len = m_new->m_len;
1482 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1483 frag = 1;
1484 }
1485
1486 if (total_len < WB_MIN_FRAMELEN) {
1487 f = &c->wb_ptr->wb_frag[frag];
1488 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1489 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1490 f->wb_ctl |= WB_TXCTL_TLINK;
1491 f->wb_status = WB_TXSTAT_OWN;
1492 frag++;
1493 }
1494
1495 c->wb_mbuf = m_head;
1496 c->wb_lastdesc = frag - 1;
1497 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1498 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1499
1500 return(0);
1501}
1502
1503/*
1504 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1505 * to the mbuf data regions directly in the transmit lists. We also save a
1506 * copy of the pointers since the transmit list fragment pointers are
1507 * physical addresses.
1508 */
1509
1510static void wb_start(ifp)
1511 struct ifnet *ifp;
1512{
1513 struct wb_softc *sc;
1514 struct mbuf *m_head = NULL;
1515 struct wb_chain *cur_tx = NULL, *start_tx;
1516
1517 sc = ifp->if_softc;
1518
1519 /*
1520 * Check for an available queue slot. If there are none,
1521 * punt.
1522 */
1523 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1524 ifp->if_flags |= IFF_OACTIVE;
1525 return;
1526 }
1527
1528 start_tx = sc->wb_cdata.wb_tx_free;
1529
1530 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1531 IF_DEQUEUE(&ifp->if_snd, m_head);
1532 if (m_head == NULL)
1533 break;
1534
1535 /* Pick a descriptor off the free list. */
1536 cur_tx = sc->wb_cdata.wb_tx_free;
1537 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1538
1539 /* Pack the data into the descriptor. */
1540 wb_encap(sc, cur_tx, m_head);
1541
1542 if (cur_tx != start_tx)
1543 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1544
1545 /*
1546 * If there's a BPF listener, bounce a copy of this frame
1547 * to him.
1548 */
1549 if (ifp->if_bpf)
1550 bpf_mtap(ifp, cur_tx->wb_mbuf);
1551 }
1552
1553 /*
1554 * If there are no packets queued, bail.
1555 */
1556 if (cur_tx == NULL)
1557 return;
1558
1559 /*
1560 * Place the request for the upload interrupt
1561 * in the last descriptor in the chain. This way, if
1562 * we're chaining several packets at once, we'll only
1563 * get an interupt once for the whole chain rather than
1564 * once for each packet.
1565 */
1566 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1567 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1568 sc->wb_cdata.wb_tx_tail = cur_tx;
1569
1570 if (sc->wb_cdata.wb_tx_head == NULL) {
1571 sc->wb_cdata.wb_tx_head = start_tx;
1572 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1573 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1574 } else {
1575 /*
1576 * We need to distinguish between the case where
1577 * the own bit is clear because the chip cleared it
1578 * and where the own bit is clear because we haven't
1579 * set it yet. The magic value WB_UNSET is just some
1580 * ramdomly chosen number which doesn't have the own
1581 * bit set. When we actually transmit the frame, the
1582 * status word will have _only_ the own bit set, so
1583 * the txeoc handler will be able to tell if it needs
1584 * to initiate another transmission to flush out pending
1585 * frames.
1586 */
1587 WB_TXOWN(start_tx) = WB_UNSENT;
1588 }
1589
1590 /*
1591 * Set a timeout in case the chip goes out to lunch.
1592 */
1593 ifp->if_timer = 5;
1594
1595 return;
1596}
1597
1598static void wb_init(xsc)
1599 void *xsc;
1600{
1601 struct wb_softc *sc = xsc;
1602 struct ifnet *ifp = &sc->arpcom.ac_if;
1603 int s, i;
1604 struct mii_data *mii;
1605
1606 s = splimp();
1607
1608 mii = device_get_softc(sc->wb_miibus);
1609
1610 /*
1611 * Cancel pending I/O and free all RX/TX buffers.
1612 */
1613 wb_stop(sc);
1614 wb_reset(sc);
1615
1616 sc->wb_txthresh = WB_TXTHRESH_INIT;
1617
1618 /*
1619 * Set cache alignment and burst length.
1620 */
1621#ifdef foo
1622 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1623 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1624 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1625#endif
1626
1627 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1628 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1629 switch(sc->wb_cachesize) {
1630 case 32:
1631 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1632 break;
1633 case 16:
1634 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1635 break;
1636 case 8:
1637 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1638 break;
1639 case 0:
1640 default:
1641 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1642 break;
1643 }
1644
1645 /* This doesn't tend to work too well at 100Mbps. */
1646 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1647
1648 /* Init our MAC address */
1649 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1650 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
1651 }
1652
1653 /* Init circular RX list. */
1654 if (wb_list_rx_init(sc) == ENOBUFS) {
1655 printf("wb%d: initialization failed: no "
1656 "memory for rx buffers\n", sc->wb_unit);
1657 wb_stop(sc);
1658 (void)splx(s);
1659 return;
1660 }
1661
1662 /* Init TX descriptors. */
1663 wb_list_tx_init(sc);
1664
1665 /* If we want promiscuous mode, set the allframes bit. */
1666 if (ifp->if_flags & IFF_PROMISC) {
1667 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1668 } else {
1669 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1670 }
1671
1672 /*
1673 * Set capture broadcast bit to capture broadcast frames.
1674 */
1675 if (ifp->if_flags & IFF_BROADCAST) {
1676 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1677 } else {
1678 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1679 }
1680
1681 /*
1682 * Program the multicast filter, if necessary.
1683 */
1684 wb_setmulti(sc);
1685
1686 /*
1687 * Load the address of the RX list.
1688 */
1689 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1690 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1691
1692 /*
1693 * Enable interrupts.
1694 */
1695 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1696 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1697
1698 /* Enable receiver and transmitter. */
1699 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1700 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1701
1702 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1703 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1704 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1705
1706 mii_mediachg(mii);
1707
1708 ifp->if_flags |= IFF_RUNNING;
1709 ifp->if_flags &= ~IFF_OACTIVE;
1710
1711 (void)splx(s);
1712
1713 sc->wb_stat_ch = timeout(wb_tick, sc, hz);
1714
1715 return;
1716}
1717
1718/*
1719 * Set media options.
1720 */
1721static int wb_ifmedia_upd(ifp)
1722 struct ifnet *ifp;
1723{
1724 struct wb_softc *sc;
1725
1726 sc = ifp->if_softc;
1727
1728 if (ifp->if_flags & IFF_UP)
1729 wb_init(sc);
1730
1731 return(0);
1732}
1733
1734/*
1735 * Report current media status.
1736 */
1737static void wb_ifmedia_sts(ifp, ifmr)
1738 struct ifnet *ifp;
1739 struct ifmediareq *ifmr;
1740{
1741 struct wb_softc *sc;
1742 struct mii_data *mii;
1743
1744 sc = ifp->if_softc;
1745
1746 mii = device_get_softc(sc->wb_miibus);
1747
1748 mii_pollstat(mii);
1749 ifmr->ifm_active = mii->mii_media_active;
1750 ifmr->ifm_status = mii->mii_media_status;
1751
1752 return;
1753}
1754
1755static int wb_ioctl(ifp, command, data)
1756 struct ifnet *ifp;
1757 u_long command;
1758 caddr_t data;
1759{
1760 struct wb_softc *sc = ifp->if_softc;
1761 struct mii_data *mii;
1762 struct ifreq *ifr = (struct ifreq *) data;
1763 int s, error = 0;
1764
1765 s = splimp();
1766
1767 switch(command) {
1768 case SIOCSIFADDR:
1769 case SIOCGIFADDR:
1770 case SIOCSIFMTU:
1771 error = ether_ioctl(ifp, command, data);
1772 break;
1773 case SIOCSIFFLAGS:
1774 if (ifp->if_flags & IFF_UP) {
1775 wb_init(sc);
1776 } else {
1777 if (ifp->if_flags & IFF_RUNNING)
1778 wb_stop(sc);
1779 }
1780 error = 0;
1781 break;
1782 case SIOCADDMULTI:
1783 case SIOCDELMULTI:
1784 wb_setmulti(sc);
1785 error = 0;
1786 break;
1787 case SIOCGIFMEDIA:
1788 case SIOCSIFMEDIA:
1789 mii = device_get_softc(sc->wb_miibus);
1790 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1791 break;
1792 default:
1793 error = EINVAL;
1794 break;
1795 }
1796
1797 (void)splx(s);
1798
1799 return(error);
1800}
1801
1802static void wb_watchdog(ifp)
1803 struct ifnet *ifp;
1804{
1805 struct wb_softc *sc;
1806
1807 sc = ifp->if_softc;
1808
1809 ifp->if_oerrors++;
1810 printf("wb%d: watchdog timeout\n", sc->wb_unit);
1811#ifdef foo
1812 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1813 printf("wb%d: no carrier - transceiver cable problem?\n",
1814 sc->wb_unit);
1815#endif
1816 wb_stop(sc);
1817 wb_reset(sc);
1818 wb_init(sc);
1819
1820 if (ifp->if_snd.ifq_head != NULL)
1821 wb_start(ifp);
1822
1823 return;
1824}
1825
1826/*
1827 * Stop the adapter and free any mbufs allocated to the
1828 * RX and TX lists.
1829 */
1830static void wb_stop(sc)
1831 struct wb_softc *sc;
1832{
1833 register int i;
1834 struct ifnet *ifp;
1835
1836 ifp = &sc->arpcom.ac_if;
1837 ifp->if_timer = 0;
1838
1839 untimeout(wb_tick, sc, sc->wb_stat_ch);
1840
1841 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1842 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1843 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1844 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1845
1846 /*
1847 * Free data in the RX lists.
1848 */
1849 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1850 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1851 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1852 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1853 }
1854 }
1855 bzero((char *)&sc->wb_ldata->wb_rx_list,
1856 sizeof(sc->wb_ldata->wb_rx_list));
1857
1858 /*
1859 * Free the TX list buffers.
1860 */
1861 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1862 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1863 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1864 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1865 }
1866 }
1867
1868 bzero((char *)&sc->wb_ldata->wb_tx_list,
1869 sizeof(sc->wb_ldata->wb_tx_list));
1870
1871 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1872
1873 return;
1874}
1875
1876/*
1877 * Stop all chip I/O so that the kernel's probe routines don't
1878 * get confused by errant DMAs when rebooting.
1879 */
1880static void wb_shutdown(dev)
1881 device_t dev;
1882{
1883 struct wb_softc *sc;
1884
1885 sc = device_get_softc(dev);
1886 wb_stop(sc);
1887
1888 return;
1889}
| 996
997 /* Delete any miibus and phy devices attached to this interface */
998 bus_generic_detach(dev);
999 device_delete_child(dev, sc->wb_miibus);
1000
1001 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
1002 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
1003 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
1004
1005 free(sc->wb_ldata_ptr, M_DEVBUF);
1006
1007 splx(s);
1008
1009 return(0);
1010}
1011
1012/*
1013 * Initialize the transmit descriptors.
1014 */
1015static int wb_list_tx_init(sc)
1016 struct wb_softc *sc;
1017{
1018 struct wb_chain_data *cd;
1019 struct wb_list_data *ld;
1020 int i;
1021
1022 cd = &sc->wb_cdata;
1023 ld = sc->wb_ldata;
1024
1025 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1026 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
1027 if (i == (WB_TX_LIST_CNT - 1)) {
1028 cd->wb_tx_chain[i].wb_nextdesc =
1029 &cd->wb_tx_chain[0];
1030 } else {
1031 cd->wb_tx_chain[i].wb_nextdesc =
1032 &cd->wb_tx_chain[i + 1];
1033 }
1034 }
1035
1036 cd->wb_tx_free = &cd->wb_tx_chain[0];
1037 cd->wb_tx_tail = cd->wb_tx_head = NULL;
1038
1039 return(0);
1040}
1041
1042
1043/*
1044 * Initialize the RX descriptors and allocate mbufs for them. Note that
1045 * we arrange the descriptors in a closed ring, so that the last descriptor
1046 * points back to the first.
1047 */
1048static int wb_list_rx_init(sc)
1049 struct wb_softc *sc;
1050{
1051 struct wb_chain_data *cd;
1052 struct wb_list_data *ld;
1053 int i;
1054
1055 cd = &sc->wb_cdata;
1056 ld = sc->wb_ldata;
1057
1058 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1059 cd->wb_rx_chain[i].wb_ptr =
1060 (struct wb_desc *)&ld->wb_rx_list[i];
1061 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
1062 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
1063 return(ENOBUFS);
1064 if (i == (WB_RX_LIST_CNT - 1)) {
1065 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
1066 ld->wb_rx_list[i].wb_next =
1067 vtophys(&ld->wb_rx_list[0]);
1068 } else {
1069 cd->wb_rx_chain[i].wb_nextdesc =
1070 &cd->wb_rx_chain[i + 1];
1071 ld->wb_rx_list[i].wb_next =
1072 vtophys(&ld->wb_rx_list[i + 1]);
1073 }
1074 }
1075
1076 cd->wb_rx_head = &cd->wb_rx_chain[0];
1077
1078 return(0);
1079}
1080
1081static void wb_bfree(buf, size)
1082 caddr_t buf;
1083 u_int size;
1084{
1085 return;
1086}
1087
1088/*
1089 * Initialize an RX descriptor and attach an MBUF cluster.
1090 */
1091static int wb_newbuf(sc, c, m)
1092 struct wb_softc *sc;
1093 struct wb_chain_onefrag *c;
1094 struct mbuf *m;
1095{
1096 struct mbuf *m_new = NULL;
1097
1098 if (m == NULL) {
1099 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1100 if (m_new == NULL) {
1101 printf("wb%d: no memory for rx "
1102 "list -- packet dropped!\n", sc->wb_unit);
1103 return(ENOBUFS);
1104 }
1105
1106 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf;
1107 m_new->m_flags |= M_EXT;
1108 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
1109 m_new->m_len = WB_BUFBYTES;
1110 m_new->m_ext.ext_free = wb_bfree;
1111 m_new->m_ext.ext_ref = wb_bfree;
1112 } else {
1113 m_new = m;
1114 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
1115 m_new->m_data = m_new->m_ext.ext_buf;
1116 }
1117
1118 m_adj(m_new, sizeof(u_int64_t));
1119
1120 c->wb_mbuf = m_new;
1121 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
1122 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
1123 c->wb_ptr->wb_status = WB_RXSTAT;
1124
1125 return(0);
1126}
1127
1128/*
1129 * A frame has been uploaded: pass the resulting mbuf chain up to
1130 * the higher level protocols.
1131 */
1132static void wb_rxeof(sc)
1133 struct wb_softc *sc;
1134{
1135 struct ether_header *eh;
1136 struct mbuf *m = NULL;
1137 struct ifnet *ifp;
1138 struct wb_chain_onefrag *cur_rx;
1139 int total_len = 0;
1140 u_int32_t rxstat;
1141
1142 ifp = &sc->arpcom.ac_if;
1143
1144 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
1145 WB_RXSTAT_OWN)) {
1146 struct mbuf *m0 = NULL;
1147
1148 cur_rx = sc->wb_cdata.wb_rx_head;
1149 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
1150
1151 m = cur_rx->wb_mbuf;
1152
1153 if ((rxstat & WB_RXSTAT_MIIERR) ||
1154 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
1155 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
1156 !(rxstat & WB_RXSTAT_LASTFRAG) ||
1157 !(rxstat & WB_RXSTAT_RXCMP)) {
1158 ifp->if_ierrors++;
1159 wb_newbuf(sc, cur_rx, m);
1160 printf("wb%x: receiver babbling: possible chip "
1161 "bug, forcing reset\n", sc->wb_unit);
1162 wb_fixmedia(sc);
1163 wb_reset(sc);
1164 wb_init(sc);
1165 return;
1166 }
1167
1168 if (rxstat & WB_RXSTAT_RXERR) {
1169 ifp->if_ierrors++;
1170 wb_newbuf(sc, cur_rx, m);
1171 break;
1172 }
1173
1174 /* No errors; receive the packet. */
1175 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1176
1177 /*
1178 * XXX The Winbond chip includes the CRC with every
1179 * received frame, and there's no way to turn this
1180 * behavior off (at least, I can't find anything in
1181 * the manual that explains how to do it) so we have
1182 * to trim off the CRC manually.
1183 */
1184 total_len -= ETHER_CRC_LEN;
1185
1186 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1187 total_len + ETHER_ALIGN, 0, ifp, NULL);
1188 wb_newbuf(sc, cur_rx, m);
1189 if (m0 == NULL) {
1190 ifp->if_ierrors++;
1191 break;
1192 }
1193 m_adj(m0, ETHER_ALIGN);
1194 m = m0;
1195
1196 ifp->if_ipackets++;
1197 eh = mtod(m, struct ether_header *);
1198
1199 /* Remove header from mbuf and pass it on. */
1200 m_adj(m, sizeof(struct ether_header));
1201 ether_input(ifp, eh, m);
1202 }
1203}
1204
1205void wb_rxeoc(sc)
1206 struct wb_softc *sc;
1207{
1208 wb_rxeof(sc);
1209
1210 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1211 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1212 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1213 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1214 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1215
1216 return;
1217}
1218
1219/*
1220 * A frame was downloaded to the chip. It's safe for us to clean up
1221 * the list buffers.
1222 */
1223static void wb_txeof(sc)
1224 struct wb_softc *sc;
1225{
1226 struct wb_chain *cur_tx;
1227 struct ifnet *ifp;
1228
1229 ifp = &sc->arpcom.ac_if;
1230
1231 /* Clear the timeout timer. */
1232 ifp->if_timer = 0;
1233
1234 if (sc->wb_cdata.wb_tx_head == NULL)
1235 return;
1236
1237 /*
1238 * Go through our tx list and free mbufs for those
1239 * frames that have been transmitted.
1240 */
1241 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1242 u_int32_t txstat;
1243
1244 cur_tx = sc->wb_cdata.wb_tx_head;
1245 txstat = WB_TXSTATUS(cur_tx);
1246
1247 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1248 break;
1249
1250 if (txstat & WB_TXSTAT_TXERR) {
1251 ifp->if_oerrors++;
1252 if (txstat & WB_TXSTAT_ABORT)
1253 ifp->if_collisions++;
1254 if (txstat & WB_TXSTAT_LATECOLL)
1255 ifp->if_collisions++;
1256 }
1257
1258 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1259
1260 ifp->if_opackets++;
1261 m_freem(cur_tx->wb_mbuf);
1262 cur_tx->wb_mbuf = NULL;
1263
1264 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1265 sc->wb_cdata.wb_tx_head = NULL;
1266 sc->wb_cdata.wb_tx_tail = NULL;
1267 break;
1268 }
1269
1270 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1271 }
1272
1273 return;
1274}
1275
1276/*
1277 * TX 'end of channel' interrupt handler.
1278 */
1279static void wb_txeoc(sc)
1280 struct wb_softc *sc;
1281{
1282 struct ifnet *ifp;
1283
1284 ifp = &sc->arpcom.ac_if;
1285
1286 ifp->if_timer = 0;
1287
1288 if (sc->wb_cdata.wb_tx_head == NULL) {
1289 ifp->if_flags &= ~IFF_OACTIVE;
1290 sc->wb_cdata.wb_tx_tail = NULL;
1291 } else {
1292 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1293 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1294 ifp->if_timer = 5;
1295 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1296 }
1297 }
1298
1299 return;
1300}
1301
1302static void wb_intr(arg)
1303 void *arg;
1304{
1305 struct wb_softc *sc;
1306 struct ifnet *ifp;
1307 u_int32_t status;
1308
1309 sc = arg;
1310 ifp = &sc->arpcom.ac_if;
1311
1312 if (!(ifp->if_flags & IFF_UP))
1313 return;
1314
1315 /* Disable interrupts. */
1316 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1317
1318 for (;;) {
1319
1320 status = CSR_READ_4(sc, WB_ISR);
1321 if (status)
1322 CSR_WRITE_4(sc, WB_ISR, status);
1323
1324 if ((status & WB_INTRS) == 0)
1325 break;
1326
1327 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1328 ifp->if_ierrors++;
1329 wb_reset(sc);
1330 if (status & WB_ISR_RX_ERR)
1331 wb_fixmedia(sc);
1332 wb_init(sc);
1333 continue;
1334 }
1335
1336 if (status & WB_ISR_RX_OK)
1337 wb_rxeof(sc);
1338
1339 if (status & WB_ISR_RX_IDLE)
1340 wb_rxeoc(sc);
1341
1342 if (status & WB_ISR_TX_OK)
1343 wb_txeof(sc);
1344
1345 if (status & WB_ISR_TX_NOBUF)
1346 wb_txeoc(sc);
1347
1348 if (status & WB_ISR_TX_IDLE) {
1349 wb_txeof(sc);
1350 if (sc->wb_cdata.wb_tx_head != NULL) {
1351 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1352 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1353 }
1354 }
1355
1356 if (status & WB_ISR_TX_UNDERRUN) {
1357 ifp->if_oerrors++;
1358 wb_txeof(sc);
1359 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1360 /* Jack up TX threshold */
1361 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1362 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1363 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1364 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1365 }
1366
1367 if (status & WB_ISR_BUS_ERR) {
1368 wb_reset(sc);
1369 wb_init(sc);
1370 }
1371
1372 }
1373
1374 /* Re-enable interrupts. */
1375 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1376
1377 if (ifp->if_snd.ifq_head != NULL) {
1378 wb_start(ifp);
1379 }
1380
1381 return;
1382}
1383
1384static void wb_tick(xsc)
1385 void *xsc;
1386{
1387 struct wb_softc *sc;
1388 struct mii_data *mii;
1389 int s;
1390
1391 s = splimp();
1392
1393 sc = xsc;
1394 mii = device_get_softc(sc->wb_miibus);
1395
1396 mii_tick(mii);
1397
1398 sc->wb_stat_ch = timeout(wb_tick, sc, hz);
1399
1400 splx(s);
1401
1402 return;
1403}
1404
1405/*
1406 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1407 * pointers to the fragment pointers.
1408 */
1409static int wb_encap(sc, c, m_head)
1410 struct wb_softc *sc;
1411 struct wb_chain *c;
1412 struct mbuf *m_head;
1413{
1414 int frag = 0;
1415 struct wb_desc *f = NULL;
1416 int total_len;
1417 struct mbuf *m;
1418
1419 /*
1420 * Start packing the mbufs in this chain into
1421 * the fragment pointers. Stop when we run out
1422 * of fragments or hit the end of the mbuf chain.
1423 */
1424 m = m_head;
1425 total_len = 0;
1426
1427 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1428 if (m->m_len != 0) {
1429 if (frag == WB_MAXFRAGS)
1430 break;
1431 total_len += m->m_len;
1432 f = &c->wb_ptr->wb_frag[frag];
1433 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1434 if (frag == 0) {
1435 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1436 f->wb_status = 0;
1437 } else
1438 f->wb_status = WB_TXSTAT_OWN;
1439 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1440 f->wb_data = vtophys(mtod(m, vm_offset_t));
1441 frag++;
1442 }
1443 }
1444
1445 /*
1446 * Handle special case: we used up all 16 fragments,
1447 * but we have more mbufs left in the chain. Copy the
1448 * data into an mbuf cluster. Note that we don't
1449 * bother clearing the values in the other fragment
1450 * pointers/counters; it wouldn't gain us anything,
1451 * and would waste cycles.
1452 */
1453 if (m != NULL) {
1454 struct mbuf *m_new = NULL;
1455
1456 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1457 if (m_new == NULL) {
1458 printf("wb%d: no memory for tx list", sc->wb_unit);
1459 return(1);
1460 }
1461 if (m_head->m_pkthdr.len > MHLEN) {
1462 MCLGET(m_new, M_DONTWAIT);
1463 if (!(m_new->m_flags & M_EXT)) {
1464 m_freem(m_new);
1465 printf("wb%d: no memory for tx list",
1466 sc->wb_unit);
1467 return(1);
1468 }
1469 }
1470 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1471 mtod(m_new, caddr_t));
1472 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1473 m_freem(m_head);
1474 m_head = m_new;
1475 f = &c->wb_ptr->wb_frag[0];
1476 f->wb_status = 0;
1477 f->wb_data = vtophys(mtod(m_new, caddr_t));
1478 f->wb_ctl = total_len = m_new->m_len;
1479 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1480 frag = 1;
1481 }
1482
1483 if (total_len < WB_MIN_FRAMELEN) {
1484 f = &c->wb_ptr->wb_frag[frag];
1485 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1486 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1487 f->wb_ctl |= WB_TXCTL_TLINK;
1488 f->wb_status = WB_TXSTAT_OWN;
1489 frag++;
1490 }
1491
1492 c->wb_mbuf = m_head;
1493 c->wb_lastdesc = frag - 1;
1494 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1495 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1496
1497 return(0);
1498}
1499
1500/*
1501 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1502 * to the mbuf data regions directly in the transmit lists. We also save a
1503 * copy of the pointers since the transmit list fragment pointers are
1504 * physical addresses.
1505 */
1506
1507static void wb_start(ifp)
1508 struct ifnet *ifp;
1509{
1510 struct wb_softc *sc;
1511 struct mbuf *m_head = NULL;
1512 struct wb_chain *cur_tx = NULL, *start_tx;
1513
1514 sc = ifp->if_softc;
1515
1516 /*
1517 * Check for an available queue slot. If there are none,
1518 * punt.
1519 */
1520 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1521 ifp->if_flags |= IFF_OACTIVE;
1522 return;
1523 }
1524
1525 start_tx = sc->wb_cdata.wb_tx_free;
1526
1527 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1528 IF_DEQUEUE(&ifp->if_snd, m_head);
1529 if (m_head == NULL)
1530 break;
1531
1532 /* Pick a descriptor off the free list. */
1533 cur_tx = sc->wb_cdata.wb_tx_free;
1534 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1535
1536 /* Pack the data into the descriptor. */
1537 wb_encap(sc, cur_tx, m_head);
1538
1539 if (cur_tx != start_tx)
1540 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1541
1542 /*
1543 * If there's a BPF listener, bounce a copy of this frame
1544 * to him.
1545 */
1546 if (ifp->if_bpf)
1547 bpf_mtap(ifp, cur_tx->wb_mbuf);
1548 }
1549
1550 /*
1551 * If there are no packets queued, bail.
1552 */
1553 if (cur_tx == NULL)
1554 return;
1555
1556 /*
1557 * Place the request for the upload interrupt
1558 * in the last descriptor in the chain. This way, if
1559 * we're chaining several packets at once, we'll only
1560 * get an interupt once for the whole chain rather than
1561 * once for each packet.
1562 */
1563 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1564 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1565 sc->wb_cdata.wb_tx_tail = cur_tx;
1566
1567 if (sc->wb_cdata.wb_tx_head == NULL) {
1568 sc->wb_cdata.wb_tx_head = start_tx;
1569 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1570 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1571 } else {
1572 /*
1573 * We need to distinguish between the case where
1574 * the own bit is clear because the chip cleared it
1575 * and where the own bit is clear because we haven't
1576 * set it yet. The magic value WB_UNSET is just some
1577 * ramdomly chosen number which doesn't have the own
1578 * bit set. When we actually transmit the frame, the
1579 * status word will have _only_ the own bit set, so
1580 * the txeoc handler will be able to tell if it needs
1581 * to initiate another transmission to flush out pending
1582 * frames.
1583 */
1584 WB_TXOWN(start_tx) = WB_UNSENT;
1585 }
1586
1587 /*
1588 * Set a timeout in case the chip goes out to lunch.
1589 */
1590 ifp->if_timer = 5;
1591
1592 return;
1593}
1594
1595static void wb_init(xsc)
1596 void *xsc;
1597{
1598 struct wb_softc *sc = xsc;
1599 struct ifnet *ifp = &sc->arpcom.ac_if;
1600 int s, i;
1601 struct mii_data *mii;
1602
1603 s = splimp();
1604
1605 mii = device_get_softc(sc->wb_miibus);
1606
1607 /*
1608 * Cancel pending I/O and free all RX/TX buffers.
1609 */
1610 wb_stop(sc);
1611 wb_reset(sc);
1612
1613 sc->wb_txthresh = WB_TXTHRESH_INIT;
1614
1615 /*
1616 * Set cache alignment and burst length.
1617 */
1618#ifdef foo
1619 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1620 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1621 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1622#endif
1623
1624 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1625 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1626 switch(sc->wb_cachesize) {
1627 case 32:
1628 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1629 break;
1630 case 16:
1631 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1632 break;
1633 case 8:
1634 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1635 break;
1636 case 0:
1637 default:
1638 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1639 break;
1640 }
1641
1642 /* This doesn't tend to work too well at 100Mbps. */
1643 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1644
1645 /* Init our MAC address */
1646 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1647 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
1648 }
1649
1650 /* Init circular RX list. */
1651 if (wb_list_rx_init(sc) == ENOBUFS) {
1652 printf("wb%d: initialization failed: no "
1653 "memory for rx buffers\n", sc->wb_unit);
1654 wb_stop(sc);
1655 (void)splx(s);
1656 return;
1657 }
1658
1659 /* Init TX descriptors. */
1660 wb_list_tx_init(sc);
1661
1662 /* If we want promiscuous mode, set the allframes bit. */
1663 if (ifp->if_flags & IFF_PROMISC) {
1664 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1665 } else {
1666 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1667 }
1668
1669 /*
1670 * Set capture broadcast bit to capture broadcast frames.
1671 */
1672 if (ifp->if_flags & IFF_BROADCAST) {
1673 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1674 } else {
1675 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1676 }
1677
1678 /*
1679 * Program the multicast filter, if necessary.
1680 */
1681 wb_setmulti(sc);
1682
1683 /*
1684 * Load the address of the RX list.
1685 */
1686 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1687 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1688
1689 /*
1690 * Enable interrupts.
1691 */
1692 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1693 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1694
1695 /* Enable receiver and transmitter. */
1696 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1697 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1698
1699 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1700 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1701 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1702
1703 mii_mediachg(mii);
1704
1705 ifp->if_flags |= IFF_RUNNING;
1706 ifp->if_flags &= ~IFF_OACTIVE;
1707
1708 (void)splx(s);
1709
1710 sc->wb_stat_ch = timeout(wb_tick, sc, hz);
1711
1712 return;
1713}
1714
1715/*
1716 * Set media options.
1717 */
1718static int wb_ifmedia_upd(ifp)
1719 struct ifnet *ifp;
1720{
1721 struct wb_softc *sc;
1722
1723 sc = ifp->if_softc;
1724
1725 if (ifp->if_flags & IFF_UP)
1726 wb_init(sc);
1727
1728 return(0);
1729}
1730
1731/*
1732 * Report current media status.
1733 */
1734static void wb_ifmedia_sts(ifp, ifmr)
1735 struct ifnet *ifp;
1736 struct ifmediareq *ifmr;
1737{
1738 struct wb_softc *sc;
1739 struct mii_data *mii;
1740
1741 sc = ifp->if_softc;
1742
1743 mii = device_get_softc(sc->wb_miibus);
1744
1745 mii_pollstat(mii);
1746 ifmr->ifm_active = mii->mii_media_active;
1747 ifmr->ifm_status = mii->mii_media_status;
1748
1749 return;
1750}
1751
1752static int wb_ioctl(ifp, command, data)
1753 struct ifnet *ifp;
1754 u_long command;
1755 caddr_t data;
1756{
1757 struct wb_softc *sc = ifp->if_softc;
1758 struct mii_data *mii;
1759 struct ifreq *ifr = (struct ifreq *) data;
1760 int s, error = 0;
1761
1762 s = splimp();
1763
1764 switch(command) {
1765 case SIOCSIFADDR:
1766 case SIOCGIFADDR:
1767 case SIOCSIFMTU:
1768 error = ether_ioctl(ifp, command, data);
1769 break;
1770 case SIOCSIFFLAGS:
1771 if (ifp->if_flags & IFF_UP) {
1772 wb_init(sc);
1773 } else {
1774 if (ifp->if_flags & IFF_RUNNING)
1775 wb_stop(sc);
1776 }
1777 error = 0;
1778 break;
1779 case SIOCADDMULTI:
1780 case SIOCDELMULTI:
1781 wb_setmulti(sc);
1782 error = 0;
1783 break;
1784 case SIOCGIFMEDIA:
1785 case SIOCSIFMEDIA:
1786 mii = device_get_softc(sc->wb_miibus);
1787 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1788 break;
1789 default:
1790 error = EINVAL;
1791 break;
1792 }
1793
1794 (void)splx(s);
1795
1796 return(error);
1797}
1798
1799static void wb_watchdog(ifp)
1800 struct ifnet *ifp;
1801{
1802 struct wb_softc *sc;
1803
1804 sc = ifp->if_softc;
1805
1806 ifp->if_oerrors++;
1807 printf("wb%d: watchdog timeout\n", sc->wb_unit);
1808#ifdef foo
1809 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1810 printf("wb%d: no carrier - transceiver cable problem?\n",
1811 sc->wb_unit);
1812#endif
1813 wb_stop(sc);
1814 wb_reset(sc);
1815 wb_init(sc);
1816
1817 if (ifp->if_snd.ifq_head != NULL)
1818 wb_start(ifp);
1819
1820 return;
1821}
1822
1823/*
1824 * Stop the adapter and free any mbufs allocated to the
1825 * RX and TX lists.
1826 */
1827static void wb_stop(sc)
1828 struct wb_softc *sc;
1829{
1830 register int i;
1831 struct ifnet *ifp;
1832
1833 ifp = &sc->arpcom.ac_if;
1834 ifp->if_timer = 0;
1835
1836 untimeout(wb_tick, sc, sc->wb_stat_ch);
1837
1838 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1839 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1840 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1841 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1842
1843 /*
1844 * Free data in the RX lists.
1845 */
1846 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1847 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1848 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1849 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1850 }
1851 }
1852 bzero((char *)&sc->wb_ldata->wb_rx_list,
1853 sizeof(sc->wb_ldata->wb_rx_list));
1854
1855 /*
1856 * Free the TX list buffers.
1857 */
1858 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1859 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1860 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1861 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1862 }
1863 }
1864
1865 bzero((char *)&sc->wb_ldata->wb_tx_list,
1866 sizeof(sc->wb_ldata->wb_tx_list));
1867
1868 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1869
1870 return;
1871}
1872
1873/*
1874 * Stop all chip I/O so that the kernel's probe routines don't
1875 * get confused by errant DMAs when rebooting.
1876 */
1877static void wb_shutdown(dev)
1878 device_t dev;
1879{
1880 struct wb_softc *sc;
1881
1882 sc = device_get_softc(dev);
1883 wb_stop(sc);
1884
1885 return;
1886}
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