1/*-
2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 * $OpenBSD: if_rsureg.h,v 1.3 2013/04/15 09:23:01 mglocker Exp $
| 1/*-
2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 * $OpenBSD: if_rsureg.h,v 1.3 2013/04/15 09:23:01 mglocker Exp $
|
18 */
19
20/* USB Requests. */
21#define R92S_REQ_REGS 0x05
22
23/*
24 * MAC registers.
25 */
26#define R92S_SYSCFG 0x0000
27#define R92S_SYS_ISO_CTRL (R92S_SYSCFG + 0x000)
28#define R92S_SYS_FUNC_EN (R92S_SYSCFG + 0x002)
29#define R92S_PMC_FSM (R92S_SYSCFG + 0x004)
30#define R92S_SYS_CLKR (R92S_SYSCFG + 0x008)
31#define R92S_EE_9346CR (R92S_SYSCFG + 0x00a)
32#define R92S_AFE_MISC (R92S_SYSCFG + 0x010)
33#define R92S_SPS0_CTRL (R92S_SYSCFG + 0x011)
34#define R92S_SPS1_CTRL (R92S_SYSCFG + 0x018)
35#define R92S_RF_CTRL (R92S_SYSCFG + 0x01f)
36#define R92S_LDOA15_CTRL (R92S_SYSCFG + 0x020)
37#define R92S_LDOV12D_CTRL (R92S_SYSCFG + 0x021)
38#define R92S_AFE_XTAL_CTRL (R92S_SYSCFG + 0x026)
39#define R92S_AFE_PLL_CTRL (R92S_SYSCFG + 0x028)
40#define R92S_EFUSE_CTRL (R92S_SYSCFG + 0x030)
41#define R92S_EFUSE_TEST (R92S_SYSCFG + 0x034)
42#define R92S_EFUSE_CLK_CTRL (R92S_SYSCFG + 0x2f8)
43
44#define R92S_CMDCTRL 0x0040
45#define R92S_CR (R92S_CMDCTRL + 0x000)
46#define R92S_TCR (R92S_CMDCTRL + 0x004)
47#define R92S_RCR (R92S_CMDCTRL + 0x008)
48
49#define R92S_MACIDSETTING 0x0050
50#define R92S_MACID (R92S_MACIDSETTING + 0x000)
51
52#define R92S_GP 0x01e0
53#define R92S_GPIO_CTRL (R92S_GP + 0x00c)
54#define R92S_GPIO_IO_SEL (R92S_GP + 0x00e)
55#define R92S_MAC_PINMUX_CTRL (R92S_GP + 0x011)
56
57#define R92S_IOCMD_CTRL 0x0370
58#define R92S_IOCMD_DATA 0x0374
59
60#define R92S_USB_HRPWM 0xfe58
61
62/* Bits for R92S_SYS_FUNC_EN. */
63#define R92S_FEN_CPUEN 0x0400
64
65/* Bits for R92S_PMC_FSM. */
66#define R92S_PMC_FSM_CUT_M 0x000f8000
67#define R92S_PMC_FSM_CUT_S 15
68
69/* Bits for R92S_SYS_CLKR. */
70#define R92S_SYS_CLKSEL 0x0001
71#define R92S_SYS_PS_CLKSEL 0x0002
72#define R92S_SYS_CPU_CLKSEL 0x0004
73#define R92S_MAC_CLK_EN 0x0800
74#define R92S_SYS_CLK_EN 0x1000
75#define R92S_SWHW_SEL 0x4000
76#define R92S_FWHW_SEL 0x8000
77
78/* Bits for R92S_EE_9346CR. */
79#define R92S_9356SEL 0x10
80#define R92S_EEPROM_EN 0x20
81
82/* Bits for R92S_AFE_MISC. */
83#define R92S_AFE_MISC_BGEN 0x01
84#define R92S_AFE_MISC_MBEN 0x02
85#define R92S_AFE_MISC_I32_EN 0x08
86
87/* Bits for R92S_SPS1_CTRL. */
88#define R92S_SPS1_LDEN 0x01
89#define R92S_SPS1_SWEN 0x02
90
91/* Bits for R92S_LDOA15_CTRL. */
92#define R92S_LDA15_EN 0x01
93
94/* Bits for R92S_LDOV12D_CTRL. */
95#define R92S_LDV12_EN 0x01
96
97/* Bits for R92C_EFUSE_CTRL. */
98#define R92S_EFUSE_CTRL_DATA_M 0x000000ff
99#define R92S_EFUSE_CTRL_DATA_S 0
100#define R92S_EFUSE_CTRL_ADDR_M 0x0003ff00
101#define R92S_EFUSE_CTRL_ADDR_S 8
102#define R92S_EFUSE_CTRL_VALID 0x80000000
103
104/* Bits for R92S_CR. */
105#define R92S_CR_TXDMA_EN 0x10
106
107/* Bits for R92S_TCR. */
108#define R92S_TCR_IMEM_CODE_DONE 0x01
109#define R92S_TCR_IMEM_CHK_RPT 0x02
110#define R92S_TCR_EMEM_CODE_DONE 0x04
111#define R92S_TCR_EMEM_CHK_RPT 0x08
112#define R92S_TCR_DMEM_CODE_DONE 0x10
113#define R92S_TCR_IMEM_RDY 0x20
114#define R92S_TCR_FWRDY 0x80
115
116/* Bits for R92S_GPIO_IO_SEL. */
117#define R92S_GPIO_WPS 0x10
118
119/* Bits for R92S_MAC_PINMUX_CTRL. */
120#define R92S_GPIOSEL_GPIO_M 0x03
121#define R92S_GPIOSEL_GPIO_S 0
122#define R92S_GPIOSEL_GPIO_JTAG 0
123#define R92S_GPIOSEL_GPIO_PHYDBG 1
124#define R92S_GPIOSEL_GPIO_BT 2
125#define R92S_GPIOSEL_GPIO_WLANDBG 3
126#define R92S_GPIOMUX_EN 0x08
127
128/* Bits for R92S_IOCMD_CTRL. */
129#define R92S_IOCMD_CLASS_M 0xff000000
130#define R92S_IOCMD_CLASS_S 24
131#define R92S_IOCMD_CLASS_BB_RF 0xf0
132#define R92S_IOCMD_VALUE_M 0x00ffff00
133#define R92S_IOCMD_VALUE_S 8
134#define R92S_IOCMD_INDEX_M 0x000000ff
135#define R92S_IOCMD_INDEX_S 0
136#define R92S_IOCMD_INDEX_BB_READ 0
137#define R92S_IOCMD_INDEX_BB_WRITE 1
138#define R92S_IOCMD_INDEX_RF_READ 2
139#define R92S_IOCMD_INDEX_RF_WRITE 3
140
141/* Bits for R92S_USB_HRPWM. */
142#define R92S_USB_HRPWM_PS_ALL_ON 0x04
143#define R92S_USB_HRPWM_PS_ST_ACTIVE 0x08
144
145/*
146 * Macros to access subfields in registers.
147 */
148/* Mask and Shift (getter). */
149#define MS(val, field) \
150 (((val) & field##_M) >> field##_S)
151
152/* Shift and Mask (setter). */
153#define SM(field, val) \
154 (((val) << field##_S) & field##_M)
155
156/* Rewrite. */
157#define RW(var, field, val) \
158 (((var) & ~field##_M) | SM(field, val))
159
160/*
161 * ROM field with RF config.
162 */
163enum {
164 RTL8712_RFCONFIG_1T = 0x10,
165 RTL8712_RFCONFIG_2T = 0x20,
166 RTL8712_RFCONFIG_1R = 0x01,
167 RTL8712_RFCONFIG_2R = 0x02,
168 RTL8712_RFCONFIG_1T1R = 0x11,
169 RTL8712_RFCONFIG_1T2R = 0x12,
170 RTL8712_RFCONFIG_TURBO = 0x92,
171 RTL8712_RFCONFIG_2T2R = 0x22
172};
173
174/*
175 * Firmware image header.
176 */
177struct r92s_fw_priv {
178 /* QWORD0 */
179 uint16_t signature;
180 uint8_t hci_sel;
181#define R92S_HCI_SEL_PCIE 0x01
182#define R92S_HCI_SEL_USB 0x02
183#define R92S_HCI_SEL_SDIO 0x04
184#define R92S_HCI_SEL_8172 0x10
185#define R92S_HCI_SEL_AP 0x80
186
187 uint8_t chip_version;
188 uint16_t custid;
189 uint8_t rf_config;
190//0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R
191 uint8_t nendpoints;
192 /* QWORD1 */
193 uint32_t regulatory;
194 uint8_t rfintfs;
195 uint8_t def_nettype;
196 uint8_t turbo_mode;
197 uint8_t lowpower_mode;
198 /* QWORD2 */
199 uint8_t lbk_mode;
200 uint8_t mp_mode;
201 uint8_t vcs_type;
202#define R92S_VCS_TYPE_DISABLE 0
203#define R92S_VCS_TYPE_ENABLE 1
204#define R92S_VCS_TYPE_AUTO 2
205
206 uint8_t vcs_mode;
207#define R92S_VCS_MODE_NONE 0
208#define R92S_VCS_MODE_RTS_CTS 1
209#define R92S_VCS_MODE_CTS2SELF 2
210
211 uint32_t reserved1;
212 /* QWORD3 */
213 uint8_t qos_en;
214 uint8_t bw40_en;
215 uint8_t amsdu2ampdu_en;
216 uint8_t ampdu_en;
217 uint8_t rc_offload;
218 uint8_t agg_offload;
219 uint16_t reserved2;
220 /* QWORD4 */
221 uint8_t beacon_offload;
222 uint8_t mlme_offload;
223 uint8_t hwpc_offload;
224 uint8_t tcpcsum_offload;
225 uint8_t tcp_offload;
226 uint8_t ps_offload;
227 uint8_t wwlan_offload;
228 uint8_t reserved3;
229 /* QWORD5 */
230 uint16_t tcp_tx_len;
231 uint16_t tcp_rx_len;
232 uint32_t reserved4;
233} __packed;
234
235struct r92s_fw_hdr {
236 uint16_t signature;
237 uint16_t version;
238 uint32_t dmemsz;
239 uint32_t imemsz;
240 uint32_t sramsz;
241 uint32_t privsz;
242 uint16_t efuse_addr;
243 uint16_t h2c_resp_addr;
244 uint32_t svnrev;
245 uint8_t month;
246 uint8_t day;
247 uint8_t hour;
248 uint8_t minute;
249 struct r92s_fw_priv priv;
250} __packed;
251
252/* Structure for FW commands and FW events notifications. */
253struct r92s_fw_cmd_hdr {
254 uint16_t len;
255 uint8_t code;
256 uint8_t seq;
257#define R92S_FW_CMD_MORE 0x80
258
259 uint32_t reserved;
260} __packed;
261
262/* FW commands codes. */
263#define R92S_CMD_READ_MACREG 0
264#define R92S_CMD_WRITE_MACREG 1
265#define R92S_CMD_READ_BBREG 2
266#define R92S_CMD_WRITE_BBREG 3
267#define R92S_CMD_READ_RFREG 4
268#define R92S_CMD_WRITE_RFREG 5
269#define R92S_CMD_READ_EEPROM 6
270#define R92S_CMD_WRITE_EEPROM 7
271#define R92S_CMD_READ_EFUSE 8
272#define R92S_CMD_WRITE_EFUSE 9
273#define R92S_CMD_READ_CAM 10
274#define R92S_CMD_WRITE_CAM 11
275#define R92S_CMD_SET_BCNITV 12
276#define R92S_CMD_SET_MBIDCFG 13
277#define R92S_CMD_JOIN_BSS 14
278#define R92S_CMD_DISCONNECT 15
279#define R92S_CMD_CREATE_BSS 16
280#define R92S_CMD_SET_OPMODE 17
281#define R92S_CMD_SITE_SURVEY 18
282#define R92S_CMD_SET_AUTH 19
283#define R92S_CMD_SET_KEY 20
284#define R92S_CMD_SET_STA_KEY 21
285#define R92S_CMD_SET_ASSOC_STA 22
286#define R92S_CMD_DEL_ASSOC_STA 23
287#define R92S_CMD_SET_STAPWRSTATE 24
288#define R92S_CMD_SET_BASIC_RATE 25
289#define R92S_CMD_GET_BASIC_RATE 26
290#define R92S_CMD_SET_DATA_RATE 27
291#define R92S_CMD_GET_DATA_RATE 28
292#define R92S_CMD_SET_PHY_INFO 29
293#define R92S_CMD_GET_PHY_INFO 30
294#define R92S_CMD_SET_PHY 31
295#define R92S_CMD_GET_PHY 32
296#define R92S_CMD_READ_RSSI 33
297#define R92S_CMD_READ_GAIN 34
298#define R92S_CMD_SET_ATIM 35
299#define R92S_CMD_SET_PWR_MODE 36
300#define R92S_CMD_JOIN_BSS_RPT 37
301#define R92S_CMD_SET_RA_TABLE 38
302#define R92S_CMD_GET_RA_TABLE 39
303#define R92S_CMD_GET_CCX_REPORT 40
304#define R92S_CMD_GET_DTM_REPORT 41
305#define R92S_CMD_GET_TXRATE_STATS 42
306#define R92S_CMD_SET_USB_SUSPEND 43
307#define R92S_CMD_SET_H2C_LBK 44
308#define R92S_CMD_ADDBA_REQ 45
309#define R92S_CMD_SET_CHANNEL 46
310#define R92S_CMD_SET_TXPOWER 47
311#define R92S_CMD_SWITCH_ANTENNA 48
312#define R92S_CMD_SET_CRYSTAL_CAL 49
313#define R92S_CMD_SET_SINGLE_CARRIER_TX 50
314#define R92S_CMD_SET_SINGLE_TONE_TX 51
315#define R92S_CMD_SET_CARRIER_SUPPR_TX 52
316#define R92S_CMD_SET_CONTINUOUS_TX 53
317#define R92S_CMD_SWITCH_BANDWIDTH 54
318#define R92S_CMD_TX_BEACON 55
319#define R92S_CMD_SET_POWER_TRACKING 56
320#define R92S_CMD_AMSDU_TO_AMPDU 57
321#define R92S_CMD_SET_MAC_ADDRESS 58
322#define R92S_CMD_GET_H2C_LBK 59
323#define R92S_CMD_SET_PBREQ_IE 60
324#define R92S_CMD_SET_ASSOCREQ_IE 61
325#define R92S_CMD_SET_PBRESP_IE 62
326#define R92S_CMD_SET_ASSOCRESP_IE 63
327#define R92S_CMD_GET_CURDATARATE 64
328#define R92S_CMD_GET_TXRETRY_CNT 65
329#define R92S_CMD_GET_RXRETRY_CNT 66
330#define R92S_CMD_GET_BCNOK_CNT 67
331#define R92S_CMD_GET_BCNERR_CNT 68
332#define R92S_CMD_GET_CURTXPWR_LEVEL 69
333#define R92S_CMD_SET_DIG 70
334#define R92S_CMD_SET_RA 71
335#define R92S_CMD_SET_PT 72
336#define R92S_CMD_READ_TSSI 73
337
338/* FW events notifications codes. */
339#define R92S_EVT_READ_MACREG 0
340#define R92S_EVT_READ_BBREG 1
341#define R92S_EVT_READ_RFREG 2
342#define R92S_EVT_READ_EEPROM 3
343#define R92S_EVT_READ_EFUSE 4
344#define R92S_EVT_READ_CAM 5
345#define R92S_EVT_GET_BASICRATE 6
346#define R92S_EVT_GET_DATARATE 7
347#define R92S_EVT_SURVEY 8
348#define R92S_EVT_SURVEY_DONE 9
349#define R92S_EVT_JOIN_BSS 10
350#define R92S_EVT_ADD_STA 11
351#define R92S_EVT_DEL_STA 12
352#define R92S_EVT_ATIM_DONE 13
353#define R92S_EVT_TX_REPORT 14
354#define R92S_EVT_CCX_REPORT 15
355#define R92S_EVT_DTM_REPORT 16
356#define R92S_EVT_TXRATE_STATS 17
357#define R92S_EVT_C2H_LBK 18
358#define R92S_EVT_FWDBG 19
359#define R92S_EVT_C2H_FEEDBACK 20
360#define R92S_EVT_ADDBA 21
361#define R92S_EVT_C2H_BCN 22
362#define R92S_EVT_PWR_STATE 23
363#define R92S_EVT_WPS_PBC 24
364#define R92S_EVT_ADDBA_REQ_REPORT 25
365
366/* Structure for R92S_CMD_SITE_SURVEY. */
367struct r92s_fw_cmd_sitesurvey {
368 uint32_t active;
369 uint32_t limit;
370 uint32_t ssidlen;
371 uint8_t ssid[32 + 1];
372} __packed;
373
374/* Structure for R92S_CMD_SET_AUTH. */
375struct r92s_fw_cmd_auth {
376 uint8_t mode;
377#define R92S_AUTHMODE_OPEN 0
378#define R92S_AUTHMODE_SHARED 1
379#define R92S_AUTHMODE_WPA 2
380
381 uint8_t dot1x;
382} __packed;
383
384/* Structure for R92S_CMD_SET_KEY. */
385struct r92s_fw_cmd_set_key {
386 uint8_t algo;
387#define R92S_KEY_ALGO_NONE 0
388#define R92S_KEY_ALGO_WEP40 1
389#define R92S_KEY_ALGO_TKIP 2
390#define R92S_KEY_ALGO_TKIP_MMIC 3
391#define R92S_KEY_ALGO_AES 4
392#define R92S_KEY_ALGO_WEP104 5
393
394 uint8_t id;
395 uint8_t grpkey;
396 uint8_t key[16];
397} __packed;
398
399/* Structures for R92S_EVENT_SURVEY/R92S_CMD_JOIN_BSS. */
400/* NDIS_802_11_SSID. */
401struct ndis_802_11_ssid {
402 uint32_t ssidlen;
403 uint8_t ssid[32];
404} __packed;
405
406/* NDIS_802_11_CONFIGURATION_FH. */
407struct ndis_802_11_configuration_fh {
408 uint32_t len;
409 uint32_t hoppattern;
410 uint32_t hopset;
411 uint32_t dwelltime;
412} __packed;
413
414/* NDIS_802_11_CONFIGURATION. */
415struct ndis_802_11_configuration {
416 uint32_t len;
417 uint32_t bintval;
418 uint32_t atim;
419 uint32_t dsconfig;
420 struct ndis_802_11_configuration_fh fhconfig;
421} __packed;
422
423/* NDIS_WLAN_BSSID_EX. */
424struct ndis_wlan_bssid_ex {
425 uint32_t len;
426 uint8_t macaddr[IEEE80211_ADDR_LEN];
427 uint8_t reserved[2];
428 struct ndis_802_11_ssid ssid;
429 uint32_t privacy;
430 int32_t rssi;
431 uint32_t networktype;
432#define NDIS802_11FH 0
433#define NDIS802_11DS 1
434#define NDIS802_11OFDM5 2
435#define NDIS802_11OFDM24 3
436#define NDIS802_11AUTOMODE 4
437
438 struct ndis_802_11_configuration config;
439 uint32_t inframode;
440#define NDIS802_11IBSS 0
441#define NDIS802_11INFRASTRUCTURE 1
442#define NDIS802_11AUTOUNKNOWN 2
443#define NDIS802_11MONITOR 3
444#define NDIS802_11APMODE 4
445
446 uint8_t supprates[16];
447 uint32_t ieslen;
448 /* Followed by ``ieslen'' bytes. */
449} __packed;
450
451/* NDIS_802_11_FIXED_IEs. */
452struct ndis_802_11_fixed_ies {
453 uint8_t tstamp[8];
454 uint16_t bintval;
455 uint16_t capabilities;
456} __packed;
457
458/* Structure for R92S_CMD_SET_PWR_MODE. */
459struct r92s_set_pwr_mode {
460 uint8_t mode;
461#define R92S_PS_MODE_ACTIVE 0
462#define R92S_PS_MODE_MIN 1
463#define R92S_PS_MODE_MAX 2
464#define R92S_PS_MODE_DTIM 3
465#define R92S_PS_MODE_VOIP 4
466#define R92S_PS_MODE_UAPSD_WMM 5
467#define R92S_PS_MODE_UAPSD 6
468#define R92S_PS_MODE_IBSS 7
469#define R92S_PS_MODE_WWLAN 8
470#define R92S_PS_MODE_RADIOOFF 9
471#define R92S_PS_MODE_DISABLE 10
472
473 uint8_t low_traffic_en;
474 uint8_t lpnav_en;
475 uint8_t rf_low_snr_en;
476 uint8_t dps_en;
477 uint8_t bcn_rx_en;
478 uint8_t bcn_pass_cnt;
479 uint8_t bcn_to;
480 uint16_t bcn_itv;
481 uint8_t app_itv;
482 uint8_t awake_bcn_itv;
483 uint8_t smart_ps;
484 uint8_t bcn_pass_time;
485} __packed;
486
487/* Structure for event R92S_EVENT_JOIN_BSS. */
488struct r92s_event_join_bss {
489 uint32_t next;
490 uint32_t prev;
491 uint32_t networktype;
492 uint32_t fixed;
493 uint32_t lastscanned;
494 uint32_t associd;
495 uint32_t join_res;
496 struct ndis_wlan_bssid_ex bss;
497} __packed;
498
499#define R92S_MACID_BSS 5
500
501/* Rx MAC descriptor. */
502struct r92s_rx_stat {
503 uint32_t rxdw0;
504#define R92S_RXDW0_PKTLEN_M 0x00003fff
505#define R92S_RXDW0_PKTLEN_S 0
506#define R92S_RXDW0_CRCERR 0x00004000
507#define R92S_RXDW0_INFOSZ_M 0x000f0000
508#define R92S_RXDW0_INFOSZ_S 16
509#define R92S_RXDW0_QOS 0x00800000
510#define R92S_RXDW0_SHIFT_M 0x03000000
511#define R92S_RXDW0_SHIFT_S 24
512#define R92S_RXDW0_DECRYPTED 0x08000000
513
514 uint32_t rxdw1;
515#define R92S_RXDW1_MOREFRAG 0x08000000
516
517 uint32_t rxdw2;
518#define R92S_RXDW2_FRAG_M 0x0000f000
519#define R92S_RXDW2_FRAG_S 12
520#define R92S_RXDW2_PKTCNT_M 0x00ff0000
521#define R92S_RXDW2_PKTCNT_S 16
522
523 uint32_t rxdw3;
524#define R92S_RXDW3_RATE_M 0x0000003f
525#define R92S_RXDW3_RATE_S 0
526#define R92S_RXDW3_TCPCHKRPT 0x00000800
527#define R92S_RXDW3_IPCHKRPT 0x00001000
528#define R92S_RXDW3_TCPCHKVALID 0x00002000
529#define R92S_RXDW3_HTC 0x00004000
530
531 uint32_t rxdw4;
532 uint32_t rxdw5;
533} __packed __aligned(4);
534
535/* Rx PHY descriptor. */
536struct r92s_rx_phystat {
537 uint32_t phydw0;
538 uint32_t phydw1;
539 uint32_t phydw2;
540 uint32_t phydw3;
541 uint32_t phydw4;
542 uint32_t phydw5;
543 uint32_t phydw6;
544 uint32_t phydw7;
545} __packed __aligned(4);
546
547/* Rx PHY CCK descriptor. */
548struct r92s_rx_cck {
549 uint8_t adc_pwdb[4];
550 uint8_t sq_rpt;
551 uint8_t agc_rpt;
552} __packed;
553
554/* Tx MAC descriptor. */
555struct r92s_tx_desc {
556 uint32_t txdw0;
557#define R92S_TXDW0_PKTLEN_M 0x0000ffff
558#define R92S_TXDW0_PKTLEN_S 0
559#define R92S_TXDW0_OFFSET_M 0x00ff0000
560#define R92S_TXDW0_OFFSET_S 16
561#define R92S_TXDW0_TYPE_M 0x03000000
562#define R92S_TXDW0_TYPE_S 24
563#define R92S_TXDW0_LSG 0x04000000
564#define R92S_TXDW0_FSG 0x08000000
565#define R92S_TXDW0_LINIP 0x10000000
566#define R92S_TXDW0_OWN 0x80000000
567
568 uint32_t txdw1;
569#define R92S_TXDW1_MACID_M 0x0000001f
570#define R92S_TXDW1_MACID_S 0
571#define R92S_TXDW1_MOREDATA 0x00000020
572#define R92S_TXDW1_MOREFRAG 0x00000040
573#define R92S_TXDW1_QSEL_M 0x00001f00
574#define R92S_TXDW1_QSEL_S 8
575#define R92S_TXDW1_QSEL_BE 0x03
576#define R92S_TXDW1_QSEL_H2C 0x1f
577#define R92S_TXDW1_NONQOS 0x00010000
578#define R92S_TXDW1_KEYIDX_M 0x00060000
579#define R92S_TXDW1_KEYIDX_S 17
580#define R92S_TXDW1_CIPHER_M 0x00c00000
581#define R92S_TXDW1_CIPHER_S 22
582#define R92S_TXDW1_CIPHER_WEP 1
583#define R92S_TXDW1_CIPHER_TKIP 2
584#define R92S_TXDW1_CIPHER_AES 3
585#define R92S_TXDW1_HWPC 0x80000000
586
587 uint32_t txdw2;
588#define R92S_TXDW2_BMCAST 0x00000080
589#define R92S_TXDW2_AGGEN 0x20000000
590#define R92S_TXDW2_BK 0x40000000
591
592 uint32_t txdw3;
593#define R92S_TXDW3_SEQ_M 0x0fff0000
594#define R92S_TXDW3_SEQ_S 16
595#define R92S_TXDW3_FRAG_M 0xf0000000
596#define R92S_TXDW3_FRAG_S 28
597
598 uint32_t txdw4;
599#define R92S_TXDW4_TXBW 0x00040000
600
601 uint32_t txdw5;
602#define R92S_TXDW5_DISFB 0x00008000
603
604 uint16_t ipchksum;
605 uint16_t tcpchksum;
606
607 uint16_t txbufsize;
608 uint16_t reserved1;
609} __packed __aligned(4);
610
611struct r92s_add_ba_event {
612 uint8_t mac_addr[IEEE80211_ADDR_LEN];
613 uint16_t ssn;
614 uint8_t tid;
615};
616
617struct r92s_add_ba_req {
618 uint32_t tid;
619};
620
621/*
622 * Driver definitions.
623 */
624#define RSU_RX_LIST_COUNT 100
625#define RSU_TX_LIST_COUNT 32
626
627#define RSU_HOST_CMD_RING_COUNT 32
628
629#define RSU_RXBUFSZ (8 * 1024)
630#define RSU_TXBUFSZ \
631 ((sizeof(struct r92s_tx_desc) + IEEE80211_MAX_LEN + 3) & ~3)
632
633#define RSU_TX_TIMEOUT 5000 /* ms */
634#define RSU_CMD_TIMEOUT 2000 /* ms */
635
636/* Queue ids (used by soft only). */
637#define RSU_QID_BCN 0
638#define RSU_QID_MGT 1
639#define RSU_QID_BMC 2
640#define RSU_QID_VO 3
641#define RSU_QID_VI 4
642#define RSU_QID_BE 5
643#define RSU_QID_BK 6
644#define RSU_QID_RXOFF 7
645#define RSU_QID_H2C 8
646#define RSU_QID_C2H 9
647
648/* Map AC to queue id. */
649static const uint8_t rsu_ac2qid[WME_NUM_AC] = {
650 RSU_QID_BE,
651 RSU_QID_BK,
652 RSU_QID_VI,
653 RSU_QID_VO
654};
655
656/* Pipe index to endpoint address mapping. */
657static const uint8_t r92s_epaddr[] =
658 { 0x83, 0x04, 0x06, 0x0d,
659 0x05, 0x07,
660 0x89, 0x0a, 0x0b, 0x0c };
661
662/* Queue id to pipe index mapping for 4 endpoints configurations. */
663static const uint8_t rsu_qid2idx_4ep[] =
664 { 3, 3, 3, 1, 1, 2, 2, 0, 3, 0 };
665
666/* Queue id to pipe index mapping for 6 endpoints configurations. */
667static const uint8_t rsu_qid2idx_6ep[] =
668 { 3, 3, 3, 1, 4, 2, 5, 0, 3, 0 };
669
670/* Queue id to pipe index mapping for 11 endpoints configurations. */
671static const uint8_t rsu_qid2idx_11ep[] =
672 { 7, 9, 8, 1, 4, 2, 5, 0, 3, 6 };
673
674struct rsu_rx_radiotap_header {
675 struct ieee80211_radiotap_header wr_ihdr;
676 uint8_t wr_flags;
677 uint8_t wr_rate;
678 uint16_t wr_chan_freq;
679 uint16_t wr_chan_flags;
680 uint8_t wr_dbm_antsignal;
681} __packed __aligned(8);
682
683#define RSU_RX_RADIOTAP_PRESENT \
684 (1 << IEEE80211_RADIOTAP_FLAGS | \
685 1 << IEEE80211_RADIOTAP_RATE | \
686 1 << IEEE80211_RADIOTAP_CHANNEL | \
687 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)
688
689struct rsu_tx_radiotap_header {
690 struct ieee80211_radiotap_header wt_ihdr;
691 uint8_t wt_flags;
692 uint16_t wt_chan_freq;
693 uint16_t wt_chan_flags;
694} __packed __aligned(8);
695
696#define RSU_TX_RADIOTAP_PRESENT \
697 (1 << IEEE80211_RADIOTAP_FLAGS | \
698 1 << IEEE80211_RADIOTAP_CHANNEL)
699
700struct rsu_softc;
701
702struct rsu_host_cmd {
703 void (*cb)(struct rsu_softc *, void *);
704 uint8_t data[256];
705};
706
707struct rsu_cmd_newstate {
708 enum ieee80211_state state;
709 int arg;
710};
711
712struct rsu_cmd_key {
713 struct ieee80211_key key;
714};
715
716struct rsu_host_cmd_ring {
717 struct rsu_host_cmd cmd[RSU_HOST_CMD_RING_COUNT];
718 int cur;
719 int next;
720 int queued;
721};
722
723enum {
724 RSU_BULK_RX,
725 RSU_BULK_TX_BE_BK, /* = WME_AC_BE/BK */
726 RSU_BULK_TX_VI_VO, /* = WME_AC_VI/VO */
727 RSU_BULK_TX_H2C, /* H2C */
728 RSU_N_TRANSFER,
729};
730
731struct rsu_data {
732 struct rsu_softc *sc;
733 uint8_t *buf;
734 uint16_t buflen;
735 struct mbuf *m;
736 struct ieee80211_node *ni;
737 STAILQ_ENTRY(rsu_data) next;
738};
739
740struct rsu_vap {
741 struct ieee80211vap vap;
742
743 int (*newstate)(struct ieee80211vap *,
744 enum ieee80211_state, int);
745};
746#define RSU_VAP(vap) ((struct rsu_vap *)(vap))
747
748#define RSU_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
749#define RSU_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
750#define RSU_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
751
752struct rsu_softc {
753 struct ieee80211com sc_ic;
754 struct mbufq sc_snd;
755 device_t sc_dev;
756 struct usb_device *sc_udev;
757 int (*sc_newstate)(struct ieee80211com *,
758 enum ieee80211_state, int);
759 struct usbd_interface *sc_iface;
760 struct timeout_task calib_task;
761 struct task tx_task;
762 const uint8_t *qid2idx;
763 struct mtx sc_mtx;
764 int sc_ht;
765 int sc_nendpoints;
766 int sc_curpwrstate;
767 int sc_currssi;
768
769 u_int sc_running:1,
770 sc_calibrating:1,
771 sc_scanning:1,
772 sc_scan_pass:1;
773 u_int cut;
774 uint8_t sc_rftype;
775 int8_t sc_nrxstream;
776 int8_t sc_ntxstream;
777 struct rsu_host_cmd_ring cmdq;
778 struct rsu_data sc_rx[RSU_RX_LIST_COUNT];
779 struct rsu_data sc_tx[RSU_TX_LIST_COUNT];
780 struct rsu_data *fwcmd_data;
781 uint8_t cmd_seq;
782 uint8_t rom[128];
783 struct usb_xfer *sc_xfer[RSU_N_TRANSFER];
784
785 STAILQ_HEAD(, rsu_data) sc_rx_active;
786 STAILQ_HEAD(, rsu_data) sc_rx_inactive;
787 STAILQ_HEAD(, rsu_data) sc_tx_active[RSU_N_TRANSFER];
788 STAILQ_HEAD(, rsu_data) sc_tx_inactive;
789 STAILQ_HEAD(, rsu_data) sc_tx_pending[RSU_N_TRANSFER];
790
791 union {
792 struct rsu_rx_radiotap_header th;
793 uint8_t pad[64];
794 } sc_rxtapu;
795#define sc_rxtap sc_rxtapu.th
| 18 */
19
20/* USB Requests. */
21#define R92S_REQ_REGS 0x05
22
23/*
24 * MAC registers.
25 */
26#define R92S_SYSCFG 0x0000
27#define R92S_SYS_ISO_CTRL (R92S_SYSCFG + 0x000)
28#define R92S_SYS_FUNC_EN (R92S_SYSCFG + 0x002)
29#define R92S_PMC_FSM (R92S_SYSCFG + 0x004)
30#define R92S_SYS_CLKR (R92S_SYSCFG + 0x008)
31#define R92S_EE_9346CR (R92S_SYSCFG + 0x00a)
32#define R92S_AFE_MISC (R92S_SYSCFG + 0x010)
33#define R92S_SPS0_CTRL (R92S_SYSCFG + 0x011)
34#define R92S_SPS1_CTRL (R92S_SYSCFG + 0x018)
35#define R92S_RF_CTRL (R92S_SYSCFG + 0x01f)
36#define R92S_LDOA15_CTRL (R92S_SYSCFG + 0x020)
37#define R92S_LDOV12D_CTRL (R92S_SYSCFG + 0x021)
38#define R92S_AFE_XTAL_CTRL (R92S_SYSCFG + 0x026)
39#define R92S_AFE_PLL_CTRL (R92S_SYSCFG + 0x028)
40#define R92S_EFUSE_CTRL (R92S_SYSCFG + 0x030)
41#define R92S_EFUSE_TEST (R92S_SYSCFG + 0x034)
42#define R92S_EFUSE_CLK_CTRL (R92S_SYSCFG + 0x2f8)
43
44#define R92S_CMDCTRL 0x0040
45#define R92S_CR (R92S_CMDCTRL + 0x000)
46#define R92S_TCR (R92S_CMDCTRL + 0x004)
47#define R92S_RCR (R92S_CMDCTRL + 0x008)
48
49#define R92S_MACIDSETTING 0x0050
50#define R92S_MACID (R92S_MACIDSETTING + 0x000)
51
52#define R92S_GP 0x01e0
53#define R92S_GPIO_CTRL (R92S_GP + 0x00c)
54#define R92S_GPIO_IO_SEL (R92S_GP + 0x00e)
55#define R92S_MAC_PINMUX_CTRL (R92S_GP + 0x011)
56
57#define R92S_IOCMD_CTRL 0x0370
58#define R92S_IOCMD_DATA 0x0374
59
60#define R92S_USB_HRPWM 0xfe58
61
62/* Bits for R92S_SYS_FUNC_EN. */
63#define R92S_FEN_CPUEN 0x0400
64
65/* Bits for R92S_PMC_FSM. */
66#define R92S_PMC_FSM_CUT_M 0x000f8000
67#define R92S_PMC_FSM_CUT_S 15
68
69/* Bits for R92S_SYS_CLKR. */
70#define R92S_SYS_CLKSEL 0x0001
71#define R92S_SYS_PS_CLKSEL 0x0002
72#define R92S_SYS_CPU_CLKSEL 0x0004
73#define R92S_MAC_CLK_EN 0x0800
74#define R92S_SYS_CLK_EN 0x1000
75#define R92S_SWHW_SEL 0x4000
76#define R92S_FWHW_SEL 0x8000
77
78/* Bits for R92S_EE_9346CR. */
79#define R92S_9356SEL 0x10
80#define R92S_EEPROM_EN 0x20
81
82/* Bits for R92S_AFE_MISC. */
83#define R92S_AFE_MISC_BGEN 0x01
84#define R92S_AFE_MISC_MBEN 0x02
85#define R92S_AFE_MISC_I32_EN 0x08
86
87/* Bits for R92S_SPS1_CTRL. */
88#define R92S_SPS1_LDEN 0x01
89#define R92S_SPS1_SWEN 0x02
90
91/* Bits for R92S_LDOA15_CTRL. */
92#define R92S_LDA15_EN 0x01
93
94/* Bits for R92S_LDOV12D_CTRL. */
95#define R92S_LDV12_EN 0x01
96
97/* Bits for R92C_EFUSE_CTRL. */
98#define R92S_EFUSE_CTRL_DATA_M 0x000000ff
99#define R92S_EFUSE_CTRL_DATA_S 0
100#define R92S_EFUSE_CTRL_ADDR_M 0x0003ff00
101#define R92S_EFUSE_CTRL_ADDR_S 8
102#define R92S_EFUSE_CTRL_VALID 0x80000000
103
104/* Bits for R92S_CR. */
105#define R92S_CR_TXDMA_EN 0x10
106
107/* Bits for R92S_TCR. */
108#define R92S_TCR_IMEM_CODE_DONE 0x01
109#define R92S_TCR_IMEM_CHK_RPT 0x02
110#define R92S_TCR_EMEM_CODE_DONE 0x04
111#define R92S_TCR_EMEM_CHK_RPT 0x08
112#define R92S_TCR_DMEM_CODE_DONE 0x10
113#define R92S_TCR_IMEM_RDY 0x20
114#define R92S_TCR_FWRDY 0x80
115
116/* Bits for R92S_GPIO_IO_SEL. */
117#define R92S_GPIO_WPS 0x10
118
119/* Bits for R92S_MAC_PINMUX_CTRL. */
120#define R92S_GPIOSEL_GPIO_M 0x03
121#define R92S_GPIOSEL_GPIO_S 0
122#define R92S_GPIOSEL_GPIO_JTAG 0
123#define R92S_GPIOSEL_GPIO_PHYDBG 1
124#define R92S_GPIOSEL_GPIO_BT 2
125#define R92S_GPIOSEL_GPIO_WLANDBG 3
126#define R92S_GPIOMUX_EN 0x08
127
128/* Bits for R92S_IOCMD_CTRL. */
129#define R92S_IOCMD_CLASS_M 0xff000000
130#define R92S_IOCMD_CLASS_S 24
131#define R92S_IOCMD_CLASS_BB_RF 0xf0
132#define R92S_IOCMD_VALUE_M 0x00ffff00
133#define R92S_IOCMD_VALUE_S 8
134#define R92S_IOCMD_INDEX_M 0x000000ff
135#define R92S_IOCMD_INDEX_S 0
136#define R92S_IOCMD_INDEX_BB_READ 0
137#define R92S_IOCMD_INDEX_BB_WRITE 1
138#define R92S_IOCMD_INDEX_RF_READ 2
139#define R92S_IOCMD_INDEX_RF_WRITE 3
140
141/* Bits for R92S_USB_HRPWM. */
142#define R92S_USB_HRPWM_PS_ALL_ON 0x04
143#define R92S_USB_HRPWM_PS_ST_ACTIVE 0x08
144
145/*
146 * Macros to access subfields in registers.
147 */
148/* Mask and Shift (getter). */
149#define MS(val, field) \
150 (((val) & field##_M) >> field##_S)
151
152/* Shift and Mask (setter). */
153#define SM(field, val) \
154 (((val) << field##_S) & field##_M)
155
156/* Rewrite. */
157#define RW(var, field, val) \
158 (((var) & ~field##_M) | SM(field, val))
159
160/*
161 * ROM field with RF config.
162 */
163enum {
164 RTL8712_RFCONFIG_1T = 0x10,
165 RTL8712_RFCONFIG_2T = 0x20,
166 RTL8712_RFCONFIG_1R = 0x01,
167 RTL8712_RFCONFIG_2R = 0x02,
168 RTL8712_RFCONFIG_1T1R = 0x11,
169 RTL8712_RFCONFIG_1T2R = 0x12,
170 RTL8712_RFCONFIG_TURBO = 0x92,
171 RTL8712_RFCONFIG_2T2R = 0x22
172};
173
174/*
175 * Firmware image header.
176 */
177struct r92s_fw_priv {
178 /* QWORD0 */
179 uint16_t signature;
180 uint8_t hci_sel;
181#define R92S_HCI_SEL_PCIE 0x01
182#define R92S_HCI_SEL_USB 0x02
183#define R92S_HCI_SEL_SDIO 0x04
184#define R92S_HCI_SEL_8172 0x10
185#define R92S_HCI_SEL_AP 0x80
186
187 uint8_t chip_version;
188 uint16_t custid;
189 uint8_t rf_config;
190//0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R
191 uint8_t nendpoints;
192 /* QWORD1 */
193 uint32_t regulatory;
194 uint8_t rfintfs;
195 uint8_t def_nettype;
196 uint8_t turbo_mode;
197 uint8_t lowpower_mode;
198 /* QWORD2 */
199 uint8_t lbk_mode;
200 uint8_t mp_mode;
201 uint8_t vcs_type;
202#define R92S_VCS_TYPE_DISABLE 0
203#define R92S_VCS_TYPE_ENABLE 1
204#define R92S_VCS_TYPE_AUTO 2
205
206 uint8_t vcs_mode;
207#define R92S_VCS_MODE_NONE 0
208#define R92S_VCS_MODE_RTS_CTS 1
209#define R92S_VCS_MODE_CTS2SELF 2
210
211 uint32_t reserved1;
212 /* QWORD3 */
213 uint8_t qos_en;
214 uint8_t bw40_en;
215 uint8_t amsdu2ampdu_en;
216 uint8_t ampdu_en;
217 uint8_t rc_offload;
218 uint8_t agg_offload;
219 uint16_t reserved2;
220 /* QWORD4 */
221 uint8_t beacon_offload;
222 uint8_t mlme_offload;
223 uint8_t hwpc_offload;
224 uint8_t tcpcsum_offload;
225 uint8_t tcp_offload;
226 uint8_t ps_offload;
227 uint8_t wwlan_offload;
228 uint8_t reserved3;
229 /* QWORD5 */
230 uint16_t tcp_tx_len;
231 uint16_t tcp_rx_len;
232 uint32_t reserved4;
233} __packed;
234
235struct r92s_fw_hdr {
236 uint16_t signature;
237 uint16_t version;
238 uint32_t dmemsz;
239 uint32_t imemsz;
240 uint32_t sramsz;
241 uint32_t privsz;
242 uint16_t efuse_addr;
243 uint16_t h2c_resp_addr;
244 uint32_t svnrev;
245 uint8_t month;
246 uint8_t day;
247 uint8_t hour;
248 uint8_t minute;
249 struct r92s_fw_priv priv;
250} __packed;
251
252/* Structure for FW commands and FW events notifications. */
253struct r92s_fw_cmd_hdr {
254 uint16_t len;
255 uint8_t code;
256 uint8_t seq;
257#define R92S_FW_CMD_MORE 0x80
258
259 uint32_t reserved;
260} __packed;
261
262/* FW commands codes. */
263#define R92S_CMD_READ_MACREG 0
264#define R92S_CMD_WRITE_MACREG 1
265#define R92S_CMD_READ_BBREG 2
266#define R92S_CMD_WRITE_BBREG 3
267#define R92S_CMD_READ_RFREG 4
268#define R92S_CMD_WRITE_RFREG 5
269#define R92S_CMD_READ_EEPROM 6
270#define R92S_CMD_WRITE_EEPROM 7
271#define R92S_CMD_READ_EFUSE 8
272#define R92S_CMD_WRITE_EFUSE 9
273#define R92S_CMD_READ_CAM 10
274#define R92S_CMD_WRITE_CAM 11
275#define R92S_CMD_SET_BCNITV 12
276#define R92S_CMD_SET_MBIDCFG 13
277#define R92S_CMD_JOIN_BSS 14
278#define R92S_CMD_DISCONNECT 15
279#define R92S_CMD_CREATE_BSS 16
280#define R92S_CMD_SET_OPMODE 17
281#define R92S_CMD_SITE_SURVEY 18
282#define R92S_CMD_SET_AUTH 19
283#define R92S_CMD_SET_KEY 20
284#define R92S_CMD_SET_STA_KEY 21
285#define R92S_CMD_SET_ASSOC_STA 22
286#define R92S_CMD_DEL_ASSOC_STA 23
287#define R92S_CMD_SET_STAPWRSTATE 24
288#define R92S_CMD_SET_BASIC_RATE 25
289#define R92S_CMD_GET_BASIC_RATE 26
290#define R92S_CMD_SET_DATA_RATE 27
291#define R92S_CMD_GET_DATA_RATE 28
292#define R92S_CMD_SET_PHY_INFO 29
293#define R92S_CMD_GET_PHY_INFO 30
294#define R92S_CMD_SET_PHY 31
295#define R92S_CMD_GET_PHY 32
296#define R92S_CMD_READ_RSSI 33
297#define R92S_CMD_READ_GAIN 34
298#define R92S_CMD_SET_ATIM 35
299#define R92S_CMD_SET_PWR_MODE 36
300#define R92S_CMD_JOIN_BSS_RPT 37
301#define R92S_CMD_SET_RA_TABLE 38
302#define R92S_CMD_GET_RA_TABLE 39
303#define R92S_CMD_GET_CCX_REPORT 40
304#define R92S_CMD_GET_DTM_REPORT 41
305#define R92S_CMD_GET_TXRATE_STATS 42
306#define R92S_CMD_SET_USB_SUSPEND 43
307#define R92S_CMD_SET_H2C_LBK 44
308#define R92S_CMD_ADDBA_REQ 45
309#define R92S_CMD_SET_CHANNEL 46
310#define R92S_CMD_SET_TXPOWER 47
311#define R92S_CMD_SWITCH_ANTENNA 48
312#define R92S_CMD_SET_CRYSTAL_CAL 49
313#define R92S_CMD_SET_SINGLE_CARRIER_TX 50
314#define R92S_CMD_SET_SINGLE_TONE_TX 51
315#define R92S_CMD_SET_CARRIER_SUPPR_TX 52
316#define R92S_CMD_SET_CONTINUOUS_TX 53
317#define R92S_CMD_SWITCH_BANDWIDTH 54
318#define R92S_CMD_TX_BEACON 55
319#define R92S_CMD_SET_POWER_TRACKING 56
320#define R92S_CMD_AMSDU_TO_AMPDU 57
321#define R92S_CMD_SET_MAC_ADDRESS 58
322#define R92S_CMD_GET_H2C_LBK 59
323#define R92S_CMD_SET_PBREQ_IE 60
324#define R92S_CMD_SET_ASSOCREQ_IE 61
325#define R92S_CMD_SET_PBRESP_IE 62
326#define R92S_CMD_SET_ASSOCRESP_IE 63
327#define R92S_CMD_GET_CURDATARATE 64
328#define R92S_CMD_GET_TXRETRY_CNT 65
329#define R92S_CMD_GET_RXRETRY_CNT 66
330#define R92S_CMD_GET_BCNOK_CNT 67
331#define R92S_CMD_GET_BCNERR_CNT 68
332#define R92S_CMD_GET_CURTXPWR_LEVEL 69
333#define R92S_CMD_SET_DIG 70
334#define R92S_CMD_SET_RA 71
335#define R92S_CMD_SET_PT 72
336#define R92S_CMD_READ_TSSI 73
337
338/* FW events notifications codes. */
339#define R92S_EVT_READ_MACREG 0
340#define R92S_EVT_READ_BBREG 1
341#define R92S_EVT_READ_RFREG 2
342#define R92S_EVT_READ_EEPROM 3
343#define R92S_EVT_READ_EFUSE 4
344#define R92S_EVT_READ_CAM 5
345#define R92S_EVT_GET_BASICRATE 6
346#define R92S_EVT_GET_DATARATE 7
347#define R92S_EVT_SURVEY 8
348#define R92S_EVT_SURVEY_DONE 9
349#define R92S_EVT_JOIN_BSS 10
350#define R92S_EVT_ADD_STA 11
351#define R92S_EVT_DEL_STA 12
352#define R92S_EVT_ATIM_DONE 13
353#define R92S_EVT_TX_REPORT 14
354#define R92S_EVT_CCX_REPORT 15
355#define R92S_EVT_DTM_REPORT 16
356#define R92S_EVT_TXRATE_STATS 17
357#define R92S_EVT_C2H_LBK 18
358#define R92S_EVT_FWDBG 19
359#define R92S_EVT_C2H_FEEDBACK 20
360#define R92S_EVT_ADDBA 21
361#define R92S_EVT_C2H_BCN 22
362#define R92S_EVT_PWR_STATE 23
363#define R92S_EVT_WPS_PBC 24
364#define R92S_EVT_ADDBA_REQ_REPORT 25
365
366/* Structure for R92S_CMD_SITE_SURVEY. */
367struct r92s_fw_cmd_sitesurvey {
368 uint32_t active;
369 uint32_t limit;
370 uint32_t ssidlen;
371 uint8_t ssid[32 + 1];
372} __packed;
373
374/* Structure for R92S_CMD_SET_AUTH. */
375struct r92s_fw_cmd_auth {
376 uint8_t mode;
377#define R92S_AUTHMODE_OPEN 0
378#define R92S_AUTHMODE_SHARED 1
379#define R92S_AUTHMODE_WPA 2
380
381 uint8_t dot1x;
382} __packed;
383
384/* Structure for R92S_CMD_SET_KEY. */
385struct r92s_fw_cmd_set_key {
386 uint8_t algo;
387#define R92S_KEY_ALGO_NONE 0
388#define R92S_KEY_ALGO_WEP40 1
389#define R92S_KEY_ALGO_TKIP 2
390#define R92S_KEY_ALGO_TKIP_MMIC 3
391#define R92S_KEY_ALGO_AES 4
392#define R92S_KEY_ALGO_WEP104 5
393
394 uint8_t id;
395 uint8_t grpkey;
396 uint8_t key[16];
397} __packed;
398
399/* Structures for R92S_EVENT_SURVEY/R92S_CMD_JOIN_BSS. */
400/* NDIS_802_11_SSID. */
401struct ndis_802_11_ssid {
402 uint32_t ssidlen;
403 uint8_t ssid[32];
404} __packed;
405
406/* NDIS_802_11_CONFIGURATION_FH. */
407struct ndis_802_11_configuration_fh {
408 uint32_t len;
409 uint32_t hoppattern;
410 uint32_t hopset;
411 uint32_t dwelltime;
412} __packed;
413
414/* NDIS_802_11_CONFIGURATION. */
415struct ndis_802_11_configuration {
416 uint32_t len;
417 uint32_t bintval;
418 uint32_t atim;
419 uint32_t dsconfig;
420 struct ndis_802_11_configuration_fh fhconfig;
421} __packed;
422
423/* NDIS_WLAN_BSSID_EX. */
424struct ndis_wlan_bssid_ex {
425 uint32_t len;
426 uint8_t macaddr[IEEE80211_ADDR_LEN];
427 uint8_t reserved[2];
428 struct ndis_802_11_ssid ssid;
429 uint32_t privacy;
430 int32_t rssi;
431 uint32_t networktype;
432#define NDIS802_11FH 0
433#define NDIS802_11DS 1
434#define NDIS802_11OFDM5 2
435#define NDIS802_11OFDM24 3
436#define NDIS802_11AUTOMODE 4
437
438 struct ndis_802_11_configuration config;
439 uint32_t inframode;
440#define NDIS802_11IBSS 0
441#define NDIS802_11INFRASTRUCTURE 1
442#define NDIS802_11AUTOUNKNOWN 2
443#define NDIS802_11MONITOR 3
444#define NDIS802_11APMODE 4
445
446 uint8_t supprates[16];
447 uint32_t ieslen;
448 /* Followed by ``ieslen'' bytes. */
449} __packed;
450
451/* NDIS_802_11_FIXED_IEs. */
452struct ndis_802_11_fixed_ies {
453 uint8_t tstamp[8];
454 uint16_t bintval;
455 uint16_t capabilities;
456} __packed;
457
458/* Structure for R92S_CMD_SET_PWR_MODE. */
459struct r92s_set_pwr_mode {
460 uint8_t mode;
461#define R92S_PS_MODE_ACTIVE 0
462#define R92S_PS_MODE_MIN 1
463#define R92S_PS_MODE_MAX 2
464#define R92S_PS_MODE_DTIM 3
465#define R92S_PS_MODE_VOIP 4
466#define R92S_PS_MODE_UAPSD_WMM 5
467#define R92S_PS_MODE_UAPSD 6
468#define R92S_PS_MODE_IBSS 7
469#define R92S_PS_MODE_WWLAN 8
470#define R92S_PS_MODE_RADIOOFF 9
471#define R92S_PS_MODE_DISABLE 10
472
473 uint8_t low_traffic_en;
474 uint8_t lpnav_en;
475 uint8_t rf_low_snr_en;
476 uint8_t dps_en;
477 uint8_t bcn_rx_en;
478 uint8_t bcn_pass_cnt;
479 uint8_t bcn_to;
480 uint16_t bcn_itv;
481 uint8_t app_itv;
482 uint8_t awake_bcn_itv;
483 uint8_t smart_ps;
484 uint8_t bcn_pass_time;
485} __packed;
486
487/* Structure for event R92S_EVENT_JOIN_BSS. */
488struct r92s_event_join_bss {
489 uint32_t next;
490 uint32_t prev;
491 uint32_t networktype;
492 uint32_t fixed;
493 uint32_t lastscanned;
494 uint32_t associd;
495 uint32_t join_res;
496 struct ndis_wlan_bssid_ex bss;
497} __packed;
498
499#define R92S_MACID_BSS 5
500
501/* Rx MAC descriptor. */
502struct r92s_rx_stat {
503 uint32_t rxdw0;
504#define R92S_RXDW0_PKTLEN_M 0x00003fff
505#define R92S_RXDW0_PKTLEN_S 0
506#define R92S_RXDW0_CRCERR 0x00004000
507#define R92S_RXDW0_INFOSZ_M 0x000f0000
508#define R92S_RXDW0_INFOSZ_S 16
509#define R92S_RXDW0_QOS 0x00800000
510#define R92S_RXDW0_SHIFT_M 0x03000000
511#define R92S_RXDW0_SHIFT_S 24
512#define R92S_RXDW0_DECRYPTED 0x08000000
513
514 uint32_t rxdw1;
515#define R92S_RXDW1_MOREFRAG 0x08000000
516
517 uint32_t rxdw2;
518#define R92S_RXDW2_FRAG_M 0x0000f000
519#define R92S_RXDW2_FRAG_S 12
520#define R92S_RXDW2_PKTCNT_M 0x00ff0000
521#define R92S_RXDW2_PKTCNT_S 16
522
523 uint32_t rxdw3;
524#define R92S_RXDW3_RATE_M 0x0000003f
525#define R92S_RXDW3_RATE_S 0
526#define R92S_RXDW3_TCPCHKRPT 0x00000800
527#define R92S_RXDW3_IPCHKRPT 0x00001000
528#define R92S_RXDW3_TCPCHKVALID 0x00002000
529#define R92S_RXDW3_HTC 0x00004000
530
531 uint32_t rxdw4;
532 uint32_t rxdw5;
533} __packed __aligned(4);
534
535/* Rx PHY descriptor. */
536struct r92s_rx_phystat {
537 uint32_t phydw0;
538 uint32_t phydw1;
539 uint32_t phydw2;
540 uint32_t phydw3;
541 uint32_t phydw4;
542 uint32_t phydw5;
543 uint32_t phydw6;
544 uint32_t phydw7;
545} __packed __aligned(4);
546
547/* Rx PHY CCK descriptor. */
548struct r92s_rx_cck {
549 uint8_t adc_pwdb[4];
550 uint8_t sq_rpt;
551 uint8_t agc_rpt;
552} __packed;
553
554/* Tx MAC descriptor. */
555struct r92s_tx_desc {
556 uint32_t txdw0;
557#define R92S_TXDW0_PKTLEN_M 0x0000ffff
558#define R92S_TXDW0_PKTLEN_S 0
559#define R92S_TXDW0_OFFSET_M 0x00ff0000
560#define R92S_TXDW0_OFFSET_S 16
561#define R92S_TXDW0_TYPE_M 0x03000000
562#define R92S_TXDW0_TYPE_S 24
563#define R92S_TXDW0_LSG 0x04000000
564#define R92S_TXDW0_FSG 0x08000000
565#define R92S_TXDW0_LINIP 0x10000000
566#define R92S_TXDW0_OWN 0x80000000
567
568 uint32_t txdw1;
569#define R92S_TXDW1_MACID_M 0x0000001f
570#define R92S_TXDW1_MACID_S 0
571#define R92S_TXDW1_MOREDATA 0x00000020
572#define R92S_TXDW1_MOREFRAG 0x00000040
573#define R92S_TXDW1_QSEL_M 0x00001f00
574#define R92S_TXDW1_QSEL_S 8
575#define R92S_TXDW1_QSEL_BE 0x03
576#define R92S_TXDW1_QSEL_H2C 0x1f
577#define R92S_TXDW1_NONQOS 0x00010000
578#define R92S_TXDW1_KEYIDX_M 0x00060000
579#define R92S_TXDW1_KEYIDX_S 17
580#define R92S_TXDW1_CIPHER_M 0x00c00000
581#define R92S_TXDW1_CIPHER_S 22
582#define R92S_TXDW1_CIPHER_WEP 1
583#define R92S_TXDW1_CIPHER_TKIP 2
584#define R92S_TXDW1_CIPHER_AES 3
585#define R92S_TXDW1_HWPC 0x80000000
586
587 uint32_t txdw2;
588#define R92S_TXDW2_BMCAST 0x00000080
589#define R92S_TXDW2_AGGEN 0x20000000
590#define R92S_TXDW2_BK 0x40000000
591
592 uint32_t txdw3;
593#define R92S_TXDW3_SEQ_M 0x0fff0000
594#define R92S_TXDW3_SEQ_S 16
595#define R92S_TXDW3_FRAG_M 0xf0000000
596#define R92S_TXDW3_FRAG_S 28
597
598 uint32_t txdw4;
599#define R92S_TXDW4_TXBW 0x00040000
600
601 uint32_t txdw5;
602#define R92S_TXDW5_DISFB 0x00008000
603
604 uint16_t ipchksum;
605 uint16_t tcpchksum;
606
607 uint16_t txbufsize;
608 uint16_t reserved1;
609} __packed __aligned(4);
610
611struct r92s_add_ba_event {
612 uint8_t mac_addr[IEEE80211_ADDR_LEN];
613 uint16_t ssn;
614 uint8_t tid;
615};
616
617struct r92s_add_ba_req {
618 uint32_t tid;
619};
620
621/*
622 * Driver definitions.
623 */
624#define RSU_RX_LIST_COUNT 100
625#define RSU_TX_LIST_COUNT 32
626
627#define RSU_HOST_CMD_RING_COUNT 32
628
629#define RSU_RXBUFSZ (8 * 1024)
630#define RSU_TXBUFSZ \
631 ((sizeof(struct r92s_tx_desc) + IEEE80211_MAX_LEN + 3) & ~3)
632
633#define RSU_TX_TIMEOUT 5000 /* ms */
634#define RSU_CMD_TIMEOUT 2000 /* ms */
635
636/* Queue ids (used by soft only). */
637#define RSU_QID_BCN 0
638#define RSU_QID_MGT 1
639#define RSU_QID_BMC 2
640#define RSU_QID_VO 3
641#define RSU_QID_VI 4
642#define RSU_QID_BE 5
643#define RSU_QID_BK 6
644#define RSU_QID_RXOFF 7
645#define RSU_QID_H2C 8
646#define RSU_QID_C2H 9
647
648/* Map AC to queue id. */
649static const uint8_t rsu_ac2qid[WME_NUM_AC] = {
650 RSU_QID_BE,
651 RSU_QID_BK,
652 RSU_QID_VI,
653 RSU_QID_VO
654};
655
656/* Pipe index to endpoint address mapping. */
657static const uint8_t r92s_epaddr[] =
658 { 0x83, 0x04, 0x06, 0x0d,
659 0x05, 0x07,
660 0x89, 0x0a, 0x0b, 0x0c };
661
662/* Queue id to pipe index mapping for 4 endpoints configurations. */
663static const uint8_t rsu_qid2idx_4ep[] =
664 { 3, 3, 3, 1, 1, 2, 2, 0, 3, 0 };
665
666/* Queue id to pipe index mapping for 6 endpoints configurations. */
667static const uint8_t rsu_qid2idx_6ep[] =
668 { 3, 3, 3, 1, 4, 2, 5, 0, 3, 0 };
669
670/* Queue id to pipe index mapping for 11 endpoints configurations. */
671static const uint8_t rsu_qid2idx_11ep[] =
672 { 7, 9, 8, 1, 4, 2, 5, 0, 3, 6 };
673
674struct rsu_rx_radiotap_header {
675 struct ieee80211_radiotap_header wr_ihdr;
676 uint8_t wr_flags;
677 uint8_t wr_rate;
678 uint16_t wr_chan_freq;
679 uint16_t wr_chan_flags;
680 uint8_t wr_dbm_antsignal;
681} __packed __aligned(8);
682
683#define RSU_RX_RADIOTAP_PRESENT \
684 (1 << IEEE80211_RADIOTAP_FLAGS | \
685 1 << IEEE80211_RADIOTAP_RATE | \
686 1 << IEEE80211_RADIOTAP_CHANNEL | \
687 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)
688
689struct rsu_tx_radiotap_header {
690 struct ieee80211_radiotap_header wt_ihdr;
691 uint8_t wt_flags;
692 uint16_t wt_chan_freq;
693 uint16_t wt_chan_flags;
694} __packed __aligned(8);
695
696#define RSU_TX_RADIOTAP_PRESENT \
697 (1 << IEEE80211_RADIOTAP_FLAGS | \
698 1 << IEEE80211_RADIOTAP_CHANNEL)
699
700struct rsu_softc;
701
702struct rsu_host_cmd {
703 void (*cb)(struct rsu_softc *, void *);
704 uint8_t data[256];
705};
706
707struct rsu_cmd_newstate {
708 enum ieee80211_state state;
709 int arg;
710};
711
712struct rsu_cmd_key {
713 struct ieee80211_key key;
714};
715
716struct rsu_host_cmd_ring {
717 struct rsu_host_cmd cmd[RSU_HOST_CMD_RING_COUNT];
718 int cur;
719 int next;
720 int queued;
721};
722
723enum {
724 RSU_BULK_RX,
725 RSU_BULK_TX_BE_BK, /* = WME_AC_BE/BK */
726 RSU_BULK_TX_VI_VO, /* = WME_AC_VI/VO */
727 RSU_BULK_TX_H2C, /* H2C */
728 RSU_N_TRANSFER,
729};
730
731struct rsu_data {
732 struct rsu_softc *sc;
733 uint8_t *buf;
734 uint16_t buflen;
735 struct mbuf *m;
736 struct ieee80211_node *ni;
737 STAILQ_ENTRY(rsu_data) next;
738};
739
740struct rsu_vap {
741 struct ieee80211vap vap;
742
743 int (*newstate)(struct ieee80211vap *,
744 enum ieee80211_state, int);
745};
746#define RSU_VAP(vap) ((struct rsu_vap *)(vap))
747
748#define RSU_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
749#define RSU_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
750#define RSU_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
751
752struct rsu_softc {
753 struct ieee80211com sc_ic;
754 struct mbufq sc_snd;
755 device_t sc_dev;
756 struct usb_device *sc_udev;
757 int (*sc_newstate)(struct ieee80211com *,
758 enum ieee80211_state, int);
759 struct usbd_interface *sc_iface;
760 struct timeout_task calib_task;
761 struct task tx_task;
762 const uint8_t *qid2idx;
763 struct mtx sc_mtx;
764 int sc_ht;
765 int sc_nendpoints;
766 int sc_curpwrstate;
767 int sc_currssi;
768
769 u_int sc_running:1,
770 sc_calibrating:1,
771 sc_scanning:1,
772 sc_scan_pass:1;
773 u_int cut;
774 uint8_t sc_rftype;
775 int8_t sc_nrxstream;
776 int8_t sc_ntxstream;
777 struct rsu_host_cmd_ring cmdq;
778 struct rsu_data sc_rx[RSU_RX_LIST_COUNT];
779 struct rsu_data sc_tx[RSU_TX_LIST_COUNT];
780 struct rsu_data *fwcmd_data;
781 uint8_t cmd_seq;
782 uint8_t rom[128];
783 struct usb_xfer *sc_xfer[RSU_N_TRANSFER];
784
785 STAILQ_HEAD(, rsu_data) sc_rx_active;
786 STAILQ_HEAD(, rsu_data) sc_rx_inactive;
787 STAILQ_HEAD(, rsu_data) sc_tx_active[RSU_N_TRANSFER];
788 STAILQ_HEAD(, rsu_data) sc_tx_inactive;
789 STAILQ_HEAD(, rsu_data) sc_tx_pending[RSU_N_TRANSFER];
790
791 union {
792 struct rsu_rx_radiotap_header th;
793 uint8_t pad[64];
794 } sc_rxtapu;
795#define sc_rxtap sc_rxtapu.th
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