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if_txpreg.h (189690) if_txpreg.h (189714)
1/* $OpenBSD: if_txpreg.h,v 1.30 2001/06/23 04:18:02 jason Exp $ */
1/* $OpenBSD: if_txpreg.h,v 1.30 2001/06/23 04:18:02 jason Exp $ */
2/* $FreeBSD: head/sys/dev/txp/if_txpreg.h 189690 2009-03-11 09:57:11Z yongari $ */
2/* $FreeBSD: head/sys/dev/txp/if_txpreg.h 189714 2009-03-12 01:14:47Z yongari $ */
3
4/*-
5 * Copyright (c) 2001 Aaron Campbell <aaron@monkey.org>.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:

--- 16 unchanged lines hidden (view full) ---

27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
31 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
3
4/*-
5 * Copyright (c) 2001 Aaron Campbell <aaron@monkey.org>.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:

--- 16 unchanged lines hidden (view full) ---

27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
31 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#define TXP_PCI_LOMEM PCIR_BAR(1) /* memory map BAR */
36#define TXP_PCI_LOIO PCIR_BAR(0) /* IO map BAR */
37
38/*
39 * Typhoon registers.
40 */
41#define TXP_SRR 0x00 /* soft reset register */
42#define TXP_ISR 0x04 /* interrupt status register */
43#define TXP_IER 0x08 /* interrupt enable register */
44#define TXP_IMR 0x0c /* interrupt mask register */
45#define TXP_SIR 0x10 /* self interrupt register */

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73#define TXP_INT_DMA0 0x00000020 /* dma0 done */
74#define TXP_INT_A2H_3 0x00000010 /* arm->host comm 3 */
75#define TXP_INT_A2H_2 0x00000008 /* arm->host comm 2 */
76#define TXP_INT_A2H_1 0x00000004 /* arm->host comm 1 */
77#define TXP_INT_A2H_0 0x00000002 /* arm->host comm 0 */
78#define TXP_INT_LATCH 0x00000001 /* interrupt latch */
79
80/*
35/*
36 * Typhoon registers.
37 */
38#define TXP_SRR 0x00 /* soft reset register */
39#define TXP_ISR 0x04 /* interrupt status register */
40#define TXP_IER 0x08 /* interrupt enable register */
41#define TXP_IMR 0x0c /* interrupt mask register */
42#define TXP_SIR 0x10 /* self interrupt register */

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70#define TXP_INT_DMA0 0x00000020 /* dma0 done */
71#define TXP_INT_A2H_3 0x00000010 /* arm->host comm 3 */
72#define TXP_INT_A2H_2 0x00000008 /* arm->host comm 2 */
73#define TXP_INT_A2H_1 0x00000004 /* arm->host comm 1 */
74#define TXP_INT_A2H_0 0x00000002 /* arm->host comm 0 */
75#define TXP_INT_LATCH 0x00000001 /* interrupt latch */
76
77/*
78 * Controller periodically generates TXP_INT_A2H_3 interrupt so
79 * we don't want to see them in interrupt handler.
80 */
81#define TXP_INTRS 0xFFFFFFEF
82#define TXP_INTR_ALL 0xFFFFFFFF
83#define TXP_INTR_NONE 0x00000000
84
85/*
81 * soft reset register (SRR)
82 */
83#define TXP_SRR_ALL 0x0000007f /* full reset */
84
85/*
86 * Typhoon boot commands.
87 */
88#define TXP_BOOTCMD_NULL 0x00
86 * soft reset register (SRR)
87 */
88#define TXP_SRR_ALL 0x0000007f /* full reset */
89
90/*
91 * Typhoon boot commands.
92 */
93#define TXP_BOOTCMD_NULL 0x00
94#define TXP_BOOTCMD_WAKEUP 0xfa
89#define TXP_BOOTCMD_DOWNLOAD_COMPLETE 0xfb
90#define TXP_BOOTCMD_SEGMENT_AVAILABLE 0xfc
91#define TXP_BOOTCMD_RUNTIME_IMAGE 0xfd
92#define TXP_BOOTCMD_REGISTER_BOOT_RECORD 0xff
93
94/*
95 * Typhoon runtime commands.
96 */

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153#define TXP_CMD_RANDOM_NUMBER_READ 0x38
154#define TXP_CMD_MATRIX_TABLE_MODE_WRITE 0x39
155#define TXP_CMD_MATRIX_DETAIL_READ 0x3a
156#define TXP_CMD_FILTER_ARRAY_READ 0x3b
157#define TXP_CMD_FILTER_DETAIL_READ 0x3c
158#define TXP_CMD_FILTER_TABLE_MODE_WRITE 0x3d
159#define TXP_CMD_FILTER_TCL_WRITE 0x3e
160#define TXP_CMD_FILTER_TBL_READ 0x3f
95#define TXP_BOOTCMD_DOWNLOAD_COMPLETE 0xfb
96#define TXP_BOOTCMD_SEGMENT_AVAILABLE 0xfc
97#define TXP_BOOTCMD_RUNTIME_IMAGE 0xfd
98#define TXP_BOOTCMD_REGISTER_BOOT_RECORD 0xff
99
100/*
101 * Typhoon runtime commands.
102 */

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159#define TXP_CMD_RANDOM_NUMBER_READ 0x38
160#define TXP_CMD_MATRIX_TABLE_MODE_WRITE 0x39
161#define TXP_CMD_MATRIX_DETAIL_READ 0x3a
162#define TXP_CMD_FILTER_ARRAY_READ 0x3b
163#define TXP_CMD_FILTER_DETAIL_READ 0x3c
164#define TXP_CMD_FILTER_TABLE_MODE_WRITE 0x3d
165#define TXP_CMD_FILTER_TCL_WRITE 0x3e
166#define TXP_CMD_FILTER_TBL_READ 0x3f
167#define TXP_CMD_READ_VERSION 0x43
161#define TXP_CMD_FILTER_DEFINE 0x45
162#define TXP_CMD_ADD_WAKEUP_PKT 0x46
163#define TXP_CMD_ADD_SLEEP_PKT 0x47
164#define TXP_CMD_ENABLE_SLEEP_EVENTS 0x48
165#define TXP_CMD_ENABLE_WAKEUP_EVENTS 0x49
166#define TXP_CMD_GET_IP_ADDRESS 0x4a
167#define TXP_CMD_READ_PCI_REG 0x4c
168#define TXP_CMD_WRITE_PCI_REG 0x4d

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220#define TXP_STAT_IPCKSUMBAD 0x0010
221#define TXP_STAT_TCPCKSUMBAD 0x0020
222#define TXP_STAT_UDPCKSUMBAD 0x0040
223#define TXP_STAT_IPCKSUMGOOD 0x0080
224#define TXP_STAT_TCPCKSUMGOOD 0x0100
225#define TXP_STAT_UDPCKSUMGOOD 0x0200
226
227struct txp_tx_desc {
168#define TXP_CMD_FILTER_DEFINE 0x45
169#define TXP_CMD_ADD_WAKEUP_PKT 0x46
170#define TXP_CMD_ADD_SLEEP_PKT 0x47
171#define TXP_CMD_ENABLE_SLEEP_EVENTS 0x48
172#define TXP_CMD_ENABLE_WAKEUP_EVENTS 0x49
173#define TXP_CMD_GET_IP_ADDRESS 0x4a
174#define TXP_CMD_READ_PCI_REG 0x4c
175#define TXP_CMD_WRITE_PCI_REG 0x4d

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227#define TXP_STAT_IPCKSUMBAD 0x0010
228#define TXP_STAT_TCPCKSUMBAD 0x0020
229#define TXP_STAT_UDPCKSUMBAD 0x0040
230#define TXP_STAT_IPCKSUMGOOD 0x0080
231#define TXP_STAT_TCPCKSUMGOOD 0x0100
232#define TXP_STAT_UDPCKSUMGOOD 0x0200
233
234struct txp_tx_desc {
228 volatile uint8_t tx_flags; /* type/descriptor flags */
229 volatile uint8_t tx_numdesc; /* number of descriptors */
230 volatile uint16_t tx_totlen; /* total packet length */
231 volatile uint32_t tx_addrlo; /* virt addr low word */
232 volatile uint32_t tx_addrhi; /* virt addr high word */
233 volatile uint32_t tx_pflags; /* processing flags */
235 uint8_t tx_flags; /* type/descriptor flags */
236 uint8_t tx_numdesc; /* number of descriptors */
237 uint16_t tx_totlen; /* total packet length */
238 uint32_t tx_addrlo; /* virt addr low word */
239 uint32_t tx_addrhi; /* virt addr high word */
240 uint32_t tx_pflags; /* processing flags */
234};
235#define TX_FLAGS_TYPE_M 0x07 /* type mask */
236#define TX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
237#define TX_FLAGS_TYPE_DATA 0x01 /* type: data frame */
238#define TX_FLAGS_TYPE_CMD 0x02 /* type: command frame */
239#define TX_FLAGS_TYPE_OPT 0x03 /* type: options */
240#define TX_FLAGS_TYPE_RX 0x04 /* type: command */
241#define TX_FLAGS_TYPE_RESP 0x05 /* type: response */

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251#define TX_PFLAGS_PRIO 0x00000040 /* priority field valid */
252#define TX_PFLAGS_UDPCKSUM 0x00000080 /* udp checksum */
253#define TX_PFLAGS_PADFRAME 0x00000100 /* pad frame */
254#define TX_PFLAGS_VLANTAG_M 0x0ffff000 /* vlan tag mask */
255#define TX_PFLAGS_VLANPRI_M 0x00700000 /* vlan priority mask */
256#define TX_PFLAGS_VLANTAG_S 12 /* amount to shift tag */
257
258struct txp_rx_desc {
241};
242#define TX_FLAGS_TYPE_M 0x07 /* type mask */
243#define TX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
244#define TX_FLAGS_TYPE_DATA 0x01 /* type: data frame */
245#define TX_FLAGS_TYPE_CMD 0x02 /* type: command frame */
246#define TX_FLAGS_TYPE_OPT 0x03 /* type: options */
247#define TX_FLAGS_TYPE_RX 0x04 /* type: command */
248#define TX_FLAGS_TYPE_RESP 0x05 /* type: response */

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258#define TX_PFLAGS_PRIO 0x00000040 /* priority field valid */
259#define TX_PFLAGS_UDPCKSUM 0x00000080 /* udp checksum */
260#define TX_PFLAGS_PADFRAME 0x00000100 /* pad frame */
261#define TX_PFLAGS_VLANTAG_M 0x0ffff000 /* vlan tag mask */
262#define TX_PFLAGS_VLANPRI_M 0x00700000 /* vlan priority mask */
263#define TX_PFLAGS_VLANTAG_S 12 /* amount to shift tag */
264
265struct txp_rx_desc {
259 volatile uint8_t rx_flags; /* type/descriptor flags */
260 volatile uint8_t rx_numdesc; /* number of descriptors */
261 volatile uint16_t rx_len; /* frame length */
262#ifdef notdef
263 volatile uint32_t rx_vaddrlo; /* virtual address, lo word */
264 volatile uint32_t rx_vaddrhi; /* virtual address, hi word */
265#endif
266 union {
267 struct txp_swdesc *rx_sd;
268 uint64_t rx_dummy;
269 } txp_rx_u;
270 volatile uint32_t rx_stat; /* status */
271 volatile uint16_t rx_filter; /* filter status */
272 volatile uint16_t rx_hash; /* hash status */
273 volatile uint32_t rx_vlan; /* vlan tag/priority */
266 uint8_t rx_flags; /* type/descriptor flags */
267 uint8_t rx_numdesc; /* number of descriptors */
268 uint16_t rx_len; /* frame length */
269 uint32_t rx_vaddrlo; /* virtual address, lo word */
270 uint32_t rx_vaddrhi; /* virtual address, hi word */
271 uint32_t rx_stat; /* status */
272 uint16_t rx_filter; /* filter status */
273 uint16_t rx_hash; /* hash status */
274 uint32_t rx_vlan; /* vlan tag/priority */
274};
275
275};
276
276#define rx_sd txp_rx_u.rx_sd
277
278/* txp_rx_desc.rx_flags */
279#define RX_FLAGS_TYPE_M 0x07 /* type mask */
280#define RX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
281#define RX_FLAGS_TYPE_DATA 0x01 /* type: data frame */
282#define RX_FLAGS_TYPE_CMD 0x02 /* type: command frame */
283#define RX_FLAGS_TYPE_OPT 0x03 /* type: options */
284#define RX_FLAGS_TYPE_RX 0x04 /* type: command */
285#define RX_FLAGS_TYPE_RESP 0x05 /* type: response */

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292#define RX_ERROR_ADAPTER 0x00000000 /* adapter internal error */
293#define RX_ERROR_FIFO 0x00000001 /* fifo underrun */
294#define RX_ERROR_BADSSD 0x00000002 /* bad ssd */
295#define RX_ERROR_RUNT 0x00000003 /* runt packet */
296#define RX_ERROR_CRC 0x00000004 /* bad crc */
297#define RX_ERROR_OVERSIZE 0x00000005 /* oversized packet */
298#define RX_ERROR_ALIGN 0x00000006 /* alignment error */
299#define RX_ERROR_DRIBBLE 0x00000007 /* dribble bit */
277/* txp_rx_desc.rx_flags */
278#define RX_FLAGS_TYPE_M 0x07 /* type mask */
279#define RX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
280#define RX_FLAGS_TYPE_DATA 0x01 /* type: data frame */
281#define RX_FLAGS_TYPE_CMD 0x02 /* type: command frame */
282#define RX_FLAGS_TYPE_OPT 0x03 /* type: options */
283#define RX_FLAGS_TYPE_RX 0x04 /* type: command */
284#define RX_FLAGS_TYPE_RESP 0x05 /* type: response */

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291#define RX_ERROR_ADAPTER 0x00000000 /* adapter internal error */
292#define RX_ERROR_FIFO 0x00000001 /* fifo underrun */
293#define RX_ERROR_BADSSD 0x00000002 /* bad ssd */
294#define RX_ERROR_RUNT 0x00000003 /* runt packet */
295#define RX_ERROR_CRC 0x00000004 /* bad crc */
296#define RX_ERROR_OVERSIZE 0x00000005 /* oversized packet */
297#define RX_ERROR_ALIGN 0x00000006 /* alignment error */
298#define RX_ERROR_DRIBBLE 0x00000007 /* dribble bit */
299#define RX_ERROR_MASK 0x07
300
301/* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR not bit set) */
302#define RX_STAT_PROTO_M 0x00000003 /* protocol mask */
303#define RX_STAT_PROTO_UK 0x00000000 /* unknown protocol */
304#define RX_STAT_PROTO_IPX 0x00000001 /* IPX */
305#define RX_STAT_PROTO_IP 0x00000002 /* IP */
306#define RX_STAT_PROTO_RSV 0x00000003 /* reserved */
307#define RX_STAT_VLAN 0x00000004 /* vlan tag (in rxd) */
308#define RX_STAT_IPFRAG 0x00000008 /* fragment, ipsec not done */
309#define RX_STAT_IPSEC 0x00000010 /* ipsec decoded packet */
310#define RX_STAT_IPCKSUMBAD 0x00000020 /* ip checksum failed */
311#define RX_STAT_UDPCKSUMBAD 0x00000040 /* udp checksum failed */
312#define RX_STAT_TCPCKSUMBAD 0x00000080 /* tcp checksum failed */
313#define RX_STAT_IPCKSUMGOOD 0x00000100 /* ip checksum succeeded */
314#define RX_STAT_UDPCKSUMGOOD 0x00000200 /* udp checksum succeeded */
315#define RX_STAT_TCPCKSUMGOOD 0x00000400 /* tcp checksum succeeded */
316
317
318struct txp_rxbuf_desc {
300
301/* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR not bit set) */
302#define RX_STAT_PROTO_M 0x00000003 /* protocol mask */
303#define RX_STAT_PROTO_UK 0x00000000 /* unknown protocol */
304#define RX_STAT_PROTO_IPX 0x00000001 /* IPX */
305#define RX_STAT_PROTO_IP 0x00000002 /* IP */
306#define RX_STAT_PROTO_RSV 0x00000003 /* reserved */
307#define RX_STAT_VLAN 0x00000004 /* vlan tag (in rxd) */
308#define RX_STAT_IPFRAG 0x00000008 /* fragment, ipsec not done */
309#define RX_STAT_IPSEC 0x00000010 /* ipsec decoded packet */
310#define RX_STAT_IPCKSUMBAD 0x00000020 /* ip checksum failed */
311#define RX_STAT_UDPCKSUMBAD 0x00000040 /* udp checksum failed */
312#define RX_STAT_TCPCKSUMBAD 0x00000080 /* tcp checksum failed */
313#define RX_STAT_IPCKSUMGOOD 0x00000100 /* ip checksum succeeded */
314#define RX_STAT_UDPCKSUMGOOD 0x00000200 /* udp checksum succeeded */
315#define RX_STAT_TCPCKSUMGOOD 0x00000400 /* tcp checksum succeeded */
316
317
318struct txp_rxbuf_desc {
319 volatile uint32_t rb_paddrlo;
320 volatile uint32_t rb_paddrhi;
321#ifdef notdef
322 volatile uint32_t rb_vaddrlo;
323 volatile uint32_t rb_vaddrhi;
324#endif
325 union {
326 struct txp_swdesc *rb_sd;
327 uint64_t rb_dummy;
328 } txp_rb_u;
319 uint32_t rb_paddrlo;
320 uint32_t rb_paddrhi;
321 uint32_t rb_vaddrlo;
322 uint32_t rb_vaddrhi;
329};
330
323};
324
331#define rb_sd txp_rb_u.rb_sd
332
333/* Extension descriptor */
334struct txp_ext_desc {
325/* Extension descriptor */
326struct txp_ext_desc {
335 volatile uint32_t ext_1;
336 volatile uint32_t ext_2;
337 volatile uint32_t ext_3;
338 volatile uint32_t ext_4;
327 uint32_t ext_1;
328 uint32_t ext_2;
329 uint32_t ext_3;
330 uint32_t ext_4;
339};
340
341struct txp_cmd_desc {
331};
332
333struct txp_cmd_desc {
342 volatile uint8_t cmd_flags;
343 volatile uint8_t cmd_numdesc;
344 volatile uint16_t cmd_id;
345 volatile uint16_t cmd_seq;
346 volatile uint16_t cmd_par1;
347 volatile uint32_t cmd_par2;
348 volatile uint32_t cmd_par3;
334 uint8_t cmd_flags;
335 uint8_t cmd_numdesc;
336 uint16_t cmd_id;
337 uint16_t cmd_seq;
338 uint16_t cmd_par1;
339 uint32_t cmd_par2;
340 uint32_t cmd_par3;
349};
350#define CMD_FLAGS_TYPE_M 0x07 /* type mask */
351#define CMD_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
352#define CMD_FLAGS_TYPE_DATA 0x01 /* type: data frame */
353#define CMD_FLAGS_TYPE_CMD 0x02 /* type: command frame */
354#define CMD_FLAGS_TYPE_OPT 0x03 /* type: options */
355#define CMD_FLAGS_TYPE_RX 0x04 /* type: command */
356#define CMD_FLAGS_TYPE_RESP 0x05 /* type: response */
357#define CMD_FLAGS_RESP 0x40 /* response requested */
358#define CMD_FLAGS_VALID 0x80 /* valid descriptor */
359
360struct txp_rsp_desc {
341};
342#define CMD_FLAGS_TYPE_M 0x07 /* type mask */
343#define CMD_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
344#define CMD_FLAGS_TYPE_DATA 0x01 /* type: data frame */
345#define CMD_FLAGS_TYPE_CMD 0x02 /* type: command frame */
346#define CMD_FLAGS_TYPE_OPT 0x03 /* type: options */
347#define CMD_FLAGS_TYPE_RX 0x04 /* type: command */
348#define CMD_FLAGS_TYPE_RESP 0x05 /* type: response */
349#define CMD_FLAGS_RESP 0x40 /* response requested */
350#define CMD_FLAGS_VALID 0x80 /* valid descriptor */
351
352struct txp_rsp_desc {
361 volatile uint8_t rsp_flags;
362 volatile uint8_t rsp_numdesc;
363 volatile uint16_t rsp_id;
364 volatile uint16_t rsp_seq;
365 volatile uint16_t rsp_par1;
366 volatile uint32_t rsp_par2;
367 volatile uint32_t rsp_par3;
353 uint8_t rsp_flags;
354 uint8_t rsp_numdesc;
355 uint16_t rsp_id;
356 uint16_t rsp_seq;
357 uint16_t rsp_par1;
358 uint32_t rsp_par2;
359 uint32_t rsp_par3;
368};
369#define RSP_FLAGS_TYPE_M 0x07 /* type mask */
370#define RSP_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
371#define RSP_FLAGS_TYPE_DATA 0x01 /* type: data frame */
372#define RSP_FLAGS_TYPE_CMD 0x02 /* type: command frame */
373#define RSP_FLAGS_TYPE_OPT 0x03 /* type: options */
374#define RSP_FLAGS_TYPE_RX 0x04 /* type: command */
375#define RSP_FLAGS_TYPE_RESP 0x05 /* type: response */
376#define RSP_FLAGS_ERROR 0x40 /* response error */
377
378struct txp_frag_desc {
360};
361#define RSP_FLAGS_TYPE_M 0x07 /* type mask */
362#define RSP_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
363#define RSP_FLAGS_TYPE_DATA 0x01 /* type: data frame */
364#define RSP_FLAGS_TYPE_CMD 0x02 /* type: command frame */
365#define RSP_FLAGS_TYPE_OPT 0x03 /* type: options */
366#define RSP_FLAGS_TYPE_RX 0x04 /* type: command */
367#define RSP_FLAGS_TYPE_RESP 0x05 /* type: response */
368#define RSP_FLAGS_ERROR 0x40 /* response error */
369
370struct txp_frag_desc {
379 volatile uint8_t frag_flags; /* type/descriptor flags */
380 volatile uint8_t frag_rsvd1;
381 volatile uint16_t frag_len; /* bytes in this fragment */
382 volatile uint32_t frag_addrlo; /* phys addr low word */
383 volatile uint32_t frag_addrhi; /* phys addr high word */
384 volatile uint32_t frag_rsvd2;
371 uint8_t frag_flags; /* type/descriptor flags */
372 uint8_t frag_rsvd1;
373 uint16_t frag_len; /* bytes in this fragment */
374 uint32_t frag_addrlo; /* phys addr low word */
375 uint32_t frag_addrhi; /* phys addr high word */
376 uint32_t frag_rsvd2;
385};
386#define FRAG_FLAGS_TYPE_M 0x07 /* type mask */
387#define FRAG_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
388#define FRAG_FLAGS_TYPE_DATA 0x01 /* type: data frame */
389#define FRAG_FLAGS_TYPE_CMD 0x02 /* type: command frame */
390#define FRAG_FLAGS_TYPE_OPT 0x03 /* type: options */
391#define FRAG_FLAGS_TYPE_RX 0x04 /* type: command */
392#define FRAG_FLAGS_TYPE_RESP 0x05 /* type: response */

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413 uint16_t ipsec_ah1;
414 uint16_t ipsec_esp1;
415 uint16_t ipsec_ah2;
416 uint16_t ipsec_esp2;
417 uint32_t ipsec_rsvd1;
418};
419
420struct txp_tcpseg_desc {
377};
378#define FRAG_FLAGS_TYPE_M 0x07 /* type mask */
379#define FRAG_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
380#define FRAG_FLAGS_TYPE_DATA 0x01 /* type: data frame */
381#define FRAG_FLAGS_TYPE_CMD 0x02 /* type: command frame */
382#define FRAG_FLAGS_TYPE_OPT 0x03 /* type: options */
383#define FRAG_FLAGS_TYPE_RX 0x04 /* type: command */
384#define FRAG_FLAGS_TYPE_RESP 0x05 /* type: response */

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405 uint16_t ipsec_ah1;
406 uint16_t ipsec_esp1;
407 uint16_t ipsec_ah2;
408 uint16_t ipsec_esp2;
409 uint32_t ipsec_rsvd1;
410};
411
412struct txp_tcpseg_desc {
421 uint8_t tcpseg_desctype:3,
422 tcpseg_rsvd:1,
423 tcpseg_type:4;
424
413 uint8_t tcpseg_type;
425 uint8_t tcpseg_num;
414 uint8_t tcpseg_num;
426
427 uint16_t tcpseg_mss:12,
428 tcpseg_misc:4;
429
415 uint16_t tcpseg_mss;
430 uint32_t tcpseg_respaddr;
431 uint32_t tcpseg_txbytes;
432 uint32_t tcpseg_lss;
433};
416 uint32_t tcpseg_respaddr;
417 uint32_t tcpseg_txbytes;
418 uint32_t tcpseg_lss;
419};
420#define TCPSEG_DESC_TYPE_M 0x07 /* type mask */
421#define TCPSEG_DESC_TYPE_FRAG 0x00 /* type: fragment */
422#define TCPSEG_DESC_TYPE_DATA 0x01 /* type: data frame */
423#define TCPSEG_DESC_TYPE_CMD 0x02 /* type: command frame */
424#define TCPSEG_DESC_TYPE_OPT 0x03 /* type: options */
425#define TCPSEG_DESC_TYPE_RX 0x04 /* type: command */
426#define TCPSEG_DESC_TYPE_RESP 0x05 /* type: response */
427#define TCPSEG_OPT_IPSEC 0x00
428#define TCPSEG_OPT_TSO 0x10
429#define TCPSEG_MSS_MASK 0x0FFF
430#define TCPSEG_MSS_FIRST 0x1000
431#define TCPSEG_MSS_LAST 0x2000
434
435/*
436 * Transceiver types
437 */
438#define TXP_XCVR_10_HDX 0
439#define TXP_XCVR_10_FDX 1
440#define TXP_XCVR_100_HDX 2
441#define TXP_XCVR_100_FDX 3

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455#define TXP_RXFILT_BROADCAST 0x0004 /* broadcast packets */
456#define TXP_RXFILT_PROMISC 0x0008 /* promiscuous mode */
457#define TXP_RXFILT_HASHMULTI 0x0010 /* use multicast filter */
458
459/*
460 * boot record (pointers to rings)
461 */
462struct txp_boot_record {
432
433/*
434 * Transceiver types
435 */
436#define TXP_XCVR_10_HDX 0
437#define TXP_XCVR_10_FDX 1
438#define TXP_XCVR_100_HDX 2
439#define TXP_XCVR_100_FDX 3

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453#define TXP_RXFILT_BROADCAST 0x0004 /* broadcast packets */
454#define TXP_RXFILT_PROMISC 0x0008 /* promiscuous mode */
455#define TXP_RXFILT_HASHMULTI 0x0010 /* use multicast filter */
456
457/*
458 * boot record (pointers to rings)
459 */
460struct txp_boot_record {
463 volatile uint32_t br_hostvar_lo; /* host ring pointer */
464 volatile uint32_t br_hostvar_hi;
465 volatile uint32_t br_txlopri_lo; /* tx low pri ring */
466 volatile uint32_t br_txlopri_hi;
467 volatile uint32_t br_txlopri_siz;
468 volatile uint32_t br_txhipri_lo; /* tx high pri ring */
469 volatile uint32_t br_txhipri_hi;
470 volatile uint32_t br_txhipri_siz;
471 volatile uint32_t br_rxlopri_lo; /* rx low pri ring */
472 volatile uint32_t br_rxlopri_hi;
473 volatile uint32_t br_rxlopri_siz;
474 volatile uint32_t br_rxbuf_lo; /* rx buffer ring */
475 volatile uint32_t br_rxbuf_hi;
476 volatile uint32_t br_rxbuf_siz;
477 volatile uint32_t br_cmd_lo; /* command ring */
478 volatile uint32_t br_cmd_hi;
479 volatile uint32_t br_cmd_siz;
480 volatile uint32_t br_resp_lo; /* response ring */
481 volatile uint32_t br_resp_hi;
482 volatile uint32_t br_resp_siz;
483 volatile uint32_t br_zero_lo; /* zero word */
484 volatile uint32_t br_zero_hi;
485 volatile uint32_t br_rxhipri_lo; /* rx high pri ring */
486 volatile uint32_t br_rxhipri_hi;
487 volatile uint32_t br_rxhipri_siz;
461 uint32_t br_hostvar_lo; /* host ring pointer */
462 uint32_t br_hostvar_hi;
463 uint32_t br_txlopri_lo; /* tx low pri ring */
464 uint32_t br_txlopri_hi;
465 uint32_t br_txlopri_siz;
466 uint32_t br_txhipri_lo; /* tx high pri ring */
467 uint32_t br_txhipri_hi;
468 uint32_t br_txhipri_siz;
469 uint32_t br_rxlopri_lo; /* rx low pri ring */
470 uint32_t br_rxlopri_hi;
471 uint32_t br_rxlopri_siz;
472 uint32_t br_rxbuf_lo; /* rx buffer ring */
473 uint32_t br_rxbuf_hi;
474 uint32_t br_rxbuf_siz;
475 uint32_t br_cmd_lo; /* command ring */
476 uint32_t br_cmd_hi;
477 uint32_t br_cmd_siz;
478 uint32_t br_resp_lo; /* response ring */
479 uint32_t br_resp_hi;
480 uint32_t br_resp_siz;
481 uint32_t br_zero_lo; /* zero word */
482 uint32_t br_zero_hi;
483 uint32_t br_rxhipri_lo; /* rx high pri ring */
484 uint32_t br_rxhipri_hi;
485 uint32_t br_rxhipri_siz;
488};
489
490/*
491 * hostvar structure (shared with typhoon)
492 */
493struct txp_hostvar {
486};
487
488/*
489 * hostvar structure (shared with typhoon)
490 */
491struct txp_hostvar {
494 volatile uint32_t hv_rx_hi_read_idx; /* host->arm */
495 volatile uint32_t hv_rx_lo_read_idx; /* host->arm */
496 volatile uint32_t hv_rx_buf_write_idx; /* host->arm */
497 volatile uint32_t hv_resp_read_idx; /* host->arm */
498 volatile uint32_t hv_tx_lo_desc_read_idx; /* arm->host */
499 volatile uint32_t hv_tx_hi_desc_read_idx; /* arm->host */
500 volatile uint32_t hv_rx_lo_write_idx; /* arm->host */
501 volatile uint32_t hv_rx_buf_read_idx; /* arm->host */
502 volatile uint32_t hv_cmd_read_idx; /* arm->host */
503 volatile uint32_t hv_resp_write_idx; /* arm->host */
504 volatile uint32_t hv_rx_hi_write_idx; /* arm->host */
492 uint32_t hv_rx_hi_read_idx; /* host->arm */
493 uint32_t hv_rx_lo_read_idx; /* host->arm */
494 uint32_t hv_rx_buf_write_idx; /* host->arm */
495 uint32_t hv_resp_read_idx; /* host->arm */
496 uint32_t hv_tx_lo_desc_read_idx; /* arm->host */
497 uint32_t hv_tx_hi_desc_read_idx; /* arm->host */
498 uint32_t hv_rx_lo_write_idx; /* arm->host */
499 uint32_t hv_rx_buf_read_idx; /* arm->host */
500 uint32_t hv_cmd_read_idx; /* arm->host */
501 uint32_t hv_resp_write_idx; /* arm->host */
502 uint32_t hv_rx_hi_write_idx; /* arm->host */
505};
506
507/*
508 * TYPHOON status register state (in TXP_A2H_0)
509 */
510#define STAT_ROM_CODE 0x00000001
511#define STAT_ROM_EEPROM_LOAD 0x00000002
512#define STAT_WAITING_FOR_BOOT 0x00000007

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550struct txp_rsp_ring {
551 struct txp_rsp_desc *base;
552 uint32_t lastwrite;
553 uint32_t size;
554};
555
556struct txp_tx_ring {
557 struct txp_tx_desc *r_desc; /* base address of descs */
503};
504
505/*
506 * TYPHOON status register state (in TXP_A2H_0)
507 */
508#define STAT_ROM_CODE 0x00000001
509#define STAT_ROM_EEPROM_LOAD 0x00000002
510#define STAT_WAITING_FOR_BOOT 0x00000007

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548struct txp_rsp_ring {
549 struct txp_rsp_desc *base;
550 uint32_t lastwrite;
551 uint32_t size;
552};
553
554struct txp_tx_ring {
555 struct txp_tx_desc *r_desc; /* base address of descs */
556 bus_dma_tag_t r_tag;
557 bus_dmamap_t r_map;
558 uint32_t r_reg; /* register to activate */
559 uint32_t r_prod; /* producer */
560 uint32_t r_cons; /* consumer */
561 uint32_t r_cnt; /* # descs in use */
558 uint32_t r_reg; /* register to activate */
559 uint32_t r_prod; /* producer */
560 uint32_t r_cons; /* consumer */
561 uint32_t r_cnt; /* # descs in use */
562 volatile uint32_t *r_off; /* hostvar index pointer */
562 uint32_t *r_off; /* hostvar index pointer */
563};
564
565struct txp_swdesc {
563};
564
565struct txp_swdesc {
566 struct mbuf * sd_mbuf;
566 struct mbuf *sd_mbuf;
567 bus_dmamap_t sd_map;
568};
569
567 bus_dmamap_t sd_map;
568};
569
570struct txp_rx_swdesc {
571 TAILQ_ENTRY(txp_rx_swdesc) sd_next;
572 struct mbuf *sd_mbuf;
573 bus_dmamap_t sd_map;
574};
575
570struct txp_rx_ring {
571 struct txp_rx_desc *r_desc; /* base address of descs */
576struct txp_rx_ring {
577 struct txp_rx_desc *r_desc; /* base address of descs */
572 volatile uint32_t *r_roff; /* hv read offset ptr */
573 volatile uint32_t *r_woff; /* hv write offset ptr */
578 bus_dma_tag_t r_tag;
579 bus_dmamap_t r_map;
580 uint32_t *r_roff; /* hv read offset ptr */
581 uint32_t *r_woff; /* hv write offset ptr */
574};
575
576struct txp_ldata {
582};
583
584struct txp_ldata {
577 struct txp_boot_record txp_boot;
578 struct txp_hostvar txp_hostvar;
579 struct txp_tx_desc txp_txhiring[TX_ENTRIES];
580 struct txp_tx_desc txp_txloring[TX_ENTRIES];
581 struct txp_rxbuf_desc txp_rxbufs[RXBUF_ENTRIES];
582 struct txp_rx_desc txp_rxhiring[RX_ENTRIES];
583 struct txp_rx_desc txp_rxloring[RX_ENTRIES];
584 struct txp_cmd_desc txp_cmdring[CMD_ENTRIES];
585 struct txp_rsp_desc txp_rspring[RSP_ENTRIES];
586 uint32_t txp_zero;
585 struct txp_boot_record *txp_boot;
586 bus_addr_t txp_boot_paddr;
587 struct txp_hostvar *txp_hostvar;
588 bus_addr_t txp_hostvar_paddr;
589 struct txp_tx_desc *txp_txhiring;
590 bus_addr_t txp_txhiring_paddr;
591 struct txp_tx_desc *txp_txloring;
592 bus_addr_t txp_txloring_paddr;
593 struct txp_rxbuf_desc *txp_rxbufs;
594 bus_addr_t txp_rxbufs_paddr;
595 struct txp_rx_desc *txp_rxhiring;
596 bus_addr_t txp_rxhiring_paddr;
597 struct txp_rx_desc *txp_rxloring;
598 bus_addr_t txp_rxloring_paddr;
599 struct txp_cmd_desc *txp_cmdring;
600 bus_addr_t txp_cmdring_paddr;
601 struct txp_rsp_desc *txp_rspring;
602 bus_addr_t txp_rspring_paddr;
603 uint32_t *txp_zero;
604 bus_addr_t txp_zero_paddr;
587};
588
605};
606
607struct txp_chain_data {
608 bus_dma_tag_t txp_parent_tag;
609 bus_dma_tag_t txp_boot_tag;
610 bus_dmamap_t txp_boot_map;
611 bus_dma_tag_t txp_hostvar_tag;
612 bus_dmamap_t txp_hostvar_map;
613 bus_dma_tag_t txp_txhiring_tag;
614 bus_dmamap_t txp_txhiring_map;
615 bus_dma_tag_t txp_txloring_tag;
616 bus_dmamap_t txp_txloring_map;
617 bus_dma_tag_t txp_tx_tag;
618 bus_dma_tag_t txp_rx_tag;
619 bus_dma_tag_t txp_rxbufs_tag;
620 bus_dmamap_t txp_rxbufs_map;
621 bus_dma_tag_t txp_rxhiring_tag;
622 bus_dmamap_t txp_rxhiring_map;
623 bus_dma_tag_t txp_rxloring_tag;
624 bus_dmamap_t txp_rxloring_map;
625 bus_dma_tag_t txp_cmdring_tag;
626 bus_dmamap_t txp_cmdring_map;
627 bus_dma_tag_t txp_rspring_tag;
628 bus_dmamap_t txp_rspring_map;
629 bus_dma_tag_t txp_zero_tag;
630 bus_dmamap_t txp_zero_map;
631};
632
633struct txp_hw_stats {
634 uint32_t tx_frames;
635 uint64_t tx_bytes;
636 uint32_t tx_deferred;
637 uint32_t tx_late_colls;
638 uint32_t tx_colls;
639 uint32_t tx_carrier_lost;
640 uint32_t tx_multi_colls;
641 uint32_t tx_excess_colls;
642 uint32_t tx_fifo_underruns;
643 uint32_t tx_mcast_oflows;
644 uint32_t tx_filtered;
645 uint32_t rx_frames;
646 uint64_t rx_bytes;
647 uint32_t rx_fifo_oflows;
648 uint32_t rx_badssd;
649 uint32_t rx_crcerrs;
650 uint32_t rx_lenerrs;
651 uint32_t rx_bcast_frames;
652 uint32_t rx_mcast_frames;
653 uint32_t rx_oflows;
654 uint32_t rx_filtered;
655};
656
589struct txp_softc {
590 struct ifnet *sc_ifp;
591 device_t sc_dev;
592 struct txp_hostvar *sc_hostvar;
593 struct txp_boot_record *sc_boot;
657struct txp_softc {
658 struct ifnet *sc_ifp;
659 device_t sc_dev;
660 struct txp_hostvar *sc_hostvar;
661 struct txp_boot_record *sc_boot;
594 bus_space_handle_t sc_bh; /* bus handle (regs) */
595 bus_space_tag_t sc_bt; /* bus tag (regs) */
596 struct resource *sc_res;
662 struct resource *sc_res;
663 int sc_res_id;
664 int sc_res_type;
597 struct resource *sc_irq;
598 void *sc_intrhand;
665 struct resource *sc_irq;
666 void *sc_intrhand;
599 struct mtx sc_mtx;
600 struct txp_ldata *sc_ldata;
601 void *sc_fwbuf;
667 struct txp_chain_data sc_cdata;
668 struct txp_ldata sc_ldata;
602 int sc_rxbufprod;
669 int sc_rxbufprod;
670 int sc_process_limit;
603 struct txp_cmd_ring sc_cmdring;
604 struct txp_rsp_ring sc_rspring;
671 struct txp_cmd_ring sc_cmdring;
672 struct txp_rsp_ring sc_rspring;
605 struct txp_swdesc sc_txd[TX_ENTRIES];
606 struct callout sc_tick;
607 struct ifmedia sc_ifmedia;
673 struct callout sc_tick;
674 struct ifmedia sc_ifmedia;
675 struct txp_hw_stats sc_ostats;
676 struct txp_hw_stats sc_stats;
608 struct txp_tx_ring sc_txhir, sc_txlor;
677 struct txp_tx_ring sc_txhir, sc_txlor;
678 struct txp_swdesc sc_txd[TX_ENTRIES];
609 struct txp_rxbuf_desc *sc_rxbufs;
610 struct txp_rx_ring sc_rxhir, sc_rxlor;
611 uint16_t sc_xcvr;
612 uint16_t sc_seq;
679 struct txp_rxbuf_desc *sc_rxbufs;
680 struct txp_rx_ring sc_rxhir, sc_rxlor;
681 uint16_t sc_xcvr;
682 uint16_t sc_seq;
613 int sc_cold;
614 uint32_t sc_rx_capability, sc_tx_capability;
683 int sc_watchdog_timer;
684 int sc_if_flags;
685 int sc_flags;
686#define TXP_FLAG_DETACH 0x4000
687#define TXP_FLAG_LINK 0x8000
688 TAILQ_HEAD(, txp_rx_swdesc) sc_free_list;
689 TAILQ_HEAD(, txp_rx_swdesc) sc_busy_list;
690 struct task sc_int_task;
691 struct taskqueue *sc_tq;
692 struct mtx sc_mtx;
615};
616
617struct txp_fw_file_header {
618 uint8_t magicid[8]; /* TYPHOON\0 */
619 uint32_t version;
620 uint32_t nsections;
621 uint32_t addr;
622 uint32_t hmac[5];
623};
624
625struct txp_fw_section_header {
626 uint32_t nbytes;
627 uint16_t cksum;
628 uint16_t reserved;
629 uint32_t addr;
630};
631
632#define TXP_MAX_SEGLEN 0xffff
693};
694
695struct txp_fw_file_header {
696 uint8_t magicid[8]; /* TYPHOON\0 */
697 uint32_t version;
698 uint32_t nsections;
699 uint32_t addr;
700 uint32_t hmac[5];
701};
702
703struct txp_fw_section_header {
704 uint32_t nbytes;
705 uint16_t cksum;
706 uint16_t reserved;
707 uint32_t addr;
708};
709
710#define TXP_MAX_SEGLEN 0xffff
633#define TXP_MAX_PKTLEN 0x0800
711#define TXP_MAX_PKTLEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)
634
712
635#define WRITE_REG(sc,reg,val) \
636 bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, reg, val)
637#define READ_REG(sc,reg) \
638 bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, reg)
713#define WRITE_REG(sc, reg, val) bus_write_4((sc)->sc_res, reg, val)
714#define READ_REG(sc, reg) bus_read_4((sc)->sc_res, reg)
715#define TXP_BARRIER(sc, o, l, f) bus_barrier((sc)->sc_res, (o), (l), (f))
639
640#define TXP_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
641#define TXP_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
642#define TXP_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
643
716
717#define TXP_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
718#define TXP_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
719#define TXP_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
720
721#define TXP_MAXTXSEGS 16
722#define TXP_RXBUF_ALIGN (sizeof(uint32_t))
723
724#define TXP_PROC_MIN 16
725#define TXP_PROC_MAX RX_ENTRIES
726#define TXP_PROC_DEFAULT (RX_ENTRIES / 2)
727
728#define TXP_ADDR_HI(x) ((uint64_t)(x) >> 32)
729#define TXP_ADDR_LO(x) ((uint64_t)(x) & 0xffffffff)
730
644/*
645 * 3Com PCI vendor ID.
646 */
647#define TXP_VENDORID_3COM 0x10B7
648
649/*
650 * 3cR990 device IDs
651 */

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656#define TXP_DEVICEID_3CR990_SRV_97 0x9909
657#define TXP_DEVICEID_3CR990B_SRV 0x990A
658
659struct txp_type {
660 uint16_t txp_vid;
661 uint16_t txp_did;
662 char *txp_name;
663};
731/*
732 * 3Com PCI vendor ID.
733 */
734#define TXP_VENDORID_3COM 0x10B7
735
736/*
737 * 3cR990 device IDs
738 */

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743#define TXP_DEVICEID_3CR990_SRV_97 0x9909
744#define TXP_DEVICEID_3CR990B_SRV 0x990A
745
746struct txp_type {
747 uint16_t txp_vid;
748 uint16_t txp_did;
749 char *txp_name;
750};
751
752#define TXP_TIMEOUT 10000
753#define TXP_CMD_NOWAIT 0
754#define TXP_CMD_WAIT 1
755#define TXP_TX_TIMEOUT 5
756
757/*
758 * Each frame requires one frame descriptor and one or more
759 * fragment descriptors. If TSO is used frame descriptor block
760 * requires one or two option frame descriptors depending on
761 * number of framents. Therefore we will consume three
762 * additional descriptors at most to use TSO for a frame and
763 * one reserved descriptor in order not to full Tx descriptor
764 * ring.
765 */
766#define TXP_TXD_RESERVED 4
767
768#define TXP_DESC_INC(x, y) ((x) = ((x) + 1) % (y))