1/*-
2 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Gardner Buchanan.
16 * 4. The name of Gardner Buchanan may not be used to endorse or promote
17 * products derived from this software without specific prior written
18 * permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Gardner Buchanan.
16 * 4. The name of Gardner Buchanan may not be used to endorse or promote
17 * products derived from this software without specific prior written
18 * permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
|
33__FBSDID("$FreeBSD: head/sys/dev/sn/if_sn.c 199414 2009-11-17 18:22:14Z jhb $");
| 33__FBSDID("$FreeBSD: head/sys/dev/sn/if_sn.c 199559 2009-11-19 22:06:40Z jhb $");
|
34
35/*
36 * This is a driver for SMC's 9000 series of Ethernet adapters.
37 *
38 * This FreeBSD driver is derived from the smc9194 Linux driver by
39 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman.
40 * This driver also shamelessly borrows from the FreeBSD ep driver
41 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca>
42 * All rights reserved.
43 *
44 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded
45 * PC. It is adapted from Erik Stahlman's Linux driver which worked
46 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook,
47 * it will work for the entire SMC 9xxx series. (Ha Ha)
48 *
49 * "Features" of the SMC chip:
50 * 4608 byte packet memory. (for the 91C92. Others have more)
51 * EEPROM for configuration
52 * AUI/TP selection
53 *
54 * Authors:
55 * Erik Stahlman erik@vt.edu
56 * Herb Peyerl hpeyerl@novatel.ca
57 * Andres Vega Garcia avega@sophia.inria.fr
58 * Serge Babkin babkin@hq.icb.chel.su
59 * Gardner Buchanan gbuchanan@shl.com
60 *
61 * Sources:
62 * o SMC databook
63 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)"
64 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp"
65 *
66 * Known Bugs:
67 * o Setting of the hardware address isn't supported.
68 * o Hardware padding isn't used.
69 */
70
71/*
72 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT)
73 *
74 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org>
75 * BSD-nomads, Tokyo, Japan.
76 */
77/*
78 * Multicast support by Kei TANAKA <kei@pal.xerox.com>
79 * Special thanks to itojun@itojun.org
80 */
81
82#include <sys/param.h>
83#include <sys/systm.h>
84#include <sys/errno.h>
| 34
35/*
36 * This is a driver for SMC's 9000 series of Ethernet adapters.
37 *
38 * This FreeBSD driver is derived from the smc9194 Linux driver by
39 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman.
40 * This driver also shamelessly borrows from the FreeBSD ep driver
41 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca>
42 * All rights reserved.
43 *
44 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded
45 * PC. It is adapted from Erik Stahlman's Linux driver which worked
46 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook,
47 * it will work for the entire SMC 9xxx series. (Ha Ha)
48 *
49 * "Features" of the SMC chip:
50 * 4608 byte packet memory. (for the 91C92. Others have more)
51 * EEPROM for configuration
52 * AUI/TP selection
53 *
54 * Authors:
55 * Erik Stahlman erik@vt.edu
56 * Herb Peyerl hpeyerl@novatel.ca
57 * Andres Vega Garcia avega@sophia.inria.fr
58 * Serge Babkin babkin@hq.icb.chel.su
59 * Gardner Buchanan gbuchanan@shl.com
60 *
61 * Sources:
62 * o SMC databook
63 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)"
64 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp"
65 *
66 * Known Bugs:
67 * o Setting of the hardware address isn't supported.
68 * o Hardware padding isn't used.
69 */
70
71/*
72 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT)
73 *
74 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org>
75 * BSD-nomads, Tokyo, Japan.
76 */
77/*
78 * Multicast support by Kei TANAKA <kei@pal.xerox.com>
79 * Special thanks to itojun@itojun.org
80 */
81
82#include <sys/param.h>
83#include <sys/systm.h>
84#include <sys/errno.h>
|
| 85#include <sys/kernel.h>
|
85#include <sys/sockio.h>
86#include <sys/mbuf.h>
87#include <sys/socket.h>
88#include <sys/syslog.h>
89
90#include <sys/module.h>
91#include <sys/bus.h>
92
93#include <machine/bus.h>
94#include <machine/resource.h>
95#include <sys/rman.h>
96
97#include <net/ethernet.h>
98#include <net/if.h>
99#include <net/if_arp.h>
100#include <net/if_dl.h>
101#include <net/if_types.h>
102#include <net/if_mib.h>
103
104#ifdef INET
105#include <netinet/in.h>
106#include <netinet/in_systm.h>
107#include <netinet/in_var.h>
108#include <netinet/ip.h>
109#endif
110
111#include <net/bpf.h>
112#include <net/bpfdesc.h>
113
114#include <dev/sn/if_snreg.h>
115#include <dev/sn/if_snvar.h>
116
117/* Exported variables */
118devclass_t sn_devclass;
119
120static int snioctl(struct ifnet * ifp, u_long, caddr_t);
121
122static void snresume(struct ifnet *);
123
| 86#include <sys/sockio.h>
87#include <sys/mbuf.h>
88#include <sys/socket.h>
89#include <sys/syslog.h>
90
91#include <sys/module.h>
92#include <sys/bus.h>
93
94#include <machine/bus.h>
95#include <machine/resource.h>
96#include <sys/rman.h>
97
98#include <net/ethernet.h>
99#include <net/if.h>
100#include <net/if_arp.h>
101#include <net/if_dl.h>
102#include <net/if_types.h>
103#include <net/if_mib.h>
104
105#ifdef INET
106#include <netinet/in.h>
107#include <netinet/in_systm.h>
108#include <netinet/in_var.h>
109#include <netinet/ip.h>
110#endif
111
112#include <net/bpf.h>
113#include <net/bpfdesc.h>
114
115#include <dev/sn/if_snreg.h>
116#include <dev/sn/if_snvar.h>
117
118/* Exported variables */
119devclass_t sn_devclass;
120
121static int snioctl(struct ifnet * ifp, u_long, caddr_t);
122
123static void snresume(struct ifnet *);
124
|
| 125static void snintr_locked(struct sn_softc *);
|
124static void sninit_locked(void *);
125static void snstart_locked(struct ifnet *);
126
127static void sninit(void *);
128static void snread(struct ifnet *);
129static void snstart(struct ifnet *);
130static void snstop(struct sn_softc *);
| 126static void sninit_locked(void *);
127static void snstart_locked(struct ifnet *);
128
129static void sninit(void *);
130static void snread(struct ifnet *);
131static void snstart(struct ifnet *);
132static void snstop(struct sn_softc *);
|
131static void snwatchdog(struct ifnet *);
| 133static void snwatchdog(void *);
|
132
133static void sn_setmcast(struct sn_softc *);
134static int sn_getmcf(struct ifnet *ifp, u_char *mcf);
135
136/* I (GB) have been unlucky getting the hardware padding
137 * to work properly.
138 */
139#define SW_PAD
140
141static const char *chip_ids[15] = {
142 NULL, NULL, NULL,
143 /* 3 */ "SMC91C90/91C92",
144 /* 4 */ "SMC91C94/91C96",
145 /* 5 */ "SMC91C95",
146 NULL,
147 /* 7 */ "SMC91C100",
148 /* 8 */ "SMC91C100FD",
149 /* 9 */ "SMC91C110",
150 NULL, NULL,
151 NULL, NULL, NULL
152};
153
154int
155sn_attach(device_t dev)
156{
157 struct sn_softc *sc = device_get_softc(dev);
158 struct ifnet *ifp;
159 uint16_t i;
160 uint8_t *p;
161 int rev;
162 uint16_t address;
163 int err;
164 u_char eaddr[6];
165
166 ifp = sc->ifp = if_alloc(IFT_ETHER);
167 if (ifp == NULL) {
168 device_printf(dev, "can not if_alloc()\n");
169 return (ENOSPC);
170 }
171
172 SN_LOCK_INIT(sc);
| 134
135static void sn_setmcast(struct sn_softc *);
136static int sn_getmcf(struct ifnet *ifp, u_char *mcf);
137
138/* I (GB) have been unlucky getting the hardware padding
139 * to work properly.
140 */
141#define SW_PAD
142
143static const char *chip_ids[15] = {
144 NULL, NULL, NULL,
145 /* 3 */ "SMC91C90/91C92",
146 /* 4 */ "SMC91C94/91C96",
147 /* 5 */ "SMC91C95",
148 NULL,
149 /* 7 */ "SMC91C100",
150 /* 8 */ "SMC91C100FD",
151 /* 9 */ "SMC91C110",
152 NULL, NULL,
153 NULL, NULL, NULL
154};
155
156int
157sn_attach(device_t dev)
158{
159 struct sn_softc *sc = device_get_softc(dev);
160 struct ifnet *ifp;
161 uint16_t i;
162 uint8_t *p;
163 int rev;
164 uint16_t address;
165 int err;
166 u_char eaddr[6];
167
168 ifp = sc->ifp = if_alloc(IFT_ETHER);
169 if (ifp == NULL) {
170 device_printf(dev, "can not if_alloc()\n");
171 return (ENOSPC);
172 }
173
174 SN_LOCK_INIT(sc);
|
| 175 callout_init_mtx(&sc->watchdog, &sc->sc_mtx, 0);
|
173 snstop(sc);
174 sc->pages_wanted = -1;
175
176 if (bootverbose || 1) {
177 SMC_SELECT_BANK(sc, 3);
178 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf;
179 if (chip_ids[rev])
180 device_printf(dev, " %s ", chip_ids[rev]);
181 else
182 device_printf(dev, " unsupported chip: rev %d ", rev);
183 SMC_SELECT_BANK(sc, 1);
184 i = CSR_READ_2(sc, CONFIG_REG_W);
185 printf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP");
186 }
187
188 /*
189 * Read the station address from the chip. The MAC address is bank 1,
190 * regs 4 - 9
191 */
192 SMC_SELECT_BANK(sc, 1);
193 p = (uint8_t *) eaddr;
194 for (i = 0; i < 6; i += 2) {
195 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i);
196 p[i + 1] = address >> 8;
197 p[i] = address & 0xFF;
198 }
199 ifp->if_softc = sc;
200 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
201 ifp->if_mtu = ETHERMTU;
202 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
203 ifp->if_start = snstart;
204 ifp->if_ioctl = snioctl;
| 176 snstop(sc);
177 sc->pages_wanted = -1;
178
179 if (bootverbose || 1) {
180 SMC_SELECT_BANK(sc, 3);
181 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf;
182 if (chip_ids[rev])
183 device_printf(dev, " %s ", chip_ids[rev]);
184 else
185 device_printf(dev, " unsupported chip: rev %d ", rev);
186 SMC_SELECT_BANK(sc, 1);
187 i = CSR_READ_2(sc, CONFIG_REG_W);
188 printf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP");
189 }
190
191 /*
192 * Read the station address from the chip. The MAC address is bank 1,
193 * regs 4 - 9
194 */
195 SMC_SELECT_BANK(sc, 1);
196 p = (uint8_t *) eaddr;
197 for (i = 0; i < 6; i += 2) {
198 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i);
199 p[i + 1] = address >> 8;
200 p[i] = address & 0xFF;
201 }
202 ifp->if_softc = sc;
203 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
204 ifp->if_mtu = ETHERMTU;
205 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
206 ifp->if_start = snstart;
207 ifp->if_ioctl = snioctl;
|
205 ifp->if_watchdog = snwatchdog;
| |
206 ifp->if_init = sninit;
207 ifp->if_baudrate = 10000000;
208 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
209 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
210 IFQ_SET_READY(&ifp->if_snd);
| 208 ifp->if_init = sninit;
209 ifp->if_baudrate = 10000000;
210 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
211 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
212 IFQ_SET_READY(&ifp->if_snd);
|
211 ifp->if_timer = 0;
| |
212
213 ether_ifattach(ifp, eaddr);
214
215 /*
216 * Activate the interrupt so we can get card interrupts. This
217 * needs to be done last so that we don't have/hold the lock
218 * during startup to avoid LORs in the network layer.
219 */
220 if ((err = bus_setup_intr(dev, sc->irq_res,
221 INTR_TYPE_NET | INTR_MPSAFE, NULL, sn_intr, sc,
222 &sc->intrhand)) != 0) {
223 sn_detach(dev);
224 return err;
225 }
226 return 0;
227}
228
229
230int
231sn_detach(device_t dev)
232{
233 struct sn_softc *sc = device_get_softc(dev);
234 struct ifnet *ifp = sc->ifp;
235
| 213
214 ether_ifattach(ifp, eaddr);
215
216 /*
217 * Activate the interrupt so we can get card interrupts. This
218 * needs to be done last so that we don't have/hold the lock
219 * during startup to avoid LORs in the network layer.
220 */
221 if ((err = bus_setup_intr(dev, sc->irq_res,
222 INTR_TYPE_NET | INTR_MPSAFE, NULL, sn_intr, sc,
223 &sc->intrhand)) != 0) {
224 sn_detach(dev);
225 return err;
226 }
227 return 0;
228}
229
230
231int
232sn_detach(device_t dev)
233{
234 struct sn_softc *sc = device_get_softc(dev);
235 struct ifnet *ifp = sc->ifp;
236
|
236 snstop(sc);
237 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
| |
238 ether_ifdetach(ifp);
| 237 ether_ifdetach(ifp);
|
| 238 SN_LOCK(sc);
239 snstop(sc);
240 SN_UNLOCK(sc);
241 callout_drain(&sc->watchdog);
|
239 sn_deactivate(dev);
240 if_free(ifp);
241 SN_LOCK_DESTROY(sc);
242 return 0;
243}
244
245static void
246sninit(void *xsc)
247{
248 struct sn_softc *sc = xsc;
249 SN_LOCK(sc);
250 sninit_locked(sc);
251 SN_UNLOCK(sc);
252}
253
254/*
255 * Reset and initialize the chip
256 */
257static void
258sninit_locked(void *xsc)
259{
260 struct sn_softc *sc = xsc;
261 struct ifnet *ifp = sc->ifp;
262 int flags;
263 int mask;
264
265 SN_ASSERT_LOCKED(sc);
266
267 /*
268 * This resets the registers mostly to defaults, but doesn't affect
269 * EEPROM. After the reset cycle, we pause briefly for the chip to
270 * be happy.
271 */
272 SMC_SELECT_BANK(sc, 0);
273 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
274 SMC_DELAY(sc);
275 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
276 SMC_DELAY(sc);
277 SMC_DELAY(sc);
278
279 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
280
281 /*
282 * Set the control register to automatically release succesfully
283 * transmitted packets (making the best use out of our limited
284 * memory) and to enable the EPH interrupt on certain TX errors.
285 */
286 SMC_SELECT_BANK(sc, 1);
287 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
288 CTR_CR_ENABLE | CTR_LE_ENABLE));
289
290 /* Set squelch level to 240mV (default 480mV) */
291 flags = CSR_READ_2(sc, CONFIG_REG_W);
292 flags |= CR_SET_SQLCH;
293 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
294
295 /*
296 * Reset the MMU and wait for it to be un-busy.
297 */
298 SMC_SELECT_BANK(sc, 2);
299 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
300 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
301 ;
302
303 /*
304 * Disable all interrupts
305 */
306 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
307
308 sn_setmcast(sc);
309
310 /*
311 * Set the transmitter control. We want it enabled.
312 */
313 flags = TCR_ENABLE;
314
315#ifndef SW_PAD
316 /*
317 * I (GB) have been unlucky getting this to work.
318 */
319 flags |= TCR_PAD_ENABLE;
320#endif /* SW_PAD */
321
322 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
323
324
325 /*
326 * Now, enable interrupts
327 */
328 SMC_SELECT_BANK(sc, 2);
329
330 mask = IM_EPH_INT |
331 IM_RX_OVRN_INT |
332 IM_RCV_INT |
333 IM_TX_INT;
334
335 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
336 sc->intr_mask = mask;
337 sc->pages_wanted = -1;
338
339
340 /*
341 * Mark the interface running but not active.
342 */
343 ifp->if_drv_flags |= IFF_DRV_RUNNING;
344 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
| 242 sn_deactivate(dev);
243 if_free(ifp);
244 SN_LOCK_DESTROY(sc);
245 return 0;
246}
247
248static void
249sninit(void *xsc)
250{
251 struct sn_softc *sc = xsc;
252 SN_LOCK(sc);
253 sninit_locked(sc);
254 SN_UNLOCK(sc);
255}
256
257/*
258 * Reset and initialize the chip
259 */
260static void
261sninit_locked(void *xsc)
262{
263 struct sn_softc *sc = xsc;
264 struct ifnet *ifp = sc->ifp;
265 int flags;
266 int mask;
267
268 SN_ASSERT_LOCKED(sc);
269
270 /*
271 * This resets the registers mostly to defaults, but doesn't affect
272 * EEPROM. After the reset cycle, we pause briefly for the chip to
273 * be happy.
274 */
275 SMC_SELECT_BANK(sc, 0);
276 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
277 SMC_DELAY(sc);
278 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
279 SMC_DELAY(sc);
280 SMC_DELAY(sc);
281
282 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
283
284 /*
285 * Set the control register to automatically release succesfully
286 * transmitted packets (making the best use out of our limited
287 * memory) and to enable the EPH interrupt on certain TX errors.
288 */
289 SMC_SELECT_BANK(sc, 1);
290 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
291 CTR_CR_ENABLE | CTR_LE_ENABLE));
292
293 /* Set squelch level to 240mV (default 480mV) */
294 flags = CSR_READ_2(sc, CONFIG_REG_W);
295 flags |= CR_SET_SQLCH;
296 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
297
298 /*
299 * Reset the MMU and wait for it to be un-busy.
300 */
301 SMC_SELECT_BANK(sc, 2);
302 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
303 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
304 ;
305
306 /*
307 * Disable all interrupts
308 */
309 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
310
311 sn_setmcast(sc);
312
313 /*
314 * Set the transmitter control. We want it enabled.
315 */
316 flags = TCR_ENABLE;
317
318#ifndef SW_PAD
319 /*
320 * I (GB) have been unlucky getting this to work.
321 */
322 flags |= TCR_PAD_ENABLE;
323#endif /* SW_PAD */
324
325 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
326
327
328 /*
329 * Now, enable interrupts
330 */
331 SMC_SELECT_BANK(sc, 2);
332
333 mask = IM_EPH_INT |
334 IM_RX_OVRN_INT |
335 IM_RCV_INT |
336 IM_TX_INT;
337
338 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
339 sc->intr_mask = mask;
340 sc->pages_wanted = -1;
341
342
343 /*
344 * Mark the interface running but not active.
345 */
346 ifp->if_drv_flags |= IFF_DRV_RUNNING;
347 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
|
| 348 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
|
345
346 /*
347 * Attempt to push out any waiting packets.
348 */
349 snstart_locked(ifp);
350}
351
352static void
353snstart(struct ifnet *ifp)
354{
355 struct sn_softc *sc = ifp->if_softc;
356 SN_LOCK(sc);
357 snstart_locked(ifp);
358 SN_UNLOCK(sc);
359}
360
361
362static void
363snstart_locked(struct ifnet *ifp)
364{
365 struct sn_softc *sc = ifp->if_softc;
366 u_int len;
367 struct mbuf *m;
368 struct mbuf *top;
369 int pad;
370 int mask;
371 uint16_t length;
372 uint16_t numPages;
373 uint8_t packet_no;
374 int time_out;
375 int junk = 0;
376
377 SN_ASSERT_LOCKED(sc);
378
379 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
380 return;
381 if (sc->pages_wanted != -1) {
382 if_printf(ifp, "snstart() while memory allocation pending\n");
383 return;
384 }
385startagain:
386
387 /*
388 * Sneak a peek at the next packet
389 */
390 m = ifp->if_snd.ifq_head;
391 if (m == 0)
392 return;
393 /*
394 * Compute the frame length and set pad to give an overall even
395 * number of bytes. Below we assume that the packet length is even.
396 */
397 for (len = 0, top = m; m; m = m->m_next)
398 len += m->m_len;
399
400 pad = (len & 1);
401
402 /*
403 * We drop packets that are too large. Perhaps we should truncate
404 * them instead?
405 */
406 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
407 if_printf(ifp, "large packet discarded (A)\n");
408 ++ifp->if_oerrors;
409 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
410 m_freem(m);
411 goto readcheck;
412 }
413#ifdef SW_PAD
414
415 /*
416 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
417 */
418 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
419 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
420
421#endif /* SW_PAD */
422
423 length = pad + len;
424
425 /*
426 * The MMU wants the number of pages to be the number of 256 byte
427 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
428 * include space for the status word, byte count and control bytes in
429 * the allocation request.
430 */
431 numPages = (length + 6) >> 8;
432
433
434 /*
435 * Now, try to allocate the memory
436 */
437 SMC_SELECT_BANK(sc, 2);
438 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
439
440 /*
441 * Wait a short amount of time to see if the allocation request
442 * completes. Otherwise, I enable the interrupt and wait for
443 * completion asyncronously.
444 */
445
446 time_out = MEMORY_WAIT_TIME;
447 do {
448 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT)
449 break;
450 } while (--time_out);
451
452 if (!time_out || junk > 10) {
453
454 /*
455 * No memory now. Oh well, wait until the chip finds memory
456 * later. Remember how many pages we were asking for and
457 * enable the allocation completion interrupt. Also set a
458 * watchdog in case we miss the interrupt. We mark the
459 * interface active since there is no point in attempting an
460 * snstart() until after the memory is available.
461 */
462 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT;
463 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
464 sc->intr_mask = mask;
465
| 349
350 /*
351 * Attempt to push out any waiting packets.
352 */
353 snstart_locked(ifp);
354}
355
356static void
357snstart(struct ifnet *ifp)
358{
359 struct sn_softc *sc = ifp->if_softc;
360 SN_LOCK(sc);
361 snstart_locked(ifp);
362 SN_UNLOCK(sc);
363}
364
365
366static void
367snstart_locked(struct ifnet *ifp)
368{
369 struct sn_softc *sc = ifp->if_softc;
370 u_int len;
371 struct mbuf *m;
372 struct mbuf *top;
373 int pad;
374 int mask;
375 uint16_t length;
376 uint16_t numPages;
377 uint8_t packet_no;
378 int time_out;
379 int junk = 0;
380
381 SN_ASSERT_LOCKED(sc);
382
383 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
384 return;
385 if (sc->pages_wanted != -1) {
386 if_printf(ifp, "snstart() while memory allocation pending\n");
387 return;
388 }
389startagain:
390
391 /*
392 * Sneak a peek at the next packet
393 */
394 m = ifp->if_snd.ifq_head;
395 if (m == 0)
396 return;
397 /*
398 * Compute the frame length and set pad to give an overall even
399 * number of bytes. Below we assume that the packet length is even.
400 */
401 for (len = 0, top = m; m; m = m->m_next)
402 len += m->m_len;
403
404 pad = (len & 1);
405
406 /*
407 * We drop packets that are too large. Perhaps we should truncate
408 * them instead?
409 */
410 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
411 if_printf(ifp, "large packet discarded (A)\n");
412 ++ifp->if_oerrors;
413 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
414 m_freem(m);
415 goto readcheck;
416 }
417#ifdef SW_PAD
418
419 /*
420 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
421 */
422 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
423 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
424
425#endif /* SW_PAD */
426
427 length = pad + len;
428
429 /*
430 * The MMU wants the number of pages to be the number of 256 byte
431 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
432 * include space for the status word, byte count and control bytes in
433 * the allocation request.
434 */
435 numPages = (length + 6) >> 8;
436
437
438 /*
439 * Now, try to allocate the memory
440 */
441 SMC_SELECT_BANK(sc, 2);
442 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
443
444 /*
445 * Wait a short amount of time to see if the allocation request
446 * completes. Otherwise, I enable the interrupt and wait for
447 * completion asyncronously.
448 */
449
450 time_out = MEMORY_WAIT_TIME;
451 do {
452 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT)
453 break;
454 } while (--time_out);
455
456 if (!time_out || junk > 10) {
457
458 /*
459 * No memory now. Oh well, wait until the chip finds memory
460 * later. Remember how many pages we were asking for and
461 * enable the allocation completion interrupt. Also set a
462 * watchdog in case we miss the interrupt. We mark the
463 * interface active since there is no point in attempting an
464 * snstart() until after the memory is available.
465 */
466 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT;
467 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
468 sc->intr_mask = mask;
469
|
466 ifp->if_timer = 1;
| 470 sc->timer = 1;
|
467 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
468 sc->pages_wanted = numPages;
469 return;
470 }
471 /*
472 * The memory allocation completed. Check the results.
473 */
474 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
475 if (packet_no & ARR_FAILED) {
476 if (junk++ > 10)
477 if_printf(ifp, "Memory allocation failed\n");
478 goto startagain;
479 }
480 /*
481 * We have a packet number, so tell the card to use it.
482 */
483 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
484
485 /*
486 * Point to the beginning of the packet
487 */
488 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
489
490 /*
491 * Send the packet length (+6 for status, length and control byte)
492 * and the status word (set to zeros)
493 */
494 CSR_WRITE_2(sc, DATA_REG_W, 0);
495 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
496 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
497
498 /*
499 * Get the packet from the kernel. This will include the Ethernet
500 * frame header, MAC Addresses etc.
501 */
502 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
503
504 /*
505 * Push out the data to the card.
506 */
507 for (top = m; m != 0; m = m->m_next) {
508
509 /*
510 * Push out words.
511 */
512 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
513 m->m_len / 2);
514
515 /*
516 * Push out remaining byte.
517 */
518 if (m->m_len & 1)
519 CSR_WRITE_1(sc, DATA_REG_B,
520 *(mtod(m, caddr_t) + m->m_len - 1));
521 }
522
523 /*
524 * Push out padding.
525 */
526 while (pad > 1) {
527 CSR_WRITE_2(sc, DATA_REG_W, 0);
528 pad -= 2;
529 }
530 if (pad)
531 CSR_WRITE_1(sc, DATA_REG_B, 0);
532
533 /*
534 * Push out control byte and unused packet byte The control byte is 0
535 * meaning the packet is even lengthed and no special CRC handling is
536 * desired.
537 */
538 CSR_WRITE_2(sc, DATA_REG_W, 0);
539
540 /*
541 * Enable the interrupts and let the chipset deal with it Also set a
542 * watchdog in case we miss the interrupt.
543 */
544 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
545 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
546 sc->intr_mask = mask;
547
548 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
549
550 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
| 471 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
472 sc->pages_wanted = numPages;
473 return;
474 }
475 /*
476 * The memory allocation completed. Check the results.
477 */
478 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
479 if (packet_no & ARR_FAILED) {
480 if (junk++ > 10)
481 if_printf(ifp, "Memory allocation failed\n");
482 goto startagain;
483 }
484 /*
485 * We have a packet number, so tell the card to use it.
486 */
487 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
488
489 /*
490 * Point to the beginning of the packet
491 */
492 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
493
494 /*
495 * Send the packet length (+6 for status, length and control byte)
496 * and the status word (set to zeros)
497 */
498 CSR_WRITE_2(sc, DATA_REG_W, 0);
499 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
500 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
501
502 /*
503 * Get the packet from the kernel. This will include the Ethernet
504 * frame header, MAC Addresses etc.
505 */
506 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
507
508 /*
509 * Push out the data to the card.
510 */
511 for (top = m; m != 0; m = m->m_next) {
512
513 /*
514 * Push out words.
515 */
516 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
517 m->m_len / 2);
518
519 /*
520 * Push out remaining byte.
521 */
522 if (m->m_len & 1)
523 CSR_WRITE_1(sc, DATA_REG_B,
524 *(mtod(m, caddr_t) + m->m_len - 1));
525 }
526
527 /*
528 * Push out padding.
529 */
530 while (pad > 1) {
531 CSR_WRITE_2(sc, DATA_REG_W, 0);
532 pad -= 2;
533 }
534 if (pad)
535 CSR_WRITE_1(sc, DATA_REG_B, 0);
536
537 /*
538 * Push out control byte and unused packet byte The control byte is 0
539 * meaning the packet is even lengthed and no special CRC handling is
540 * desired.
541 */
542 CSR_WRITE_2(sc, DATA_REG_W, 0);
543
544 /*
545 * Enable the interrupts and let the chipset deal with it Also set a
546 * watchdog in case we miss the interrupt.
547 */
548 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
549 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
550 sc->intr_mask = mask;
551
552 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
553
554 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
|
551 ifp->if_timer = 1;
| 555 sc->timer = 1;
|
552
553 BPF_MTAP(ifp, top);
554
555 ifp->if_opackets++;
556 m_freem(top);
557
558
559readcheck:
560
561 /*
562 * Is another packet coming in? We don't want to overflow the tiny
563 * RX FIFO. If nothing has arrived then attempt to queue another
564 * transmit packet.
565 */
566 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY)
567 goto startagain;
568 return;
569}
570
571
572
573/* Resume a packet transmit operation after a memory allocation
574 * has completed.
575 *
576 * This is basically a hacked up copy of snstart() which handles
577 * a completed memory allocation the same way snstart() does.
578 * It then passes control to snstart to handle any other queued
579 * packets.
580 */
581static void
582snresume(struct ifnet *ifp)
583{
584 struct sn_softc *sc = ifp->if_softc;
585 u_int len;
586 struct mbuf *m;
587 struct mbuf *top;
588 int pad;
589 int mask;
590 uint16_t length;
591 uint16_t numPages;
592 uint16_t pages_wanted;
593 uint8_t packet_no;
594
595 if (sc->pages_wanted < 0)
596 return;
597
598 pages_wanted = sc->pages_wanted;
599 sc->pages_wanted = -1;
600
601 /*
602 * Sneak a peek at the next packet
603 */
604 m = ifp->if_snd.ifq_head;
605 if (m == 0) {
606 if_printf(ifp, "snresume() with nothing to send\n");
607 return;
608 }
609 /*
610 * Compute the frame length and set pad to give an overall even
611 * number of bytes. Below we assume that the packet length is even.
612 */
613 for (len = 0, top = m; m; m = m->m_next)
614 len += m->m_len;
615
616 pad = (len & 1);
617
618 /*
619 * We drop packets that are too large. Perhaps we should truncate
620 * them instead?
621 */
622 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
623 if_printf(ifp, "large packet discarded (B)\n");
624 ++ifp->if_oerrors;
625 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
626 m_freem(m);
627 return;
628 }
629#ifdef SW_PAD
630
631 /*
632 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
633 */
634 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
635 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
636
637#endif /* SW_PAD */
638
639 length = pad + len;
640
641
642 /*
643 * The MMU wants the number of pages to be the number of 256 byte
644 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
645 * include space for the status word, byte count and control bytes in
646 * the allocation request.
647 */
648 numPages = (length + 6) >> 8;
649
650
651 SMC_SELECT_BANK(sc, 2);
652
653 /*
654 * The memory allocation completed. Check the results. If it failed,
655 * we simply set a watchdog timer and hope for the best.
656 */
657 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
658 if (packet_no & ARR_FAILED) {
659 if_printf(ifp, "Memory allocation failed. Weird.\n");
| 556
557 BPF_MTAP(ifp, top);
558
559 ifp->if_opackets++;
560 m_freem(top);
561
562
563readcheck:
564
565 /*
566 * Is another packet coming in? We don't want to overflow the tiny
567 * RX FIFO. If nothing has arrived then attempt to queue another
568 * transmit packet.
569 */
570 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY)
571 goto startagain;
572 return;
573}
574
575
576
577/* Resume a packet transmit operation after a memory allocation
578 * has completed.
579 *
580 * This is basically a hacked up copy of snstart() which handles
581 * a completed memory allocation the same way snstart() does.
582 * It then passes control to snstart to handle any other queued
583 * packets.
584 */
585static void
586snresume(struct ifnet *ifp)
587{
588 struct sn_softc *sc = ifp->if_softc;
589 u_int len;
590 struct mbuf *m;
591 struct mbuf *top;
592 int pad;
593 int mask;
594 uint16_t length;
595 uint16_t numPages;
596 uint16_t pages_wanted;
597 uint8_t packet_no;
598
599 if (sc->pages_wanted < 0)
600 return;
601
602 pages_wanted = sc->pages_wanted;
603 sc->pages_wanted = -1;
604
605 /*
606 * Sneak a peek at the next packet
607 */
608 m = ifp->if_snd.ifq_head;
609 if (m == 0) {
610 if_printf(ifp, "snresume() with nothing to send\n");
611 return;
612 }
613 /*
614 * Compute the frame length and set pad to give an overall even
615 * number of bytes. Below we assume that the packet length is even.
616 */
617 for (len = 0, top = m; m; m = m->m_next)
618 len += m->m_len;
619
620 pad = (len & 1);
621
622 /*
623 * We drop packets that are too large. Perhaps we should truncate
624 * them instead?
625 */
626 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
627 if_printf(ifp, "large packet discarded (B)\n");
628 ++ifp->if_oerrors;
629 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
630 m_freem(m);
631 return;
632 }
633#ifdef SW_PAD
634
635 /*
636 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
637 */
638 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
639 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
640
641#endif /* SW_PAD */
642
643 length = pad + len;
644
645
646 /*
647 * The MMU wants the number of pages to be the number of 256 byte
648 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
649 * include space for the status word, byte count and control bytes in
650 * the allocation request.
651 */
652 numPages = (length + 6) >> 8;
653
654
655 SMC_SELECT_BANK(sc, 2);
656
657 /*
658 * The memory allocation completed. Check the results. If it failed,
659 * we simply set a watchdog timer and hope for the best.
660 */
661 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
662 if (packet_no & ARR_FAILED) {
663 if_printf(ifp, "Memory allocation failed. Weird.\n");
|
660 ifp->if_timer = 1;
| 664 sc->timer = 1;
|
661 goto try_start;
662 }
663 /*
664 * We have a packet number, so tell the card to use it.
665 */
666 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
667
668 /*
669 * Now, numPages should match the pages_wanted recorded when the
670 * memory allocation was initiated.
671 */
672 if (pages_wanted != numPages) {
673 if_printf(ifp, "memory allocation wrong size. Weird.\n");
674 /*
675 * If the allocation was the wrong size we simply release the
676 * memory once it is granted. Wait for the MMU to be un-busy.
677 */
678 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
679 ;
680 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
681
682 return;
683 }
684 /*
685 * Point to the beginning of the packet
686 */
687 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
688
689 /*
690 * Send the packet length (+6 for status, length and control byte)
691 * and the status word (set to zeros)
692 */
693 CSR_WRITE_2(sc, DATA_REG_W, 0);
694 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
695 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
696
697 /*
698 * Get the packet from the kernel. This will include the Ethernet
699 * frame header, MAC Addresses etc.
700 */
701 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
702
703 /*
704 * Push out the data to the card.
705 */
706 for (top = m; m != 0; m = m->m_next) {
707
708 /*
709 * Push out words.
710 */
711 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
712 m->m_len / 2);
713 /*
714 * Push out remaining byte.
715 */
716 if (m->m_len & 1)
717 CSR_WRITE_1(sc, DATA_REG_B,
718 *(mtod(m, caddr_t) + m->m_len - 1));
719 }
720
721 /*
722 * Push out padding.
723 */
724 while (pad > 1) {
725 CSR_WRITE_2(sc, DATA_REG_W, 0);
726 pad -= 2;
727 }
728 if (pad)
729 CSR_WRITE_1(sc, DATA_REG_B, 0);
730
731 /*
732 * Push out control byte and unused packet byte The control byte is 0
733 * meaning the packet is even lengthed and no special CRC handling is
734 * desired.
735 */
736 CSR_WRITE_2(sc, DATA_REG_W, 0);
737
738 /*
739 * Enable the interrupts and let the chipset deal with it Also set a
740 * watchdog in case we miss the interrupt.
741 */
742 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
743 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
744 sc->intr_mask = mask;
745 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
746
747 BPF_MTAP(ifp, top);
748
749 ifp->if_opackets++;
750 m_freem(top);
751
752try_start:
753
754 /*
755 * Now pass control to snstart() to queue any additional packets
756 */
757 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
| 665 goto try_start;
666 }
667 /*
668 * We have a packet number, so tell the card to use it.
669 */
670 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
671
672 /*
673 * Now, numPages should match the pages_wanted recorded when the
674 * memory allocation was initiated.
675 */
676 if (pages_wanted != numPages) {
677 if_printf(ifp, "memory allocation wrong size. Weird.\n");
678 /*
679 * If the allocation was the wrong size we simply release the
680 * memory once it is granted. Wait for the MMU to be un-busy.
681 */
682 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
683 ;
684 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
685
686 return;
687 }
688 /*
689 * Point to the beginning of the packet
690 */
691 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
692
693 /*
694 * Send the packet length (+6 for status, length and control byte)
695 * and the status word (set to zeros)
696 */
697 CSR_WRITE_2(sc, DATA_REG_W, 0);
698 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
699 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
700
701 /*
702 * Get the packet from the kernel. This will include the Ethernet
703 * frame header, MAC Addresses etc.
704 */
705 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
706
707 /*
708 * Push out the data to the card.
709 */
710 for (top = m; m != 0; m = m->m_next) {
711
712 /*
713 * Push out words.
714 */
715 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
716 m->m_len / 2);
717 /*
718 * Push out remaining byte.
719 */
720 if (m->m_len & 1)
721 CSR_WRITE_1(sc, DATA_REG_B,
722 *(mtod(m, caddr_t) + m->m_len - 1));
723 }
724
725 /*
726 * Push out padding.
727 */
728 while (pad > 1) {
729 CSR_WRITE_2(sc, DATA_REG_W, 0);
730 pad -= 2;
731 }
732 if (pad)
733 CSR_WRITE_1(sc, DATA_REG_B, 0);
734
735 /*
736 * Push out control byte and unused packet byte The control byte is 0
737 * meaning the packet is even lengthed and no special CRC handling is
738 * desired.
739 */
740 CSR_WRITE_2(sc, DATA_REG_W, 0);
741
742 /*
743 * Enable the interrupts and let the chipset deal with it Also set a
744 * watchdog in case we miss the interrupt.
745 */
746 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
747 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
748 sc->intr_mask = mask;
749 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
750
751 BPF_MTAP(ifp, top);
752
753 ifp->if_opackets++;
754 m_freem(top);
755
756try_start:
757
758 /*
759 * Now pass control to snstart() to queue any additional packets
760 */
761 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
|
758 snstart(ifp);
| 762 snstart_locked(ifp);
|
759
760 /*
761 * We've sent something, so we're active. Set a watchdog in case the
762 * TX_EMPTY interrupt is lost.
763 */
764 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
| 763
764 /*
765 * We've sent something, so we're active. Set a watchdog in case the
766 * TX_EMPTY interrupt is lost.
767 */
768 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
|
765 ifp->if_timer = 1;
| 769 sc->timer = 1;
|
766
767 return;
768}
769
| 770
771 return;
772}
773
|
770
| |
771void
772sn_intr(void *arg)
773{
| 774void
775sn_intr(void *arg)
776{
|
774 int status, interrupts;
| |
775 struct sn_softc *sc = (struct sn_softc *) arg;
| 777 struct sn_softc *sc = (struct sn_softc *) arg;
|
| 778
779 SN_LOCK(sc);
780 snintr_locked(sc);
781 SN_UNLOCK(sc);
782}
783
784static void
785snintr_locked(struct sn_softc *sc)
786{
787 int status, interrupts;
|
776 struct ifnet *ifp = sc->ifp;
777
778 /*
779 * Chip state registers
780 */
781 uint8_t mask;
782 uint8_t packet_no;
783 uint16_t tx_status;
784 uint16_t card_stats;
785
| 788 struct ifnet *ifp = sc->ifp;
789
790 /*
791 * Chip state registers
792 */
793 uint8_t mask;
794 uint8_t packet_no;
795 uint16_t tx_status;
796 uint16_t card_stats;
797
|
786 SN_LOCK(sc);
787
| |
788 /*
789 * Clear the watchdog.
790 */
| 798 /*
799 * Clear the watchdog.
800 */
|
791 ifp->if_timer = 0;
| 801 sc->timer = 0;
|
792
793 SMC_SELECT_BANK(sc, 2);
794
795 /*
796 * Obtain the current interrupt mask and clear the hardware mask
797 * while servicing interrupts.
798 */
799 mask = CSR_READ_1(sc, INTR_MASK_REG_B);
800 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
801
802 /*
803 * Get the set of interrupts which occurred and eliminate any which
804 * are masked.
805 */
806 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B);
807 status = interrupts & mask;
808
809 /*
810 * Now, process each of the interrupt types.
811 */
812
813 /*
814 * Receive Overrun.
815 */
816 if (status & IM_RX_OVRN_INT) {
817 /*
818 * Acknowlege Interrupt
819 */
820 SMC_SELECT_BANK(sc, 2);
821 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT);
822
823 ++ifp->if_ierrors;
824 }
825 /*
826 * Got a packet.
827 */
828 if (status & IM_RCV_INT) {
829 int packet_number;
830
831 SMC_SELECT_BANK(sc, 2);
832 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
833
834 if (packet_number & FIFO_REMPTY) {
835 /*
836 * we got called , but nothing was on the FIFO
837 */
838 printf("sn: Receive interrupt with nothing on FIFO\n");
839 goto out;
840 }
841 snread(ifp);
842 }
843 /*
844 * An on-card memory allocation came through.
845 */
846 if (status & IM_ALLOC_INT) {
847 /*
848 * Disable this interrupt.
849 */
850 mask &= ~IM_ALLOC_INT;
851 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
852 snresume(ifp);
853 }
854 /*
855 * TX Completion. Handle a transmit error message. This will only be
856 * called when there is an error, because of the AUTO_RELEASE mode.
857 */
858 if (status & IM_TX_INT) {
859 /*
860 * Acknowlege Interrupt
861 */
862 SMC_SELECT_BANK(sc, 2);
863 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT);
864
865 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W);
866 packet_no &= FIFO_TX_MASK;
867
868 /*
869 * select this as the packet to read from
870 */
871 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
872
873 /*
874 * Position the pointer to the first word from this packet
875 */
876 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
877
878 /*
879 * Fetch the TX status word. The value found here will be a
880 * copy of the EPH_STATUS_REG_W at the time the transmit
881 * failed.
882 */
883 tx_status = CSR_READ_2(sc, DATA_REG_W);
884
885 if (tx_status & EPHSR_TX_SUC) {
886 device_printf(sc->dev,
887 "Successful packet caused interrupt\n");
888 } else {
889 ++ifp->if_oerrors;
890 }
891
892 if (tx_status & EPHSR_LATCOL)
893 ++ifp->if_collisions;
894
895 /*
896 * Some of these errors will have disabled transmit.
897 * Re-enable transmit now.
898 */
899 SMC_SELECT_BANK(sc, 0);
900
901#ifdef SW_PAD
902 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE);
903#else
904 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
905#endif /* SW_PAD */
906
907 /*
908 * kill the failed packet. Wait for the MMU to be un-busy.
909 */
910 SMC_SELECT_BANK(sc, 2);
911 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
912 ;
913 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
914
915 /*
916 * Attempt to queue more transmits.
917 */
918 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
919 snstart_locked(ifp);
920 }
921 /*
922 * Transmit underrun. We use this opportunity to update transmit
923 * statistics from the card.
924 */
925 if (status & IM_TX_EMPTY_INT) {
926
927 /*
928 * Acknowlege Interrupt
929 */
930 SMC_SELECT_BANK(sc, 2);
931 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT);
932
933 /*
934 * Disable this interrupt.
935 */
936 mask &= ~IM_TX_EMPTY_INT;
937
938 SMC_SELECT_BANK(sc, 0);
939 card_stats = CSR_READ_2(sc, COUNTER_REG_W);
940
941 /*
942 * Single collisions
943 */
944 ifp->if_collisions += card_stats & ECR_COLN_MASK;
945
946 /*
947 * Multiple collisions
948 */
949 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4;
950
951 SMC_SELECT_BANK(sc, 2);
952
953 /*
954 * Attempt to enqueue some more stuff.
955 */
956 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
957 snstart_locked(ifp);
958 }
959 /*
960 * Some other error. Try to fix it by resetting the adapter.
961 */
962 if (status & IM_EPH_INT) {
963 snstop(sc);
964 sninit_locked(sc);
965 }
966
967out:
968 /*
969 * Handled all interrupt sources.
970 */
971
972 SMC_SELECT_BANK(sc, 2);
973
974 /*
975 * Reestablish interrupts from mask which have not been deselected
976 * during this interrupt. Note that the hardware mask, which was set
977 * to 0x00 at the start of this service routine, may have been
978 * updated by one or more of the interrupt handers and we must let
979 * those new interrupts stay enabled here.
980 */
981 mask |= CSR_READ_1(sc, INTR_MASK_REG_B);
982 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
983 sc->intr_mask = mask;
| 802
803 SMC_SELECT_BANK(sc, 2);
804
805 /*
806 * Obtain the current interrupt mask and clear the hardware mask
807 * while servicing interrupts.
808 */
809 mask = CSR_READ_1(sc, INTR_MASK_REG_B);
810 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
811
812 /*
813 * Get the set of interrupts which occurred and eliminate any which
814 * are masked.
815 */
816 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B);
817 status = interrupts & mask;
818
819 /*
820 * Now, process each of the interrupt types.
821 */
822
823 /*
824 * Receive Overrun.
825 */
826 if (status & IM_RX_OVRN_INT) {
827 /*
828 * Acknowlege Interrupt
829 */
830 SMC_SELECT_BANK(sc, 2);
831 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT);
832
833 ++ifp->if_ierrors;
834 }
835 /*
836 * Got a packet.
837 */
838 if (status & IM_RCV_INT) {
839 int packet_number;
840
841 SMC_SELECT_BANK(sc, 2);
842 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
843
844 if (packet_number & FIFO_REMPTY) {
845 /*
846 * we got called , but nothing was on the FIFO
847 */
848 printf("sn: Receive interrupt with nothing on FIFO\n");
849 goto out;
850 }
851 snread(ifp);
852 }
853 /*
854 * An on-card memory allocation came through.
855 */
856 if (status & IM_ALLOC_INT) {
857 /*
858 * Disable this interrupt.
859 */
860 mask &= ~IM_ALLOC_INT;
861 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
862 snresume(ifp);
863 }
864 /*
865 * TX Completion. Handle a transmit error message. This will only be
866 * called when there is an error, because of the AUTO_RELEASE mode.
867 */
868 if (status & IM_TX_INT) {
869 /*
870 * Acknowlege Interrupt
871 */
872 SMC_SELECT_BANK(sc, 2);
873 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT);
874
875 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W);
876 packet_no &= FIFO_TX_MASK;
877
878 /*
879 * select this as the packet to read from
880 */
881 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
882
883 /*
884 * Position the pointer to the first word from this packet
885 */
886 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
887
888 /*
889 * Fetch the TX status word. The value found here will be a
890 * copy of the EPH_STATUS_REG_W at the time the transmit
891 * failed.
892 */
893 tx_status = CSR_READ_2(sc, DATA_REG_W);
894
895 if (tx_status & EPHSR_TX_SUC) {
896 device_printf(sc->dev,
897 "Successful packet caused interrupt\n");
898 } else {
899 ++ifp->if_oerrors;
900 }
901
902 if (tx_status & EPHSR_LATCOL)
903 ++ifp->if_collisions;
904
905 /*
906 * Some of these errors will have disabled transmit.
907 * Re-enable transmit now.
908 */
909 SMC_SELECT_BANK(sc, 0);
910
911#ifdef SW_PAD
912 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE);
913#else
914 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
915#endif /* SW_PAD */
916
917 /*
918 * kill the failed packet. Wait for the MMU to be un-busy.
919 */
920 SMC_SELECT_BANK(sc, 2);
921 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
922 ;
923 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
924
925 /*
926 * Attempt to queue more transmits.
927 */
928 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
929 snstart_locked(ifp);
930 }
931 /*
932 * Transmit underrun. We use this opportunity to update transmit
933 * statistics from the card.
934 */
935 if (status & IM_TX_EMPTY_INT) {
936
937 /*
938 * Acknowlege Interrupt
939 */
940 SMC_SELECT_BANK(sc, 2);
941 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT);
942
943 /*
944 * Disable this interrupt.
945 */
946 mask &= ~IM_TX_EMPTY_INT;
947
948 SMC_SELECT_BANK(sc, 0);
949 card_stats = CSR_READ_2(sc, COUNTER_REG_W);
950
951 /*
952 * Single collisions
953 */
954 ifp->if_collisions += card_stats & ECR_COLN_MASK;
955
956 /*
957 * Multiple collisions
958 */
959 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4;
960
961 SMC_SELECT_BANK(sc, 2);
962
963 /*
964 * Attempt to enqueue some more stuff.
965 */
966 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
967 snstart_locked(ifp);
968 }
969 /*
970 * Some other error. Try to fix it by resetting the adapter.
971 */
972 if (status & IM_EPH_INT) {
973 snstop(sc);
974 sninit_locked(sc);
975 }
976
977out:
978 /*
979 * Handled all interrupt sources.
980 */
981
982 SMC_SELECT_BANK(sc, 2);
983
984 /*
985 * Reestablish interrupts from mask which have not been deselected
986 * during this interrupt. Note that the hardware mask, which was set
987 * to 0x00 at the start of this service routine, may have been
988 * updated by one or more of the interrupt handers and we must let
989 * those new interrupts stay enabled here.
990 */
991 mask |= CSR_READ_1(sc, INTR_MASK_REG_B);
992 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
993 sc->intr_mask = mask;
|
984 SN_UNLOCK(sc);
| |
985}
986
987static void
988snread(struct ifnet *ifp)
989{
990 struct sn_softc *sc = ifp->if_softc;
991 struct ether_header *eh;
992 struct mbuf *m;
993 short status;
994 int packet_number;
995 uint16_t packet_length;
996 uint8_t *data;
997
998 SMC_SELECT_BANK(sc, 2);
999#if 0
1000 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1001
1002 if (packet_number & FIFO_REMPTY) {
1003
1004 /*
1005 * we got called , but nothing was on the FIFO
1006 */
1007 printf("sn: Receive interrupt with nothing on FIFO\n");
1008 return;
1009 }
1010#endif
1011read_another:
1012
1013 /*
1014 * Start reading from the start of the packet. Since PTR_RCV is set,
1015 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK.
1016 */
1017 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
1018
1019 /*
1020 * First two words are status and packet_length
1021 */
1022 status = CSR_READ_2(sc, DATA_REG_W);
1023 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK;
1024
1025 /*
1026 * The packet length contains 3 extra words: status, length, and a
1027 * extra word with the control byte.
1028 */
1029 packet_length -= 6;
1030
1031 /*
1032 * Account for receive errors and discard.
1033 */
1034 if (status & RS_ERRORS) {
1035 ++ifp->if_ierrors;
1036 goto out;
1037 }
1038 /*
1039 * A packet is received.
1040 */
1041
1042 /*
1043 * Adjust for odd-length packet.
1044 */
1045 if (status & RS_ODDFRAME)
1046 packet_length++;
1047
1048 /*
1049 * Allocate a header mbuf from the kernel.
1050 */
1051 MGETHDR(m, M_DONTWAIT, MT_DATA);
1052 if (m == NULL)
1053 goto out;
1054
1055 m->m_pkthdr.rcvif = ifp;
1056 m->m_pkthdr.len = m->m_len = packet_length;
1057
1058 /*
1059 * Attach an mbuf cluster
1060 */
1061 MCLGET(m, M_DONTWAIT);
1062
1063 /*
1064 * Insist on getting a cluster
1065 */
1066 if ((m->m_flags & M_EXT) == 0) {
1067 m_freem(m);
1068 ++ifp->if_ierrors;
1069 printf("sn: snread() kernel memory allocation problem\n");
1070 goto out;
1071 }
1072 eh = mtod(m, struct ether_header *);
1073
1074 /*
1075 * Get packet, including link layer address, from interface.
1076 */
1077 data = (uint8_t *) eh;
1078 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1);
1079 if (packet_length & 1) {
1080 data += packet_length & ~1;
1081 *data = CSR_READ_1(sc, DATA_REG_B);
1082 }
1083 ++ifp->if_ipackets;
1084
1085 /*
1086 * Remove link layer addresses and whatnot.
1087 */
1088 m->m_pkthdr.len = m->m_len = packet_length;
1089
1090 /*
1091 * Drop locks before calling if_input() since it may re-enter
1092 * snstart() in the netisr case. This would result in a
1093 * lock reversal. Better performance might be obtained by
1094 * chaining all packets received, dropping the lock, and then
1095 * calling if_input() on each one.
1096 */
1097 SN_UNLOCK(sc);
1098 (*ifp->if_input)(ifp, m);
1099 SN_LOCK(sc);
1100
1101out:
1102
1103 /*
1104 * Error or good, tell the card to get rid of this packet Wait for
1105 * the MMU to be un-busy.
1106 */
1107 SMC_SELECT_BANK(sc, 2);
1108 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
1109 ;
1110 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE);
1111
1112 /*
1113 * Check whether another packet is ready
1114 */
1115 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1116 if (packet_number & FIFO_REMPTY) {
1117 return;
1118 }
1119 goto read_another;
1120}
1121
1122
1123/*
1124 * Handle IOCTLS. This function is completely stolen from if_ep.c
1125 * As with its progenitor, it does not handle hardware address
1126 * changes.
1127 */
1128static int
1129snioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1130{
1131 struct sn_softc *sc = ifp->if_softc;
1132 int error = 0;
1133
1134 switch (cmd) {
1135 case SIOCSIFFLAGS:
1136 SN_LOCK(sc);
1137 if ((ifp->if_flags & IFF_UP) == 0 &&
1138 ifp->if_drv_flags & IFF_DRV_RUNNING) {
| 994}
995
996static void
997snread(struct ifnet *ifp)
998{
999 struct sn_softc *sc = ifp->if_softc;
1000 struct ether_header *eh;
1001 struct mbuf *m;
1002 short status;
1003 int packet_number;
1004 uint16_t packet_length;
1005 uint8_t *data;
1006
1007 SMC_SELECT_BANK(sc, 2);
1008#if 0
1009 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1010
1011 if (packet_number & FIFO_REMPTY) {
1012
1013 /*
1014 * we got called , but nothing was on the FIFO
1015 */
1016 printf("sn: Receive interrupt with nothing on FIFO\n");
1017 return;
1018 }
1019#endif
1020read_another:
1021
1022 /*
1023 * Start reading from the start of the packet. Since PTR_RCV is set,
1024 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK.
1025 */
1026 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
1027
1028 /*
1029 * First two words are status and packet_length
1030 */
1031 status = CSR_READ_2(sc, DATA_REG_W);
1032 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK;
1033
1034 /*
1035 * The packet length contains 3 extra words: status, length, and a
1036 * extra word with the control byte.
1037 */
1038 packet_length -= 6;
1039
1040 /*
1041 * Account for receive errors and discard.
1042 */
1043 if (status & RS_ERRORS) {
1044 ++ifp->if_ierrors;
1045 goto out;
1046 }
1047 /*
1048 * A packet is received.
1049 */
1050
1051 /*
1052 * Adjust for odd-length packet.
1053 */
1054 if (status & RS_ODDFRAME)
1055 packet_length++;
1056
1057 /*
1058 * Allocate a header mbuf from the kernel.
1059 */
1060 MGETHDR(m, M_DONTWAIT, MT_DATA);
1061 if (m == NULL)
1062 goto out;
1063
1064 m->m_pkthdr.rcvif = ifp;
1065 m->m_pkthdr.len = m->m_len = packet_length;
1066
1067 /*
1068 * Attach an mbuf cluster
1069 */
1070 MCLGET(m, M_DONTWAIT);
1071
1072 /*
1073 * Insist on getting a cluster
1074 */
1075 if ((m->m_flags & M_EXT) == 0) {
1076 m_freem(m);
1077 ++ifp->if_ierrors;
1078 printf("sn: snread() kernel memory allocation problem\n");
1079 goto out;
1080 }
1081 eh = mtod(m, struct ether_header *);
1082
1083 /*
1084 * Get packet, including link layer address, from interface.
1085 */
1086 data = (uint8_t *) eh;
1087 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1);
1088 if (packet_length & 1) {
1089 data += packet_length & ~1;
1090 *data = CSR_READ_1(sc, DATA_REG_B);
1091 }
1092 ++ifp->if_ipackets;
1093
1094 /*
1095 * Remove link layer addresses and whatnot.
1096 */
1097 m->m_pkthdr.len = m->m_len = packet_length;
1098
1099 /*
1100 * Drop locks before calling if_input() since it may re-enter
1101 * snstart() in the netisr case. This would result in a
1102 * lock reversal. Better performance might be obtained by
1103 * chaining all packets received, dropping the lock, and then
1104 * calling if_input() on each one.
1105 */
1106 SN_UNLOCK(sc);
1107 (*ifp->if_input)(ifp, m);
1108 SN_LOCK(sc);
1109
1110out:
1111
1112 /*
1113 * Error or good, tell the card to get rid of this packet Wait for
1114 * the MMU to be un-busy.
1115 */
1116 SMC_SELECT_BANK(sc, 2);
1117 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
1118 ;
1119 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE);
1120
1121 /*
1122 * Check whether another packet is ready
1123 */
1124 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1125 if (packet_number & FIFO_REMPTY) {
1126 return;
1127 }
1128 goto read_another;
1129}
1130
1131
1132/*
1133 * Handle IOCTLS. This function is completely stolen from if_ep.c
1134 * As with its progenitor, it does not handle hardware address
1135 * changes.
1136 */
1137static int
1138snioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1139{
1140 struct sn_softc *sc = ifp->if_softc;
1141 int error = 0;
1142
1143 switch (cmd) {
1144 case SIOCSIFFLAGS:
1145 SN_LOCK(sc);
1146 if ((ifp->if_flags & IFF_UP) == 0 &&
1147 ifp->if_drv_flags & IFF_DRV_RUNNING) {
|
1139 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
| |
1140 snstop(sc);
1141 } else {
1142 /* reinitialize card on any parameter change */
1143 sninit_locked(sc);
1144 }
1145 SN_UNLOCK(sc);
1146 break;
1147
1148 case SIOCADDMULTI:
1149 case SIOCDELMULTI:
1150 /* update multicast filter list. */
1151 SN_LOCK(sc);
1152 sn_setmcast(sc);
1153 error = 0;
1154 SN_UNLOCK(sc);
1155 break;
1156 default:
1157 error = ether_ioctl(ifp, cmd, data);
1158 break;
1159 }
1160 return (error);
1161}
1162
1163static void
| 1148 snstop(sc);
1149 } else {
1150 /* reinitialize card on any parameter change */
1151 sninit_locked(sc);
1152 }
1153 SN_UNLOCK(sc);
1154 break;
1155
1156 case SIOCADDMULTI:
1157 case SIOCDELMULTI:
1158 /* update multicast filter list. */
1159 SN_LOCK(sc);
1160 sn_setmcast(sc);
1161 error = 0;
1162 SN_UNLOCK(sc);
1163 break;
1164 default:
1165 error = ether_ioctl(ifp, cmd, data);
1166 break;
1167 }
1168 return (error);
1169}
1170
1171static void
|
1164snwatchdog(struct ifnet *ifp)
| 1172snwatchdog(void *arg)
|
1165{
| 1173{
|
1166 sn_intr(ifp->if_softc);
| 1174 struct sn_softc *sc;
1175
1176 sc = arg;
1177 SN_ASSERT_LOCKED(sc);
1178 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
1179 if (sc->timer == 0 || --sc->timer > 0)
1180 return;
1181 snintr_locked(sc);
|
1167}
1168
1169
1170/* 1. zero the interrupt mask
1171 * 2. clear the enable receive flag
1172 * 3. clear the enable xmit flags
1173 */
1174static void
1175snstop(struct sn_softc *sc)
1176{
1177
1178 struct ifnet *ifp = sc->ifp;
1179
1180 /*
1181 * Clear interrupt mask; disable all interrupts.
1182 */
1183 SMC_SELECT_BANK(sc, 2);
1184 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
1185
1186 /*
1187 * Disable transmitter and Receiver
1188 */
1189 SMC_SELECT_BANK(sc, 0);
1190 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
1191 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
1192
1193 /*
1194 * Cancel watchdog.
1195 */
| 1182}
1183
1184
1185/* 1. zero the interrupt mask
1186 * 2. clear the enable receive flag
1187 * 3. clear the enable xmit flags
1188 */
1189static void
1190snstop(struct sn_softc *sc)
1191{
1192
1193 struct ifnet *ifp = sc->ifp;
1194
1195 /*
1196 * Clear interrupt mask; disable all interrupts.
1197 */
1198 SMC_SELECT_BANK(sc, 2);
1199 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
1200
1201 /*
1202 * Disable transmitter and Receiver
1203 */
1204 SMC_SELECT_BANK(sc, 0);
1205 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
1206 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
1207
1208 /*
1209 * Cancel watchdog.
1210 */
|
1196 ifp->if_timer = 0;
| 1211 sc->timer = 0;
1212 callout_stop(&sc->watchdog);
1213 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
|
1197}
1198
1199
1200int
1201sn_activate(device_t dev)
1202{
1203 struct sn_softc *sc = device_get_softc(dev);
1204
1205 sc->port_rid = 0;
1206 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid,
1207 0, ~0, SMC_IO_EXTENT, RF_ACTIVE);
1208 if (!sc->port_res) {
1209 if (bootverbose)
1210 device_printf(dev, "Cannot allocate ioport\n");
1211 return ENOMEM;
1212 }
1213
1214 sc->irq_rid = 0;
1215 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
1216 RF_ACTIVE);
1217 if (!sc->irq_res) {
1218 if (bootverbose)
1219 device_printf(dev, "Cannot allocate irq\n");
1220 sn_deactivate(dev);
1221 return ENOMEM;
1222 }
1223 return (0);
1224}
1225
1226void
1227sn_deactivate(device_t dev)
1228{
1229 struct sn_softc *sc = device_get_softc(dev);
1230
1231 if (sc->intrhand)
1232 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1233 sc->intrhand = 0;
1234 if (sc->port_res)
1235 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
1236 sc->port_res);
1237 sc->port_res = 0;
1238 if (sc->modem_res)
1239 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid,
1240 sc->modem_res);
1241 sc->modem_res = 0;
1242 if (sc->irq_res)
1243 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
1244 sc->irq_res);
1245 sc->irq_res = 0;
1246 return;
1247}
1248
1249/*
1250 * Function: sn_probe(device_t dev)
1251 *
1252 * Purpose:
1253 * Tests to see if a given ioaddr points to an SMC9xxx chip.
1254 * Tries to cause as little damage as possible if it's not a SMC chip.
1255 * Returns a 0 on success
1256 *
1257 * Algorithm:
1258 * (1) see if the high byte of BANK_SELECT is 0x33
1259 * (2) compare the ioaddr with the base register's address
1260 * (3) see if I recognize the chip ID in the appropriate register
1261 *
1262 *
1263 */
1264int
1265sn_probe(device_t dev)
1266{
1267 struct sn_softc *sc = device_get_softc(dev);
1268 uint16_t bank;
1269 uint16_t revision_register;
1270 uint16_t base_address_register;
1271 int err;
1272
1273 if ((err = sn_activate(dev)) != 0)
1274 return err;
1275
1276 /*
1277 * First, see if the high byte is 0x33
1278 */
1279 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1280 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1281#ifdef SN_DEBUG
1282 device_printf(dev, "test1 failed\n");
1283#endif
1284 goto error;
1285 }
1286 /*
1287 * The above MIGHT indicate a device, but I need to write to further
1288 * test this. Go to bank 0, then test that the register still
1289 * reports the high byte is 0x33.
1290 */
1291 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000);
1292 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1293 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1294#ifdef SN_DEBUG
1295 device_printf(dev, "test2 failed\n");
1296#endif
1297 goto error;
1298 }
1299 /*
1300 * well, we've already written once, so hopefully another time won't
1301 * hurt. This time, I need to switch the bank register to bank 1, so
1302 * I can access the base address register. The contents of the
1303 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected
1304 * to match the I/O port address where the adapter is being probed.
1305 */
1306 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001);
1307 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0;
1308
1309 if (rman_get_start(sc->port_res) != base_address_register) {
1310
1311 /*
1312 * Well, the base address register didn't match. Must not
1313 * have been a SMC chip after all.
1314 */
1315#ifdef SN_DEBUG
1316 device_printf(dev, "test3 failed ioaddr = 0x%x, "
1317 "base_address_register = 0x%x\n",
1318 rman_get_start(sc->port_res), base_address_register);
1319#endif
1320 goto error;
1321 }
1322
1323 /*
1324 * Check if the revision register is something that I recognize.
1325 * These might need to be added to later, as future revisions could
1326 * be added.
1327 */
1328 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3);
1329 revision_register = CSR_READ_2(sc, REVISION_REG_W);
1330 if (!chip_ids[(revision_register >> 4) & 0xF]) {
1331
1332 /*
1333 * I don't regonize this chip, so...
1334 */
1335#ifdef SN_DEBUG
1336 device_printf(dev, "test4 failed\n");
1337#endif
1338 goto error;
1339 }
1340
1341 /*
1342 * at this point I'll assume that the chip is an SMC9xxx. It might be
1343 * prudent to check a listing of MAC addresses against the hardware
1344 * address, or do some other tests.
1345 */
1346 sn_deactivate(dev);
1347 return 0;
1348 error:
1349 sn_deactivate(dev);
1350 return ENXIO;
1351}
1352
1353#define MCFSZ 8
1354
1355static void
1356sn_setmcast(struct sn_softc *sc)
1357{
1358 struct ifnet *ifp = sc->ifp;
1359 int flags;
1360 uint8_t mcf[MCFSZ];
1361
1362 SN_ASSERT_LOCKED(sc);
1363
1364 /*
1365 * Set the receiver filter. We want receive enabled and auto strip
1366 * of CRC from received packet. If we are promiscuous then set that
1367 * bit too.
1368 */
1369 flags = RCR_ENABLE | RCR_STRIP_CRC;
1370
1371 if (ifp->if_flags & IFF_PROMISC) {
1372 flags |= RCR_PROMISC | RCR_ALMUL;
1373 } else if (ifp->if_flags & IFF_ALLMULTI) {
1374 flags |= RCR_ALMUL;
1375 } else {
1376 if (sn_getmcf(ifp, mcf)) {
1377 /* set filter */
1378 SMC_SELECT_BANK(sc, 3);
1379 CSR_WRITE_2(sc, MULTICAST1_REG_W,
1380 ((uint16_t)mcf[1] << 8) | mcf[0]);
1381 CSR_WRITE_2(sc, MULTICAST2_REG_W,
1382 ((uint16_t)mcf[3] << 8) | mcf[2]);
1383 CSR_WRITE_2(sc, MULTICAST3_REG_W,
1384 ((uint16_t)mcf[5] << 8) | mcf[4]);
1385 CSR_WRITE_2(sc, MULTICAST4_REG_W,
1386 ((uint16_t)mcf[7] << 8) | mcf[6]);
1387 } else {
1388 flags |= RCR_ALMUL;
1389 }
1390 }
1391 SMC_SELECT_BANK(sc, 0);
1392 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags);
1393}
1394
1395static int
1396sn_getmcf(struct ifnet *ifp, uint8_t *mcf)
1397{
1398 int i;
1399 uint32_t index, index2;
1400 uint8_t *af = mcf;
1401 struct ifmultiaddr *ifma;
1402
1403 bzero(mcf, MCFSZ);
1404
1405 if_maddr_rlock(ifp);
1406 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1407 if (ifma->ifma_addr->sa_family != AF_LINK) {
1408 if_maddr_runlock(ifp);
1409 return 0;
1410 }
1411 index = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1412 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f;
1413 index2 = 0;
1414 for (i = 0; i < 6; i++) {
1415 index2 <<= 1;
1416 index2 |= (index & 0x01);
1417 index >>= 1;
1418 }
1419 af[index2 >> 3] |= 1 << (index2 & 7);
1420 }
1421 if_maddr_runlock(ifp);
1422 return 1; /* use multicast filter */
1423}
| 1214}
1215
1216
1217int
1218sn_activate(device_t dev)
1219{
1220 struct sn_softc *sc = device_get_softc(dev);
1221
1222 sc->port_rid = 0;
1223 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid,
1224 0, ~0, SMC_IO_EXTENT, RF_ACTIVE);
1225 if (!sc->port_res) {
1226 if (bootverbose)
1227 device_printf(dev, "Cannot allocate ioport\n");
1228 return ENOMEM;
1229 }
1230
1231 sc->irq_rid = 0;
1232 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
1233 RF_ACTIVE);
1234 if (!sc->irq_res) {
1235 if (bootverbose)
1236 device_printf(dev, "Cannot allocate irq\n");
1237 sn_deactivate(dev);
1238 return ENOMEM;
1239 }
1240 return (0);
1241}
1242
1243void
1244sn_deactivate(device_t dev)
1245{
1246 struct sn_softc *sc = device_get_softc(dev);
1247
1248 if (sc->intrhand)
1249 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1250 sc->intrhand = 0;
1251 if (sc->port_res)
1252 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
1253 sc->port_res);
1254 sc->port_res = 0;
1255 if (sc->modem_res)
1256 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid,
1257 sc->modem_res);
1258 sc->modem_res = 0;
1259 if (sc->irq_res)
1260 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
1261 sc->irq_res);
1262 sc->irq_res = 0;
1263 return;
1264}
1265
1266/*
1267 * Function: sn_probe(device_t dev)
1268 *
1269 * Purpose:
1270 * Tests to see if a given ioaddr points to an SMC9xxx chip.
1271 * Tries to cause as little damage as possible if it's not a SMC chip.
1272 * Returns a 0 on success
1273 *
1274 * Algorithm:
1275 * (1) see if the high byte of BANK_SELECT is 0x33
1276 * (2) compare the ioaddr with the base register's address
1277 * (3) see if I recognize the chip ID in the appropriate register
1278 *
1279 *
1280 */
1281int
1282sn_probe(device_t dev)
1283{
1284 struct sn_softc *sc = device_get_softc(dev);
1285 uint16_t bank;
1286 uint16_t revision_register;
1287 uint16_t base_address_register;
1288 int err;
1289
1290 if ((err = sn_activate(dev)) != 0)
1291 return err;
1292
1293 /*
1294 * First, see if the high byte is 0x33
1295 */
1296 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1297 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1298#ifdef SN_DEBUG
1299 device_printf(dev, "test1 failed\n");
1300#endif
1301 goto error;
1302 }
1303 /*
1304 * The above MIGHT indicate a device, but I need to write to further
1305 * test this. Go to bank 0, then test that the register still
1306 * reports the high byte is 0x33.
1307 */
1308 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000);
1309 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1310 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1311#ifdef SN_DEBUG
1312 device_printf(dev, "test2 failed\n");
1313#endif
1314 goto error;
1315 }
1316 /*
1317 * well, we've already written once, so hopefully another time won't
1318 * hurt. This time, I need to switch the bank register to bank 1, so
1319 * I can access the base address register. The contents of the
1320 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected
1321 * to match the I/O port address where the adapter is being probed.
1322 */
1323 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001);
1324 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0;
1325
1326 if (rman_get_start(sc->port_res) != base_address_register) {
1327
1328 /*
1329 * Well, the base address register didn't match. Must not
1330 * have been a SMC chip after all.
1331 */
1332#ifdef SN_DEBUG
1333 device_printf(dev, "test3 failed ioaddr = 0x%x, "
1334 "base_address_register = 0x%x\n",
1335 rman_get_start(sc->port_res), base_address_register);
1336#endif
1337 goto error;
1338 }
1339
1340 /*
1341 * Check if the revision register is something that I recognize.
1342 * These might need to be added to later, as future revisions could
1343 * be added.
1344 */
1345 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3);
1346 revision_register = CSR_READ_2(sc, REVISION_REG_W);
1347 if (!chip_ids[(revision_register >> 4) & 0xF]) {
1348
1349 /*
1350 * I don't regonize this chip, so...
1351 */
1352#ifdef SN_DEBUG
1353 device_printf(dev, "test4 failed\n");
1354#endif
1355 goto error;
1356 }
1357
1358 /*
1359 * at this point I'll assume that the chip is an SMC9xxx. It might be
1360 * prudent to check a listing of MAC addresses against the hardware
1361 * address, or do some other tests.
1362 */
1363 sn_deactivate(dev);
1364 return 0;
1365 error:
1366 sn_deactivate(dev);
1367 return ENXIO;
1368}
1369
1370#define MCFSZ 8
1371
1372static void
1373sn_setmcast(struct sn_softc *sc)
1374{
1375 struct ifnet *ifp = sc->ifp;
1376 int flags;
1377 uint8_t mcf[MCFSZ];
1378
1379 SN_ASSERT_LOCKED(sc);
1380
1381 /*
1382 * Set the receiver filter. We want receive enabled and auto strip
1383 * of CRC from received packet. If we are promiscuous then set that
1384 * bit too.
1385 */
1386 flags = RCR_ENABLE | RCR_STRIP_CRC;
1387
1388 if (ifp->if_flags & IFF_PROMISC) {
1389 flags |= RCR_PROMISC | RCR_ALMUL;
1390 } else if (ifp->if_flags & IFF_ALLMULTI) {
1391 flags |= RCR_ALMUL;
1392 } else {
1393 if (sn_getmcf(ifp, mcf)) {
1394 /* set filter */
1395 SMC_SELECT_BANK(sc, 3);
1396 CSR_WRITE_2(sc, MULTICAST1_REG_W,
1397 ((uint16_t)mcf[1] << 8) | mcf[0]);
1398 CSR_WRITE_2(sc, MULTICAST2_REG_W,
1399 ((uint16_t)mcf[3] << 8) | mcf[2]);
1400 CSR_WRITE_2(sc, MULTICAST3_REG_W,
1401 ((uint16_t)mcf[5] << 8) | mcf[4]);
1402 CSR_WRITE_2(sc, MULTICAST4_REG_W,
1403 ((uint16_t)mcf[7] << 8) | mcf[6]);
1404 } else {
1405 flags |= RCR_ALMUL;
1406 }
1407 }
1408 SMC_SELECT_BANK(sc, 0);
1409 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags);
1410}
1411
1412static int
1413sn_getmcf(struct ifnet *ifp, uint8_t *mcf)
1414{
1415 int i;
1416 uint32_t index, index2;
1417 uint8_t *af = mcf;
1418 struct ifmultiaddr *ifma;
1419
1420 bzero(mcf, MCFSZ);
1421
1422 if_maddr_rlock(ifp);
1423 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1424 if (ifma->ifma_addr->sa_family != AF_LINK) {
1425 if_maddr_runlock(ifp);
1426 return 0;
1427 }
1428 index = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1429 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f;
1430 index2 = 0;
1431 for (i = 0; i < 6; i++) {
1432 index2 <<= 1;
1433 index2 |= (index & 0x01);
1434 index >>= 1;
1435 }
1436 af[index2 >> 3] |= 1 << (index2 & 7);
1437 }
1438 if_maddr_runlock(ifp);
1439 return 1; /* use multicast filter */
1440}
|