238 SN_LOCK_DESTROY(sc);
239 return 0;
240}
241
242static void
243sninit(void *xsc)
244{
245 struct sn_softc *sc = xsc;
246 SN_LOCK(sc);
247 sninit_locked(sc);
248 SN_UNLOCK(sc);
249}
250
251/*
252 * Reset and initialize the chip
253 */
254static void
255sninit_locked(void *xsc)
256{
257 struct sn_softc *sc = xsc;
258 struct ifnet *ifp = sc->ifp;
259 int flags;
260 int mask;
261
262 SN_ASSERT_LOCKED(sc);
263
264 /*
265 * This resets the registers mostly to defaults, but doesn't affect
266 * EEPROM. After the reset cycle, we pause briefly for the chip to
267 * be happy.
268 */
269 SMC_SELECT_BANK(sc, 0);
270 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
271 SMC_DELAY(sc);
272 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
273 SMC_DELAY(sc);
274 SMC_DELAY(sc);
275
276 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
277
278 /*
279 * Set the control register to automatically release succesfully
280 * transmitted packets (making the best use out of our limited
281 * memory) and to enable the EPH interrupt on certain TX errors.
282 */
283 SMC_SELECT_BANK(sc, 1);
284 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
285 CTR_CR_ENABLE | CTR_LE_ENABLE));
286
287 /* Set squelch level to 240mV (default 480mV) */
288 flags = CSR_READ_2(sc, CONFIG_REG_W);
289 flags |= CR_SET_SQLCH;
290 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
291
292 /*
293 * Reset the MMU and wait for it to be un-busy.
294 */
295 SMC_SELECT_BANK(sc, 2);
296 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
297 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
298 ;
299
300 /*
301 * Disable all interrupts
302 */
303 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
304
305 sn_setmcast(sc);
306
307 /*
308 * Set the transmitter control. We want it enabled.
309 */
310 flags = TCR_ENABLE;
311
312#ifndef SW_PAD
313 /*
314 * I (GB) have been unlucky getting this to work.
315 */
316 flags |= TCR_PAD_ENABLE;
317#endif /* SW_PAD */
318
319 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
320
321
322 /*
323 * Now, enable interrupts
324 */
325 SMC_SELECT_BANK(sc, 2);
326
327 mask = IM_EPH_INT |
328 IM_RX_OVRN_INT |
329 IM_RCV_INT |
330 IM_TX_INT;
331
332 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
333 sc->intr_mask = mask;
334 sc->pages_wanted = -1;
335
336
337 /*
338 * Mark the interface running but not active.
339 */
340 ifp->if_drv_flags |= IFF_DRV_RUNNING;
341 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
342
343 /*
344 * Attempt to push out any waiting packets.
345 */
346 snstart_locked(ifp);
347}
348
349static void
350snstart(struct ifnet *ifp)
351{
352 struct sn_softc *sc = ifp->if_softc;
353 SN_LOCK(sc);
354 snstart_locked(ifp);
355 SN_UNLOCK(sc);
356}
357
358
359static void
360snstart_locked(struct ifnet *ifp)
361{
362 struct sn_softc *sc = ifp->if_softc;
363 u_int len;
364 struct mbuf *m;
365 struct mbuf *top;
366 int pad;
367 int mask;
368 uint16_t length;
369 uint16_t numPages;
370 uint8_t packet_no;
371 int time_out;
372 int junk = 0;
373
374 SN_ASSERT_LOCKED(sc);
375
376 if (sc->ifp->if_drv_flags & IFF_DRV_OACTIVE)
377 return;
378 if (sc->pages_wanted != -1) {
379 if_printf(ifp, "snstart() while memory allocation pending\n");
380 return;
381 }
382startagain:
383
384 /*
385 * Sneak a peek at the next packet
386 */
387 m = sc->ifp->if_snd.ifq_head;
388 if (m == 0)
389 return;
390 /*
391 * Compute the frame length and set pad to give an overall even
392 * number of bytes. Below we assume that the packet length is even.
393 */
394 for (len = 0, top = m; m; m = m->m_next)
395 len += m->m_len;
396
397 pad = (len & 1);
398
399 /*
400 * We drop packets that are too large. Perhaps we should truncate
401 * them instead?
402 */
403 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
404 if_printf(ifp, "large packet discarded (A)\n");
405 ++sc->ifp->if_oerrors;
406 IF_DEQUEUE(&sc->ifp->if_snd, m);
407 m_freem(m);
408 goto readcheck;
409 }
410#ifdef SW_PAD
411
412 /*
413 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
414 */
415 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
416 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
417
418#endif /* SW_PAD */
419
420 length = pad + len;
421
422 /*
423 * The MMU wants the number of pages to be the number of 256 byte
424 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
425 * include space for the status word, byte count and control bytes in
426 * the allocation request.
427 */
428 numPages = (length + 6) >> 8;
429
430
431 /*
432 * Now, try to allocate the memory
433 */
434 SMC_SELECT_BANK(sc, 2);
435 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
436
437 /*
438 * Wait a short amount of time to see if the allocation request
439 * completes. Otherwise, I enable the interrupt and wait for
440 * completion asyncronously.
441 */
442
443 time_out = MEMORY_WAIT_TIME;
444 do {
445 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT)
446 break;
447 } while (--time_out);
448
449 if (!time_out || junk > 10) {
450
451 /*
452 * No memory now. Oh well, wait until the chip finds memory
453 * later. Remember how many pages we were asking for and
454 * enable the allocation completion interrupt. Also set a
455 * watchdog in case we miss the interrupt. We mark the
456 * interface active since there is no point in attempting an
457 * snstart() until after the memory is available.
458 */
459 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT;
460 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
461 sc->intr_mask = mask;
462
463 sc->ifp->if_timer = 1;
464 sc->ifp->if_drv_flags |= IFF_DRV_OACTIVE;
465 sc->pages_wanted = numPages;
466 return;
467 }
468 /*
469 * The memory allocation completed. Check the results.
470 */
471 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
472 if (packet_no & ARR_FAILED) {
473 if (junk++ > 10)
474 if_printf(ifp, "Memory allocation failed\n");
475 goto startagain;
476 }
477 /*
478 * We have a packet number, so tell the card to use it.
479 */
480 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
481
482 /*
483 * Point to the beginning of the packet
484 */
485 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
486
487 /*
488 * Send the packet length (+6 for status, length and control byte)
489 * and the status word (set to zeros)
490 */
491 CSR_WRITE_2(sc, DATA_REG_W, 0);
492 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
493 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
494
495 /*
496 * Get the packet from the kernel. This will include the Ethernet
497 * frame header, MAC Addresses etc.
498 */
499 IF_DEQUEUE(&sc->ifp->if_snd, m);
500
501 /*
502 * Push out the data to the card.
503 */
504 for (top = m; m != 0; m = m->m_next) {
505
506 /*
507 * Push out words.
508 */
509 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
510 m->m_len / 2);
511
512 /*
513 * Push out remaining byte.
514 */
515 if (m->m_len & 1)
516 CSR_WRITE_1(sc, DATA_REG_B,
517 *(mtod(m, caddr_t) + m->m_len - 1));
518 }
519
520 /*
521 * Push out padding.
522 */
523 while (pad > 1) {
524 CSR_WRITE_2(sc, DATA_REG_W, 0);
525 pad -= 2;
526 }
527 if (pad)
528 CSR_WRITE_1(sc, DATA_REG_B, 0);
529
530 /*
531 * Push out control byte and unused packet byte The control byte is 0
532 * meaning the packet is even lengthed and no special CRC handling is
533 * desired.
534 */
535 CSR_WRITE_2(sc, DATA_REG_W, 0);
536
537 /*
538 * Enable the interrupts and let the chipset deal with it Also set a
539 * watchdog in case we miss the interrupt.
540 */
541 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
542 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
543 sc->intr_mask = mask;
544
545 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
546
547 sc->ifp->if_drv_flags |= IFF_DRV_OACTIVE;
548 sc->ifp->if_timer = 1;
549
550 BPF_MTAP(ifp, top);
551
552 sc->ifp->if_opackets++;
553 m_freem(top);
554
555
556readcheck:
557
558 /*
559 * Is another packet coming in? We don't want to overflow the tiny
560 * RX FIFO. If nothing has arrived then attempt to queue another
561 * transmit packet.
562 */
563 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY)
564 goto startagain;
565 return;
566}
567
568
569
570/* Resume a packet transmit operation after a memory allocation
571 * has completed.
572 *
573 * This is basically a hacked up copy of snstart() which handles
574 * a completed memory allocation the same way snstart() does.
575 * It then passes control to snstart to handle any other queued
576 * packets.
577 */
578static void
579snresume(struct ifnet *ifp)
580{
581 struct sn_softc *sc = ifp->if_softc;
582 u_int len;
583 struct mbuf *m;
584 struct mbuf *top;
585 int pad;
586 int mask;
587 uint16_t length;
588 uint16_t numPages;
589 uint16_t pages_wanted;
590 uint8_t packet_no;
591
592 if (sc->pages_wanted < 0)
593 return;
594
595 pages_wanted = sc->pages_wanted;
596 sc->pages_wanted = -1;
597
598 /*
599 * Sneak a peek at the next packet
600 */
601 m = sc->ifp->if_snd.ifq_head;
602 if (m == 0) {
603 if_printf(ifp, "snresume() with nothing to send\n");
604 return;
605 }
606 /*
607 * Compute the frame length and set pad to give an overall even
608 * number of bytes. Below we assume that the packet length is even.
609 */
610 for (len = 0, top = m; m; m = m->m_next)
611 len += m->m_len;
612
613 pad = (len & 1);
614
615 /*
616 * We drop packets that are too large. Perhaps we should truncate
617 * them instead?
618 */
619 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
620 if_printf(ifp, "large packet discarded (B)\n");
621 ++sc->ifp->if_oerrors;
622 IF_DEQUEUE(&sc->ifp->if_snd, m);
623 m_freem(m);
624 return;
625 }
626#ifdef SW_PAD
627
628 /*
629 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
630 */
631 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
632 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
633
634#endif /* SW_PAD */
635
636 length = pad + len;
637
638
639 /*
640 * The MMU wants the number of pages to be the number of 256 byte
641 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
642 * include space for the status word, byte count and control bytes in
643 * the allocation request.
644 */
645 numPages = (length + 6) >> 8;
646
647
648 SMC_SELECT_BANK(sc, 2);
649
650 /*
651 * The memory allocation completed. Check the results. If it failed,
652 * we simply set a watchdog timer and hope for the best.
653 */
654 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
655 if (packet_no & ARR_FAILED) {
656 if_printf(ifp, "Memory allocation failed. Weird.\n");
657 sc->ifp->if_timer = 1;
658 goto try_start;
659 }
660 /*
661 * We have a packet number, so tell the card to use it.
662 */
663 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
664
665 /*
666 * Now, numPages should match the pages_wanted recorded when the
667 * memory allocation was initiated.
668 */
669 if (pages_wanted != numPages) {
670 if_printf(ifp, "memory allocation wrong size. Weird.\n");
671 /*
672 * If the allocation was the wrong size we simply release the
673 * memory once it is granted. Wait for the MMU to be un-busy.
674 */
675 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
676 ;
677 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
678
679 return;
680 }
681 /*
682 * Point to the beginning of the packet
683 */
684 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
685
686 /*
687 * Send the packet length (+6 for status, length and control byte)
688 * and the status word (set to zeros)
689 */
690 CSR_WRITE_2(sc, DATA_REG_W, 0);
691 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
692 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
693
694 /*
695 * Get the packet from the kernel. This will include the Ethernet
696 * frame header, MAC Addresses etc.
697 */
698 IF_DEQUEUE(&sc->ifp->if_snd, m);
699
700 /*
701 * Push out the data to the card.
702 */
703 for (top = m; m != 0; m = m->m_next) {
704
705 /*
706 * Push out words.
707 */
708 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
709 m->m_len / 2);
710 /*
711 * Push out remaining byte.
712 */
713 if (m->m_len & 1)
714 CSR_WRITE_1(sc, DATA_REG_B,
715 *(mtod(m, caddr_t) + m->m_len - 1));
716 }
717
718 /*
719 * Push out padding.
720 */
721 while (pad > 1) {
722 CSR_WRITE_2(sc, DATA_REG_W, 0);
723 pad -= 2;
724 }
725 if (pad)
726 CSR_WRITE_1(sc, DATA_REG_B, 0);
727
728 /*
729 * Push out control byte and unused packet byte The control byte is 0
730 * meaning the packet is even lengthed and no special CRC handling is
731 * desired.
732 */
733 CSR_WRITE_2(sc, DATA_REG_W, 0);
734
735 /*
736 * Enable the interrupts and let the chipset deal with it Also set a
737 * watchdog in case we miss the interrupt.
738 */
739 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
740 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
741 sc->intr_mask = mask;
742 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
743
744 BPF_MTAP(ifp, top);
745
746 sc->ifp->if_opackets++;
747 m_freem(top);
748
749try_start:
750
751 /*
752 * Now pass control to snstart() to queue any additional packets
753 */
754 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
755 snstart(ifp);
756
757 /*
758 * We've sent something, so we're active. Set a watchdog in case the
759 * TX_EMPTY interrupt is lost.
760 */
761 sc->ifp->if_drv_flags |= IFF_DRV_OACTIVE;
762 sc->ifp->if_timer = 1;
763
764 return;
765}
766
767
768void
769sn_intr(void *arg)
770{
771 int status, interrupts;
772 struct sn_softc *sc = (struct sn_softc *) arg;
773 struct ifnet *ifp = sc->ifp;
774
775 /*
776 * Chip state registers
777 */
778 uint8_t mask;
779 uint8_t packet_no;
780 uint16_t tx_status;
781 uint16_t card_stats;
782
783 SN_LOCK(sc);
784
785 /*
786 * Clear the watchdog.
787 */
788 ifp->if_timer = 0;
789
790 SMC_SELECT_BANK(sc, 2);
791
792 /*
793 * Obtain the current interrupt mask and clear the hardware mask
794 * while servicing interrupts.
795 */
796 mask = CSR_READ_1(sc, INTR_MASK_REG_B);
797 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
798
799 /*
800 * Get the set of interrupts which occurred and eliminate any which
801 * are masked.
802 */
803 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B);
804 status = interrupts & mask;
805
806 /*
807 * Now, process each of the interrupt types.
808 */
809
810 /*
811 * Receive Overrun.
812 */
813 if (status & IM_RX_OVRN_INT) {
814 /*
815 * Acknowlege Interrupt
816 */
817 SMC_SELECT_BANK(sc, 2);
818 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT);
819
820 ++sc->ifp->if_ierrors;
821 }
822 /*
823 * Got a packet.
824 */
825 if (status & IM_RCV_INT) {
826 int packet_number;
827
828 SMC_SELECT_BANK(sc, 2);
829 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
830
831 if (packet_number & FIFO_REMPTY) {
832 /*
833 * we got called , but nothing was on the FIFO
834 */
835 printf("sn: Receive interrupt with nothing on FIFO\n");
836 goto out;
837 }
838 snread(ifp);
839 }
840 /*
841 * An on-card memory allocation came through.
842 */
843 if (status & IM_ALLOC_INT) {
844 /*
845 * Disable this interrupt.
846 */
847 mask &= ~IM_ALLOC_INT;
848 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
849 snresume(sc->ifp);
850 }
851 /*
852 * TX Completion. Handle a transmit error message. This will only be
853 * called when there is an error, because of the AUTO_RELEASE mode.
854 */
855 if (status & IM_TX_INT) {
856 /*
857 * Acknowlege Interrupt
858 */
859 SMC_SELECT_BANK(sc, 2);
860 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT);
861
862 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W);
863 packet_no &= FIFO_TX_MASK;
864
865 /*
866 * select this as the packet to read from
867 */
868 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
869
870 /*
871 * Position the pointer to the first word from this packet
872 */
873 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
874
875 /*
876 * Fetch the TX status word. The value found here will be a
877 * copy of the EPH_STATUS_REG_W at the time the transmit
878 * failed.
879 */
880 tx_status = CSR_READ_2(sc, DATA_REG_W);
881
882 if (tx_status & EPHSR_TX_SUC) {
883 device_printf(sc->dev,
884 "Successful packet caused interrupt\n");
885 } else {
886 ++sc->ifp->if_oerrors;
887 }
888
889 if (tx_status & EPHSR_LATCOL)
890 ++sc->ifp->if_collisions;
891
892 /*
893 * Some of these errors will have disabled transmit.
894 * Re-enable transmit now.
895 */
896 SMC_SELECT_BANK(sc, 0);
897
898#ifdef SW_PAD
899 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE);
900#else
901 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
902#endif /* SW_PAD */
903
904 /*
905 * kill the failed packet. Wait for the MMU to be un-busy.
906 */
907 SMC_SELECT_BANK(sc, 2);
908 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
909 ;
910 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
911
912 /*
913 * Attempt to queue more transmits.
914 */
915 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
916 snstart_locked(sc->ifp);
917 }
918 /*
919 * Transmit underrun. We use this opportunity to update transmit
920 * statistics from the card.
921 */
922 if (status & IM_TX_EMPTY_INT) {
923
924 /*
925 * Acknowlege Interrupt
926 */
927 SMC_SELECT_BANK(sc, 2);
928 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT);
929
930 /*
931 * Disable this interrupt.
932 */
933 mask &= ~IM_TX_EMPTY_INT;
934
935 SMC_SELECT_BANK(sc, 0);
936 card_stats = CSR_READ_2(sc, COUNTER_REG_W);
937
938 /*
939 * Single collisions
940 */
941 sc->ifp->if_collisions += card_stats & ECR_COLN_MASK;
942
943 /*
944 * Multiple collisions
945 */
946 sc->ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4;
947
948 SMC_SELECT_BANK(sc, 2);
949
950 /*
951 * Attempt to enqueue some more stuff.
952 */
953 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
954 snstart_locked(sc->ifp);
955 }
956 /*
957 * Some other error. Try to fix it by resetting the adapter.
958 */
959 if (status & IM_EPH_INT) {
960 snstop(sc);
961 sninit_locked(sc);
962 }
963
964out:
965 /*
966 * Handled all interrupt sources.
967 */
968
969 SMC_SELECT_BANK(sc, 2);
970
971 /*
972 * Reestablish interrupts from mask which have not been deselected
973 * during this interrupt. Note that the hardware mask, which was set
974 * to 0x00 at the start of this service routine, may have been
975 * updated by one or more of the interrupt handers and we must let
976 * those new interrupts stay enabled here.
977 */
978 mask |= CSR_READ_1(sc, INTR_MASK_REG_B);
979 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
980 sc->intr_mask = mask;
981 SN_UNLOCK(sc);
982}
983
984static void
985snread(struct ifnet *ifp)
986{
987 struct sn_softc *sc = ifp->if_softc;
988 struct ether_header *eh;
989 struct mbuf *m;
990 short status;
991 int packet_number;
992 uint16_t packet_length;
993 uint8_t *data;
994
995 SMC_SELECT_BANK(sc, 2);
996#if 0
997 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
998
999 if (packet_number & FIFO_REMPTY) {
1000
1001 /*
1002 * we got called , but nothing was on the FIFO
1003 */
1004 printf("sn: Receive interrupt with nothing on FIFO\n");
1005 return;
1006 }
1007#endif
1008read_another:
1009
1010 /*
1011 * Start reading from the start of the packet. Since PTR_RCV is set,
1012 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK.
1013 */
1014 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
1015
1016 /*
1017 * First two words are status and packet_length
1018 */
1019 status = CSR_READ_2(sc, DATA_REG_W);
1020 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK;
1021
1022 /*
1023 * The packet length contains 3 extra words: status, length, and a
1024 * extra word with the control byte.
1025 */
1026 packet_length -= 6;
1027
1028 /*
1029 * Account for receive errors and discard.
1030 */
1031 if (status & RS_ERRORS) {
1032 ++sc->ifp->if_ierrors;
1033 goto out;
1034 }
1035 /*
1036 * A packet is received.
1037 */
1038
1039 /*
1040 * Adjust for odd-length packet.
1041 */
1042 if (status & RS_ODDFRAME)
1043 packet_length++;
1044
1045 /*
1046 * Allocate a header mbuf from the kernel.
1047 */
1048 MGETHDR(m, M_DONTWAIT, MT_DATA);
1049 if (m == NULL)
1050 goto out;
1051
1052 m->m_pkthdr.rcvif = sc->ifp;
1053 m->m_pkthdr.len = m->m_len = packet_length;
1054
1055 /*
1056 * Attach an mbuf cluster
1057 */
1058 MCLGET(m, M_DONTWAIT);
1059
1060 /*
1061 * Insist on getting a cluster
1062 */
1063 if ((m->m_flags & M_EXT) == 0) {
1064 m_freem(m);
1065 ++sc->ifp->if_ierrors;
1066 printf("sn: snread() kernel memory allocation problem\n");
1067 goto out;
1068 }
1069 eh = mtod(m, struct ether_header *);
1070
1071 /*
1072 * Get packet, including link layer address, from interface.
1073 */
1074 data = (uint8_t *) eh;
1075 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1);
1076 if (packet_length & 1) {
1077 data += packet_length & ~1;
1078 *data = CSR_READ_1(sc, DATA_REG_B);
1079 }
1080 ++sc->ifp->if_ipackets;
1081
1082 /*
1083 * Remove link layer addresses and whatnot.
1084 */
1085 m->m_pkthdr.len = m->m_len = packet_length;
1086
1087 /*
1088 * Drop locks before calling if_input() since it may re-enter
1089 * snstart() in the netisr case. This would result in a
1090 * lock reversal. Better performance might be obtained by
1091 * chaining all packets received, dropping the lock, and then
1092 * calling if_input() on each one.
1093 */
1094 SN_UNLOCK(sc);
1095 (*ifp->if_input)(ifp, m);
1096 SN_LOCK(sc);
1097
1098out:
1099
1100 /*
1101 * Error or good, tell the card to get rid of this packet Wait for
1102 * the MMU to be un-busy.
1103 */
1104 SMC_SELECT_BANK(sc, 2);
1105 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
1106 ;
1107 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE);
1108
1109 /*
1110 * Check whether another packet is ready
1111 */
1112 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1113 if (packet_number & FIFO_REMPTY) {
1114 return;
1115 }
1116 goto read_another;
1117}
1118
1119
1120/*
1121 * Handle IOCTLS. This function is completely stolen from if_ep.c
1122 * As with its progenitor, it does not handle hardware address
1123 * changes.
1124 */
1125static int
1126snioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1127{
1128 struct sn_softc *sc = ifp->if_softc;
1129 int error = 0;
1130
1131 switch (cmd) {
1132 case SIOCSIFFLAGS:
1133 SN_LOCK(sc);
1134 if ((ifp->if_flags & IFF_UP) == 0 &&
1135 ifp->if_drv_flags & IFF_DRV_RUNNING) {
1136 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1137 snstop(sc);
1138 } else {
1139 /* reinitialize card on any parameter change */
1140 sninit_locked(sc);
1141 }
1142 SN_UNLOCK(sc);
1143 break;
1144
1145#ifdef notdef
1146 case SIOCGHWADDR:
1147 bcopy((caddr_t) sc->sc_addr, (caddr_t) & ifr->ifr_data,
1148 sizeof(sc->sc_addr));
1149 break;
1150#endif
1151
1152 case SIOCADDMULTI:
1153 /* update multicast filter list. */
1154 SN_LOCK(sc);
1155 sn_setmcast(sc);
1156 error = 0;
1157 SN_UNLOCK(sc);
1158 break;
1159 case SIOCDELMULTI:
1160 /* update multicast filter list. */
1161 SN_LOCK(sc);
1162 sn_setmcast(sc);
1163 error = 0;
1164 SN_UNLOCK(sc);
1165 break;
1166 default:
1167 error = EINVAL;
1168 error = ether_ioctl(ifp, cmd, data);
1169 break;
1170 }
1171 return (error);
1172}
1173
1174static void
1175snwatchdog(struct ifnet *ifp)
1176{
1177 sn_intr(ifp->if_softc);
1178}
1179
1180
1181/* 1. zero the interrupt mask
1182 * 2. clear the enable receive flag
1183 * 3. clear the enable xmit flags
1184 */
1185static void
1186snstop(struct sn_softc *sc)
1187{
1188
1189 struct ifnet *ifp = sc->ifp;
1190
1191 /*
1192 * Clear interrupt mask; disable all interrupts.
1193 */
1194 SMC_SELECT_BANK(sc, 2);
1195 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
1196
1197 /*
1198 * Disable transmitter and Receiver
1199 */
1200 SMC_SELECT_BANK(sc, 0);
1201 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
1202 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
1203
1204 /*
1205 * Cancel watchdog.
1206 */
1207 ifp->if_timer = 0;
1208}
1209
1210
1211int
1212sn_activate(device_t dev)
1213{
1214 struct sn_softc *sc = device_get_softc(dev);
1215
1216 sc->port_rid = 0;
1217 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid,
1218 0, ~0, SMC_IO_EXTENT, RF_ACTIVE);
1219 if (!sc->port_res) {
1220 if (bootverbose)
1221 device_printf(dev, "Cannot allocate ioport\n");
1222 return ENOMEM;
1223 }
1224
1225 sc->irq_rid = 0;
1226 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
1227 RF_ACTIVE);
1228 if (!sc->irq_res) {
1229 if (bootverbose)
1230 device_printf(dev, "Cannot allocate irq\n");
1231 sn_deactivate(dev);
1232 return ENOMEM;
1233 }
1234 sc->bst = rman_get_bustag(sc->port_res);
1235 sc->bsh = rman_get_bushandle(sc->port_res);
1236 return (0);
1237}
1238
1239void
1240sn_deactivate(device_t dev)
1241{
1242 struct sn_softc *sc = device_get_softc(dev);
1243
1244 if (sc->intrhand)
1245 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1246 sc->intrhand = 0;
1247 if (sc->port_res)
1248 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
1249 sc->port_res);
1250 sc->port_res = 0;
1251 if (sc->modem_res)
1252 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid,
1253 sc->modem_res);
1254 sc->modem_res = 0;
1255 if (sc->irq_res)
1256 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
1257 sc->irq_res);
1258 sc->irq_res = 0;
1259 return;
1260}
1261
1262/*
1263 * Function: sn_probe(device_t dev)
1264 *
1265 * Purpose:
1266 * Tests to see if a given ioaddr points to an SMC9xxx chip.
1267 * Tries to cause as little damage as possible if it's not a SMC chip.
1268 * Returns a 0 on success
1269 *
1270 * Algorithm:
1271 * (1) see if the high byte of BANK_SELECT is 0x33
1272 * (2) compare the ioaddr with the base register's address
1273 * (3) see if I recognize the chip ID in the appropriate register
1274 *
1275 *
1276 */
1277int
1278sn_probe(device_t dev)
1279{
1280 struct sn_softc *sc = device_get_softc(dev);
1281 uint16_t bank;
1282 uint16_t revision_register;
1283 uint16_t base_address_register;
1284 int err;
1285
1286 if ((err = sn_activate(dev)) != 0)
1287 return err;
1288
1289 /*
1290 * First, see if the high byte is 0x33
1291 */
1292 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1293 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1294#ifdef SN_DEBUG
1295 device_printf(dev, "test1 failed\n");
1296#endif
1297 goto error;
1298 }
1299 /*
1300 * The above MIGHT indicate a device, but I need to write to further
1301 * test this. Go to bank 0, then test that the register still
1302 * reports the high byte is 0x33.
1303 */
1304 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000);
1305 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1306 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1307#ifdef SN_DEBUG
1308 device_printf(dev, "test2 failed\n");
1309#endif
1310 goto error;
1311 }
1312 /*
1313 * well, we've already written once, so hopefully another time won't
1314 * hurt. This time, I need to switch the bank register to bank 1, so
1315 * I can access the base address register. The contents of the
1316 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected
1317 * to match the I/O port address where the adapter is being probed.
1318 */
1319 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001);
1320 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0;
1321
1322 if (rman_get_start(sc->port_res) != base_address_register) {
1323
1324 /*
1325 * Well, the base address register didn't match. Must not
1326 * have been a SMC chip after all.
1327 */
1328#ifdef SN_DEBUG
1329 device_printf(dev, "test3 failed ioaddr = 0x%x, "
1330 "base_address_register = 0x%x\n",
1331 rman_get_start(sc->port_res), base_address_register);
1332#endif
1333 goto error;
1334 }
1335
1336 /*
1337 * Check if the revision register is something that I recognize.
1338 * These might need to be added to later, as future revisions could
1339 * be added.
1340 */
1341 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3);
1342 revision_register = CSR_READ_2(sc, REVISION_REG_W);
1343 if (!chip_ids[(revision_register >> 4) & 0xF]) {
1344
1345 /*
1346 * I don't regonize this chip, so...
1347 */
1348#ifdef SN_DEBUG
1349 device_printf(dev, "test4 failed\n");
1350#endif
1351 goto error;
1352 }
1353
1354 /*
1355 * at this point I'll assume that the chip is an SMC9xxx. It might be
1356 * prudent to check a listing of MAC addresses against the hardware
1357 * address, or do some other tests.
1358 */
1359 sn_deactivate(dev);
1360 return 0;
1361 error:
1362 sn_deactivate(dev);
1363 return ENXIO;
1364}
1365
1366#define MCFSZ 8
1367
1368static void
1369sn_setmcast(struct sn_softc *sc)
1370{
1371 struct ifnet *ifp = sc->ifp;
1372 int flags;
1373 uint8_t mcf[MCFSZ];
1374
1375 SN_ASSERT_LOCKED(sc);
1376
1377 /*
1378 * Set the receiver filter. We want receive enabled and auto strip
1379 * of CRC from received packet. If we are promiscuous then set that
1380 * bit too.
1381 */
1382 flags = RCR_ENABLE | RCR_STRIP_CRC;
1383
1384 if (ifp->if_flags & IFF_PROMISC) {
1385 flags |= RCR_PROMISC | RCR_ALMUL;
1386 } else if (ifp->if_flags & IFF_ALLMULTI) {
1387 flags |= RCR_ALMUL;
1388 } else {
1389 if (sn_getmcf(ifp, mcf)) {
1390 /* set filter */
1391 SMC_SELECT_BANK(sc, 3);
1392 CSR_WRITE_2(sc, MULTICAST1_REG_W,
1393 ((uint16_t)mcf[1] << 8) | mcf[0]);
1394 CSR_WRITE_2(sc, MULTICAST2_REG_W,
1395 ((uint16_t)mcf[3] << 8) | mcf[2]);
1396 CSR_WRITE_2(sc, MULTICAST3_REG_W,
1397 ((uint16_t)mcf[5] << 8) | mcf[4]);
1398 CSR_WRITE_2(sc, MULTICAST4_REG_W,
1399 ((uint16_t)mcf[7] << 8) | mcf[6]);
1400 } else {
1401 flags |= RCR_ALMUL;
1402 }
1403 }
1404 SMC_SELECT_BANK(sc, 0);
1405 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags);
1406}
1407
1408static int
1409sn_getmcf(struct ifnet *ifp, uint8_t *mcf)
1410{
1411 int i;
1412 uint32_t index, index2;
1413 uint8_t *af = mcf;
1414 struct ifmultiaddr *ifma;
1415
1416 bzero(mcf, MCFSZ);
1417
1418 IF_ADDR_LOCK(ifp);
1419 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1420 if (ifma->ifma_addr->sa_family != AF_LINK) {
1421 IF_ADDR_UNLOCK(ifp);
1422 return 0;
1423 }
1424 index = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1425 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f;
1426 index2 = 0;
1427 for (i = 0; i < 6; i++) {
1428 index2 <<= 1;
1429 index2 |= (index & 0x01);
1430 index >>= 1;
1431 }
1432 af[index2 >> 3] |= 1 << (index2 & 7);
1433 }
1434 IF_ADDR_UNLOCK(ifp);
1435 return 1; /* use multicast filter */
1436}
| 238 SN_LOCK_DESTROY(sc);
239 return 0;
240}
241
242static void
243sninit(void *xsc)
244{
245 struct sn_softc *sc = xsc;
246 SN_LOCK(sc);
247 sninit_locked(sc);
248 SN_UNLOCK(sc);
249}
250
251/*
252 * Reset and initialize the chip
253 */
254static void
255sninit_locked(void *xsc)
256{
257 struct sn_softc *sc = xsc;
258 struct ifnet *ifp = sc->ifp;
259 int flags;
260 int mask;
261
262 SN_ASSERT_LOCKED(sc);
263
264 /*
265 * This resets the registers mostly to defaults, but doesn't affect
266 * EEPROM. After the reset cycle, we pause briefly for the chip to
267 * be happy.
268 */
269 SMC_SELECT_BANK(sc, 0);
270 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
271 SMC_DELAY(sc);
272 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
273 SMC_DELAY(sc);
274 SMC_DELAY(sc);
275
276 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
277
278 /*
279 * Set the control register to automatically release succesfully
280 * transmitted packets (making the best use out of our limited
281 * memory) and to enable the EPH interrupt on certain TX errors.
282 */
283 SMC_SELECT_BANK(sc, 1);
284 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
285 CTR_CR_ENABLE | CTR_LE_ENABLE));
286
287 /* Set squelch level to 240mV (default 480mV) */
288 flags = CSR_READ_2(sc, CONFIG_REG_W);
289 flags |= CR_SET_SQLCH;
290 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
291
292 /*
293 * Reset the MMU and wait for it to be un-busy.
294 */
295 SMC_SELECT_BANK(sc, 2);
296 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
297 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
298 ;
299
300 /*
301 * Disable all interrupts
302 */
303 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
304
305 sn_setmcast(sc);
306
307 /*
308 * Set the transmitter control. We want it enabled.
309 */
310 flags = TCR_ENABLE;
311
312#ifndef SW_PAD
313 /*
314 * I (GB) have been unlucky getting this to work.
315 */
316 flags |= TCR_PAD_ENABLE;
317#endif /* SW_PAD */
318
319 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
320
321
322 /*
323 * Now, enable interrupts
324 */
325 SMC_SELECT_BANK(sc, 2);
326
327 mask = IM_EPH_INT |
328 IM_RX_OVRN_INT |
329 IM_RCV_INT |
330 IM_TX_INT;
331
332 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
333 sc->intr_mask = mask;
334 sc->pages_wanted = -1;
335
336
337 /*
338 * Mark the interface running but not active.
339 */
340 ifp->if_drv_flags |= IFF_DRV_RUNNING;
341 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
342
343 /*
344 * Attempt to push out any waiting packets.
345 */
346 snstart_locked(ifp);
347}
348
349static void
350snstart(struct ifnet *ifp)
351{
352 struct sn_softc *sc = ifp->if_softc;
353 SN_LOCK(sc);
354 snstart_locked(ifp);
355 SN_UNLOCK(sc);
356}
357
358
359static void
360snstart_locked(struct ifnet *ifp)
361{
362 struct sn_softc *sc = ifp->if_softc;
363 u_int len;
364 struct mbuf *m;
365 struct mbuf *top;
366 int pad;
367 int mask;
368 uint16_t length;
369 uint16_t numPages;
370 uint8_t packet_no;
371 int time_out;
372 int junk = 0;
373
374 SN_ASSERT_LOCKED(sc);
375
376 if (sc->ifp->if_drv_flags & IFF_DRV_OACTIVE)
377 return;
378 if (sc->pages_wanted != -1) {
379 if_printf(ifp, "snstart() while memory allocation pending\n");
380 return;
381 }
382startagain:
383
384 /*
385 * Sneak a peek at the next packet
386 */
387 m = sc->ifp->if_snd.ifq_head;
388 if (m == 0)
389 return;
390 /*
391 * Compute the frame length and set pad to give an overall even
392 * number of bytes. Below we assume that the packet length is even.
393 */
394 for (len = 0, top = m; m; m = m->m_next)
395 len += m->m_len;
396
397 pad = (len & 1);
398
399 /*
400 * We drop packets that are too large. Perhaps we should truncate
401 * them instead?
402 */
403 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
404 if_printf(ifp, "large packet discarded (A)\n");
405 ++sc->ifp->if_oerrors;
406 IF_DEQUEUE(&sc->ifp->if_snd, m);
407 m_freem(m);
408 goto readcheck;
409 }
410#ifdef SW_PAD
411
412 /*
413 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
414 */
415 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
416 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
417
418#endif /* SW_PAD */
419
420 length = pad + len;
421
422 /*
423 * The MMU wants the number of pages to be the number of 256 byte
424 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
425 * include space for the status word, byte count and control bytes in
426 * the allocation request.
427 */
428 numPages = (length + 6) >> 8;
429
430
431 /*
432 * Now, try to allocate the memory
433 */
434 SMC_SELECT_BANK(sc, 2);
435 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
436
437 /*
438 * Wait a short amount of time to see if the allocation request
439 * completes. Otherwise, I enable the interrupt and wait for
440 * completion asyncronously.
441 */
442
443 time_out = MEMORY_WAIT_TIME;
444 do {
445 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT)
446 break;
447 } while (--time_out);
448
449 if (!time_out || junk > 10) {
450
451 /*
452 * No memory now. Oh well, wait until the chip finds memory
453 * later. Remember how many pages we were asking for and
454 * enable the allocation completion interrupt. Also set a
455 * watchdog in case we miss the interrupt. We mark the
456 * interface active since there is no point in attempting an
457 * snstart() until after the memory is available.
458 */
459 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT;
460 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
461 sc->intr_mask = mask;
462
463 sc->ifp->if_timer = 1;
464 sc->ifp->if_drv_flags |= IFF_DRV_OACTIVE;
465 sc->pages_wanted = numPages;
466 return;
467 }
468 /*
469 * The memory allocation completed. Check the results.
470 */
471 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
472 if (packet_no & ARR_FAILED) {
473 if (junk++ > 10)
474 if_printf(ifp, "Memory allocation failed\n");
475 goto startagain;
476 }
477 /*
478 * We have a packet number, so tell the card to use it.
479 */
480 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
481
482 /*
483 * Point to the beginning of the packet
484 */
485 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
486
487 /*
488 * Send the packet length (+6 for status, length and control byte)
489 * and the status word (set to zeros)
490 */
491 CSR_WRITE_2(sc, DATA_REG_W, 0);
492 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
493 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
494
495 /*
496 * Get the packet from the kernel. This will include the Ethernet
497 * frame header, MAC Addresses etc.
498 */
499 IF_DEQUEUE(&sc->ifp->if_snd, m);
500
501 /*
502 * Push out the data to the card.
503 */
504 for (top = m; m != 0; m = m->m_next) {
505
506 /*
507 * Push out words.
508 */
509 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
510 m->m_len / 2);
511
512 /*
513 * Push out remaining byte.
514 */
515 if (m->m_len & 1)
516 CSR_WRITE_1(sc, DATA_REG_B,
517 *(mtod(m, caddr_t) + m->m_len - 1));
518 }
519
520 /*
521 * Push out padding.
522 */
523 while (pad > 1) {
524 CSR_WRITE_2(sc, DATA_REG_W, 0);
525 pad -= 2;
526 }
527 if (pad)
528 CSR_WRITE_1(sc, DATA_REG_B, 0);
529
530 /*
531 * Push out control byte and unused packet byte The control byte is 0
532 * meaning the packet is even lengthed and no special CRC handling is
533 * desired.
534 */
535 CSR_WRITE_2(sc, DATA_REG_W, 0);
536
537 /*
538 * Enable the interrupts and let the chipset deal with it Also set a
539 * watchdog in case we miss the interrupt.
540 */
541 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
542 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
543 sc->intr_mask = mask;
544
545 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
546
547 sc->ifp->if_drv_flags |= IFF_DRV_OACTIVE;
548 sc->ifp->if_timer = 1;
549
550 BPF_MTAP(ifp, top);
551
552 sc->ifp->if_opackets++;
553 m_freem(top);
554
555
556readcheck:
557
558 /*
559 * Is another packet coming in? We don't want to overflow the tiny
560 * RX FIFO. If nothing has arrived then attempt to queue another
561 * transmit packet.
562 */
563 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY)
564 goto startagain;
565 return;
566}
567
568
569
570/* Resume a packet transmit operation after a memory allocation
571 * has completed.
572 *
573 * This is basically a hacked up copy of snstart() which handles
574 * a completed memory allocation the same way snstart() does.
575 * It then passes control to snstart to handle any other queued
576 * packets.
577 */
578static void
579snresume(struct ifnet *ifp)
580{
581 struct sn_softc *sc = ifp->if_softc;
582 u_int len;
583 struct mbuf *m;
584 struct mbuf *top;
585 int pad;
586 int mask;
587 uint16_t length;
588 uint16_t numPages;
589 uint16_t pages_wanted;
590 uint8_t packet_no;
591
592 if (sc->pages_wanted < 0)
593 return;
594
595 pages_wanted = sc->pages_wanted;
596 sc->pages_wanted = -1;
597
598 /*
599 * Sneak a peek at the next packet
600 */
601 m = sc->ifp->if_snd.ifq_head;
602 if (m == 0) {
603 if_printf(ifp, "snresume() with nothing to send\n");
604 return;
605 }
606 /*
607 * Compute the frame length and set pad to give an overall even
608 * number of bytes. Below we assume that the packet length is even.
609 */
610 for (len = 0, top = m; m; m = m->m_next)
611 len += m->m_len;
612
613 pad = (len & 1);
614
615 /*
616 * We drop packets that are too large. Perhaps we should truncate
617 * them instead?
618 */
619 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
620 if_printf(ifp, "large packet discarded (B)\n");
621 ++sc->ifp->if_oerrors;
622 IF_DEQUEUE(&sc->ifp->if_snd, m);
623 m_freem(m);
624 return;
625 }
626#ifdef SW_PAD
627
628 /*
629 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
630 */
631 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
632 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
633
634#endif /* SW_PAD */
635
636 length = pad + len;
637
638
639 /*
640 * The MMU wants the number of pages to be the number of 256 byte
641 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
642 * include space for the status word, byte count and control bytes in
643 * the allocation request.
644 */
645 numPages = (length + 6) >> 8;
646
647
648 SMC_SELECT_BANK(sc, 2);
649
650 /*
651 * The memory allocation completed. Check the results. If it failed,
652 * we simply set a watchdog timer and hope for the best.
653 */
654 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
655 if (packet_no & ARR_FAILED) {
656 if_printf(ifp, "Memory allocation failed. Weird.\n");
657 sc->ifp->if_timer = 1;
658 goto try_start;
659 }
660 /*
661 * We have a packet number, so tell the card to use it.
662 */
663 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
664
665 /*
666 * Now, numPages should match the pages_wanted recorded when the
667 * memory allocation was initiated.
668 */
669 if (pages_wanted != numPages) {
670 if_printf(ifp, "memory allocation wrong size. Weird.\n");
671 /*
672 * If the allocation was the wrong size we simply release the
673 * memory once it is granted. Wait for the MMU to be un-busy.
674 */
675 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
676 ;
677 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
678
679 return;
680 }
681 /*
682 * Point to the beginning of the packet
683 */
684 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
685
686 /*
687 * Send the packet length (+6 for status, length and control byte)
688 * and the status word (set to zeros)
689 */
690 CSR_WRITE_2(sc, DATA_REG_W, 0);
691 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
692 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
693
694 /*
695 * Get the packet from the kernel. This will include the Ethernet
696 * frame header, MAC Addresses etc.
697 */
698 IF_DEQUEUE(&sc->ifp->if_snd, m);
699
700 /*
701 * Push out the data to the card.
702 */
703 for (top = m; m != 0; m = m->m_next) {
704
705 /*
706 * Push out words.
707 */
708 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
709 m->m_len / 2);
710 /*
711 * Push out remaining byte.
712 */
713 if (m->m_len & 1)
714 CSR_WRITE_1(sc, DATA_REG_B,
715 *(mtod(m, caddr_t) + m->m_len - 1));
716 }
717
718 /*
719 * Push out padding.
720 */
721 while (pad > 1) {
722 CSR_WRITE_2(sc, DATA_REG_W, 0);
723 pad -= 2;
724 }
725 if (pad)
726 CSR_WRITE_1(sc, DATA_REG_B, 0);
727
728 /*
729 * Push out control byte and unused packet byte The control byte is 0
730 * meaning the packet is even lengthed and no special CRC handling is
731 * desired.
732 */
733 CSR_WRITE_2(sc, DATA_REG_W, 0);
734
735 /*
736 * Enable the interrupts and let the chipset deal with it Also set a
737 * watchdog in case we miss the interrupt.
738 */
739 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
740 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
741 sc->intr_mask = mask;
742 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
743
744 BPF_MTAP(ifp, top);
745
746 sc->ifp->if_opackets++;
747 m_freem(top);
748
749try_start:
750
751 /*
752 * Now pass control to snstart() to queue any additional packets
753 */
754 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
755 snstart(ifp);
756
757 /*
758 * We've sent something, so we're active. Set a watchdog in case the
759 * TX_EMPTY interrupt is lost.
760 */
761 sc->ifp->if_drv_flags |= IFF_DRV_OACTIVE;
762 sc->ifp->if_timer = 1;
763
764 return;
765}
766
767
768void
769sn_intr(void *arg)
770{
771 int status, interrupts;
772 struct sn_softc *sc = (struct sn_softc *) arg;
773 struct ifnet *ifp = sc->ifp;
774
775 /*
776 * Chip state registers
777 */
778 uint8_t mask;
779 uint8_t packet_no;
780 uint16_t tx_status;
781 uint16_t card_stats;
782
783 SN_LOCK(sc);
784
785 /*
786 * Clear the watchdog.
787 */
788 ifp->if_timer = 0;
789
790 SMC_SELECT_BANK(sc, 2);
791
792 /*
793 * Obtain the current interrupt mask and clear the hardware mask
794 * while servicing interrupts.
795 */
796 mask = CSR_READ_1(sc, INTR_MASK_REG_B);
797 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
798
799 /*
800 * Get the set of interrupts which occurred and eliminate any which
801 * are masked.
802 */
803 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B);
804 status = interrupts & mask;
805
806 /*
807 * Now, process each of the interrupt types.
808 */
809
810 /*
811 * Receive Overrun.
812 */
813 if (status & IM_RX_OVRN_INT) {
814 /*
815 * Acknowlege Interrupt
816 */
817 SMC_SELECT_BANK(sc, 2);
818 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT);
819
820 ++sc->ifp->if_ierrors;
821 }
822 /*
823 * Got a packet.
824 */
825 if (status & IM_RCV_INT) {
826 int packet_number;
827
828 SMC_SELECT_BANK(sc, 2);
829 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
830
831 if (packet_number & FIFO_REMPTY) {
832 /*
833 * we got called , but nothing was on the FIFO
834 */
835 printf("sn: Receive interrupt with nothing on FIFO\n");
836 goto out;
837 }
838 snread(ifp);
839 }
840 /*
841 * An on-card memory allocation came through.
842 */
843 if (status & IM_ALLOC_INT) {
844 /*
845 * Disable this interrupt.
846 */
847 mask &= ~IM_ALLOC_INT;
848 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
849 snresume(sc->ifp);
850 }
851 /*
852 * TX Completion. Handle a transmit error message. This will only be
853 * called when there is an error, because of the AUTO_RELEASE mode.
854 */
855 if (status & IM_TX_INT) {
856 /*
857 * Acknowlege Interrupt
858 */
859 SMC_SELECT_BANK(sc, 2);
860 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT);
861
862 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W);
863 packet_no &= FIFO_TX_MASK;
864
865 /*
866 * select this as the packet to read from
867 */
868 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
869
870 /*
871 * Position the pointer to the first word from this packet
872 */
873 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
874
875 /*
876 * Fetch the TX status word. The value found here will be a
877 * copy of the EPH_STATUS_REG_W at the time the transmit
878 * failed.
879 */
880 tx_status = CSR_READ_2(sc, DATA_REG_W);
881
882 if (tx_status & EPHSR_TX_SUC) {
883 device_printf(sc->dev,
884 "Successful packet caused interrupt\n");
885 } else {
886 ++sc->ifp->if_oerrors;
887 }
888
889 if (tx_status & EPHSR_LATCOL)
890 ++sc->ifp->if_collisions;
891
892 /*
893 * Some of these errors will have disabled transmit.
894 * Re-enable transmit now.
895 */
896 SMC_SELECT_BANK(sc, 0);
897
898#ifdef SW_PAD
899 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE);
900#else
901 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
902#endif /* SW_PAD */
903
904 /*
905 * kill the failed packet. Wait for the MMU to be un-busy.
906 */
907 SMC_SELECT_BANK(sc, 2);
908 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
909 ;
910 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
911
912 /*
913 * Attempt to queue more transmits.
914 */
915 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
916 snstart_locked(sc->ifp);
917 }
918 /*
919 * Transmit underrun. We use this opportunity to update transmit
920 * statistics from the card.
921 */
922 if (status & IM_TX_EMPTY_INT) {
923
924 /*
925 * Acknowlege Interrupt
926 */
927 SMC_SELECT_BANK(sc, 2);
928 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT);
929
930 /*
931 * Disable this interrupt.
932 */
933 mask &= ~IM_TX_EMPTY_INT;
934
935 SMC_SELECT_BANK(sc, 0);
936 card_stats = CSR_READ_2(sc, COUNTER_REG_W);
937
938 /*
939 * Single collisions
940 */
941 sc->ifp->if_collisions += card_stats & ECR_COLN_MASK;
942
943 /*
944 * Multiple collisions
945 */
946 sc->ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4;
947
948 SMC_SELECT_BANK(sc, 2);
949
950 /*
951 * Attempt to enqueue some more stuff.
952 */
953 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
954 snstart_locked(sc->ifp);
955 }
956 /*
957 * Some other error. Try to fix it by resetting the adapter.
958 */
959 if (status & IM_EPH_INT) {
960 snstop(sc);
961 sninit_locked(sc);
962 }
963
964out:
965 /*
966 * Handled all interrupt sources.
967 */
968
969 SMC_SELECT_BANK(sc, 2);
970
971 /*
972 * Reestablish interrupts from mask which have not been deselected
973 * during this interrupt. Note that the hardware mask, which was set
974 * to 0x00 at the start of this service routine, may have been
975 * updated by one or more of the interrupt handers and we must let
976 * those new interrupts stay enabled here.
977 */
978 mask |= CSR_READ_1(sc, INTR_MASK_REG_B);
979 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
980 sc->intr_mask = mask;
981 SN_UNLOCK(sc);
982}
983
984static void
985snread(struct ifnet *ifp)
986{
987 struct sn_softc *sc = ifp->if_softc;
988 struct ether_header *eh;
989 struct mbuf *m;
990 short status;
991 int packet_number;
992 uint16_t packet_length;
993 uint8_t *data;
994
995 SMC_SELECT_BANK(sc, 2);
996#if 0
997 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
998
999 if (packet_number & FIFO_REMPTY) {
1000
1001 /*
1002 * we got called , but nothing was on the FIFO
1003 */
1004 printf("sn: Receive interrupt with nothing on FIFO\n");
1005 return;
1006 }
1007#endif
1008read_another:
1009
1010 /*
1011 * Start reading from the start of the packet. Since PTR_RCV is set,
1012 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK.
1013 */
1014 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
1015
1016 /*
1017 * First two words are status and packet_length
1018 */
1019 status = CSR_READ_2(sc, DATA_REG_W);
1020 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK;
1021
1022 /*
1023 * The packet length contains 3 extra words: status, length, and a
1024 * extra word with the control byte.
1025 */
1026 packet_length -= 6;
1027
1028 /*
1029 * Account for receive errors and discard.
1030 */
1031 if (status & RS_ERRORS) {
1032 ++sc->ifp->if_ierrors;
1033 goto out;
1034 }
1035 /*
1036 * A packet is received.
1037 */
1038
1039 /*
1040 * Adjust for odd-length packet.
1041 */
1042 if (status & RS_ODDFRAME)
1043 packet_length++;
1044
1045 /*
1046 * Allocate a header mbuf from the kernel.
1047 */
1048 MGETHDR(m, M_DONTWAIT, MT_DATA);
1049 if (m == NULL)
1050 goto out;
1051
1052 m->m_pkthdr.rcvif = sc->ifp;
1053 m->m_pkthdr.len = m->m_len = packet_length;
1054
1055 /*
1056 * Attach an mbuf cluster
1057 */
1058 MCLGET(m, M_DONTWAIT);
1059
1060 /*
1061 * Insist on getting a cluster
1062 */
1063 if ((m->m_flags & M_EXT) == 0) {
1064 m_freem(m);
1065 ++sc->ifp->if_ierrors;
1066 printf("sn: snread() kernel memory allocation problem\n");
1067 goto out;
1068 }
1069 eh = mtod(m, struct ether_header *);
1070
1071 /*
1072 * Get packet, including link layer address, from interface.
1073 */
1074 data = (uint8_t *) eh;
1075 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1);
1076 if (packet_length & 1) {
1077 data += packet_length & ~1;
1078 *data = CSR_READ_1(sc, DATA_REG_B);
1079 }
1080 ++sc->ifp->if_ipackets;
1081
1082 /*
1083 * Remove link layer addresses and whatnot.
1084 */
1085 m->m_pkthdr.len = m->m_len = packet_length;
1086
1087 /*
1088 * Drop locks before calling if_input() since it may re-enter
1089 * snstart() in the netisr case. This would result in a
1090 * lock reversal. Better performance might be obtained by
1091 * chaining all packets received, dropping the lock, and then
1092 * calling if_input() on each one.
1093 */
1094 SN_UNLOCK(sc);
1095 (*ifp->if_input)(ifp, m);
1096 SN_LOCK(sc);
1097
1098out:
1099
1100 /*
1101 * Error or good, tell the card to get rid of this packet Wait for
1102 * the MMU to be un-busy.
1103 */
1104 SMC_SELECT_BANK(sc, 2);
1105 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
1106 ;
1107 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE);
1108
1109 /*
1110 * Check whether another packet is ready
1111 */
1112 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1113 if (packet_number & FIFO_REMPTY) {
1114 return;
1115 }
1116 goto read_another;
1117}
1118
1119
1120/*
1121 * Handle IOCTLS. This function is completely stolen from if_ep.c
1122 * As with its progenitor, it does not handle hardware address
1123 * changes.
1124 */
1125static int
1126snioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1127{
1128 struct sn_softc *sc = ifp->if_softc;
1129 int error = 0;
1130
1131 switch (cmd) {
1132 case SIOCSIFFLAGS:
1133 SN_LOCK(sc);
1134 if ((ifp->if_flags & IFF_UP) == 0 &&
1135 ifp->if_drv_flags & IFF_DRV_RUNNING) {
1136 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1137 snstop(sc);
1138 } else {
1139 /* reinitialize card on any parameter change */
1140 sninit_locked(sc);
1141 }
1142 SN_UNLOCK(sc);
1143 break;
1144
1145#ifdef notdef
1146 case SIOCGHWADDR:
1147 bcopy((caddr_t) sc->sc_addr, (caddr_t) & ifr->ifr_data,
1148 sizeof(sc->sc_addr));
1149 break;
1150#endif
1151
1152 case SIOCADDMULTI:
1153 /* update multicast filter list. */
1154 SN_LOCK(sc);
1155 sn_setmcast(sc);
1156 error = 0;
1157 SN_UNLOCK(sc);
1158 break;
1159 case SIOCDELMULTI:
1160 /* update multicast filter list. */
1161 SN_LOCK(sc);
1162 sn_setmcast(sc);
1163 error = 0;
1164 SN_UNLOCK(sc);
1165 break;
1166 default:
1167 error = EINVAL;
1168 error = ether_ioctl(ifp, cmd, data);
1169 break;
1170 }
1171 return (error);
1172}
1173
1174static void
1175snwatchdog(struct ifnet *ifp)
1176{
1177 sn_intr(ifp->if_softc);
1178}
1179
1180
1181/* 1. zero the interrupt mask
1182 * 2. clear the enable receive flag
1183 * 3. clear the enable xmit flags
1184 */
1185static void
1186snstop(struct sn_softc *sc)
1187{
1188
1189 struct ifnet *ifp = sc->ifp;
1190
1191 /*
1192 * Clear interrupt mask; disable all interrupts.
1193 */
1194 SMC_SELECT_BANK(sc, 2);
1195 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
1196
1197 /*
1198 * Disable transmitter and Receiver
1199 */
1200 SMC_SELECT_BANK(sc, 0);
1201 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
1202 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
1203
1204 /*
1205 * Cancel watchdog.
1206 */
1207 ifp->if_timer = 0;
1208}
1209
1210
1211int
1212sn_activate(device_t dev)
1213{
1214 struct sn_softc *sc = device_get_softc(dev);
1215
1216 sc->port_rid = 0;
1217 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid,
1218 0, ~0, SMC_IO_EXTENT, RF_ACTIVE);
1219 if (!sc->port_res) {
1220 if (bootverbose)
1221 device_printf(dev, "Cannot allocate ioport\n");
1222 return ENOMEM;
1223 }
1224
1225 sc->irq_rid = 0;
1226 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
1227 RF_ACTIVE);
1228 if (!sc->irq_res) {
1229 if (bootverbose)
1230 device_printf(dev, "Cannot allocate irq\n");
1231 sn_deactivate(dev);
1232 return ENOMEM;
1233 }
1234 sc->bst = rman_get_bustag(sc->port_res);
1235 sc->bsh = rman_get_bushandle(sc->port_res);
1236 return (0);
1237}
1238
1239void
1240sn_deactivate(device_t dev)
1241{
1242 struct sn_softc *sc = device_get_softc(dev);
1243
1244 if (sc->intrhand)
1245 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1246 sc->intrhand = 0;
1247 if (sc->port_res)
1248 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
1249 sc->port_res);
1250 sc->port_res = 0;
1251 if (sc->modem_res)
1252 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid,
1253 sc->modem_res);
1254 sc->modem_res = 0;
1255 if (sc->irq_res)
1256 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
1257 sc->irq_res);
1258 sc->irq_res = 0;
1259 return;
1260}
1261
1262/*
1263 * Function: sn_probe(device_t dev)
1264 *
1265 * Purpose:
1266 * Tests to see if a given ioaddr points to an SMC9xxx chip.
1267 * Tries to cause as little damage as possible if it's not a SMC chip.
1268 * Returns a 0 on success
1269 *
1270 * Algorithm:
1271 * (1) see if the high byte of BANK_SELECT is 0x33
1272 * (2) compare the ioaddr with the base register's address
1273 * (3) see if I recognize the chip ID in the appropriate register
1274 *
1275 *
1276 */
1277int
1278sn_probe(device_t dev)
1279{
1280 struct sn_softc *sc = device_get_softc(dev);
1281 uint16_t bank;
1282 uint16_t revision_register;
1283 uint16_t base_address_register;
1284 int err;
1285
1286 if ((err = sn_activate(dev)) != 0)
1287 return err;
1288
1289 /*
1290 * First, see if the high byte is 0x33
1291 */
1292 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1293 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1294#ifdef SN_DEBUG
1295 device_printf(dev, "test1 failed\n");
1296#endif
1297 goto error;
1298 }
1299 /*
1300 * The above MIGHT indicate a device, but I need to write to further
1301 * test this. Go to bank 0, then test that the register still
1302 * reports the high byte is 0x33.
1303 */
1304 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000);
1305 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1306 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1307#ifdef SN_DEBUG
1308 device_printf(dev, "test2 failed\n");
1309#endif
1310 goto error;
1311 }
1312 /*
1313 * well, we've already written once, so hopefully another time won't
1314 * hurt. This time, I need to switch the bank register to bank 1, so
1315 * I can access the base address register. The contents of the
1316 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected
1317 * to match the I/O port address where the adapter is being probed.
1318 */
1319 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001);
1320 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0;
1321
1322 if (rman_get_start(sc->port_res) != base_address_register) {
1323
1324 /*
1325 * Well, the base address register didn't match. Must not
1326 * have been a SMC chip after all.
1327 */
1328#ifdef SN_DEBUG
1329 device_printf(dev, "test3 failed ioaddr = 0x%x, "
1330 "base_address_register = 0x%x\n",
1331 rman_get_start(sc->port_res), base_address_register);
1332#endif
1333 goto error;
1334 }
1335
1336 /*
1337 * Check if the revision register is something that I recognize.
1338 * These might need to be added to later, as future revisions could
1339 * be added.
1340 */
1341 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3);
1342 revision_register = CSR_READ_2(sc, REVISION_REG_W);
1343 if (!chip_ids[(revision_register >> 4) & 0xF]) {
1344
1345 /*
1346 * I don't regonize this chip, so...
1347 */
1348#ifdef SN_DEBUG
1349 device_printf(dev, "test4 failed\n");
1350#endif
1351 goto error;
1352 }
1353
1354 /*
1355 * at this point I'll assume that the chip is an SMC9xxx. It might be
1356 * prudent to check a listing of MAC addresses against the hardware
1357 * address, or do some other tests.
1358 */
1359 sn_deactivate(dev);
1360 return 0;
1361 error:
1362 sn_deactivate(dev);
1363 return ENXIO;
1364}
1365
1366#define MCFSZ 8
1367
1368static void
1369sn_setmcast(struct sn_softc *sc)
1370{
1371 struct ifnet *ifp = sc->ifp;
1372 int flags;
1373 uint8_t mcf[MCFSZ];
1374
1375 SN_ASSERT_LOCKED(sc);
1376
1377 /*
1378 * Set the receiver filter. We want receive enabled and auto strip
1379 * of CRC from received packet. If we are promiscuous then set that
1380 * bit too.
1381 */
1382 flags = RCR_ENABLE | RCR_STRIP_CRC;
1383
1384 if (ifp->if_flags & IFF_PROMISC) {
1385 flags |= RCR_PROMISC | RCR_ALMUL;
1386 } else if (ifp->if_flags & IFF_ALLMULTI) {
1387 flags |= RCR_ALMUL;
1388 } else {
1389 if (sn_getmcf(ifp, mcf)) {
1390 /* set filter */
1391 SMC_SELECT_BANK(sc, 3);
1392 CSR_WRITE_2(sc, MULTICAST1_REG_W,
1393 ((uint16_t)mcf[1] << 8) | mcf[0]);
1394 CSR_WRITE_2(sc, MULTICAST2_REG_W,
1395 ((uint16_t)mcf[3] << 8) | mcf[2]);
1396 CSR_WRITE_2(sc, MULTICAST3_REG_W,
1397 ((uint16_t)mcf[5] << 8) | mcf[4]);
1398 CSR_WRITE_2(sc, MULTICAST4_REG_W,
1399 ((uint16_t)mcf[7] << 8) | mcf[6]);
1400 } else {
1401 flags |= RCR_ALMUL;
1402 }
1403 }
1404 SMC_SELECT_BANK(sc, 0);
1405 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags);
1406}
1407
1408static int
1409sn_getmcf(struct ifnet *ifp, uint8_t *mcf)
1410{
1411 int i;
1412 uint32_t index, index2;
1413 uint8_t *af = mcf;
1414 struct ifmultiaddr *ifma;
1415
1416 bzero(mcf, MCFSZ);
1417
1418 IF_ADDR_LOCK(ifp);
1419 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1420 if (ifma->ifma_addr->sa_family != AF_LINK) {
1421 IF_ADDR_UNLOCK(ifp);
1422 return 0;
1423 }
1424 index = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1425 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f;
1426 index2 = 0;
1427 for (i = 0; i < 6; i++) {
1428 index2 <<= 1;
1429 index2 |= (index & 0x01);
1430 index >>= 1;
1431 }
1432 af[index2 >> 3] |= 1 << (index2 & 7);
1433 }
1434 IF_ADDR_UNLOCK(ifp);
1435 return 1; /* use multicast filter */
1436}
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