89};
90
91#define R1BFIX_NONE 0 /* No fix needed at next interrupt. */
92#define R1BFIX_NODATA 1 /* Synthesize DATA_END for R1B w/o data. */
93#define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */
94
95#define HWTYPE_NONE 0 /* Hardware not recognized/supported. */
96#define HWTYPE_ESDHC 1 /* fsl5x and earlier. */
97#define HWTYPE_USDHC 2 /* fsl6. */
98
99/*
100 * Freescale-specific registers, or in some cases the layout of bits within the
101 * sdhci-defined register is different on Freescale. These names all begin with
102 * SDHC_ (not SDHCI_).
103 */
104
105#define SDHC_WTMK_LVL 0x44 /* Watermark Level register. */
106#define USDHC_MIX_CONTROL 0x48 /* Mix(ed) Control register. */
107#define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */
108#define SDHC_VEND_FRC_SDCLK_ON (1 << 8)
109#define SDHC_VEND_IPGEN (1 << 11)
110#define SDHC_VEND_HCKEN (1 << 12)
111#define SDHC_VEND_PEREN (1 << 13)
112
113#define SDHC_PRES_STATE 0x24
114#define SDHC_PRES_CIHB (1 << 0)
115#define SDHC_PRES_CDIHB (1 << 1)
116#define SDHC_PRES_DLA (1 << 2)
117#define SDHC_PRES_SDSTB (1 << 3)
118#define SDHC_PRES_IPGOFF (1 << 4)
119#define SDHC_PRES_HCKOFF (1 << 5)
120#define SDHC_PRES_PEROFF (1 << 6)
121#define SDHC_PRES_SDOFF (1 << 7)
122#define SDHC_PRES_WTA (1 << 8)
123#define SDHC_PRES_RTA (1 << 9)
124#define SDHC_PRES_BWEN (1 << 10)
125#define SDHC_PRES_BREN (1 << 11)
126#define SDHC_PRES_RTR (1 << 12)
127#define SDHC_PRES_CINST (1 << 16)
128#define SDHC_PRES_CDPL (1 << 18)
129#define SDHC_PRES_WPSPL (1 << 19)
130#define SDHC_PRES_CLSL (1 << 23)
131#define SDHC_PRES_DLSL_SHIFT 24
132#define SDHC_PRES_DLSL_MASK (0xffU << SDHC_PRES_DLSL_SHIFT)
133
134#define SDHC_PROT_CTRL 0x28
135#define SDHC_PROT_LED (1 << 0)
136#define SDHC_PROT_WIDTH_1BIT (0 << 1)
137#define SDHC_PROT_WIDTH_4BIT (1 << 1)
138#define SDHC_PROT_WIDTH_8BIT (2 << 1)
139#define SDHC_PROT_WIDTH_MASK (3 << 1)
140#define SDHC_PROT_D3CD (1 << 3)
141#define SDHC_PROT_EMODE_BIG (0 << 4)
142#define SDHC_PROT_EMODE_HALF (1 << 4)
143#define SDHC_PROT_EMODE_LITTLE (2 << 4)
144#define SDHC_PROT_EMODE_MASK (3 << 4)
145#define SDHC_PROT_SDMA (0 << 8)
146#define SDHC_PROT_ADMA1 (1 << 8)
147#define SDHC_PROT_ADMA2 (2 << 8)
148#define SDHC_PROT_ADMA264 (3 << 8)
149#define SDHC_PROT_DMA_MASK (3 << 8)
150#define SDHC_PROT_CDTL (1 << 6)
151#define SDHC_PROT_CDSS (1 << 7)
152
153#define SDHC_SYS_CTRL 0x2c
154
155/*
156 * The clock enable bits exist in different registers for ESDHC vs USDHC, but
157 * they are the same bits in both cases. The divisor values go into the
158 * standard sdhci clock register, but in different bit positions and meanings
159 than the sdhci spec values.
160 */
161#define SDHC_CLK_IPGEN (1 << 0)
162#define SDHC_CLK_HCKEN (1 << 1)
163#define SDHC_CLK_PEREN (1 << 2)
164#define SDHC_CLK_SDCLKEN (1 << 3)
165#define SDHC_CLK_ENABLE_MASK 0x0000000f
166#define SDHC_CLK_DIVISOR_MASK 0x000000f0
167#define SDHC_CLK_DIVISOR_SHIFT 4
168#define SDHC_CLK_PRESCALE_MASK 0x0000ff00
169#define SDHC_CLK_PRESCALE_SHIFT 8
170
171static struct ofw_compat_data compat_data[] = {
172 {"fsl,imx6q-usdhc", HWTYPE_USDHC},
173 {"fsl,imx6sl-usdhc", HWTYPE_USDHC},
174 {"fsl,imx53-esdhc", HWTYPE_ESDHC},
175 {"fsl,imx51-esdhc", HWTYPE_ESDHC},
176 {"fsl,esdhc", HWTYPE_ESDHC},
177 {NULL, HWTYPE_NONE},
178};
179
180static uint16_t fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc);
181static void fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val);
182static void fsl_sdhci_r1bfix_func(void *arg);
183
184static inline uint32_t
185RD4(struct fsl_sdhci_softc *sc, bus_size_t off)
186{
187
188 return (bus_read_4(sc->mem_res, off));
189}
190
191static inline void
192WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val)
193{
194
195 bus_write_4(sc->mem_res, off, val);
196}
197
198static uint8_t
199fsl_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
200{
201 struct fsl_sdhci_softc *sc = device_get_softc(dev);
202 uint32_t val32, wrk32;
203
204 /*
205 * Most of the things in the standard host control register are in the
206 * hardware's wider protocol control register, but some of the bits are
207 * moved around.
208 */
209 if (off == SDHCI_HOST_CONTROL) {
210 wrk32 = RD4(sc, SDHC_PROT_CTRL);
211 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET |
212 SDHCI_CTRL_FORCE_CARD);
213 switch (wrk32 & SDHC_PROT_WIDTH_MASK) {
214 case SDHC_PROT_WIDTH_1BIT:
215 /* Value is already 0. */
216 break;
217 case SDHC_PROT_WIDTH_4BIT:
218 val32 |= SDHCI_CTRL_4BITBUS;
219 break;
220 case SDHC_PROT_WIDTH_8BIT:
221 val32 |= SDHCI_CTRL_8BITBUS;
222 break;
223 }
224 switch (wrk32 & SDHC_PROT_DMA_MASK) {
225 case SDHC_PROT_SDMA:
226 /* Value is already 0. */
227 break;
228 case SDHC_PROT_ADMA1:
229 /* This value is deprecated, should never appear. */
230 break;
231 case SDHC_PROT_ADMA2:
232 val32 |= SDHCI_CTRL_ADMA2;
233 break;
234 case SDHC_PROT_ADMA264:
235 val32 |= SDHCI_CTRL_ADMA264;
236 break;
237 }
238 return val32;
239 }
240
241 /*
242 * XXX can't find the bus power on/off knob. For now we have to say the
243 * power is always on and always set to the same voltage.
244 */
245 if (off == SDHCI_POWER_CONTROL) {
246 return (SDHCI_POWER_ON | SDHCI_POWER_300);
247 }
248
249
250 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
251}
252
253static uint16_t
254fsl_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
255{
256 struct fsl_sdhci_softc *sc = device_get_softc(dev);
257 uint32_t val32;
258
259 if (sc->hwtype == HWTYPE_USDHC) {
260 /*
261 * The USDHC hardware has nothing in the version register, but
262 * it's v3 compatible with all our translation code.
263 */
264 if (off == SDHCI_HOST_VERSION) {
265 return (SDHCI_SPEC_300 << SDHCI_SPEC_VER_SHIFT);
266 }
267 /*
268 * The USDHC hardware moved the transfer mode bits to the mixed
269 * control register, fetch them from there.
270 */
271 if (off == SDHCI_TRANSFER_MODE)
272 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37);
273
274 } else if (sc->hwtype == HWTYPE_ESDHC) {
275
276 /*
277 * The ESDHC hardware has the typical 32-bit combined "command
278 * and mode" register that we have to cache so that command
279 * isn't written until after mode. On a read, just retrieve the
280 * cached values last written.
281 */
282 if (off == SDHCI_TRANSFER_MODE) {
283 return (sc->cmd_and_mode & 0x0000ffff);
284 } else if (off == SDHCI_COMMAND_FLAGS) {
285 return (sc->cmd_and_mode >> 16);
286 }
287 }
288
289 /*
290 * This hardware only manages one slot. Synthesize a slot interrupt
291 * status register... if there are any enabled interrupts active they
292 * must be coming from our one and only slot.
293 */
294 if (off == SDHCI_SLOT_INT_STATUS) {
295 val32 = RD4(sc, SDHCI_INT_STATUS);
296 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);
297 return (val32 ? 1 : 0);
298 }
299
300 /*
301 * Clock bits are scattered into various registers which differ by
302 * hardware type, complex enough to have their own function.
303 */
304 if (off == SDHCI_CLOCK_CONTROL) {
305 return (fsl_sdhc_get_clock(sc));
306 }
307
308 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
309}
310
311static uint32_t
312fsl_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
313{
314 struct fsl_sdhci_softc *sc = device_get_softc(dev);
315 uint32_t val32, wrk32;
316
317 val32 = RD4(sc, off);
318
319 /*
320 * The hardware leaves the base clock frequency out of the capabilities
321 * register, but we filled it in by setting slot->max_clk at attach time
322 * rather than here, because we can't represent frequencies above 63MHz
323 * in an sdhci 2.0 capabliities register. The timeout clock is the same
324 * as the active output sdclock; we indicate that with a quirk setting
325 * so don't populate the timeout frequency bits.
326 *
327 * XXX Turn off (for now) features the hardware can do but this driver
328 * doesn't yet handle (1.8v, suspend/resume, etc).
329 */
330 if (off == SDHCI_CAPABILITIES) {
331 val32 &= ~SDHCI_CAN_VDD_180;
332 val32 &= ~SDHCI_CAN_DO_SUSPEND;
333 val32 |= SDHCI_CAN_DO_8BITBUS;
334 return (val32);
335 }
336
337 /*
338 * The hardware moves bits around in the present state register to make
339 * room for all 8 data line state bits. To translate, mask out all the
340 * bits which are not in the same position in both registers (this also
341 * masks out some Freescale-specific bits in locations defined as
342 * reserved by sdhci), then shift the data line and retune request bits
343 * down to their standard locations.
344 */
345 if (off == SDHCI_PRESENT_STATE) {
346 wrk32 = val32;
347 val32 &= 0x000F0F07;
348 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK;
349 val32 |= (wrk32 >> 9) & SDHCI_RETUNE_REQUEST;
350 return (val32);
351 }
352
353 /*
354 * fsl_sdhci_intr() can synthesize a DATA_END interrupt following a
355 * command with an R1B response, mix it into the hardware status.
356 */
357 if (off == SDHCI_INT_STATUS) {
358 return (val32 | sc->r1bfix_intmask);
359 }
360
361 return val32;
362}
363
364static void
365fsl_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
366 uint32_t *data, bus_size_t count)
367{
368 struct fsl_sdhci_softc *sc = device_get_softc(dev);
369
370 bus_read_multi_4(sc->mem_res, off, data, count);
371}
372
373static void
374fsl_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
375{
376 struct fsl_sdhci_softc *sc = device_get_softc(dev);
377 uint32_t val32;
378
379 /*
380 * Most of the things in the standard host control register are in the
381 * hardware's wider protocol control register, but some of the bits are
382 * moved around.
383 */
384 if (off == SDHCI_HOST_CONTROL) {
385 val32 = RD4(sc, SDHC_PROT_CTRL);
386 val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK |
387 SDHC_PROT_WIDTH_MASK | SDHC_PROT_CDTL | SDHC_PROT_CDSS);
388 val32 |= (val & SDHCI_CTRL_LED);
389 if (val & SDHCI_CTRL_8BITBUS)
390 val32 |= SDHC_PROT_WIDTH_8BIT;
391 else
392 val32 |= (val & SDHCI_CTRL_4BITBUS);
393 val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4;
394 val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD));
395 WR4(sc, SDHC_PROT_CTRL, val32);
396 return;
397 }
398
399 /* XXX I can't find the bus power on/off knob; do nothing. */
400 if (off == SDHCI_POWER_CONTROL) {
401 return;
402 }
403#ifdef __powerpc__
404 /* XXX Reset doesn't seem to work as expected. Do nothing for now. */
405 if (off == SDHCI_SOFTWARE_RESET)
406 return;
407#endif
408
409 val32 = RD4(sc, off & ~3);
410 val32 &= ~(0xff << (off & 3) * 8);
411 val32 |= (val << (off & 3) * 8);
412
413 WR4(sc, off & ~3, val32);
414}
415
416static void
417fsl_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
418{
419 struct fsl_sdhci_softc *sc = device_get_softc(dev);
420 uint32_t val32;
421
422 /*
423 * The clock control stuff is complex enough to have its own function
424 * that can handle the ESDHC versus USDHC differences.
425 */
426 if (off == SDHCI_CLOCK_CONTROL) {
427 fsl_sdhc_set_clock(sc, val);
428 return;
429 }
430
431 /*
432 * Figure out whether we need to check the DAT0 line for busy status at
433 * interrupt time. The controller should be doing this, but for some
434 * reason it doesn't. There are two cases:
435 * - R1B response with no data transfer should generate a DATA_END (aka
436 * TRANSFER_COMPLETE) interrupt after waiting for busy, but if
437 * there's no data transfer there's no DATA_END interrupt. This is
438 * documented; they seem to think it's a feature.
439 * - R1B response after Auto-CMD12 appears to not work, even though
440 * there's a control bit for it (bit 3) in the vendor register.
441 * When we're starting a command that needs a manual DAT0 line check at
442 * interrupt time, we leave ourselves a note in r1bfix_type so that we
443 * can do the extra work in fsl_sdhci_intr().
444 */
445 if (off == SDHCI_COMMAND_FLAGS) {
446 if (val & SDHCI_CMD_DATA) {
447 const uint32_t MBAUTOCMD = SDHCI_TRNS_ACMD12 | SDHCI_TRNS_MULTI;
448 val32 = RD4(sc, USDHC_MIX_CONTROL);
449 if ((val32 & MBAUTOCMD) == MBAUTOCMD)
450 sc->r1bfix_type = R1BFIX_AC12;
451 } else {
452 if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) {
453 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
454 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
455 sc->r1bfix_type = R1BFIX_NODATA;
456 }
457 }
458 }
459
460 /*
461 * The USDHC hardware moved the transfer mode bits to mixed control; we
462 * just write them there and we're done. The ESDHC hardware has the
463 * typical combined cmd-and-mode register that allows only 32-bit
464 * access, so when writing the mode bits just save them, then later when
465 * writing the command bits, add in the saved mode bits.
466 */
467 if (sc->hwtype == HWTYPE_USDHC) {
468 if (off == SDHCI_TRANSFER_MODE) {
469 val32 = RD4(sc, USDHC_MIX_CONTROL);
470 val32 &= ~0x3f;
471 val32 |= val & 0x37;
472 // XXX acmd23 not supported here (or by sdhci driver)
473 WR4(sc, USDHC_MIX_CONTROL, val32);
474 return;
475 }
476 } else if (sc->hwtype == HWTYPE_ESDHC) {
477 if (off == SDHCI_TRANSFER_MODE) {
478 sc->cmd_and_mode =
479 (sc->cmd_and_mode & 0xffff0000) | val;
480 return;
481 } else if (off == SDHCI_COMMAND_FLAGS) {
482 sc->cmd_and_mode =
483 (sc->cmd_and_mode & 0xffff) | (val << 16);
484 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
485 return;
486 }
487 }
488
489 val32 = RD4(sc, off & ~3);
490 val32 &= ~(0xffff << (off & 3) * 8);
491 val32 |= ((val & 0xffff) << (off & 3) * 8);
492 WR4(sc, off & ~3, val32);
493}
494
495static void
496fsl_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
497{
498 struct fsl_sdhci_softc *sc = device_get_softc(dev);
499
500 /* Clear synthesized interrupts, then pass the value to the hardware. */
501 if (off == SDHCI_INT_STATUS) {
502 sc->r1bfix_intmask &= ~val;
503 }
504
505 WR4(sc, off, val);
506}
507
508static void
509fsl_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
510 uint32_t *data, bus_size_t count)
511{
512 struct fsl_sdhci_softc *sc = device_get_softc(dev);
513
514 bus_write_multi_4(sc->mem_res, off, data, count);
515}
516
517static uint16_t
518fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc)
519{
520 uint16_t val;
521
522 /*
523 * Whenever the sdhci driver writes the clock register we save a
524 * snapshot of just the frequency bits, so that we can play them back
525 * here on a register read without recalculating the frequency from the
526 * prescalar and divisor bits in the real register. We'll start with
527 * those bits, and mix in the clock status and enable bits that come
528 * from different places depending on which hardware we've got.
529 */
530 val = sc->sdclockreg_freq_bits;
531
532 /*
533 * The internal clock is always enabled (actually, the hardware manages
534 * it). Whether the internal clock is stable yet after a frequency
535 * change comes from the present-state register on both hardware types.
536 */
537 val |= SDHCI_CLOCK_INT_EN;
538 if (RD4(sc, SDHC_PRES_STATE) & SDHC_PRES_SDSTB)
539 val |= SDHCI_CLOCK_INT_STABLE;
540
541 /*
542 * On i.MX ESDHC hardware the card bus clock enable is in the usual
543 * sdhci register but it's a different bit, so transcribe it (note the
544 * difference between standard SDHCI_ and Freescale SDHC_ prefixes
545 * here). On USDHC and QorIQ ESDHC hardware there is a force-on bit, but
546 * no force-off for the card bus clock (the hardware runs the clock when
547 * transfers are active no matter what), so we always say the clock is
548 * on.
549 * XXX Maybe we should say it's in whatever state the sdhci driver last
550 * set it to.
551 */
552 if (sc->hwtype == HWTYPE_ESDHC) {
553#ifdef __arm__
554 if (RD4(sc, SDHC_SYS_CTRL) & SDHC_CLK_SDCLKEN)
555#endif
556 val |= SDHCI_CLOCK_CARD_EN;
557 } else {
558 val |= SDHCI_CLOCK_CARD_EN;
559 }
560
561 return (val);
562}
563
564static void
565fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val)
566{
567 uint32_t divisor, freq, prescale, val32;
568
569 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
570
571 /*
572 * Save the frequency-setting bits in SDHCI format so that we can play
573 * them back in get_clock without complex decoding of hardware regs,
574 * then deal with the freqency part of the value based on hardware type.
575 */
576 sc->sdclockreg_freq_bits = val & SDHCI_DIVIDERS_MASK;
577 if (sc->hwtype == HWTYPE_ESDHC) {
578 /*
579 * The i.MX5 ESDHC hardware requires the driver to manually
580 * start and stop the sd bus clock. If the enable bit is not
581 * set, turn off the clock in hardware and we're done, otherwise
582 * decode the requested frequency. ESDHC hardware is sdhci 2.0;
583 * the sdhci driver will use the original 8-bit divisor field
584 * and the "base / 2^N" divisor scheme.
585 */
586 if ((val & SDHCI_CLOCK_CARD_EN) == 0) {
587#ifdef __arm__
588 /* On QorIQ, this is a reserved bit. */
589 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHC_CLK_SDCLKEN);
590#endif
591 return;
592
593 }
594 divisor = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;
595 freq = sc->baseclk_hz >> ffs(divisor);
596 } else {
597 /*
598 * The USDHC hardware provides only "force always on" control
599 * over the sd bus clock, but no way to turn it off. (If a cmd
600 * or data transfer is in progress the clock is on, otherwise it
601 * is off.) If the clock is being disabled, we can just return
602 * now, otherwise we decode the requested frequency. USDHC
603 * hardware is sdhci 3.0; the sdhci driver will use a 10-bit
604 * divisor using the "base / 2*N" divisor scheme.
605 */
606 if ((val & SDHCI_CLOCK_CARD_EN) == 0)
607 return;
608 divisor = ((val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK) |
609 ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) <<
610 SDHCI_DIVIDER_MASK_LEN;
611 if (divisor == 0)
612 freq = sc->baseclk_hz;
613 else
614 freq = sc->baseclk_hz / (2 * divisor);
615 }
616
617 /*
618 * Get a prescaler and final divisor to achieve the desired frequency.
619 */
620 for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16);)
621 prescale <<= 1;
622
623 for (divisor = 1; freq < sc->baseclk_hz / (prescale * divisor);)
624 ++divisor;
625
626#ifdef DEBUG
627 device_printf(sc->dev,
628 "desired SD freq: %d, actual: %d; base %d prescale %d divisor %d\n",
629 freq, sc->baseclk_hz / (prescale * divisor), sc->baseclk_hz,
630 prescale, divisor);
631#endif
632
633 /*
634 * Adjust to zero-based values, and store them to the hardware.
635 */
636 prescale >>= 1;
637 divisor -= 1;
638
639 val32 &= ~(SDHC_CLK_DIVISOR_MASK | SDHC_CLK_PRESCALE_MASK);
640 val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT;
641 val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT;
642 val32 |= SDHC_CLK_IPGEN;
643 WR4(sc, SDHCI_CLOCK_CONTROL, val32);
644}
645
646static boolean_t
647fsl_sdhci_r1bfix_is_wait_done(struct fsl_sdhci_softc *sc)
648{
649 uint32_t inhibit;
650
651 mtx_assert(&sc->slot.mtx, MA_OWNED);
652
653 /*
654 * Check the DAT0 line status using both the DLA (data line active) and
655 * CDIHB (data inhibit) bits in the present state register. In theory
656 * just DLA should do the trick, but in practice it takes both. If the
657 * DAT0 line is still being held and we're not yet beyond the timeout
658 * point, just schedule another callout to check again later.
659 */
660 inhibit = RD4(sc, SDHC_PRES_STATE) & (SDHC_PRES_DLA | SDHC_PRES_CDIHB);
661
662 if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) {
663 callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0,
664 fsl_sdhci_r1bfix_func, sc, 0);
665 return (false);
666 }
667
668 /*
669 * If we reach this point with the inhibit bits still set, we've got a
670 * timeout, synthesize a DATA_TIMEOUT interrupt. Otherwise the DAT0
671 * line has been released, and we synthesize a DATA_END, and if the type
672 * of fix needed was on a command-without-data we also now add in the
673 * original INT_RESPONSE that we suppressed earlier.
674 */
675 if (inhibit)
676 sc->r1bfix_intmask |= SDHCI_INT_DATA_TIMEOUT;
677 else {
678 sc->r1bfix_intmask |= SDHCI_INT_DATA_END;
679 if (sc->r1bfix_type == R1BFIX_NODATA)
680 sc->r1bfix_intmask |= SDHCI_INT_RESPONSE;
681 }
682
683 sc->r1bfix_type = R1BFIX_NONE;
684 return (true);
685}
686
687static void
688fsl_sdhci_r1bfix_func(void * arg)
689{
690 struct fsl_sdhci_softc *sc = arg;
691 boolean_t r1bwait_done;
692
693 mtx_lock(&sc->slot.mtx);
694 r1bwait_done = fsl_sdhci_r1bfix_is_wait_done(sc);
695 mtx_unlock(&sc->slot.mtx);
696 if (r1bwait_done)
697 sdhci_generic_intr(&sc->slot);
698}
699
700static void
701fsl_sdhci_intr(void *arg)
702{
703 struct fsl_sdhci_softc *sc = arg;
704 uint32_t intmask;
705
706 mtx_lock(&sc->slot.mtx);
707
708 /*
709 * Manually check the DAT0 line for R1B response types that the
710 * controller fails to handle properly. The controller asserts the done
711 * interrupt while the card is still asserting busy with the DAT0 line.
712 *
713 * We check DAT0 immediately because most of the time, especially on a
714 * read, the card will actually be done by time we get here. If it's
715 * not, then the wait_done routine will schedule a callout to re-check
716 * periodically until it is done. In that case we clear the interrupt
717 * out of the hardware now so that we can present it later when the DAT0
718 * line is released.
719 *
720 * If we need to wait for the DAT0 line to be released, we set up a
721 * timeout point 250ms in the future. This number comes from the SD
722 * spec, which allows a command to take that long. In the real world,
723 * cards tend to take 10-20ms for a long-running command such as a write
724 * or erase that spans two pages.
725 */
726 switch (sc->r1bfix_type) {
727 case R1BFIX_NODATA:
728 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_RESPONSE;
729 break;
730 case R1BFIX_AC12:
731 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_DATA_END;
732 break;
733 default:
734 intmask = 0;
735 break;
736 }
737 if (intmask) {
738 sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS;
739 if (!fsl_sdhci_r1bfix_is_wait_done(sc)) {
740 WR4(sc, SDHCI_INT_STATUS, intmask);
741 bus_barrier(sc->mem_res, SDHCI_INT_STATUS, 4,
742 BUS_SPACE_BARRIER_WRITE);
743 }
744 }
745
746 mtx_unlock(&sc->slot.mtx);
747 sdhci_generic_intr(&sc->slot);
748}
749
750static int
751fsl_sdhci_get_ro(device_t bus, device_t child)
752{
753 struct fsl_sdhci_softc *sc = device_get_softc(bus);
754
755 return (sdhci_fdt_gpio_get_readonly(sc->gpio));
756}
757
758static bool
759fsl_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot)
760{
761 struct fsl_sdhci_softc *sc = device_get_softc(dev);
762
763 return (sdhci_fdt_gpio_get_present(sc->gpio));
764}
765
766#ifdef __powerpc__
767static uint32_t
768fsl_sdhci_get_platform_clock(device_t dev)
769{
770 device_t parent;
771 phandle_t node;
772 uint32_t clock;
773
774 node = ofw_bus_get_node(dev);
775
776 /* Get sdhci node properties */
777 if((OF_getprop(node, "clock-frequency", (void *)&clock,
778 sizeof(clock)) <= 0) || (clock == 0)) {
779
780 /*
781 * Trying to get clock from parent device (soc) if correct
782 * clock cannot be acquired from sdhci node.
783 */
784 parent = device_get_parent(dev);
785 node = ofw_bus_get_node(parent);
786
787 /* Get soc properties */
788 if ((OF_getprop(node, "bus-frequency", (void *)&clock,
789 sizeof(clock)) <= 0) || (clock == 0)) {
790 device_printf(dev,"Cannot acquire correct sdhci "
791 "frequency from DTS.\n");
792
793 return (0);
794 }
795 /* eSDHC clock is 1/2 platform clock. */
796 clock /= 2;
797 }
798
799 if (bootverbose)
800 device_printf(dev, "Acquired clock: %d from DTS\n", clock);
801
802 return (clock);
803}
804#endif
805
806
807static int
808fsl_sdhci_detach(device_t dev)
809{
810 struct fsl_sdhci_softc *sc = device_get_softc(dev);
811
812 if (sc->gpio != NULL)
813 sdhci_fdt_gpio_teardown(sc->gpio);
814
815 callout_drain(&sc->r1bfix_callout);
816
| 90};
91
92#define R1BFIX_NONE 0 /* No fix needed at next interrupt. */
93#define R1BFIX_NODATA 1 /* Synthesize DATA_END for R1B w/o data. */
94#define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */
95
96#define HWTYPE_NONE 0 /* Hardware not recognized/supported. */
97#define HWTYPE_ESDHC 1 /* fsl5x and earlier. */
98#define HWTYPE_USDHC 2 /* fsl6. */
99
100/*
101 * Freescale-specific registers, or in some cases the layout of bits within the
102 * sdhci-defined register is different on Freescale. These names all begin with
103 * SDHC_ (not SDHCI_).
104 */
105
106#define SDHC_WTMK_LVL 0x44 /* Watermark Level register. */
107#define USDHC_MIX_CONTROL 0x48 /* Mix(ed) Control register. */
108#define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */
109#define SDHC_VEND_FRC_SDCLK_ON (1 << 8)
110#define SDHC_VEND_IPGEN (1 << 11)
111#define SDHC_VEND_HCKEN (1 << 12)
112#define SDHC_VEND_PEREN (1 << 13)
113
114#define SDHC_PRES_STATE 0x24
115#define SDHC_PRES_CIHB (1 << 0)
116#define SDHC_PRES_CDIHB (1 << 1)
117#define SDHC_PRES_DLA (1 << 2)
118#define SDHC_PRES_SDSTB (1 << 3)
119#define SDHC_PRES_IPGOFF (1 << 4)
120#define SDHC_PRES_HCKOFF (1 << 5)
121#define SDHC_PRES_PEROFF (1 << 6)
122#define SDHC_PRES_SDOFF (1 << 7)
123#define SDHC_PRES_WTA (1 << 8)
124#define SDHC_PRES_RTA (1 << 9)
125#define SDHC_PRES_BWEN (1 << 10)
126#define SDHC_PRES_BREN (1 << 11)
127#define SDHC_PRES_RTR (1 << 12)
128#define SDHC_PRES_CINST (1 << 16)
129#define SDHC_PRES_CDPL (1 << 18)
130#define SDHC_PRES_WPSPL (1 << 19)
131#define SDHC_PRES_CLSL (1 << 23)
132#define SDHC_PRES_DLSL_SHIFT 24
133#define SDHC_PRES_DLSL_MASK (0xffU << SDHC_PRES_DLSL_SHIFT)
134
135#define SDHC_PROT_CTRL 0x28
136#define SDHC_PROT_LED (1 << 0)
137#define SDHC_PROT_WIDTH_1BIT (0 << 1)
138#define SDHC_PROT_WIDTH_4BIT (1 << 1)
139#define SDHC_PROT_WIDTH_8BIT (2 << 1)
140#define SDHC_PROT_WIDTH_MASK (3 << 1)
141#define SDHC_PROT_D3CD (1 << 3)
142#define SDHC_PROT_EMODE_BIG (0 << 4)
143#define SDHC_PROT_EMODE_HALF (1 << 4)
144#define SDHC_PROT_EMODE_LITTLE (2 << 4)
145#define SDHC_PROT_EMODE_MASK (3 << 4)
146#define SDHC_PROT_SDMA (0 << 8)
147#define SDHC_PROT_ADMA1 (1 << 8)
148#define SDHC_PROT_ADMA2 (2 << 8)
149#define SDHC_PROT_ADMA264 (3 << 8)
150#define SDHC_PROT_DMA_MASK (3 << 8)
151#define SDHC_PROT_CDTL (1 << 6)
152#define SDHC_PROT_CDSS (1 << 7)
153
154#define SDHC_SYS_CTRL 0x2c
155
156/*
157 * The clock enable bits exist in different registers for ESDHC vs USDHC, but
158 * they are the same bits in both cases. The divisor values go into the
159 * standard sdhci clock register, but in different bit positions and meanings
160 than the sdhci spec values.
161 */
162#define SDHC_CLK_IPGEN (1 << 0)
163#define SDHC_CLK_HCKEN (1 << 1)
164#define SDHC_CLK_PEREN (1 << 2)
165#define SDHC_CLK_SDCLKEN (1 << 3)
166#define SDHC_CLK_ENABLE_MASK 0x0000000f
167#define SDHC_CLK_DIVISOR_MASK 0x000000f0
168#define SDHC_CLK_DIVISOR_SHIFT 4
169#define SDHC_CLK_PRESCALE_MASK 0x0000ff00
170#define SDHC_CLK_PRESCALE_SHIFT 8
171
172static struct ofw_compat_data compat_data[] = {
173 {"fsl,imx6q-usdhc", HWTYPE_USDHC},
174 {"fsl,imx6sl-usdhc", HWTYPE_USDHC},
175 {"fsl,imx53-esdhc", HWTYPE_ESDHC},
176 {"fsl,imx51-esdhc", HWTYPE_ESDHC},
177 {"fsl,esdhc", HWTYPE_ESDHC},
178 {NULL, HWTYPE_NONE},
179};
180
181static uint16_t fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc);
182static void fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val);
183static void fsl_sdhci_r1bfix_func(void *arg);
184
185static inline uint32_t
186RD4(struct fsl_sdhci_softc *sc, bus_size_t off)
187{
188
189 return (bus_read_4(sc->mem_res, off));
190}
191
192static inline void
193WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val)
194{
195
196 bus_write_4(sc->mem_res, off, val);
197}
198
199static uint8_t
200fsl_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
201{
202 struct fsl_sdhci_softc *sc = device_get_softc(dev);
203 uint32_t val32, wrk32;
204
205 /*
206 * Most of the things in the standard host control register are in the
207 * hardware's wider protocol control register, but some of the bits are
208 * moved around.
209 */
210 if (off == SDHCI_HOST_CONTROL) {
211 wrk32 = RD4(sc, SDHC_PROT_CTRL);
212 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET |
213 SDHCI_CTRL_FORCE_CARD);
214 switch (wrk32 & SDHC_PROT_WIDTH_MASK) {
215 case SDHC_PROT_WIDTH_1BIT:
216 /* Value is already 0. */
217 break;
218 case SDHC_PROT_WIDTH_4BIT:
219 val32 |= SDHCI_CTRL_4BITBUS;
220 break;
221 case SDHC_PROT_WIDTH_8BIT:
222 val32 |= SDHCI_CTRL_8BITBUS;
223 break;
224 }
225 switch (wrk32 & SDHC_PROT_DMA_MASK) {
226 case SDHC_PROT_SDMA:
227 /* Value is already 0. */
228 break;
229 case SDHC_PROT_ADMA1:
230 /* This value is deprecated, should never appear. */
231 break;
232 case SDHC_PROT_ADMA2:
233 val32 |= SDHCI_CTRL_ADMA2;
234 break;
235 case SDHC_PROT_ADMA264:
236 val32 |= SDHCI_CTRL_ADMA264;
237 break;
238 }
239 return val32;
240 }
241
242 /*
243 * XXX can't find the bus power on/off knob. For now we have to say the
244 * power is always on and always set to the same voltage.
245 */
246 if (off == SDHCI_POWER_CONTROL) {
247 return (SDHCI_POWER_ON | SDHCI_POWER_300);
248 }
249
250
251 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
252}
253
254static uint16_t
255fsl_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
256{
257 struct fsl_sdhci_softc *sc = device_get_softc(dev);
258 uint32_t val32;
259
260 if (sc->hwtype == HWTYPE_USDHC) {
261 /*
262 * The USDHC hardware has nothing in the version register, but
263 * it's v3 compatible with all our translation code.
264 */
265 if (off == SDHCI_HOST_VERSION) {
266 return (SDHCI_SPEC_300 << SDHCI_SPEC_VER_SHIFT);
267 }
268 /*
269 * The USDHC hardware moved the transfer mode bits to the mixed
270 * control register, fetch them from there.
271 */
272 if (off == SDHCI_TRANSFER_MODE)
273 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37);
274
275 } else if (sc->hwtype == HWTYPE_ESDHC) {
276
277 /*
278 * The ESDHC hardware has the typical 32-bit combined "command
279 * and mode" register that we have to cache so that command
280 * isn't written until after mode. On a read, just retrieve the
281 * cached values last written.
282 */
283 if (off == SDHCI_TRANSFER_MODE) {
284 return (sc->cmd_and_mode & 0x0000ffff);
285 } else if (off == SDHCI_COMMAND_FLAGS) {
286 return (sc->cmd_and_mode >> 16);
287 }
288 }
289
290 /*
291 * This hardware only manages one slot. Synthesize a slot interrupt
292 * status register... if there are any enabled interrupts active they
293 * must be coming from our one and only slot.
294 */
295 if (off == SDHCI_SLOT_INT_STATUS) {
296 val32 = RD4(sc, SDHCI_INT_STATUS);
297 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);
298 return (val32 ? 1 : 0);
299 }
300
301 /*
302 * Clock bits are scattered into various registers which differ by
303 * hardware type, complex enough to have their own function.
304 */
305 if (off == SDHCI_CLOCK_CONTROL) {
306 return (fsl_sdhc_get_clock(sc));
307 }
308
309 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
310}
311
312static uint32_t
313fsl_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
314{
315 struct fsl_sdhci_softc *sc = device_get_softc(dev);
316 uint32_t val32, wrk32;
317
318 val32 = RD4(sc, off);
319
320 /*
321 * The hardware leaves the base clock frequency out of the capabilities
322 * register, but we filled it in by setting slot->max_clk at attach time
323 * rather than here, because we can't represent frequencies above 63MHz
324 * in an sdhci 2.0 capabliities register. The timeout clock is the same
325 * as the active output sdclock; we indicate that with a quirk setting
326 * so don't populate the timeout frequency bits.
327 *
328 * XXX Turn off (for now) features the hardware can do but this driver
329 * doesn't yet handle (1.8v, suspend/resume, etc).
330 */
331 if (off == SDHCI_CAPABILITIES) {
332 val32 &= ~SDHCI_CAN_VDD_180;
333 val32 &= ~SDHCI_CAN_DO_SUSPEND;
334 val32 |= SDHCI_CAN_DO_8BITBUS;
335 return (val32);
336 }
337
338 /*
339 * The hardware moves bits around in the present state register to make
340 * room for all 8 data line state bits. To translate, mask out all the
341 * bits which are not in the same position in both registers (this also
342 * masks out some Freescale-specific bits in locations defined as
343 * reserved by sdhci), then shift the data line and retune request bits
344 * down to their standard locations.
345 */
346 if (off == SDHCI_PRESENT_STATE) {
347 wrk32 = val32;
348 val32 &= 0x000F0F07;
349 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK;
350 val32 |= (wrk32 >> 9) & SDHCI_RETUNE_REQUEST;
351 return (val32);
352 }
353
354 /*
355 * fsl_sdhci_intr() can synthesize a DATA_END interrupt following a
356 * command with an R1B response, mix it into the hardware status.
357 */
358 if (off == SDHCI_INT_STATUS) {
359 return (val32 | sc->r1bfix_intmask);
360 }
361
362 return val32;
363}
364
365static void
366fsl_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
367 uint32_t *data, bus_size_t count)
368{
369 struct fsl_sdhci_softc *sc = device_get_softc(dev);
370
371 bus_read_multi_4(sc->mem_res, off, data, count);
372}
373
374static void
375fsl_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
376{
377 struct fsl_sdhci_softc *sc = device_get_softc(dev);
378 uint32_t val32;
379
380 /*
381 * Most of the things in the standard host control register are in the
382 * hardware's wider protocol control register, but some of the bits are
383 * moved around.
384 */
385 if (off == SDHCI_HOST_CONTROL) {
386 val32 = RD4(sc, SDHC_PROT_CTRL);
387 val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK |
388 SDHC_PROT_WIDTH_MASK | SDHC_PROT_CDTL | SDHC_PROT_CDSS);
389 val32 |= (val & SDHCI_CTRL_LED);
390 if (val & SDHCI_CTRL_8BITBUS)
391 val32 |= SDHC_PROT_WIDTH_8BIT;
392 else
393 val32 |= (val & SDHCI_CTRL_4BITBUS);
394 val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4;
395 val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD));
396 WR4(sc, SDHC_PROT_CTRL, val32);
397 return;
398 }
399
400 /* XXX I can't find the bus power on/off knob; do nothing. */
401 if (off == SDHCI_POWER_CONTROL) {
402 return;
403 }
404#ifdef __powerpc__
405 /* XXX Reset doesn't seem to work as expected. Do nothing for now. */
406 if (off == SDHCI_SOFTWARE_RESET)
407 return;
408#endif
409
410 val32 = RD4(sc, off & ~3);
411 val32 &= ~(0xff << (off & 3) * 8);
412 val32 |= (val << (off & 3) * 8);
413
414 WR4(sc, off & ~3, val32);
415}
416
417static void
418fsl_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
419{
420 struct fsl_sdhci_softc *sc = device_get_softc(dev);
421 uint32_t val32;
422
423 /*
424 * The clock control stuff is complex enough to have its own function
425 * that can handle the ESDHC versus USDHC differences.
426 */
427 if (off == SDHCI_CLOCK_CONTROL) {
428 fsl_sdhc_set_clock(sc, val);
429 return;
430 }
431
432 /*
433 * Figure out whether we need to check the DAT0 line for busy status at
434 * interrupt time. The controller should be doing this, but for some
435 * reason it doesn't. There are two cases:
436 * - R1B response with no data transfer should generate a DATA_END (aka
437 * TRANSFER_COMPLETE) interrupt after waiting for busy, but if
438 * there's no data transfer there's no DATA_END interrupt. This is
439 * documented; they seem to think it's a feature.
440 * - R1B response after Auto-CMD12 appears to not work, even though
441 * there's a control bit for it (bit 3) in the vendor register.
442 * When we're starting a command that needs a manual DAT0 line check at
443 * interrupt time, we leave ourselves a note in r1bfix_type so that we
444 * can do the extra work in fsl_sdhci_intr().
445 */
446 if (off == SDHCI_COMMAND_FLAGS) {
447 if (val & SDHCI_CMD_DATA) {
448 const uint32_t MBAUTOCMD = SDHCI_TRNS_ACMD12 | SDHCI_TRNS_MULTI;
449 val32 = RD4(sc, USDHC_MIX_CONTROL);
450 if ((val32 & MBAUTOCMD) == MBAUTOCMD)
451 sc->r1bfix_type = R1BFIX_AC12;
452 } else {
453 if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) {
454 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
455 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
456 sc->r1bfix_type = R1BFIX_NODATA;
457 }
458 }
459 }
460
461 /*
462 * The USDHC hardware moved the transfer mode bits to mixed control; we
463 * just write them there and we're done. The ESDHC hardware has the
464 * typical combined cmd-and-mode register that allows only 32-bit
465 * access, so when writing the mode bits just save them, then later when
466 * writing the command bits, add in the saved mode bits.
467 */
468 if (sc->hwtype == HWTYPE_USDHC) {
469 if (off == SDHCI_TRANSFER_MODE) {
470 val32 = RD4(sc, USDHC_MIX_CONTROL);
471 val32 &= ~0x3f;
472 val32 |= val & 0x37;
473 // XXX acmd23 not supported here (or by sdhci driver)
474 WR4(sc, USDHC_MIX_CONTROL, val32);
475 return;
476 }
477 } else if (sc->hwtype == HWTYPE_ESDHC) {
478 if (off == SDHCI_TRANSFER_MODE) {
479 sc->cmd_and_mode =
480 (sc->cmd_and_mode & 0xffff0000) | val;
481 return;
482 } else if (off == SDHCI_COMMAND_FLAGS) {
483 sc->cmd_and_mode =
484 (sc->cmd_and_mode & 0xffff) | (val << 16);
485 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
486 return;
487 }
488 }
489
490 val32 = RD4(sc, off & ~3);
491 val32 &= ~(0xffff << (off & 3) * 8);
492 val32 |= ((val & 0xffff) << (off & 3) * 8);
493 WR4(sc, off & ~3, val32);
494}
495
496static void
497fsl_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
498{
499 struct fsl_sdhci_softc *sc = device_get_softc(dev);
500
501 /* Clear synthesized interrupts, then pass the value to the hardware. */
502 if (off == SDHCI_INT_STATUS) {
503 sc->r1bfix_intmask &= ~val;
504 }
505
506 WR4(sc, off, val);
507}
508
509static void
510fsl_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
511 uint32_t *data, bus_size_t count)
512{
513 struct fsl_sdhci_softc *sc = device_get_softc(dev);
514
515 bus_write_multi_4(sc->mem_res, off, data, count);
516}
517
518static uint16_t
519fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc)
520{
521 uint16_t val;
522
523 /*
524 * Whenever the sdhci driver writes the clock register we save a
525 * snapshot of just the frequency bits, so that we can play them back
526 * here on a register read without recalculating the frequency from the
527 * prescalar and divisor bits in the real register. We'll start with
528 * those bits, and mix in the clock status and enable bits that come
529 * from different places depending on which hardware we've got.
530 */
531 val = sc->sdclockreg_freq_bits;
532
533 /*
534 * The internal clock is always enabled (actually, the hardware manages
535 * it). Whether the internal clock is stable yet after a frequency
536 * change comes from the present-state register on both hardware types.
537 */
538 val |= SDHCI_CLOCK_INT_EN;
539 if (RD4(sc, SDHC_PRES_STATE) & SDHC_PRES_SDSTB)
540 val |= SDHCI_CLOCK_INT_STABLE;
541
542 /*
543 * On i.MX ESDHC hardware the card bus clock enable is in the usual
544 * sdhci register but it's a different bit, so transcribe it (note the
545 * difference between standard SDHCI_ and Freescale SDHC_ prefixes
546 * here). On USDHC and QorIQ ESDHC hardware there is a force-on bit, but
547 * no force-off for the card bus clock (the hardware runs the clock when
548 * transfers are active no matter what), so we always say the clock is
549 * on.
550 * XXX Maybe we should say it's in whatever state the sdhci driver last
551 * set it to.
552 */
553 if (sc->hwtype == HWTYPE_ESDHC) {
554#ifdef __arm__
555 if (RD4(sc, SDHC_SYS_CTRL) & SDHC_CLK_SDCLKEN)
556#endif
557 val |= SDHCI_CLOCK_CARD_EN;
558 } else {
559 val |= SDHCI_CLOCK_CARD_EN;
560 }
561
562 return (val);
563}
564
565static void
566fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val)
567{
568 uint32_t divisor, freq, prescale, val32;
569
570 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
571
572 /*
573 * Save the frequency-setting bits in SDHCI format so that we can play
574 * them back in get_clock without complex decoding of hardware regs,
575 * then deal with the freqency part of the value based on hardware type.
576 */
577 sc->sdclockreg_freq_bits = val & SDHCI_DIVIDERS_MASK;
578 if (sc->hwtype == HWTYPE_ESDHC) {
579 /*
580 * The i.MX5 ESDHC hardware requires the driver to manually
581 * start and stop the sd bus clock. If the enable bit is not
582 * set, turn off the clock in hardware and we're done, otherwise
583 * decode the requested frequency. ESDHC hardware is sdhci 2.0;
584 * the sdhci driver will use the original 8-bit divisor field
585 * and the "base / 2^N" divisor scheme.
586 */
587 if ((val & SDHCI_CLOCK_CARD_EN) == 0) {
588#ifdef __arm__
589 /* On QorIQ, this is a reserved bit. */
590 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHC_CLK_SDCLKEN);
591#endif
592 return;
593
594 }
595 divisor = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;
596 freq = sc->baseclk_hz >> ffs(divisor);
597 } else {
598 /*
599 * The USDHC hardware provides only "force always on" control
600 * over the sd bus clock, but no way to turn it off. (If a cmd
601 * or data transfer is in progress the clock is on, otherwise it
602 * is off.) If the clock is being disabled, we can just return
603 * now, otherwise we decode the requested frequency. USDHC
604 * hardware is sdhci 3.0; the sdhci driver will use a 10-bit
605 * divisor using the "base / 2*N" divisor scheme.
606 */
607 if ((val & SDHCI_CLOCK_CARD_EN) == 0)
608 return;
609 divisor = ((val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK) |
610 ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) <<
611 SDHCI_DIVIDER_MASK_LEN;
612 if (divisor == 0)
613 freq = sc->baseclk_hz;
614 else
615 freq = sc->baseclk_hz / (2 * divisor);
616 }
617
618 /*
619 * Get a prescaler and final divisor to achieve the desired frequency.
620 */
621 for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16);)
622 prescale <<= 1;
623
624 for (divisor = 1; freq < sc->baseclk_hz / (prescale * divisor);)
625 ++divisor;
626
627#ifdef DEBUG
628 device_printf(sc->dev,
629 "desired SD freq: %d, actual: %d; base %d prescale %d divisor %d\n",
630 freq, sc->baseclk_hz / (prescale * divisor), sc->baseclk_hz,
631 prescale, divisor);
632#endif
633
634 /*
635 * Adjust to zero-based values, and store them to the hardware.
636 */
637 prescale >>= 1;
638 divisor -= 1;
639
640 val32 &= ~(SDHC_CLK_DIVISOR_MASK | SDHC_CLK_PRESCALE_MASK);
641 val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT;
642 val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT;
643 val32 |= SDHC_CLK_IPGEN;
644 WR4(sc, SDHCI_CLOCK_CONTROL, val32);
645}
646
647static boolean_t
648fsl_sdhci_r1bfix_is_wait_done(struct fsl_sdhci_softc *sc)
649{
650 uint32_t inhibit;
651
652 mtx_assert(&sc->slot.mtx, MA_OWNED);
653
654 /*
655 * Check the DAT0 line status using both the DLA (data line active) and
656 * CDIHB (data inhibit) bits in the present state register. In theory
657 * just DLA should do the trick, but in practice it takes both. If the
658 * DAT0 line is still being held and we're not yet beyond the timeout
659 * point, just schedule another callout to check again later.
660 */
661 inhibit = RD4(sc, SDHC_PRES_STATE) & (SDHC_PRES_DLA | SDHC_PRES_CDIHB);
662
663 if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) {
664 callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0,
665 fsl_sdhci_r1bfix_func, sc, 0);
666 return (false);
667 }
668
669 /*
670 * If we reach this point with the inhibit bits still set, we've got a
671 * timeout, synthesize a DATA_TIMEOUT interrupt. Otherwise the DAT0
672 * line has been released, and we synthesize a DATA_END, and if the type
673 * of fix needed was on a command-without-data we also now add in the
674 * original INT_RESPONSE that we suppressed earlier.
675 */
676 if (inhibit)
677 sc->r1bfix_intmask |= SDHCI_INT_DATA_TIMEOUT;
678 else {
679 sc->r1bfix_intmask |= SDHCI_INT_DATA_END;
680 if (sc->r1bfix_type == R1BFIX_NODATA)
681 sc->r1bfix_intmask |= SDHCI_INT_RESPONSE;
682 }
683
684 sc->r1bfix_type = R1BFIX_NONE;
685 return (true);
686}
687
688static void
689fsl_sdhci_r1bfix_func(void * arg)
690{
691 struct fsl_sdhci_softc *sc = arg;
692 boolean_t r1bwait_done;
693
694 mtx_lock(&sc->slot.mtx);
695 r1bwait_done = fsl_sdhci_r1bfix_is_wait_done(sc);
696 mtx_unlock(&sc->slot.mtx);
697 if (r1bwait_done)
698 sdhci_generic_intr(&sc->slot);
699}
700
701static void
702fsl_sdhci_intr(void *arg)
703{
704 struct fsl_sdhci_softc *sc = arg;
705 uint32_t intmask;
706
707 mtx_lock(&sc->slot.mtx);
708
709 /*
710 * Manually check the DAT0 line for R1B response types that the
711 * controller fails to handle properly. The controller asserts the done
712 * interrupt while the card is still asserting busy with the DAT0 line.
713 *
714 * We check DAT0 immediately because most of the time, especially on a
715 * read, the card will actually be done by time we get here. If it's
716 * not, then the wait_done routine will schedule a callout to re-check
717 * periodically until it is done. In that case we clear the interrupt
718 * out of the hardware now so that we can present it later when the DAT0
719 * line is released.
720 *
721 * If we need to wait for the DAT0 line to be released, we set up a
722 * timeout point 250ms in the future. This number comes from the SD
723 * spec, which allows a command to take that long. In the real world,
724 * cards tend to take 10-20ms for a long-running command such as a write
725 * or erase that spans two pages.
726 */
727 switch (sc->r1bfix_type) {
728 case R1BFIX_NODATA:
729 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_RESPONSE;
730 break;
731 case R1BFIX_AC12:
732 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_DATA_END;
733 break;
734 default:
735 intmask = 0;
736 break;
737 }
738 if (intmask) {
739 sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS;
740 if (!fsl_sdhci_r1bfix_is_wait_done(sc)) {
741 WR4(sc, SDHCI_INT_STATUS, intmask);
742 bus_barrier(sc->mem_res, SDHCI_INT_STATUS, 4,
743 BUS_SPACE_BARRIER_WRITE);
744 }
745 }
746
747 mtx_unlock(&sc->slot.mtx);
748 sdhci_generic_intr(&sc->slot);
749}
750
751static int
752fsl_sdhci_get_ro(device_t bus, device_t child)
753{
754 struct fsl_sdhci_softc *sc = device_get_softc(bus);
755
756 return (sdhci_fdt_gpio_get_readonly(sc->gpio));
757}
758
759static bool
760fsl_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot)
761{
762 struct fsl_sdhci_softc *sc = device_get_softc(dev);
763
764 return (sdhci_fdt_gpio_get_present(sc->gpio));
765}
766
767#ifdef __powerpc__
768static uint32_t
769fsl_sdhci_get_platform_clock(device_t dev)
770{
771 device_t parent;
772 phandle_t node;
773 uint32_t clock;
774
775 node = ofw_bus_get_node(dev);
776
777 /* Get sdhci node properties */
778 if((OF_getprop(node, "clock-frequency", (void *)&clock,
779 sizeof(clock)) <= 0) || (clock == 0)) {
780
781 /*
782 * Trying to get clock from parent device (soc) if correct
783 * clock cannot be acquired from sdhci node.
784 */
785 parent = device_get_parent(dev);
786 node = ofw_bus_get_node(parent);
787
788 /* Get soc properties */
789 if ((OF_getprop(node, "bus-frequency", (void *)&clock,
790 sizeof(clock)) <= 0) || (clock == 0)) {
791 device_printf(dev,"Cannot acquire correct sdhci "
792 "frequency from DTS.\n");
793
794 return (0);
795 }
796 /* eSDHC clock is 1/2 platform clock. */
797 clock /= 2;
798 }
799
800 if (bootverbose)
801 device_printf(dev, "Acquired clock: %d from DTS\n", clock);
802
803 return (clock);
804}
805#endif
806
807
808static int
809fsl_sdhci_detach(device_t dev)
810{
811 struct fsl_sdhci_softc *sc = device_get_softc(dev);
812
813 if (sc->gpio != NULL)
814 sdhci_fdt_gpio_teardown(sc->gpio);
815
816 callout_drain(&sc->r1bfix_callout);
817
|
844 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
845 if (sc->hwtype == HWTYPE_NONE)
846 panic("Impossible: not compatible in fsl_sdhci_attach()");
847
848 rid = 0;
849 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
850 RF_ACTIVE);
851 if (!sc->mem_res) {
852 device_printf(dev, "cannot allocate memory window\n");
853 err = ENXIO;
854 goto fail;
855 }
856
857 rid = 0;
858 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
859 RF_ACTIVE);
860 if (!sc->irq_res) {
861 device_printf(dev, "cannot allocate interrupt\n");
862 err = ENXIO;
863 goto fail;
864 }
865
866 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
867 NULL, fsl_sdhci_intr, sc, &sc->intr_cookie)) {
868 device_printf(dev, "cannot setup interrupt handler\n");
869 err = ENXIO;
870 goto fail;
871 }
872
873 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
874
875 /*
876 * DMA is not really broken, I just haven't implemented it yet.
877 */
878 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA;
879
880 /*
881 * Set the buffer watermark level to 128 words (512 bytes) for both read
882 * and write. The hardware has a restriction that when the read or
883 * write ready status is asserted, that means you can read exactly the
884 * number of words set in the watermark register before you have to
885 * re-check the status and potentially wait for more data. The main
886 * sdhci driver provides no hook for doing status checking on less than
887 * a full block boundary, so we set the watermark level to be a full
888 * block. Reads and writes where the block size is less than the
889 * watermark size will work correctly too, no need to change the
890 * watermark for different size blocks. However, 128 is the maximum
891 * allowed for the watermark, so PIO is limitted to 512 byte blocks
892 * (which works fine for SD cards, may be a problem for SDIO some day).
893 *
894 * XXX need named constants for this stuff.
895 */
896 /* P1022 has the '*_BRST_LEN' fields as reserved, always reading 0x10 */
897 if (ofw_bus_is_compatible(dev, "fsl,p1022-esdhc"))
898 WR4(sc, SDHC_WTMK_LVL, 0x10801080);
899 else
900 WR4(sc, SDHC_WTMK_LVL, 0x08800880);
901
902 /*
903 * We read in native byte order in the main driver, but the register
904 * defaults to little endian.
905 */
906#ifdef __powerpc__
907 sc->baseclk_hz = fsl_sdhci_get_platform_clock(dev);
908#else
909 sc->baseclk_hz = imx_ccm_sdhci_hz();
910#endif
911 sc->slot.max_clk = sc->baseclk_hz;
912
913 /*
914 * Set up any gpio pin handling described in the FDT data. This cannot
915 * fail; see comments in sdhci_fdt_gpio.h for details.
916 */
917 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot);
918
919#ifdef __powerpc__
920 node = ofw_bus_get_node(dev);
921 /* Default to big-endian on powerpc */
922 protctl = RD4(sc, SDHC_PROT_CTRL);
923 protctl &= ~SDHC_PROT_EMODE_MASK;
924 if (OF_hasprop(node, "little-endian"))
925 protctl |= SDHC_PROT_EMODE_LITTLE;
926 else
927 protctl |= SDHC_PROT_EMODE_BIG;
928 WR4(sc, SDHC_PROT_CTRL, protctl);
929#endif
930
| 849 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
850 if (sc->hwtype == HWTYPE_NONE)
851 panic("Impossible: not compatible in fsl_sdhci_attach()");
852
853 rid = 0;
854 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
855 RF_ACTIVE);
856 if (!sc->mem_res) {
857 device_printf(dev, "cannot allocate memory window\n");
858 err = ENXIO;
859 goto fail;
860 }
861
862 rid = 0;
863 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
864 RF_ACTIVE);
865 if (!sc->irq_res) {
866 device_printf(dev, "cannot allocate interrupt\n");
867 err = ENXIO;
868 goto fail;
869 }
870
871 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
872 NULL, fsl_sdhci_intr, sc, &sc->intr_cookie)) {
873 device_printf(dev, "cannot setup interrupt handler\n");
874 err = ENXIO;
875 goto fail;
876 }
877
878 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
879
880 /*
881 * DMA is not really broken, I just haven't implemented it yet.
882 */
883 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA;
884
885 /*
886 * Set the buffer watermark level to 128 words (512 bytes) for both read
887 * and write. The hardware has a restriction that when the read or
888 * write ready status is asserted, that means you can read exactly the
889 * number of words set in the watermark register before you have to
890 * re-check the status and potentially wait for more data. The main
891 * sdhci driver provides no hook for doing status checking on less than
892 * a full block boundary, so we set the watermark level to be a full
893 * block. Reads and writes where the block size is less than the
894 * watermark size will work correctly too, no need to change the
895 * watermark for different size blocks. However, 128 is the maximum
896 * allowed for the watermark, so PIO is limitted to 512 byte blocks
897 * (which works fine for SD cards, may be a problem for SDIO some day).
898 *
899 * XXX need named constants for this stuff.
900 */
901 /* P1022 has the '*_BRST_LEN' fields as reserved, always reading 0x10 */
902 if (ofw_bus_is_compatible(dev, "fsl,p1022-esdhc"))
903 WR4(sc, SDHC_WTMK_LVL, 0x10801080);
904 else
905 WR4(sc, SDHC_WTMK_LVL, 0x08800880);
906
907 /*
908 * We read in native byte order in the main driver, but the register
909 * defaults to little endian.
910 */
911#ifdef __powerpc__
912 sc->baseclk_hz = fsl_sdhci_get_platform_clock(dev);
913#else
914 sc->baseclk_hz = imx_ccm_sdhci_hz();
915#endif
916 sc->slot.max_clk = sc->baseclk_hz;
917
918 /*
919 * Set up any gpio pin handling described in the FDT data. This cannot
920 * fail; see comments in sdhci_fdt_gpio.h for details.
921 */
922 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot);
923
924#ifdef __powerpc__
925 node = ofw_bus_get_node(dev);
926 /* Default to big-endian on powerpc */
927 protctl = RD4(sc, SDHC_PROT_CTRL);
928 protctl &= ~SDHC_PROT_EMODE_MASK;
929 if (OF_hasprop(node, "little-endian"))
930 protctl |= SDHC_PROT_EMODE_LITTLE;
931 else
932 protctl |= SDHC_PROT_EMODE_BIG;
933 WR4(sc, SDHC_PROT_CTRL, protctl);
934#endif
935
|
933
934 bus_generic_probe(dev);
935 bus_generic_attach(dev);
936
937 sdhci_start_slot(&sc->slot);
938
939 return (0);
940
941fail:
942 fsl_sdhci_detach(dev);
943 return (err);
944}
945
946static int
947fsl_sdhci_probe(device_t dev)
948{
949
950 if (!ofw_bus_status_okay(dev))
951 return (ENXIO);
952
953 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
954 case HWTYPE_ESDHC:
955 device_set_desc(dev, "Freescale eSDHC controller");
956 return (BUS_PROBE_DEFAULT);
957 case HWTYPE_USDHC:
958 device_set_desc(dev, "Freescale uSDHC controller");
959 return (BUS_PROBE_DEFAULT);
960 default:
961 break;
962 }
963 return (ENXIO);
964}
965
966static device_method_t fsl_sdhci_methods[] = {
967 /* Device interface */
968 DEVMETHOD(device_probe, fsl_sdhci_probe),
969 DEVMETHOD(device_attach, fsl_sdhci_attach),
970 DEVMETHOD(device_detach, fsl_sdhci_detach),
971
972 /* Bus interface */
973 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
974 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
975
976 /* MMC bridge interface */
977 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
978 DEVMETHOD(mmcbr_request, sdhci_generic_request),
979 DEVMETHOD(mmcbr_get_ro, fsl_sdhci_get_ro),
980 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
981 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
982
983 /* SDHCI accessors */
984 DEVMETHOD(sdhci_read_1, fsl_sdhci_read_1),
985 DEVMETHOD(sdhci_read_2, fsl_sdhci_read_2),
986 DEVMETHOD(sdhci_read_4, fsl_sdhci_read_4),
987 DEVMETHOD(sdhci_read_multi_4, fsl_sdhci_read_multi_4),
988 DEVMETHOD(sdhci_write_1, fsl_sdhci_write_1),
989 DEVMETHOD(sdhci_write_2, fsl_sdhci_write_2),
990 DEVMETHOD(sdhci_write_4, fsl_sdhci_write_4),
991 DEVMETHOD(sdhci_write_multi_4, fsl_sdhci_write_multi_4),
992 DEVMETHOD(sdhci_get_card_present,fsl_sdhci_get_card_present),
993
994 DEVMETHOD_END
995};
996
997static devclass_t fsl_sdhci_devclass;
998
999static driver_t fsl_sdhci_driver = {
1000 "sdhci_fsl",
1001 fsl_sdhci_methods,
1002 sizeof(struct fsl_sdhci_softc),
1003};
1004
1005DRIVER_MODULE(sdhci_fsl, simplebus, fsl_sdhci_driver, fsl_sdhci_devclass,
1006 NULL, NULL);
1007MODULE_DEPEND(sdhci_fsl, sdhci, 1, 1, 1);
1008MMC_DECLARE_BRIDGE(sdhci_fsl);
| 938
939 bus_generic_probe(dev);
940 bus_generic_attach(dev);
941
942 sdhci_start_slot(&sc->slot);
943
944 return (0);
945
946fail:
947 fsl_sdhci_detach(dev);
948 return (err);
949}
950
951static int
952fsl_sdhci_probe(device_t dev)
953{
954
955 if (!ofw_bus_status_okay(dev))
956 return (ENXIO);
957
958 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
959 case HWTYPE_ESDHC:
960 device_set_desc(dev, "Freescale eSDHC controller");
961 return (BUS_PROBE_DEFAULT);
962 case HWTYPE_USDHC:
963 device_set_desc(dev, "Freescale uSDHC controller");
964 return (BUS_PROBE_DEFAULT);
965 default:
966 break;
967 }
968 return (ENXIO);
969}
970
971static device_method_t fsl_sdhci_methods[] = {
972 /* Device interface */
973 DEVMETHOD(device_probe, fsl_sdhci_probe),
974 DEVMETHOD(device_attach, fsl_sdhci_attach),
975 DEVMETHOD(device_detach, fsl_sdhci_detach),
976
977 /* Bus interface */
978 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
979 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
980
981 /* MMC bridge interface */
982 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
983 DEVMETHOD(mmcbr_request, sdhci_generic_request),
984 DEVMETHOD(mmcbr_get_ro, fsl_sdhci_get_ro),
985 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
986 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
987
988 /* SDHCI accessors */
989 DEVMETHOD(sdhci_read_1, fsl_sdhci_read_1),
990 DEVMETHOD(sdhci_read_2, fsl_sdhci_read_2),
991 DEVMETHOD(sdhci_read_4, fsl_sdhci_read_4),
992 DEVMETHOD(sdhci_read_multi_4, fsl_sdhci_read_multi_4),
993 DEVMETHOD(sdhci_write_1, fsl_sdhci_write_1),
994 DEVMETHOD(sdhci_write_2, fsl_sdhci_write_2),
995 DEVMETHOD(sdhci_write_4, fsl_sdhci_write_4),
996 DEVMETHOD(sdhci_write_multi_4, fsl_sdhci_write_multi_4),
997 DEVMETHOD(sdhci_get_card_present,fsl_sdhci_get_card_present),
998
999 DEVMETHOD_END
1000};
1001
1002static devclass_t fsl_sdhci_devclass;
1003
1004static driver_t fsl_sdhci_driver = {
1005 "sdhci_fsl",
1006 fsl_sdhci_methods,
1007 sizeof(struct fsl_sdhci_softc),
1008};
1009
1010DRIVER_MODULE(sdhci_fsl, simplebus, fsl_sdhci_driver, fsl_sdhci_devclass,
1011 NULL, NULL);
1012MODULE_DEPEND(sdhci_fsl, sdhci, 1, 1, 1);
1013MMC_DECLARE_BRIDGE(sdhci_fsl);
|