| if_rlreg.h (52426) | if_rlreg.h (67087) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/pci/if_rlreg.h 52426 1999-10-21 19:42:03Z wpaul $ | 32 * $FreeBSD: head/sys/pci/if_rlreg.h 67087 2000-10-13 17:54:19Z wpaul $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 322 unchanged lines hidden (view full) --- 363 void *rl_intrhand; 364 device_t rl_miibus; 365 u_int8_t rl_unit; /* interface number */ 366 u_int8_t rl_type; 367 u_int8_t rl_stats_no_timeout; 368 int rl_txthresh; 369 struct rl_chain_data rl_cdata; 370 struct callout_handle rl_stat_ch; | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 322 unchanged lines hidden (view full) --- 363 void *rl_intrhand; 364 device_t rl_miibus; 365 u_int8_t rl_unit; /* interface number */ 366 u_int8_t rl_type; 367 u_int8_t rl_stats_no_timeout; 368 int rl_txthresh; 369 struct rl_chain_data rl_cdata; 370 struct callout_handle rl_stat_ch; |
| 371 struct mtx rl_mtx; |
|
| 371}; 372 | 372}; 373 |
| 374#define RL_LOCK(_sc) mtx_enter(&(_sc)->rl_mtx, MTX_DEF) 375#define RL_UNLOCK(_sc) mtx_exit(&(_sc)->rl_mtx, MTX_DEF) 376 |
|
| 373/* 374 * register space access macros 375 */ 376#define CSR_WRITE_4(sc, reg, val) \ 377 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 378#define CSR_WRITE_2(sc, reg, val) \ 379 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 380#define CSR_WRITE_1(sc, reg, val) \ --- 93 unchanged lines hidden --- | 377/* 378 * register space access macros 379 */ 380#define CSR_WRITE_4(sc, reg, val) \ 381 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 382#define CSR_WRITE_2(sc, reg, val) \ 383 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 384#define CSR_WRITE_1(sc, reg, val) \ --- 93 unchanged lines hidden --- |