| if_rlreg.h (50703) | if_rlreg.h (52426) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/pci/if_rlreg.h 50703 1999-08-31 14:45:51Z wpaul $ | 32 * $FreeBSD: head/sys/pci/if_rlreg.h 52426 1999-10-21 19:42:03Z wpaul $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 253 unchanged lines hidden (view full) --- 294 * For reception, there's just one large buffer where the chip stores 295 * all received packets. 296 */ 297 298#define RL_RX_BUF_SZ RL_RXBUF_64 299#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 300#define RL_TX_LIST_CNT 4 301#define RL_MIN_FRAMELEN 60 | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 253 unchanged lines hidden (view full) --- 294 * For reception, there's just one large buffer where the chip stores 295 * all received packets. 296 */ 297 298#define RL_RX_BUF_SZ RL_RXBUF_64 299#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 300#define RL_TX_LIST_CNT 4 301#define RL_MIN_FRAMELEN 60 |
| 302#define RL_TX_EARLYTHRESH (256 << 11) | 302#define RL_TXTHRESH(x) ((x) << 11) 303#define RL_TX_THRESH_INIT 96 |
| 303#define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES 304#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 305#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 306 307#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 308#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 309 310#define RL_ETHER_ALIGN 2 --- 48 unchanged lines hidden (view full) --- 359 bus_space_tag_t rl_btag; /* bus space tag */ 360 struct resource *rl_res; 361 struct resource *rl_irq; 362 void *rl_intrhand; 363 device_t rl_miibus; 364 u_int8_t rl_unit; /* interface number */ 365 u_int8_t rl_type; 366 u_int8_t rl_stats_no_timeout; | 304#define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES 305#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 306#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 307 308#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 309#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 310 311#define RL_ETHER_ALIGN 2 --- 48 unchanged lines hidden (view full) --- 360 bus_space_tag_t rl_btag; /* bus space tag */ 361 struct resource *rl_res; 362 struct resource *rl_irq; 363 void *rl_intrhand; 364 device_t rl_miibus; 365 u_int8_t rl_unit; /* interface number */ 366 u_int8_t rl_type; 367 u_int8_t rl_stats_no_timeout; |
| 368 int rl_txthresh; |
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| 367 struct rl_chain_data rl_cdata; 368 struct callout_handle rl_stat_ch; 369}; 370 371/* 372 * register space access macros 373 */ 374#define CSR_WRITE_4(sc, reg, val) \ --- 97 unchanged lines hidden --- | 369 struct rl_chain_data rl_cdata; 370 struct callout_handle rl_stat_ch; 371}; 372 373/* 374 * register space access macros 375 */ 376#define CSR_WRITE_4(sc, reg, val) \ --- 97 unchanged lines hidden --- |