| if_rlreg.h (41243) | if_rlreg.h (41569) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $Id: if_rlreg.h,v 1.13 1998/11/18 20:27:28 wpaul Exp $ | 32 * $Id: if_rlreg.h,v 1.14 1998/12/07 00:16:44 wpaul Exp $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 285 unchanged lines hidden (view full) --- 326#define RL_FLAG_DELAYTIMEO 3 327 328#define RL_8129 1 329#define RL_8139 2 330 331struct rl_softc { 332 struct arpcom arpcom; /* interface info */ 333 struct ifmedia ifmedia; /* media info */ | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 285 unchanged lines hidden (view full) --- 326#define RL_FLAG_DELAYTIMEO 3 327 328#define RL_8129 1 329#define RL_8139 2 330 331struct rl_softc { 332 struct arpcom arpcom; /* interface info */ 333 struct ifmedia ifmedia; /* media info */ |
| 334 u_int32_t iobase; /* pointer to PIO space */ 335#ifndef RL_USEIOSPACE 336 volatile caddr_t csr; /* pointer to register map */ 337#endif | 334 bus_space_handle_t rl_bhandle; /* bus space handle */ 335 bus_space_tag_t rl_btag; /* bus space tag */ |
| 338 struct rl_type *rl_pinfo; /* phy info */ 339 u_int8_t rl_unit; /* interface number */ 340 u_int8_t rl_type; 341 u_int8_t rl_phy_addr; /* PHY address */ 342 u_int8_t rl_tx_pend; /* TX pending */ 343 u_int8_t rl_want_auto; 344 u_int8_t rl_autoneg; 345 u_int8_t rl_stats_no_timeout; 346 struct rl_chain_data rl_cdata; 347}; 348 349/* 350 * register space access macros 351 */ | 336 struct rl_type *rl_pinfo; /* phy info */ 337 u_int8_t rl_unit; /* interface number */ 338 u_int8_t rl_type; 339 u_int8_t rl_phy_addr; /* PHY address */ 340 u_int8_t rl_tx_pend; /* TX pending */ 341 u_int8_t rl_want_auto; 342 u_int8_t rl_autoneg; 343 u_int8_t rl_stats_no_timeout; 344 struct rl_chain_data rl_cdata; 345}; 346 347/* 348 * register space access macros 349 */ |
| 352#ifdef RL_USEIOSPACE | |
| 353#define CSR_WRITE_4(sc, reg, val) \ | 350#define CSR_WRITE_4(sc, reg, val) \ |
| 354 outl(sc->iobase + (u_int32_t)(reg), val) | 351 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) |
| 355#define CSR_WRITE_2(sc, reg, val) \ | 352#define CSR_WRITE_2(sc, reg, val) \ |
| 356 outw(sc->iobase + (u_int32_t)(reg), val) | 353 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) |
| 357#define CSR_WRITE_1(sc, reg, val) \ | 354#define CSR_WRITE_1(sc, reg, val) \ |
| 358 outb(sc->iobase + (u_int32_t)(reg), val) | 355 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) |
| 359 | 356 |
| 360#define CSR_READ_4(sc, reg) \ 361 inl(sc->iobase + (u_int32_t)(reg)) 362#define CSR_READ_2(sc, reg) \ 363 inw(sc->iobase + (u_int32_t)(reg)) 364#define CSR_READ_1(sc, reg) \ 365 inb(sc->iobase + (u_int32_t)(reg)) 366#else 367#define CSR_WRITE_4(sc, reg, val) \ 368 ((*(u_int32_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int32_t)(val)) 369#define CSR_WRITE_2(sc, reg, val) \ 370 ((*(u_int16_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int16_t)(val)) 371#define CSR_WRITE_1(sc, reg, val) \ 372 ((*(u_int8_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int8_t)(val)) | 357#define CSR_READ_4(sc, reg) \ 358 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 359#define CSR_READ_2(sc, reg) \ 360 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 361#define CSR_READ_1(sc, reg) \ 362 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) |
| 373 | 363 |
| 374#define CSR_READ_4(sc, reg) \ 375 (*(u_int32_t *)((sc)->csr + (u_int32_t)(reg))) 376#define CSR_READ_2(sc, reg) \ 377 (*(u_int16_t *)((sc)->csr + (u_int32_t)(reg))) 378#define CSR_READ_1(sc, reg) \ 379 (*(u_int8_t *)((sc)->csr + (u_int32_t)(reg))) 380#endif 381 | |
| 382#define RL_TIMEOUT 1000 383 384/* 385 * General constants that are fun to know. 386 * 387 * RealTek PCI vendor ID 388 */ 389#define RT_VENDORID 0x10EC --- 183 unchanged lines hidden --- | 364#define RL_TIMEOUT 1000 365 366/* 367 * General constants that are fun to know. 368 * 369 * RealTek PCI vendor ID 370 */ 371#define RT_VENDORID 0x10EC --- 183 unchanged lines hidden --- |