| if_rlreg.h (117388) | if_rlreg.h (118586) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/pci/if_rlreg.h 117388 2003-07-10 20:38:48Z wpaul $ | 32 * $FreeBSD: head/sys/pci/if_rlreg.h 118586 2003-08-07 07:00:30Z wpaul $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 74 unchanged lines hidden (view full) --- 115#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 116#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 117#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 118#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 119 120/* 121 * Registers specific to the 8169 gigE chip 122 */ | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 74 unchanged lines hidden (view full) --- 115#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 116#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 117#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 118#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 119 120/* 121 * Registers specific to the 8169 gigE chip 122 */ |
| 123#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ |
|
| 123#define RL_PHYAR 0x0060 124#define RL_TBICSR 0x0064 125#define RL_TBI_ANAR 0x0068 126#define RL_TBI_LPAR 0x006A 127#define RL_GMEDIASTAT 0x006C /* 8 bits */ 128#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 129#define RL_GTXSTART 0x0038 /* 16 bits */ 130 131/* 132 * TX config register bits 133 */ 134#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 135#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 136#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 137#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 138#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 139#define RL_TXCFG_HWREV 0x7CC00000 140 | 124#define RL_PHYAR 0x0060 125#define RL_TBICSR 0x0064 126#define RL_TBI_ANAR 0x0068 127#define RL_TBI_LPAR 0x006A 128#define RL_GMEDIASTAT 0x006C /* 8 bits */ 129#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 130#define RL_GTXSTART 0x0038 /* 16 bits */ 131 132/* 133 * TX config register bits 134 */ 135#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 136#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 137#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 138#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 139#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 140#define RL_TXCFG_HWREV 0x7CC00000 141 |
| 142#define RL_HWREV_8169 0x00000000 143#define RL_HWREV_8110 0x00800000 |
|
| 141#define RL_HWREV_8139 0x60000000 142#define RL_HWREV_8139A 0x70000000 143#define RL_HWREV_8139AG 0x70800000 144#define RL_HWREV_8139B 0x78000000 145#define RL_HWREV_8130 0x7C000000 146#define RL_HWREV_8139C 0x74000000 147#define RL_HWREV_8139D 0x74400000 148#define RL_HWREV_8139CPLUS 0x74800000 | 144#define RL_HWREV_8139 0x60000000 145#define RL_HWREV_8139A 0x70000000 146#define RL_HWREV_8139AG 0x70800000 147#define RL_HWREV_8139B 0x78000000 148#define RL_HWREV_8130 0x7C000000 149#define RL_HWREV_8139C 0x74000000 150#define RL_HWREV_8139D 0x74400000 151#define RL_HWREV_8139CPLUS 0x74800000 |
| 152#define RL_HWREV_8101 0x74c00000 153#define RL_HWREV_8100 0x78800000 |
|
| 149 150#define RL_TXDMA_16BYTES 0x00000000 151#define RL_TXDMA_32BYTES 0x00000100 152#define RL_TXDMA_64BYTES 0x00000200 153#define RL_TXDMA_128BYTES 0x00000300 154#define RL_TXDMA_256BYTES 0x00000400 155#define RL_TXDMA_512BYTES 0x00000500 156#define RL_TXDMA_1024BYTES 0x00000600 --- 681 unchanged lines hidden --- | 154 155#define RL_TXDMA_16BYTES 0x00000000 156#define RL_TXDMA_32BYTES 0x00000100 157#define RL_TXDMA_64BYTES 0x00000200 158#define RL_TXDMA_128BYTES 0x00000300 159#define RL_TXDMA_256BYTES 0x00000400 160#define RL_TXDMA_512BYTES 0x00000500 161#define RL_TXDMA_1024BYTES 0x00000600 --- 681 unchanged lines hidden --- |