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if_rlreg.h (112379) if_rlreg.h (117388)
1/*
1/*
2 * Copyright (c) 1997, 1998
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

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24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

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24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/pci/if_rlreg.h 112379 2003-03-18 14:57:09Z sanpei $
32 * $FreeBSD: head/sys/pci/if_rlreg.h 117388 2003-07-10 20:38:48Z wpaul $
33 */
34
35/*
36 * RealTek 8129/8139 register offsets
37 */
38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */
39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
40#define RL_IDR2 0x0002

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94#define RL_ANER 0x006A /* PHY autoneg expansion */
95
96#define RL_DISCCNT 0x006C /* disconnect counter */
97#define RL_FALSECAR 0x006E /* false carrier counter */
98#define RL_NWAYTST 0x0070 /* NWAY test register */
99#define RL_RX_ER 0x0072 /* RX_ER counter */
100#define RL_CSCFG 0x0074 /* CS configuration register */
101
33 */
34
35/*
36 * RealTek 8129/8139 register offsets
37 */
38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */
39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
40#define RL_IDR2 0x0002

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94#define RL_ANER 0x006A /* PHY autoneg expansion */
95
96#define RL_DISCCNT 0x006C /* disconnect counter */
97#define RL_FALSECAR 0x006E /* false carrier counter */
98#define RL_NWAYTST 0x0070 /* NWAY test register */
99#define RL_RX_ER 0x0072 /* RX_ER counter */
100#define RL_CSCFG 0x0074 /* CS configuration register */
101
102/*
103 * When operating in special C+ mode, some of the registers in an
104 * 8139C+ chip have different definitions. These are also used for
105 * the 8169 gigE chip.
106 */
107#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */
108#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */
109#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */
110#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */
111#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */
112#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */
113#define RL_TIMERINT 0x0054 /* interrupt on timer expire */
114#define RL_TXSTART 0x00D9 /* 8 bits */
115#define RL_CPLUS_CMD 0x00E0 /* 16 bits */
116#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */
117#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */
118#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */
102
103/*
119
120/*
121 * Registers specific to the 8169 gigE chip
122 */
123#define RL_PHYAR 0x0060
124#define RL_TBICSR 0x0064
125#define RL_TBI_ANAR 0x0068
126#define RL_TBI_LPAR 0x006A
127#define RL_GMEDIASTAT 0x006C /* 8 bits */
128#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
129#define RL_GTXSTART 0x0038 /* 16 bits */
130
131/*
104 * TX config register bits
105 */
106#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
107#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
108#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
109#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
110#define RL_TXCFG_IFG 0x03000000 /* interframe gap */
132 * TX config register bits
133 */
134#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
135#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
136#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
137#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
138#define RL_TXCFG_IFG 0x03000000 /* interframe gap */
139#define RL_TXCFG_HWREV 0x7CC00000
111
140
141#define RL_HWREV_8139 0x60000000
142#define RL_HWREV_8139A 0x70000000
143#define RL_HWREV_8139AG 0x70800000
144#define RL_HWREV_8139B 0x78000000
145#define RL_HWREV_8130 0x7C000000
146#define RL_HWREV_8139C 0x74000000
147#define RL_HWREV_8139D 0x74400000
148#define RL_HWREV_8139CPLUS 0x74800000
149
112#define RL_TXDMA_16BYTES 0x00000000
113#define RL_TXDMA_32BYTES 0x00000100
114#define RL_TXDMA_64BYTES 0x00000200
115#define RL_TXDMA_128BYTES 0x00000300
116#define RL_TXDMA_256BYTES 0x00000400
117#define RL_TXDMA_512BYTES 0x00000500
118#define RL_TXDMA_1024BYTES 0x00000600
119#define RL_TXDMA_2048BYTES 0x00000700

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137 */
138#define RL_ISR_RX_OK 0x0001
139#define RL_ISR_RX_ERR 0x0002
140#define RL_ISR_TX_OK 0x0004
141#define RL_ISR_TX_ERR 0x0008
142#define RL_ISR_RX_OVERRUN 0x0010
143#define RL_ISR_PKT_UNDERRUN 0x0020
144#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
150#define RL_TXDMA_16BYTES 0x00000000
151#define RL_TXDMA_32BYTES 0x00000100
152#define RL_TXDMA_64BYTES 0x00000200
153#define RL_TXDMA_128BYTES 0x00000300
154#define RL_TXDMA_256BYTES 0x00000400
155#define RL_TXDMA_512BYTES 0x00000500
156#define RL_TXDMA_1024BYTES 0x00000600
157#define RL_TXDMA_2048BYTES 0x00000700

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175 */
176#define RL_ISR_RX_OK 0x0001
177#define RL_ISR_RX_ERR 0x0002
178#define RL_ISR_TX_OK 0x0004
179#define RL_ISR_TX_ERR 0x0008
180#define RL_ISR_RX_OVERRUN 0x0010
181#define RL_ISR_PKT_UNDERRUN 0x0020
182#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
183#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */
184#define RL_ISR_SWI 0x0100 /* C+ only */
185#define RL_ISR_CABLE_LEN_CHGD 0x2000
145#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
186#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
187#define RL_ISR_TIMEOUT_EXPIRED 0x4000
146#define RL_ISR_SYSTEM_ERR 0x8000
147
148#define RL_INTRS \
149 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
150 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
151 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
152
188#define RL_ISR_SYSTEM_ERR 0x8000
189
190#define RL_INTRS \
191 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
192 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
193 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
194
195#define RL_INTRS_CPLUS \
196 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
197 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
198 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
199
153/*
154 * Media status register. (8139 only)
155 */
156#define RL_MEDIASTAT_RXPAUSE 0x01
157#define RL_MEDIASTAT_TXPAUSE 0x02
158#define RL_MEDIASTAT_LINK 0x04
159#define RL_MEDIASTAT_SPEED10 0x08
160#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */

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277#define RL_CFG1_MEMMAP 0x08
278#define RL_CFG1_RSVD 0x10
279#define RL_CFG1_DRVLOAD 0x20
280#define RL_CFG1_LED0 0x40
281#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */
282#define RL_CFG1_LED1 0x80
283
284/*
200/*
201 * Media status register. (8139 only)
202 */
203#define RL_MEDIASTAT_RXPAUSE 0x01
204#define RL_MEDIASTAT_TXPAUSE 0x02
205#define RL_MEDIASTAT_LINK 0x04
206#define RL_MEDIASTAT_SPEED10 0x08
207#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */

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324#define RL_CFG1_MEMMAP 0x08
325#define RL_CFG1_RSVD 0x10
326#define RL_CFG1_DRVLOAD 0x20
327#define RL_CFG1_LED0 0x40
328#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */
329#define RL_CFG1_LED1 0x80
330
331/*
332 * 8139C+ register definitions
333 */
334
335/* RL_DUMPSTATS_LO register */
336
337#define RL_DUMPSTATS_START 0x00000008
338
339/* Transmit start register */
340
341#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */
342#define RL_TXSTART_START 0x40 /* start normal queue transmit */
343#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */
344
345/* C+ mode command register */
346
347#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
348#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
349#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
350#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
351#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
352#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */
353
354/* C+ early transmit threshold */
355
356#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
357
358/*
359 * Gigabit PHY access register (8169 only)
360 */
361
362#define RL_PHYAR_PHYDATA 0x0000FFFF
363#define RL_PHYAR_PHYREG 0x001F0000
364#define RL_PHYAR_BUSY 0x80000000
365
366/*
367 * Gigabit media status (8169 only)
368 */
369#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */
370#define RL_GMEDIASTAT_LINK 0x02 /* link up */
371#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */
372#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */
373#define RL_GMEDIASTAT_1000MPS 0x10 /* gigE link */
374#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */
375#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */
376#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */
377
378/*
285 * The RealTek doesn't use a fragment-based descriptor mechanism.
286 * Instead, there are only four register sets, each or which represents
287 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
288 * packet buffer (32-bit aligned!) and we place the buffer addresses in
289 * the registers so the chip knows where they are.
290 *
291 * We can sort of kludge together the same kind of buffer management
292 * used in previous drivers, but we have to do buffer copies almost all

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331#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
332#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
333#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
334#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
335
336struct rl_type {
337 u_int16_t rl_vid;
338 u_int16_t rl_did;
379 * The RealTek doesn't use a fragment-based descriptor mechanism.
380 * Instead, there are only four register sets, each or which represents
381 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
382 * packet buffer (32-bit aligned!) and we place the buffer addresses in
383 * the registers so the chip knows where they are.
384 *
385 * We can sort of kludge together the same kind of buffer management
386 * used in previous drivers, but we have to do buffer copies almost all

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425#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
426#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
427#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
428#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
429
430struct rl_type {
431 u_int16_t rl_vid;
432 u_int16_t rl_did;
433 int rl_basetype;
339 char *rl_name;
340};
341
434 char *rl_name;
435};
436
437struct rl_hwrev {
438 u_int32_t rl_rev;
439 int rl_type;
440 char *rl_desc;
441};
442
342struct rl_mii_frame {
343 u_int8_t mii_stdelim;
344 u_int8_t mii_opcode;
345 u_int8_t mii_phyaddr;
346 u_int8_t mii_regaddr;
347 u_int8_t mii_turnaround;
348 u_int16_t mii_data;
349};
350
351/*
352 * MII constants
353 */
354#define RL_MII_STARTDELIM 0x01
355#define RL_MII_READOP 0x02
356#define RL_MII_WRITEOP 0x01
357#define RL_MII_TURNAROUND 0x02
358
359#define RL_8129 1
360#define RL_8139 2
443struct rl_mii_frame {
444 u_int8_t mii_stdelim;
445 u_int8_t mii_opcode;
446 u_int8_t mii_phyaddr;
447 u_int8_t mii_regaddr;
448 u_int8_t mii_turnaround;
449 u_int16_t mii_data;
450};
451
452/*
453 * MII constants
454 */
455#define RL_MII_STARTDELIM 0x01
456#define RL_MII_READOP 0x02
457#define RL_MII_WRITEOP 0x01
458#define RL_MII_TURNAROUND 0x02
459
460#define RL_8129 1
461#define RL_8139 2
462#define RL_8139CPLUS 3
463#define RL_8169 4
361
464
465#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \
466 (x)->rl_type == RL_8169)
467
468/*
469 * The 8139C+ and 8160 gigE chips support descriptor-based TX
470 * and RX. In fact, they even support TCP large send. Descriptors
471 * must be allocated in contiguous blocks that are aligned on a
472 * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
473 */
474
475/*
476 * RX/TX descriptor definition. When large send mode is enabled, the
477 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
478 * the checksum offload bits are disabled. The structure layout is
479 * the same for RX and TX descriptors
480 */
481
482struct rl_desc {
483 u_int32_t rl_cmdstat;
484 u_int32_t rl_vlanctl;
485 u_int32_t rl_bufaddr_lo;
486 u_int32_t rl_bufaddr_hi;
487};
488
489#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF
490#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */
491#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */
492#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
493#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
494#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */
495#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */
496#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */
497#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */
498#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */
499
500#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
501#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
502
503/*
504 * Error bits are valid only on the last descriptor of a frame
505 * (i.e. RL_TDESC_CMD_EOF == 1)
506 */
507
508#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */
509#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */
510#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */
511#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */
512#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */
513#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */
514#define RL_TDESC_STAT_OWN 0x80000000
515
516/*
517 * RX descriptor cmd/vlan definitions
518 */
519
520#define RL_RDESC_CMD_EOR 0x40000000
521#define RL_RDESC_CMD_OWN 0x80000000
522#define RL_RDESC_CMD_BUFLEN 0x00001FFF
523
524#define RL_RDESC_STAT_OWN 0x80000000
525#define RL_RDESC_STAT_EOR 0x40000000
526#define RL_RDESC_STAT_SOF 0x20000000
527#define RL_RDESC_STAT_EOF 0x10000000
528#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */
529#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */
530#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */
531#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */
532#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */
533#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */
534#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */
535#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */
536#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */
537#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */
538#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */
539#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */
540#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */
541#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */
542#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */
543
544#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available
545 (rl_vlandata valid)*/
546#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
547
548#define RL_PROTOID_NONIP 0x00000000
549#define RL_PROTOID_TCPIP 0x00010000
550#define RL_PROTOID_UDPIP 0x00020000
551#define RL_PROTOID_IP 0x00030000
552#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
553 RL_PROTOID_TCPIP)
554#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
555 RL_PROTOID_UDPIP)
556
557/*
558 * Statistics counter structure (8139C+ and 8169 only)
559 */
560struct rl_stats {
561 u_int32_t rl_tx_pkts_lo;
562 u_int32_t rl_tx_pkts_hi;
563 u_int32_t rl_tx_errs_lo;
564 u_int32_t rl_tx_errs_hi;
565 u_int32_t rl_tx_errs;
566 u_int16_t rl_missed_pkts;
567 u_int16_t rl_rx_framealign_errs;
568 u_int32_t rl_tx_onecoll;
569 u_int32_t rl_tx_multicolls;
570 u_int32_t rl_rx_ucasts_hi;
571 u_int32_t rl_rx_ucasts_lo;
572 u_int32_t rl_rx_bcasts_lo;
573 u_int32_t rl_rx_bcasts_hi;
574 u_int32_t rl_rx_mcasts;
575 u_int16_t rl_tx_aborts;
576 u_int16_t rl_rx_underruns;
577};
578
579#define RL_RX_DESC_CNT 64
580#define RL_TX_DESC_CNT 64
581#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc))
582#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc))
583#define RL_RING_ALIGN 256
584#define RL_IFQ_MAXLEN 512
585#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT)
586#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
587#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & \
588 RL_RDESC_STAT_FRAGLEN)
589#define RL_PKTSZ(x) ((x) >> 3)
590
591struct rl_softc;
592
593struct rl_dmaload_arg {
594 struct rl_softc *sc;
595 int rl_idx;
596 int rl_maxsegs;
597 struct rl_desc *rl_ring;
598};
599
600struct rl_list_data {
601 struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT];
602 struct mbuf *rl_rx_mbuf[RL_TX_DESC_CNT];
603 int rl_tx_prodidx;
604 int rl_rx_prodidx;
605 int rl_tx_considx;
606 int rl_tx_free;
607 bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT];
608 bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT];
609 bus_dma_tag_t rl_mtag; /* mbuf mapping tag */
610 bus_dma_tag_t rl_stag; /* stats mapping tag */
611 bus_dmamap_t rl_smap; /* stats map */
612 struct rl_stats *rl_stats;
613 u_int32_t rl_stats_addr;
614 bus_dma_tag_t rl_rx_list_tag;
615 bus_dmamap_t rl_rx_list_map;
616 struct rl_desc *rl_rx_list;
617 u_int32_t rl_rx_list_addr;
618 bus_dma_tag_t rl_tx_list_tag;
619 bus_dmamap_t rl_tx_list_map;
620 struct rl_desc *rl_tx_list;
621 u_int32_t rl_tx_list_addr;
622};
623
362struct rl_softc {
363 struct arpcom arpcom; /* interface info */
364 bus_space_handle_t rl_bhandle; /* bus space handle */
365 bus_space_tag_t rl_btag; /* bus space tag */
366 struct resource *rl_res;
367 struct resource *rl_irq;
368 void *rl_intrhand;
369 device_t rl_miibus;
370 bus_dma_tag_t rl_parent_tag;
371 bus_dma_tag_t rl_tag;
372 u_int8_t rl_unit; /* interface number */
373 u_int8_t rl_type;
374 int rl_eecmd_read;
375 u_int8_t rl_stats_no_timeout;
376 int rl_txthresh;
377 struct rl_chain_data rl_cdata;
624struct rl_softc {
625 struct arpcom arpcom; /* interface info */
626 bus_space_handle_t rl_bhandle; /* bus space handle */
627 bus_space_tag_t rl_btag; /* bus space tag */
628 struct resource *rl_res;
629 struct resource *rl_irq;
630 void *rl_intrhand;
631 device_t rl_miibus;
632 bus_dma_tag_t rl_parent_tag;
633 bus_dma_tag_t rl_tag;
634 u_int8_t rl_unit; /* interface number */
635 u_int8_t rl_type;
636 int rl_eecmd_read;
637 u_int8_t rl_stats_no_timeout;
638 int rl_txthresh;
639 struct rl_chain_data rl_cdata;
640 struct rl_list_data rl_ldata;
378 struct callout_handle rl_stat_ch;
379 struct mtx rl_mtx;
380 int suspended; /* 0 = normal 1 = suspended */
381#ifdef DEVICE_POLLING
382 int rxcycles;
383#endif
384
385 u_int32_t saved_maps[5]; /* pci data */

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419#define RT_VENDORID 0x10EC
420
421/*
422 * RealTek chip device IDs.
423 */
424#define RT_DEVICEID_8129 0x8129
425#define RT_DEVICEID_8138 0x8138
426#define RT_DEVICEID_8139 0x8139
641 struct callout_handle rl_stat_ch;
642 struct mtx rl_mtx;
643 int suspended; /* 0 = normal 1 = suspended */
644#ifdef DEVICE_POLLING
645 int rxcycles;
646#endif
647
648 u_int32_t saved_maps[5]; /* pci data */

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682#define RT_VENDORID 0x10EC
683
684/*
685 * RealTek chip device IDs.
686 */
687#define RT_DEVICEID_8129 0x8129
688#define RT_DEVICEID_8138 0x8138
689#define RT_DEVICEID_8139 0x8139
690#define RT_DEVICEID_8169 0x8169
427
691
692#define RT_REVID_8139CPLUS 0x20
693
428/*
429 * Accton PCI vendor ID
430 */
431#define ACCTON_VENDORID 0x1113
432
433/*
434 * Accton MPX 5030/5038 device ID.
435 */

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498/*
499 * Peppercon ROL-F device ID
500 */
501#define PEPPERCON_DEVICEID_ROLF 0x8139
502
503/*
504 * Planex Communications, Inc. vendor ID
505 */
694/*
695 * Accton PCI vendor ID
696 */
697#define ACCTON_VENDORID 0x1113
698
699/*
700 * Accton MPX 5030/5038 device ID.
701 */

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764/*
765 * Peppercon ROL-F device ID
766 */
767#define PEPPERCON_DEVICEID_ROLF 0x8139
768
769/*
770 * Planex Communications, Inc. vendor ID
771 */
506#define PLANEX_VENDORID 0x14ea
772#define PLANEX_VENDORID 0x14ea
507
508/*
509 * Planex FNW-3800-TX device ID
510 */
773
774/*
775 * Planex FNW-3800-TX device ID
776 */
511#define PLANEX_DEVICEID_FNW3800TX 0xab07
777#define PLANEX_DEVICEID_FNW3800TX 0xab07
512
513/*
778
779/*
780 * LevelOne vendor ID
781 */
782#define LEVEL1_VENDORID 0x018A
783
784/*
785 * LevelOne FPC-0106TX devide ID
786 */
787#define LEVEL1_DEVICEID_FPC0106TX 0x0106
788
789/*
790 * Compaq vendor ID
791 */
792#define CP_VENDORID 0x021B
793
794/*
795 * Edimax vendor ID
796 */
797#define EDIMAX_VENDORID 0x13D1
798
799/*
800 * Edimax EP-4103DL cardbus device ID
801 */
802#define EDIMAX_DEVICEID_EP4103DL 0xAB06
803
804/*
514 * PCI low memory base and low I/O base register, and
515 * other PCI registers.
516 */
517
518#define RL_PCI_VENDOR_ID 0x00
519#define RL_PCI_DEVICE_ID 0x02
520#define RL_PCI_COMMAND 0x04
521#define RL_PCI_STATUS 0x06

--- 25 unchanged lines hidden --- 		805 * PCI low memory base and low I/O base register, and
806 * other PCI registers.
807 */
808
809#define RL_PCI_VENDOR_ID 0x00
810#define RL_PCI_DEVICE_ID 0x02
811#define RL_PCI_COMMAND 0x04
812#define RL_PCI_STATUS 0x06

--- 25 unchanged lines hidden ---