1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
--- 13 unchanged lines hidden (view full) ---
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/pci/if_rlreg.h 112379 2003-03-18 14:57:09Z sanpei $
33 */
34
35/*
36 * RealTek 8129/8139 register offsets
37 */
38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */
39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
40#define RL_IDR2 0x0002
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94#define RL_ANER 0x006A /* PHY autoneg expansion */
95
96#define RL_DISCCNT 0x006C /* disconnect counter */
97#define RL_FALSECAR 0x006E /* false carrier counter */
98#define RL_NWAYTST 0x0070 /* NWAY test register */
99#define RL_RX_ER 0x0072 /* RX_ER counter */
100#define RL_CSCFG 0x0074 /* CS configuration register */
101
102
103/*
104 * TX config register bits
105 */
106#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
107#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
108#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
109#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
110#define RL_TXCFG_IFG 0x03000000 /* interframe gap */
111
112#define RL_TXDMA_16BYTES 0x00000000
113#define RL_TXDMA_32BYTES 0x00000100
114#define RL_TXDMA_64BYTES 0x00000200
115#define RL_TXDMA_128BYTES 0x00000300
116#define RL_TXDMA_256BYTES 0x00000400
117#define RL_TXDMA_512BYTES 0x00000500
118#define RL_TXDMA_1024BYTES 0x00000600
119#define RL_TXDMA_2048BYTES 0x00000700
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137 */
138#define RL_ISR_RX_OK 0x0001
139#define RL_ISR_RX_ERR 0x0002
140#define RL_ISR_TX_OK 0x0004
141#define RL_ISR_TX_ERR 0x0008
142#define RL_ISR_RX_OVERRUN 0x0010
143#define RL_ISR_PKT_UNDERRUN 0x0020
144#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
145#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
146#define RL_ISR_SYSTEM_ERR 0x8000
147
148#define RL_INTRS \
149 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
150 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
151 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
152
153/*
154 * Media status register. (8139 only)
155 */
156#define RL_MEDIASTAT_RXPAUSE 0x01
157#define RL_MEDIASTAT_TXPAUSE 0x02
158#define RL_MEDIASTAT_LINK 0x04
159#define RL_MEDIASTAT_SPEED10 0x08
160#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */
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277#define RL_CFG1_MEMMAP 0x08
278#define RL_CFG1_RSVD 0x10
279#define RL_CFG1_DRVLOAD 0x20
280#define RL_CFG1_LED0 0x40
281#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */
282#define RL_CFG1_LED1 0x80
283
284/*
285 * The RealTek doesn't use a fragment-based descriptor mechanism.
286 * Instead, there are only four register sets, each or which represents
287 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
288 * packet buffer (32-bit aligned!) and we place the buffer addresses in
289 * the registers so the chip knows where they are.
290 *
291 * We can sort of kludge together the same kind of buffer management
292 * used in previous drivers, but we have to do buffer copies almost all
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331#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
332#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
333#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
334#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
335
336struct rl_type {
337 u_int16_t rl_vid;
338 u_int16_t rl_did;
339 char *rl_name;
340};
341
342struct rl_mii_frame {
343 u_int8_t mii_stdelim;
344 u_int8_t mii_opcode;
345 u_int8_t mii_phyaddr;
346 u_int8_t mii_regaddr;
347 u_int8_t mii_turnaround;
348 u_int16_t mii_data;
349};
350
351/*
352 * MII constants
353 */
354#define RL_MII_STARTDELIM 0x01
355#define RL_MII_READOP 0x02
356#define RL_MII_WRITEOP 0x01
357#define RL_MII_TURNAROUND 0x02
358
359#define RL_8129 1
360#define RL_8139 2
361
362struct rl_softc {
363 struct arpcom arpcom; /* interface info */
364 bus_space_handle_t rl_bhandle; /* bus space handle */
365 bus_space_tag_t rl_btag; /* bus space tag */
366 struct resource *rl_res;
367 struct resource *rl_irq;
368 void *rl_intrhand;
369 device_t rl_miibus;
370 bus_dma_tag_t rl_parent_tag;
371 bus_dma_tag_t rl_tag;
372 u_int8_t rl_unit; /* interface number */
373 u_int8_t rl_type;
374 int rl_eecmd_read;
375 u_int8_t rl_stats_no_timeout;
376 int rl_txthresh;
377 struct rl_chain_data rl_cdata;
378 struct callout_handle rl_stat_ch;
379 struct mtx rl_mtx;
380 int suspended; /* 0 = normal 1 = suspended */
381#ifdef DEVICE_POLLING
382 int rxcycles;
383#endif
384
385 u_int32_t saved_maps[5]; /* pci data */
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419#define RT_VENDORID 0x10EC
420
421/*
422 * RealTek chip device IDs.
423 */
424#define RT_DEVICEID_8129 0x8129
425#define RT_DEVICEID_8138 0x8138
426#define RT_DEVICEID_8139 0x8139
427
428/*
429 * Accton PCI vendor ID
430 */
431#define ACCTON_VENDORID 0x1113
432
433/*
434 * Accton MPX 5030/5038 device ID.
435 */
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498/*
499 * Peppercon ROL-F device ID
500 */
501#define PEPPERCON_DEVICEID_ROLF 0x8139
502
503/*
504 * Planex Communications, Inc. vendor ID
505 */
506#define PLANEX_VENDORID 0x14ea
507
508/*
509 * Planex FNW-3800-TX device ID
510 */
511#define PLANEX_DEVICEID_FNW3800TX 0xab07
512
513/*
514 * PCI low memory base and low I/O base register, and
515 * other PCI registers.
516 */
517
518#define RL_PCI_VENDOR_ID 0x00
519#define RL_PCI_DEVICE_ID 0x02
520#define RL_PCI_COMMAND 0x04
521#define RL_PCI_STATUS 0x06
--- 25 unchanged lines hidden ---
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
--- 13 unchanged lines hidden (view full) ---
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/pci/if_rlreg.h 112379 2003-03-18 14:57:09Z sanpei $
33 */
34
35/*
36 * RealTek 8129/8139 register offsets
37 */
38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */
39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
40#define RL_IDR2 0x0002
--- 53 unchanged lines hidden (view full) ---
94#define RL_ANER 0x006A /* PHY autoneg expansion */
95
96#define RL_DISCCNT 0x006C /* disconnect counter */
97#define RL_FALSECAR 0x006E /* false carrier counter */
98#define RL_NWAYTST 0x0070 /* NWAY test register */
99#define RL_RX_ER 0x0072 /* RX_ER counter */
100#define RL_CSCFG 0x0074 /* CS configuration register */
101
102
103/*
104 * TX config register bits
105 */
106#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
107#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
108#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
109#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
110#define RL_TXCFG_IFG 0x03000000 /* interframe gap */
111
112#define RL_TXDMA_16BYTES 0x00000000
113#define RL_TXDMA_32BYTES 0x00000100
114#define RL_TXDMA_64BYTES 0x00000200
115#define RL_TXDMA_128BYTES 0x00000300
116#define RL_TXDMA_256BYTES 0x00000400
117#define RL_TXDMA_512BYTES 0x00000500
118#define RL_TXDMA_1024BYTES 0x00000600
119#define RL_TXDMA_2048BYTES 0x00000700
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137 */
138#define RL_ISR_RX_OK 0x0001
139#define RL_ISR_RX_ERR 0x0002
140#define RL_ISR_TX_OK 0x0004
141#define RL_ISR_TX_ERR 0x0008
142#define RL_ISR_RX_OVERRUN 0x0010
143#define RL_ISR_PKT_UNDERRUN 0x0020
144#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
145#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
146#define RL_ISR_SYSTEM_ERR 0x8000
147
148#define RL_INTRS \
149 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
150 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
151 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
152
153/*
154 * Media status register. (8139 only)
155 */
156#define RL_MEDIASTAT_RXPAUSE 0x01
157#define RL_MEDIASTAT_TXPAUSE 0x02
158#define RL_MEDIASTAT_LINK 0x04
159#define RL_MEDIASTAT_SPEED10 0x08
160#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */
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277#define RL_CFG1_MEMMAP 0x08
278#define RL_CFG1_RSVD 0x10
279#define RL_CFG1_DRVLOAD 0x20
280#define RL_CFG1_LED0 0x40
281#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */
282#define RL_CFG1_LED1 0x80
283
284/*
285 * The RealTek doesn't use a fragment-based descriptor mechanism.
286 * Instead, there are only four register sets, each or which represents
287 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
288 * packet buffer (32-bit aligned!) and we place the buffer addresses in
289 * the registers so the chip knows where they are.
290 *
291 * We can sort of kludge together the same kind of buffer management
292 * used in previous drivers, but we have to do buffer copies almost all
--- 38 unchanged lines hidden (view full) ---
331#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
332#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
333#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
334#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
335
336struct rl_type {
337 u_int16_t rl_vid;
338 u_int16_t rl_did;
339 char *rl_name;
340};
341
342struct rl_mii_frame {
343 u_int8_t mii_stdelim;
344 u_int8_t mii_opcode;
345 u_int8_t mii_phyaddr;
346 u_int8_t mii_regaddr;
347 u_int8_t mii_turnaround;
348 u_int16_t mii_data;
349};
350
351/*
352 * MII constants
353 */
354#define RL_MII_STARTDELIM 0x01
355#define RL_MII_READOP 0x02
356#define RL_MII_WRITEOP 0x01
357#define RL_MII_TURNAROUND 0x02
358
359#define RL_8129 1
360#define RL_8139 2
361
362struct rl_softc {
363 struct arpcom arpcom; /* interface info */
364 bus_space_handle_t rl_bhandle; /* bus space handle */
365 bus_space_tag_t rl_btag; /* bus space tag */
366 struct resource *rl_res;
367 struct resource *rl_irq;
368 void *rl_intrhand;
369 device_t rl_miibus;
370 bus_dma_tag_t rl_parent_tag;
371 bus_dma_tag_t rl_tag;
372 u_int8_t rl_unit; /* interface number */
373 u_int8_t rl_type;
374 int rl_eecmd_read;
375 u_int8_t rl_stats_no_timeout;
376 int rl_txthresh;
377 struct rl_chain_data rl_cdata;
378 struct callout_handle rl_stat_ch;
379 struct mtx rl_mtx;
380 int suspended; /* 0 = normal 1 = suspended */
381#ifdef DEVICE_POLLING
382 int rxcycles;
383#endif
384
385 u_int32_t saved_maps[5]; /* pci data */
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419#define RT_VENDORID 0x10EC
420
421/*
422 * RealTek chip device IDs.
423 */
424#define RT_DEVICEID_8129 0x8129
425#define RT_DEVICEID_8138 0x8138
426#define RT_DEVICEID_8139 0x8139
427
428/*
429 * Accton PCI vendor ID
430 */
431#define ACCTON_VENDORID 0x1113
432
433/*
434 * Accton MPX 5030/5038 device ID.
435 */
--- 62 unchanged lines hidden (view full) ---
498/*
499 * Peppercon ROL-F device ID
500 */
501#define PEPPERCON_DEVICEID_ROLF 0x8139
502
503/*
504 * Planex Communications, Inc. vendor ID
505 */
506#define PLANEX_VENDORID 0x14ea
507
508/*
509 * Planex FNW-3800-TX device ID
510 */
511#define PLANEX_DEVICEID_FNW3800TX 0xab07
512
513/*
514 * PCI low memory base and low I/O base register, and
515 * other PCI registers.
516 */
517
518#define RL_PCI_VENDOR_ID 0x00
519#define RL_PCI_DEVICE_ID 0x02
520#define RL_PCI_COMMAND 0x04
521#define RL_PCI_STATUS 0x06
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