1/*
2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
4 * Copyright (C) 2002 by John Baldwin <jhb@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
|
28 * $FreeBSD: head/sys/dev/rc/rc.c 111002 2003-02-16 14:13:23Z phk $
|
| 28 * $FreeBSD: head/sys/dev/rc/rc.c 111564 2003-02-26 19:21:56Z jhb $ |
29 */
30
31/*
32 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
33 *
34 */
35
36/*#define RCDEBUG*/
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/bus.h>
41#include <sys/conf.h>
42#include <sys/fcntl.h>
43#include <sys/interrupt.h>
44#include <sys/kernel.h>
45#include <sys/malloc.h>
46#include <sys/tty.h>
47#include <machine/bus.h>
48#include <machine/resource.h>
49#include <sys/rman.h>
50
51#include <dev/ic/cd180.h>
52#include <dev/rc/rcreg.h>
53#include <isa/isavar.h>
54
55#define IOBASE_ADDRS 14
56
57#define DEV_TO_RC(dev) (struct rc_chans *)((dev)->si_drv1)
58#define TTY_TO_RC(tty) DEV_TO_RC((tty)->t_dev)
59
60#define rcin(sc, port) RC_IN(sc, port)
61#define rcout(sc, port, v) RC_OUT(sc, port, v)
62
63#define WAITFORCCR(sc, chan) rc_wait0((sc), (chan), __LINE__)
64
65#define CCRCMD(sc, chan, cmd) do { \
66 WAITFORCCR((sc), (chan)); \
67 rcout((sc), CD180_CCR, (cmd)); \
68} while (0)
69
70#define RC_IBUFSIZE 256
71#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
72#define RC_OBUFSIZE 512
73#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4)
74#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
75#define LOTS_OF_EVENTS 64
76
77#define RC_FAKEID 0x10
78
79#define CALLOUT(dev) (((intptr_t)(dev)->si_drv2) != 0)
80
81/* Per-channel structure */
82struct rc_chans {
83 struct rc_softc *rc_rcb; /* back ptr */
84 dev_t rc_dev; /* non-callout device */
85 dev_t rc_cdev; /* callout device */
86 u_short rc_flags; /* Misc. flags */
87 int rc_chan; /* Channel # */
88 u_char rc_ier; /* intr. enable reg */
89 u_char rc_msvr; /* modem sig. status */
90 u_char rc_cor2; /* options reg */
91 u_char rc_pendcmd; /* special cmd pending */
92 u_int rc_dtrwait; /* dtr timeout */
93 u_int rc_dcdwaits; /* how many waits DCD in open */
94 u_char rc_hotchar; /* end packed optimize */
95 struct tty rc_tp; /* tty struct */
96 u_char *rc_iptr; /* Chars input buffer */
97 u_char *rc_hiwat; /* hi-water mark */
98 u_char *rc_bufend; /* end of buffer */
99 u_char *rc_optr; /* ptr in output buf */
100 u_char *rc_obufend; /* end of output buf */
101 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */
102 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */
103 struct callout rc_dtrcallout;
104};
105
106/* Per-board structure */
107struct rc_softc {
108 device_t sc_dev;
109 struct resource *sc_irq;
110 struct resource *sc_port[IOBASE_ADDRS];
111 int sc_irqrid;
112 void *sc_hwicookie;
113 bus_space_tag_t sc_bt;
114 bus_space_handle_t sc_bh;
115 u_int sc_unit; /* unit # */
116 u_char sc_dtr; /* DTR status */
117 int sc_opencount;
118 int sc_scheduled_event;
119 void *sc_swicookie;
120 struct rc_chans sc_channels[CD180_NCHAN]; /* channels */
121};
122
123/* Static prototypes */
124static void rc_release_resources(device_t dev);
125static void rc_intr(void *);
126static void rc_hwreset(struct rc_softc *, unsigned int);
127static int rc_test(struct rc_softc *);
128static void rc_discard_output(struct rc_chans *);
129static void rc_hardclose(struct rc_chans *);
130static int rc_modctl(struct rc_chans *, int, int);
131static void rc_start(struct tty *);
132static void rc_stop(struct tty *, int rw);
133static int rc_param(struct tty *, struct termios *);
134static void rc_pollcard(void *);
135static void rc_reinit(struct rc_softc *);
136#ifdef RCDEBUG
137static void printrcflags();
138#endif
139static void rc_dtrwakeup(void *);
140static void disc_optim(struct tty *tp, struct termios *t, struct rc_chans *);
141static void rc_wait0(struct rc_softc *sc, int chan, int line);
142
143static d_open_t rcopen;
144static d_close_t rcclose;
145static d_ioctl_t rcioctl;
146
147#define CDEV_MAJOR 63
148static struct cdevsw rc_cdevsw = {
149 /* open */ rcopen,
150 /* close */ rcclose,
151 /* read */ ttyread,
152 /* write */ ttywrite,
153 /* ioctl */ rcioctl,
154 /* poll */ ttypoll,
155 /* mmap */ nommap,
156 /* strategy */ nostrategy,
157 /* name */ "rc",
158 /* maj */ CDEV_MAJOR,
159 /* dump */ nodump,
160 /* psize */ nopsize,
161 /* flags */ D_TTY | D_KQFILTER,
162 /* kqfilter */ ttykqfilter,
163};
164
165static devclass_t rc_devclass;
166
167/* Flags */
168#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */
169#define RC_ACTOUT 0x0002 /* Dial-out port active */
170#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */
171#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */
172#define RC_DORXFER 0x0010 /* RXFER event planned */
173#define RC_DOXXFER 0x0020 /* XXFER event planned */
174#define RC_MODCHG 0x0040 /* Modem status changed */
175#define RC_OSUSP 0x0080 /* Output suspended */
176#define RC_OSBUSY 0x0100 /* start() routine in progress */
177#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */
178#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */
179#define RC_SEND_RDY 0x0800 /* ready to send */
180
181/* Table for translation of RCSR status bits to internal form */
182static int rc_rcsrt[16] = {
183 0, TTY_OE, TTY_FE,
184 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE,
185 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
186 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE,
187 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
188 TTY_BI|TTY_PE|TTY_FE|TTY_OE
189};
190
191static int rc_ports[] =
192 { 0x220, 0x240, 0x250, 0x260, 0x2a0, 0x2b0, 0x300, 0x320 };
193static int iobase_addrs[IOBASE_ADDRS] =
194 { 0, 0x400, 0x800, 0xc00, 0x1400, 0x1800, 0x1c00, 0x2000,
195 0x3000, 0x3400, 0x3800, 0x3c00, 0x4000, 0x8000 };
196
197/**********************************************/
198
199static int
200rc_probe(device_t dev)
201{
202 u_int port;
203 int i, found;
204
205 /*
206 * We don't know of any PnP ID's for these cards.
207 */
208 if (isa_get_logicalid(dev) != 0)
209 return (ENXIO);
210
211 /*
212 * We have to have an IO port hint that is valid.
213 */
214 port = isa_get_port(dev);
215 if (port == -1)
216 return (ENXIO);
217 found = 0;
218 for (i = 0; i < sizeof(rc_ports) / sizeof(int); i++)
219 if (rc_ports[i] == port) {
220 found = 1;
221 break;
222 }
223 if (!found)
224 return (ENXIO);
225
226 /*
227 * We have to have an IRQ hint.
228 */
229 if (isa_get_irq(dev) == -1)
230 return (ENXIO);
231
232 device_set_desc(dev, "SDL Riscom/8");
233 return (0);
234}
235
236static int
237rc_attach(device_t dev)
238{
239 struct rc_chans *rc;
240 struct tty *tp;
241 struct rc_softc *sc;
242 u_int port;
243 int base, chan, error, i, x;
244 dev_t cdev;
245
246 sc = device_get_softc(dev);
247 sc->sc_dev = dev;
248
249 /*
250 * We need to have IO ports. Lots of them. We need
251 * the following ranges relative to the base port:
252 * 0x0 - 0x10
253 * 0x400 - 0x410
254 * 0x800 - 0x810
255 * 0xc00 - 0xc10
256 * 0x1400 - 0x1410
257 * 0x1800 - 0x1810
258 * 0x1c00 - 0x1c10
259 * 0x2000 - 0x2010
260 * 0x3000 - 0x3010
261 * 0x3400 - 0x3410
262 * 0x3800 - 0x3810
263 * 0x3c00 - 0x3c10
264 * 0x4000 - 0x4010
265 * 0x8000 - 0x8010
266 */
267 port = isa_get_port(dev);
268 for (i = 0; i < IOBASE_ADDRS; i++)
269 if (bus_set_resource(dev, SYS_RES_IOPORT, i,
270 port + iobase_addrs[i], 0x10) != 0)
271 return (ENXIO);
272 error = ENOMEM;
273 for (i = 0; i < IOBASE_ADDRS; i++) {
274 x = i;
275 sc->sc_port[i] = bus_alloc_resource(dev, SYS_RES_IOPORT, &x,
276 0ul, ~0ul, 0x10, RF_ACTIVE);
277 if (x != i) {
278 device_printf(dev, "ioport %d was rid %d\n", i, x);
279 goto fail;
280 }
281 if (sc->sc_port[i] == NULL) {
282 device_printf(dev, "failed to alloc ioports %x-%x\n",
283 port + iobase_addrs[i],
284 port + iobase_addrs[i] + 0x10);
285 goto fail;
286 }
287 }
288 sc->sc_bt = rman_get_bustag(sc->sc_port[0]);
289 sc->sc_bh = rman_get_bushandle(sc->sc_port[0]);
290
291 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->sc_irqrid,
292 0ul, ~0ul, 1, RF_ACTIVE);
293 if (sc->sc_irq == NULL) {
294 device_printf(dev, "failed to alloc IRQ\n");
295 goto fail;
296 }
297
298 /*
299 * Now do some actual tests to make sure it works.
300 */
301 error = ENXIO;
302 rcout(sc, CD180_PPRL, 0x22); /* Random values to Prescale reg. */
303 rcout(sc, CD180_PPRH, 0x11);
304 if (rcin(sc, CD180_PPRL) != 0x22 || rcin(sc, CD180_PPRH) != 0x11)
305 goto fail;
306 if (rc_test(sc))
307 goto fail;
308
309 /*
310 * Ok, start actually hooking things up.
311 */
312 sc->sc_unit = device_get_unit(dev);
313 /*sc->sc_chipid = 0x10 + device_get_unit(dev);*/
314 device_printf(dev, "%d chans, firmware rev. %c\n",
315 CD180_NCHAN, (rcin(sc, CD180_GFRCR) & 0xF) + 'A');
316 rc = sc->sc_channels;
317 base = CD180_NCHAN * sc->sc_unit;
318 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
319 rc->rc_rcb = sc;
320 rc->rc_chan = chan;
321 rc->rc_iptr = rc->rc_ibuf;
322 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
323 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
324 rc->rc_optr = rc->rc_obufend = rc->rc_obuf;
325 rc->rc_dtrwait = 3 * hz;
326 callout_init(&rc->rc_dtrcallout, 0);
327 tp = &rc->rc_tp;
328 ttychars(tp);
329 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
330 tp->t_cflag = TTYDEF_CFLAG;
331 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
332 cdev = make_dev(&rc_cdevsw, chan + base,
333 UID_ROOT, GID_WHEEL, 0600, "ttym%d", chan + base);
334 cdev->si_drv1 = rc;
335 cdev->si_drv2 = 0;
336 cdev->si_tty = tp;
337 rc->rc_dev = cdev;
338 cdev = make_dev(&rc_cdevsw, chan + base + 128,
339 UID_UUCP, GID_DIALER, 0660, "cuam%d", chan + base);
340 cdev->si_drv1 = rc;
341 cdev->si_drv2 = (void *)1;
342 cdev->si_tty = tp;
343 rc->rc_cdev = cdev;
344 }
345
346 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_TTY, rc_intr, sc,
347 &sc->sc_hwicookie);
348 if (error) {
349 device_printf(dev, "failed to register interrupt handler\n");
350 goto fail;
351 }
352
353 swi_add(&tty_ithd, "tty:rc", rc_pollcard, sc, SWI_TTY, 0,
354 &sc->sc_swicookie);
355 return (0);
356
357fail:
358 rc_release_resources(dev);
359 return (error);
360}
361
362static int
363rc_detach(device_t dev)
364{
365 struct rc_softc *sc;
366 struct rc_chans *rc;
367 int error, i, s;
368
369 sc = device_get_softc(dev);
370 if (sc->sc_opencount > 0)
371 return (EBUSY);
372 sc->sc_opencount = -1;
373
374 rc = sc->sc_channels;
375 for (i = 0; i < CD180_NCHAN; i++, rc++) {
376 destroy_dev(rc->rc_dev);
377 destroy_dev(rc->rc_cdev);
378 }
379
380 rc = sc->sc_channels;
381 s = splsoftclock();
382 for (i = 0; i < CD180_NCHAN; i++) {
383 if ((rc->rc_flags & RC_DTR_OFF) &&
384 !callout_stop(&rc->rc_dtrcallout))
385 tsleep(&rc->rc_dtrwait, TTIPRI, "rcdtrdet", 0);
386 }
387
388 error = bus_teardown_intr(dev, sc->sc_irq, sc->sc_hwicookie);
389 if (error)
390 device_printf(dev, "failed to deregister interrupt handler\n");
391 ithread_remove_handler(sc->sc_swicookie);
392 rc_release_resources(dev);
393
394 return (0);
395}
396
397static void
398rc_release_resources(device_t dev)
399{
400 struct rc_softc *sc;
401 int i;
402
403 sc = device_get_softc(dev);
404 if (sc->sc_irq != NULL) {
405 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid,
406 sc->sc_irq);
407 sc->sc_irq = NULL;
408 }
409 for (i = 0; i < IOBASE_ADDRS; i++) {
410 if (sc->sc_port[i] == NULL)
411 break;
412 bus_release_resource(dev, SYS_RES_IOPORT, i, sc->sc_port[i]);
413 sc->sc_port[i] = NULL;
414 }
415}
416
417/* RC interrupt handling */
418static void
419rc_intr(void *arg)
420{
421 struct rc_softc *sc;
422 struct rc_chans *rc;
423 int resid, chan;
424 u_char val, iack, bsr, ucnt, *optr;
425 int good_data, t_state;
426
427 sc = (struct rc_softc *)arg;
428 bsr = ~(rcin(sc, RC_BSR));
429 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
430 device_printf(sc->sc_dev, "extra interrupt\n");
431 rcout(sc, CD180_EOIR, 0);
432 return;
433 }
434
435 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
436#ifdef RCDEBUG_DETAILED
437 device_printf(sc->sc_dev, "intr (%p) %s%s%s%s\n", arg, bsr,
438 (bsr & RC_BSR_TOUT)?"TOUT ":"",
439 (bsr & RC_BSR_RXINT)?"RXINT ":"",
440 (bsr & RC_BSR_TXINT)?"TXINT ":"",
441 (bsr & RC_BSR_MOINT)?"MOINT":"");
442#endif
443 if (bsr & RC_BSR_TOUT) {
444 device_printf(sc->sc_dev,
445 "hardware failure, reset board\n");
446 rcout(sc, RC_CTOUT, 0);
447 rc_reinit(sc);
448 return;
449 }
450 if (bsr & RC_BSR_RXINT) {
451 iack = rcin(sc, RC_PILR_RX);
452 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
453 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
454 device_printf(sc->sc_dev,
455 "fake rxint: %02x\n", iack);
456 goto more_intrs;
457 }
458 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH);
459 rc = &sc->sc_channels[chan];
460 t_state = rc->rc_tp.t_state;
461 /* Do RTS flow control stuff */
462 if ( (rc->rc_flags & RC_RTSFLOW)
463 || !(t_state & TS_ISOPEN)
464 ) {
465 if ( ( !(t_state & TS_ISOPEN)
466 || (t_state & TS_TBLOCK)
467 )
468 && (rc->rc_msvr & MSVR_RTS)
469 )
470 rcout(sc, CD180_MSVR,
471 rc->rc_msvr &= ~MSVR_RTS);
472 else if (!(rc->rc_msvr & MSVR_RTS))
473 rcout(sc, CD180_MSVR,
474 rc->rc_msvr |= MSVR_RTS);
475 }
476 ucnt = rcin(sc, CD180_RDCR) & 0xF;
477 resid = 0;
478
479 if (t_state & TS_ISOPEN) {
480 /* check for input buffer overflow */
481 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
482 resid = ucnt;
483 ucnt = rc->rc_bufend - rc->rc_iptr;
484 resid -= ucnt;
485 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
486 rc->rc_flags |= RC_WAS_BUFOVFL;
487 sc->sc_scheduled_event++;
488 }
489 }
490 optr = rc->rc_iptr;
491 /* check foor good data */
492 if (good_data) {
493 while (ucnt-- > 0) {
494 val = rcin(sc, CD180_RDR);
495 optr[0] = val;
496 optr[INPUT_FLAGS_SHIFT] = 0;
497 optr++;
498 sc->sc_scheduled_event++;
499 if (val != 0 && val == rc->rc_hotchar)
500 swi_sched(sc->sc_swicookie, 0);
501 }
502 } else {
503 /* Store also status data */
504 while (ucnt-- > 0) {
505 iack = rcin(sc, CD180_RCSR);
506 if (iack & RCSR_Timeout)
507 break;
508 if ( (iack & RCSR_OE)
509 && !(rc->rc_flags & RC_WAS_SILOVFL)) {
510 rc->rc_flags |= RC_WAS_SILOVFL;
511 sc->sc_scheduled_event++;
512 }
513 val = rcin(sc, CD180_RDR);
514 /*
515 Don't store PE if IGNPAR and BREAK if IGNBRK,
516 this hack allows "raw" tty optimization
517 works even if IGN* is set.
518 */
519 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
520 || ((!(iack & (RCSR_PE|RCSR_FE))
521 || !(rc->rc_tp.t_iflag & IGNPAR))
522 && (!(iack & RCSR_Break)
523 || !(rc->rc_tp.t_iflag & IGNBRK)))) {
524 if ( (iack & (RCSR_PE|RCSR_FE))
525 && (t_state & TS_CAN_BYPASS_L_RINT)
526 && ((iack & RCSR_FE)
527 || ((iack & RCSR_PE)
528 && (rc->rc_tp.t_iflag & INPCK))))
529 val = 0;
530 else if (val != 0 && val == rc->rc_hotchar)
531 swi_sched(sc->sc_swicookie, 0);
532 optr[0] = val;
533 optr[INPUT_FLAGS_SHIFT] = iack;
534 optr++;
535 sc->sc_scheduled_event++;
536 }
537 }
538 }
539 rc->rc_iptr = optr;
540 rc->rc_flags |= RC_DORXFER;
541 } else
542 resid = ucnt;
543 /* Clear FIFO if necessary */
544 while (resid-- > 0) {
545 if (!good_data)
546 iack = rcin(sc, CD180_RCSR);
547 else
548 iack = 0;
549 if (iack & RCSR_Timeout)
550 break;
551 (void) rcin(sc, CD180_RDR);
552 }
553 goto more_intrs;
554 }
555 if (bsr & RC_BSR_MOINT) {
556 iack = rcin(sc, RC_PILR_MODEM);
557 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
558 device_printf(sc->sc_dev, "fake moint: %02x\n",
559 iack);
560 goto more_intrs;
561 }
562 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH);
563 rc = &sc->sc_channels[chan];
564 iack = rcin(sc, CD180_MCR);
565 rc->rc_msvr = rcin(sc, CD180_MSVR);
566 rcout(sc, CD180_MCR, 0);
567#ifdef RCDEBUG
568 printrcflags(rc, "moint");
569#endif
570 if (rc->rc_flags & RC_CTSFLOW) {
571 if (rc->rc_msvr & MSVR_CTS)
572 rc->rc_flags |= RC_SEND_RDY;
573 else
574 rc->rc_flags &= ~RC_SEND_RDY;
575 } else
576 rc->rc_flags |= RC_SEND_RDY;
577 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
578 sc->sc_scheduled_event += LOTS_OF_EVENTS;
579 rc->rc_flags |= RC_MODCHG;
580 swi_sched(sc->sc_swicookie, 0);
581 }
582 goto more_intrs;
583 }
584 if (bsr & RC_BSR_TXINT) {
585 iack = rcin(sc, RC_PILR_TX);
586 if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
587 device_printf(sc->sc_dev, "fake txint: %02x\n",
588 iack);
589 goto more_intrs;
590 }
591 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH);
592 rc = &sc->sc_channels[chan];
593 if ( (rc->rc_flags & RC_OSUSP)
594 || !(rc->rc_flags & RC_SEND_RDY)
595 )
596 goto more_intrs;
597 /* Handle breaks and other stuff */
598 if (rc->rc_pendcmd) {
599 rcout(sc, CD180_COR2, rc->rc_cor2 |= COR2_ETC);
600 rcout(sc, CD180_TDR, CD180_C_ESC);
601 rcout(sc, CD180_TDR, rc->rc_pendcmd);
602 rcout(sc, CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
603 rc->rc_pendcmd = 0;
604 goto more_intrs;
605 }
606 optr = rc->rc_optr;
607 resid = rc->rc_obufend - optr;
608 if (resid > CD180_NFIFO)
609 resid = CD180_NFIFO;
610 while (resid-- > 0)
611 rcout(sc, CD180_TDR, *optr++);
612 rc->rc_optr = optr;
613
614 /* output completed? */
615 if (optr >= rc->rc_obufend) {
616 rcout(sc, CD180_IER, rc->rc_ier &= ~IER_TxRdy);
617#ifdef RCDEBUG
618 device_printf(sc->sc_dev,
619 "channel %d: output completed\n",
620 rc->rc_chan);
621#endif
622 if (!(rc->rc_flags & RC_DOXXFER)) {
623 sc->sc_scheduled_event += LOTS_OF_EVENTS;
624 rc->rc_flags |= RC_DOXXFER;
625 swi_sched(sc->sc_swicookie, 0);
626 }
627 }
628 }
629 more_intrs:
630 rcout(sc, CD180_EOIR, 0); /* end of interrupt */
631 rcout(sc, RC_CTOUT, 0);
632 bsr = ~(rcin(sc, RC_BSR));
633 }
634}
635
636/* Feed characters to output buffer */
637static void
638rc_start(struct tty *tp)
639{
640 struct rc_softc *sc;
641 struct rc_chans *rc;
642 int s;
643
644 rc = TTY_TO_RC(tp);
645 if (rc->rc_flags & RC_OSBUSY)
646 return;
647 sc = rc->rc_rcb;
648 s = spltty();
649 rc->rc_flags |= RC_OSBUSY;
650 critical_enter();
651 if (tp->t_state & TS_TTSTOP)
652 rc->rc_flags |= RC_OSUSP;
653 else
654 rc->rc_flags &= ~RC_OSUSP;
655 /* Do RTS flow control stuff */
656 if ( (rc->rc_flags & RC_RTSFLOW)
657 && (tp->t_state & TS_TBLOCK)
658 && (rc->rc_msvr & MSVR_RTS)
659 ) {
660 rcout(sc, CD180_CAR, rc->rc_chan);
661 rcout(sc, CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
662 } else if (!(rc->rc_msvr & MSVR_RTS)) {
663 rcout(sc, CD180_CAR, rc->rc_chan);
664 rcout(sc, CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
665 }
666 critical_exit();
667 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
668 goto out;
669#ifdef RCDEBUG
670 printrcflags(rc, "rcstart");
671#endif
672 ttwwakeup(tp);
673#ifdef RCDEBUG
674 printf("rcstart: outq = %d obuf = %d\n",
675 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
676#endif
677 if (tp->t_state & TS_BUSY)
678 goto out; /* output still in progress ... */
679
680 if (tp->t_outq.c_cc > 0) {
681 u_int ocnt;
682
683 tp->t_state |= TS_BUSY;
684 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
685 critical_enter();
686 rc->rc_optr = rc->rc_obuf;
687 rc->rc_obufend = rc->rc_optr + ocnt;
688 critical_exit();
689 if (!(rc->rc_ier & IER_TxRdy)) {
690#ifdef RCDEBUG
691 device_printf(sc->sc_dev,
692 "channel %d: rcstart enable txint\n", rc->rc_chan);
693#endif
694 rcout(sc, CD180_CAR, rc->rc_chan);
695 rcout(sc, CD180_IER, rc->rc_ier |= IER_TxRdy);
696 }
697 }
698out:
699 rc->rc_flags &= ~RC_OSBUSY;
700 (void) splx(s);
701}
702
703/* Handle delayed events. */
704void
705rc_pollcard(void *arg)
706{
707 struct rc_softc *sc;
708 struct rc_chans *rc;
709 struct tty *tp;
710 u_char *tptr, *eptr;
711 int chan, icnt;
712
713 sc = (struct rc_softc *)arg;
714 if (sc->sc_scheduled_event == 0)
715 return;
716 do {
717 rc = sc->sc_channels;
718 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
719 tp = &rc->rc_tp;
720#ifdef RCDEBUG
721 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
722 RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
723 printrcflags(rc, "rcevent");
724#endif
725 if (rc->rc_flags & RC_WAS_BUFOVFL) {
726 critical_enter();
727 rc->rc_flags &= ~RC_WAS_BUFOVFL;
728 sc->sc_scheduled_event--;
729 critical_exit();
730 device_printf(sc->sc_dev,
731 "channel %d: interrupt-level buffer overflow\n",
732 chan);
733 }
734 if (rc->rc_flags & RC_WAS_SILOVFL) {
735 critical_enter();
736 rc->rc_flags &= ~RC_WAS_SILOVFL;
737 sc->sc_scheduled_event--;
738 critical_exit();
739 device_printf(sc->sc_dev,
740 "channel %d: silo overflow\n", chan);
741 }
742 if (rc->rc_flags & RC_MODCHG) {
743 critical_enter();
744 rc->rc_flags &= ~RC_MODCHG;
745 sc->sc_scheduled_event -= LOTS_OF_EVENTS;
746 critical_exit();
747 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
748 }
749 if (rc->rc_flags & RC_DORXFER) {
750 critical_enter();
751 rc->rc_flags &= ~RC_DORXFER;
752 eptr = rc->rc_iptr;
753 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
754 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
755 else
756 tptr = rc->rc_ibuf;
757 icnt = eptr - tptr;
758 if (icnt > 0) {
759 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
760 rc->rc_iptr = rc->rc_ibuf;
761 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
762 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
763 } else {
764 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
765 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
766 rc->rc_hiwat =
767 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
768 }
769 if ( (rc->rc_flags & RC_RTSFLOW)
770 && (tp->t_state & TS_ISOPEN)
771 && !(tp->t_state & TS_TBLOCK)
772 && !(rc->rc_msvr & MSVR_RTS)
773 ) {
774 rcout(sc, CD180_CAR, chan);
775 rcout(sc, CD180_MSVR,
776 rc->rc_msvr |= MSVR_RTS);
777 }
778 sc->sc_scheduled_event -= icnt;
779 }
780 critical_exit();
781
782 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
783 goto done1;
784
785 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT)
786 && !(tp->t_state & TS_LOCAL)) {
787 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
788 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
789 && !(tp->t_state & TS_TBLOCK))
790 ttyblock(tp);
791 tk_nin += icnt;
792 tk_rawcc += icnt;
793 tp->t_rawcc += icnt;
794 if (b_to_q(tptr, icnt, &tp->t_rawq))
795 device_printf(sc->sc_dev,
796 "channel %d: tty-level buffer overflow\n",
797 chan);
798 ttwakeup(tp);
799 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
800 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
801 tp->t_state &= ~TS_TTSTOP;
802 tp->t_lflag &= ~FLUSHO;
803 rc_start(tp);
804 }
805 } else {
806 for (; tptr < eptr; tptr++)
807 (*linesw[tp->t_line].l_rint)
808 (tptr[0] |
809 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
810 }
811done1: ;
812 }
813 if (rc->rc_flags & RC_DOXXFER) {
814 critical_enter();
815 sc->sc_scheduled_event -= LOTS_OF_EVENTS;
816 rc->rc_flags &= ~RC_DOXXFER;
817 rc->rc_tp.t_state &= ~TS_BUSY;
818 critical_exit();
819 (*linesw[tp->t_line].l_start)(tp);
820 }
|
821 if (sc->sc_scheduled_event == 0)
822 break; |
823 }
|
822 if (sc->sc_scheduled_event == 0)
823 break;
824 }
825 while (sc->sc_scheduled_event >= LOTS_OF_EVENTS);
|
| 824 } while (sc->sc_scheduled_event >= LOTS_OF_EVENTS); |
825}
826
827static void
828rc_stop(struct tty *tp, int rw)
829{
830 struct rc_softc *sc;
831 struct rc_chans *rc;
832 u_char *tptr, *eptr;
833
834 rc = TTY_TO_RC(tp);
835 sc = rc->rc_rcb;
836#ifdef RCDEBUG
837 device_printf(sc->sc_dev, "channel %d: rc_stop %s%s\n",
838 rc->rc_chan, (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
839#endif
840 if (rw & FWRITE)
841 rc_discard_output(rc);
842 critical_enter();
843 if (rw & FREAD) {
844 rc->rc_flags &= ~RC_DORXFER;
845 eptr = rc->rc_iptr;
846 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
847 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
848 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
849 } else {
850 tptr = rc->rc_ibuf;
851 rc->rc_iptr = rc->rc_ibuf;
852 }
853 sc->sc_scheduled_event -= eptr - tptr;
854 }
855 if (tp->t_state & TS_TTSTOP)
856 rc->rc_flags |= RC_OSUSP;
857 else
858 rc->rc_flags &= ~RC_OSUSP;
859 critical_exit();
860}
861
862static int
863rcopen(dev_t dev, int flag, int mode, d_thread_t *td)
864{
865 struct rc_softc *sc;
866 struct rc_chans *rc;
867 struct tty *tp;
868 int s, error = 0;
869
870 rc = DEV_TO_RC(dev);
871 sc = rc->rc_rcb;
872 tp = &rc->rc_tp;
873 if (sc->sc_opencount < 0)
874 return (ENXIO);
875 sc->sc_opencount++;
876#ifdef RCDEBUG
877 device_printf(sc->sc_dev, "channel %d: rcopen: dev %p\n",
878 rc->rc_chan, dev);
879#endif
880 s = spltty();
881
882again:
883 while (rc->rc_flags & RC_DTR_OFF) {
884 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0);
885 if (error != 0)
886 goto out;
887 }
888 if (tp->t_state & TS_ISOPEN) {
889 if (CALLOUT(dev)) {
890 if (!(rc->rc_flags & RC_ACTOUT)) {
891 error = EBUSY;
892 goto out;
893 }
894 } else {
895 if (rc->rc_flags & RC_ACTOUT) {
896 if (flag & O_NONBLOCK) {
897 error = EBUSY;
898 goto out;
899 }
900 error = tsleep(&rc->rc_rcb,
901 TTIPRI|PCATCH, "rcbi", 0);
902 if (error)
903 goto out;
904 goto again;
905 }
906 }
907 if (tp->t_state & TS_XCLUDE &&
908 suser(td)) {
909 error = EBUSY;
910 goto out;
911 }
912 } else {
913 tp->t_oproc = rc_start;
914 tp->t_param = rc_param;
915 tp->t_stop = rc_stop;
916 tp->t_dev = dev;
917
918 if (CALLOUT(dev))
919 tp->t_cflag |= CLOCAL;
920 else
921 tp->t_cflag &= ~CLOCAL;
922
923 error = rc_param(tp, &tp->t_termios);
924 if (error)
925 goto out;
926 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
927
928 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
929 (*linesw[tp->t_line].l_modem)(tp, 1);
930 }
931 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
932 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
933 rc->rc_dcdwaits++;
934 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0);
935 rc->rc_dcdwaits--;
936 if (error != 0)
937 goto out;
938 goto again;
939 }
940 error = (*linesw[tp->t_line].l_open)(dev, tp);
941 disc_optim(tp, &tp->t_termios, rc);
942 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
943 rc->rc_flags |= RC_ACTOUT;
944out:
945 (void) splx(s);
946
947 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
948 rc_hardclose(rc);
949
950 return error;
951}
952
953static int
954rcclose(dev_t dev, int flag, int mode, d_thread_t *td)
955{
956 struct rc_softc *sc;
957 struct rc_chans *rc;
958 struct tty *tp;
959 int s;
960
961 rc = DEV_TO_RC(dev);
962 sc = rc->rc_rcb;
963 tp = &rc->rc_tp;
964#ifdef RCDEBUG
965 device_printf(sc->sc_dev, "channel %d: rcclose dev %p\n",
966 rc->rc_chan, dev);
967#endif
968 s = spltty();
969 (*linesw[tp->t_line].l_close)(tp, flag);
970 disc_optim(tp, &tp->t_termios, rc);
971 rc_stop(tp, FREAD | FWRITE);
972 rc_hardclose(rc);
973 ttyclose(tp);
974 splx(s);
975 KASSERT(sc->sc_opencount > 0, ("rcclose: non-positive open count"));
976 sc->sc_opencount--;
977 return 0;
978}
979
980static void
981rc_hardclose(struct rc_chans *rc)
982{
983 struct rc_softc *sc;
984 struct tty *tp;
985 int s;
986
987 tp = &rc->rc_tp;
988 sc = rc->rc_rcb;
989 s = spltty();
990 rcout(sc, CD180_CAR, rc->rc_chan);
991
992 /* Disable rx/tx intrs */
993 rcout(sc, CD180_IER, rc->rc_ier = 0);
994 if ( (tp->t_cflag & HUPCL)
995 || (!(rc->rc_flags & RC_ACTOUT)
996 && !(rc->rc_msvr & MSVR_CD)
997 && !(tp->t_cflag & CLOCAL))
998 || !(tp->t_state & TS_ISOPEN)
999 ) {
1000 CCRCMD(sc, rc->rc_chan, CCR_ResetChan);
1001 WAITFORCCR(sc, rc->rc_chan);
1002 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
1003 if (rc->rc_dtrwait) {
1004 callout_reset(&rc->rc_dtrcallout, rc->rc_dtrwait,
1005 rc_dtrwakeup, rc);
1006 rc->rc_flags |= RC_DTR_OFF;
1007 }
1008 }
1009 rc->rc_flags &= ~RC_ACTOUT;
1010 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */
1011 wakeup(TSA_CARR_ON(tp));
1012 (void) splx(s);
1013}
1014
1015/* Reset the bastard */
1016static void
1017rc_hwreset(struct rc_softc *sc, uint chipid)
1018{
1019 CCRCMD(sc, -1, CCR_HWRESET); /* Hardware reset */
1020 DELAY(20000);
1021 WAITFORCCR(sc, -1);
1022
1023 rcout(sc, RC_CTOUT, 0); /* Clear timeout */
1024 rcout(sc, CD180_GIVR, chipid);
1025 rcout(sc, CD180_GICR, 0);
1026
1027 /* Set Prescaler Registers (1 msec) */
1028 rcout(sc, CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
1029 rcout(sc, CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
1030
1031 /* Initialize Priority Interrupt Level Registers */
1032 rcout(sc, CD180_PILR1, RC_PILR_MODEM);
1033 rcout(sc, CD180_PILR2, RC_PILR_TX);
1034 rcout(sc, CD180_PILR3, RC_PILR_RX);
1035
1036 /* Reset DTR */
1037 rcout(sc, RC_DTREG, ~0);
1038}
1039
1040/* Set channel parameters */
1041static int
1042rc_param(struct tty *tp, struct termios *ts)
1043{
1044 struct rc_softc *sc;
1045 struct rc_chans *rc;
1046 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow;
1047
1048 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800
1049 || ts->c_ispeed < 0 || ts->c_ispeed > 76800
1050 )
1051 return (EINVAL);
1052 if (ts->c_ispeed == 0)
1053 ts->c_ispeed = ts->c_ospeed;
1054 odivs = RC_BRD(ts->c_ospeed);
1055 idivs = RC_BRD(ts->c_ispeed);
1056
1057 rc = TTY_TO_RC(tp);
1058 sc = rc->rc_rcb;
1059 s = spltty();
1060
1061 /* Select channel */
1062 rcout(sc, CD180_CAR, rc->rc_chan);
1063
1064 /* If speed == 0, hangup line */
1065 if (ts->c_ospeed == 0) {
1066 CCRCMD(sc, rc->rc_chan, CCR_ResetChan);
1067 WAITFORCCR(sc, rc->rc_chan);
1068 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1069 }
1070
1071 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1072 cflag = ts->c_cflag;
1073 iflag = ts->c_iflag;
1074 lflag = ts->c_lflag;
1075
1076 if (idivs > 0) {
1077 rcout(sc, CD180_RBPRL, idivs & 0xFF);
1078 rcout(sc, CD180_RBPRH, idivs >> 8);
1079 }
1080 if (odivs > 0) {
1081 rcout(sc, CD180_TBPRL, odivs & 0xFF);
1082 rcout(sc, CD180_TBPRH, odivs >> 8);
1083 }
1084
1085 /* set timeout value */
1086 if (ts->c_ispeed > 0) {
1087 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
1088
1089 if ( !(lflag & ICANON)
1090 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
1091 && ts->c_cc[VTIME] * 10 > itm)
1092 itm = ts->c_cc[VTIME] * 10;
1093
1094 rcout(sc, CD180_RTPR, itm <= 255 ? itm : 255);
1095 }
1096
1097 switch (cflag & CSIZE) {
1098 case CS5: val = COR1_5BITS; break;
1099 case CS6: val = COR1_6BITS; break;
1100 case CS7: val = COR1_7BITS; break;
1101 default:
1102 case CS8: val = COR1_8BITS; break;
1103 }
1104 if (cflag & PARENB) {
1105 val |= COR1_NORMPAR;
1106 if (cflag & PARODD)
1107 val |= COR1_ODDP;
1108 if (!(cflag & INPCK))
1109 val |= COR1_Ignore;
1110 } else
1111 val |= COR1_Ignore;
1112 if (cflag & CSTOPB)
1113 val |= COR1_2SB;
1114 rcout(sc, CD180_COR1, val);
1115
1116 /* Set FIFO threshold */
1117 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
1118 inpflow = 0;
1119 if ( (iflag & IXOFF)
1120 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE
1121 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE
1122 || (iflag & IXANY)
1123 )
1124 )
1125 ) {
1126 inpflow = 1;
1127 val |= COR3_SCDE|COR3_FCT;
1128 }
1129 rcout(sc, CD180_COR3, val);
1130
1131 /* Initialize on-chip automatic flow control */
1132 val = 0;
1133 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
1134 if (cflag & CCTS_OFLOW) {
1135 rc->rc_flags |= RC_CTSFLOW;
1136 val |= COR2_CtsAE;
1137 } else
1138 rc->rc_flags |= RC_SEND_RDY;
1139 if (tp->t_state & TS_TTSTOP)
1140 rc->rc_flags |= RC_OSUSP;
1141 else
1142 rc->rc_flags &= ~RC_OSUSP;
1143 if (cflag & CRTS_IFLOW)
1144 rc->rc_flags |= RC_RTSFLOW;
1145 else
1146 rc->rc_flags &= ~RC_RTSFLOW;
1147
1148 if (inpflow) {
1149 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
1150 rcout(sc, CD180_SCHR1, ts->c_cc[VSTART]);
1151 rcout(sc, CD180_SCHR2, ts->c_cc[VSTOP]);
1152 val |= COR2_TxIBE;
1153 if (iflag & IXANY)
1154 val |= COR2_IXM;
1155 }
1156
1157 rcout(sc, CD180_COR2, rc->rc_cor2 = val);
1158
1159 CCRCMD(sc, rc->rc_chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1160
1161 disc_optim(tp, ts, rc);
1162
1163 /* modem ctl */
1164 val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1165 if (cflag & CCTS_OFLOW)
1166 val |= MCOR1_CTSzd;
1167 rcout(sc, CD180_MCOR1, val);
1168
1169 val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1170 if (cflag & CCTS_OFLOW)
1171 val |= MCOR2_CTSod;
1172 rcout(sc, CD180_MCOR2, val);
1173
1174 /* enable i/o and interrupts */
1175 CCRCMD(sc, rc->rc_chan,
1176 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1177 WAITFORCCR(sc, rc->rc_chan);
1178
1179 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1180 if (cflag & CCTS_OFLOW)
1181 rc->rc_ier |= IER_CTS;
1182 if (cflag & CREAD)
1183 rc->rc_ier |= IER_RxData;
1184 if (tp->t_state & TS_BUSY)
1185 rc->rc_ier |= IER_TxRdy;
1186 if (ts->c_ospeed != 0)
1187 rc_modctl(rc, TIOCM_DTR, DMBIS);
1188 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1189 rc->rc_flags |= RC_SEND_RDY;
1190 rcout(sc, CD180_IER, rc->rc_ier);
1191 (void) splx(s);
1192 return 0;
1193}
1194
1195/* Re-initialize board after bogus interrupts */
1196static void
1197rc_reinit(struct rc_softc *sc)
1198{
1199 struct rc_chans *rc;
1200 int i;
1201
1202 rc_hwreset(sc, RC_FAKEID);
1203 rc = sc->sc_channels;
1204 for (i = 0; i < CD180_NCHAN; i++, rc++)
1205 (void) rc_param(&rc->rc_tp, &rc->rc_tp.t_termios);
1206}
1207
1208static int
1209rcioctl(dev_t dev, u_long cmd, caddr_t data, int flag, d_thread_t *td)
1210{
1211 struct rc_chans *rc;
1212 struct tty *tp;
1213 int s, error;
1214
1215 rc = DEV_TO_RC(dev);
1216 tp = &rc->rc_tp;
1217 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td);
1218 if (error != ENOIOCTL)
1219 return (error);
1220 error = ttioctl(tp, cmd, data, flag);
1221 disc_optim(tp, &tp->t_termios, rc);
1222 if (error != ENOIOCTL)
1223 return (error);
1224 s = spltty();
1225
1226 switch (cmd) {
1227 case TIOCSBRK:
1228 rc->rc_pendcmd = CD180_C_SBRK;
1229 break;
1230
1231 case TIOCCBRK:
1232 rc->rc_pendcmd = CD180_C_EBRK;
1233 break;
1234
1235 case TIOCSDTR:
1236 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1237 break;
1238
1239 case TIOCCDTR:
1240 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1241 break;
1242
1243 case TIOCMGET:
1244 *(int *) data = rc_modctl(rc, 0, DMGET);
1245 break;
1246
1247 case TIOCMSET:
1248 (void) rc_modctl(rc, *(int *) data, DMSET);
1249 break;
1250
1251 case TIOCMBIC:
1252 (void) rc_modctl(rc, *(int *) data, DMBIC);
1253 break;
1254
1255 case TIOCMBIS:
1256 (void) rc_modctl(rc, *(int *) data, DMBIS);
1257 break;
1258
1259 case TIOCMSDTRWAIT:
1260 error = suser(td);
1261 if (error != 0) {
1262 splx(s);
1263 return (error);
1264 }
1265 rc->rc_dtrwait = *(int *)data * hz / 100;
1266 break;
1267
1268 case TIOCMGDTRWAIT:
1269 *(int *)data = rc->rc_dtrwait * 100 / hz;
1270 break;
1271
1272 default:
1273 (void) splx(s);
1274 return ENOTTY;
1275 }
1276 (void) splx(s);
1277 return 0;
1278}
1279
1280
1281/* Modem control routines */
1282
1283static int
1284rc_modctl(struct rc_chans *rc, int bits, int cmd)
1285{
1286 struct rc_softc *sc;
1287 u_char *dtr;
1288 u_char msvr;
1289
1290 sc = rc->rc_rcb;
1291 dtr = &sc->sc_dtr;
1292 rcout(sc, CD180_CAR, rc->rc_chan);
1293
1294 switch (cmd) {
1295 case DMSET:
1296 rcout(sc, RC_DTREG, (bits & TIOCM_DTR) ?
1297 ~(*dtr |= 1 << rc->rc_chan) :
1298 ~(*dtr &= ~(1 << rc->rc_chan)));
1299 msvr = rcin(sc, CD180_MSVR);
1300 if (bits & TIOCM_RTS)
1301 msvr |= MSVR_RTS;
1302 else
1303 msvr &= ~MSVR_RTS;
1304 if (bits & TIOCM_DTR)
1305 msvr |= MSVR_DTR;
1306 else
1307 msvr &= ~MSVR_DTR;
1308 rcout(sc, CD180_MSVR, msvr);
1309 break;
1310
1311 case DMBIS:
1312 if (bits & TIOCM_DTR)
1313 rcout(sc, RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1314 msvr = rcin(sc, CD180_MSVR);
1315 if (bits & TIOCM_RTS)
1316 msvr |= MSVR_RTS;
1317 if (bits & TIOCM_DTR)
1318 msvr |= MSVR_DTR;
1319 rcout(sc, CD180_MSVR, msvr);
1320 break;
1321
1322 case DMGET:
1323 bits = TIOCM_LE;
1324 msvr = rc->rc_msvr = rcin(sc, CD180_MSVR);
1325
1326 if (msvr & MSVR_RTS)
1327 bits |= TIOCM_RTS;
1328 if (msvr & MSVR_CTS)
1329 bits |= TIOCM_CTS;
1330 if (msvr & MSVR_DSR)
1331 bits |= TIOCM_DSR;
1332 if (msvr & MSVR_DTR)
1333 bits |= TIOCM_DTR;
1334 if (msvr & MSVR_CD)
1335 bits |= TIOCM_CD;
1336 if (~rcin(sc, RC_RIREG) & (1 << rc->rc_chan))
1337 bits |= TIOCM_RI;
1338 return bits;
1339
1340 case DMBIC:
1341 if (bits & TIOCM_DTR)
1342 rcout(sc, RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1343 msvr = rcin(sc, CD180_MSVR);
1344 if (bits & TIOCM_RTS)
1345 msvr &= ~MSVR_RTS;
1346 if (bits & TIOCM_DTR)
1347 msvr &= ~MSVR_DTR;
1348 rcout(sc, CD180_MSVR, msvr);
1349 break;
1350 }
1351 rc->rc_msvr = rcin(sc, CD180_MSVR);
1352 return 0;
1353}
1354
1355#define ERR(s) do { \
1356 device_printf(sc->sc_dev, "%s", ""); \
1357 printf s ; \
1358 printf("\n"); \
1359 (void) splx(old_level); \
1360 return 1; \
1361} while (0)
1362
1363/* Test the board. */
1364int
1365rc_test(struct rc_softc *sc)
1366{
1367 int chan = 0;
1368 int i = 0, rcnt, old_level;
1369 unsigned int iack, chipid;
1370 unsigned short divs;
1371 static u_char ctest[] = "\377\125\252\045\244\0\377";
1372#define CTLEN 8
1373
1374 struct rtest {
1375 u_char txbuf[CD180_NFIFO]; /* TX buffer */
1376 u_char rxbuf[CD180_NFIFO]; /* RX buffer */
1377 int rxptr; /* RX pointer */
1378 int txptr; /* TX pointer */
1379 } tchans[CD180_NCHAN];
1380
1381 old_level = spltty();
1382
1383 chipid = RC_FAKEID;
1384
1385 /* First, reset board to inital state */
1386 rc_hwreset(sc, chipid);
1387
1388 divs = RC_BRD(19200);
1389
1390 /* Initialize channels */
1391 for (chan = 0; chan < CD180_NCHAN; chan++) {
1392
1393 /* Select and reset channel */
1394 rcout(sc, CD180_CAR, chan);
1395 CCRCMD(sc, chan, CCR_ResetChan);
1396 WAITFORCCR(sc, chan);
1397
1398 /* Set speed */
1399 rcout(sc, CD180_RBPRL, divs & 0xFF);
1400 rcout(sc, CD180_RBPRH, divs >> 8);
1401 rcout(sc, CD180_TBPRL, divs & 0xFF);
1402 rcout(sc, CD180_TBPRH, divs >> 8);
1403
1404 /* set timeout value */
1405 rcout(sc, CD180_RTPR, 0);
1406
1407 /* Establish local loopback */
1408 rcout(sc, CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1409 rcout(sc, CD180_COR2, COR2_LLM);
1410 rcout(sc, CD180_COR3, CD180_NFIFO);
1411 CCRCMD(sc, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1412 CCRCMD(sc, chan, CCR_RCVREN | CCR_XMTREN);
1413 WAITFORCCR(sc, chan);
1414 rcout(sc, CD180_MSVR, MSVR_RTS);
1415
1416 /* Fill TXBUF with test data */
1417 for (i = 0; i < CD180_NFIFO; i++) {
1418 tchans[chan].txbuf[i] = ctest[i];
1419 tchans[chan].rxbuf[i] = 0;
1420 }
1421 tchans[chan].txptr = tchans[chan].rxptr = 0;
1422
1423 /* Now, start transmit */
1424 rcout(sc, CD180_IER, IER_TxMpty|IER_RxData);
1425 }
1426 /* Pseudo-interrupt poll stuff */
1427 for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1428 i = ~(rcin(sc, RC_BSR));
1429 if (i & RC_BSR_TOUT)
1430 ERR(("BSR timeout bit set\n"));
1431 else if (i & RC_BSR_TXINT) {
1432 iack = rcin(sc, RC_PILR_TX);
1433 if (iack != (GIVR_IT_TDI | chipid))
1434 ERR(("Bad TX intr ack (%02x != %02x)\n",
1435 iack, GIVR_IT_TDI | chipid));
1436 chan = (rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1437 /* If no more data to transmit, disable TX intr */
1438 if (tchans[chan].txptr >= CD180_NFIFO) {
1439 iack = rcin(sc, CD180_IER);
1440 rcout(sc, CD180_IER, iack & ~IER_TxMpty);
1441 } else {
1442 for (iack = tchans[chan].txptr;
1443 iack < CD180_NFIFO; iack++)
1444 rcout(sc, CD180_TDR,
1445 tchans[chan].txbuf[iack]);
1446 tchans[chan].txptr = iack;
1447 }
1448 rcout(sc, CD180_EOIR, 0);
1449 } else if (i & RC_BSR_RXINT) {
1450 u_char ucnt;
1451
1452 iack = rcin(sc, RC_PILR_RX);
1453 if (iack != (GIVR_IT_RGDI | chipid) &&
1454 iack != (GIVR_IT_REI | chipid))
1455 ERR(("Bad RX intr ack (%02x != %02x)\n",
1456 iack, GIVR_IT_RGDI | chipid));
1457 chan = (rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1458 ucnt = rcin(sc, CD180_RDCR) & 0xF;
1459 while (ucnt-- > 0) {
1460 iack = rcin(sc, CD180_RCSR);
1461 if (iack & RCSR_Timeout)
1462 break;
1463 if (iack & 0xF)
1464 ERR(("Bad char chan %d (RCSR = %02X)\n",
1465 chan, iack));
1466 if (tchans[chan].rxptr > CD180_NFIFO)
1467 ERR(("Got extra chars chan %d\n",
1468 chan));
1469 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1470 rcin(sc, CD180_RDR);
1471 }
1472 rcout(sc, CD180_EOIR, 0);
1473 }
1474 rcout(sc, RC_CTOUT, 0);
1475 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1476 if (tchans[chan].rxptr >= CD180_NFIFO)
1477 iack++;
1478 if (iack == CD180_NCHAN)
1479 break;
1480 }
1481 for (chan = 0; chan < CD180_NCHAN; chan++) {
1482 /* Select and reset channel */
1483 rcout(sc, CD180_CAR, chan);
1484 CCRCMD(sc, chan, CCR_ResetChan);
1485 }
1486
1487 if (!rcnt)
1488 ERR(("looses characters during local loopback\n"));
1489 /* Now, check data */
1490 for (chan = 0; chan < CD180_NCHAN; chan++)
1491 for (i = 0; i < CD180_NFIFO; i++)
1492 if (ctest[i] != tchans[chan].rxbuf[i])
1493 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1494 chan, i, ctest[i], tchans[chan].rxbuf[i]));
1495 (void) splx(old_level);
1496 return 0;
1497}
1498
1499#ifdef RCDEBUG
1500static void
1501printrcflags(struct rc_chans *rc, char *comment)
1502{
1503 struct rc_softc *sc;
1504 u_short f = rc->rc_flags;
1505
1506 sc = rc->rc_rcb;
1507 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1508 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1509 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1510 (f & RC_ACTOUT) ?"ACTOUT " :"",
1511 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1512 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1513 (f & RC_DORXFER)?"DORXFER " :"",
1514 (f & RC_DOXXFER)?"DOXXFER " :"",
1515 (f & RC_MODCHG) ?"MODCHG " :"",
1516 (f & RC_OSUSP) ?"OSUSP " :"",
1517 (f & RC_OSBUSY) ?"OSBUSY " :"",
1518 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1519 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1520 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1521
1522 rcout(sc, CD180_CAR, rc->rc_chan);
1523
1524 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1525 rc->rc_rcb->rcb_unit, rc->rc_chan,
1526 rcin(sc, CD180_MSVR),
1527 rcin(sc, CD180_IER),
1528 rcin(sc, CD180_CCSR));
1529}
1530#endif /* RCDEBUG */
1531
1532static void
1533rc_dtrwakeup(void *arg)
1534{
1535 struct rc_chans *rc;
1536
1537 rc = (struct rc_chans *)arg;
1538 rc->rc_flags &= ~RC_DTR_OFF;
1539 wakeup(&rc->rc_dtrwait);
1540}
1541
1542static void
1543rc_discard_output(struct rc_chans *rc)
1544{
1545 critical_enter();
1546 if (rc->rc_flags & RC_DOXXFER) {
1547 rc->rc_rcb->sc_scheduled_event -= LOTS_OF_EVENTS;
1548 rc->rc_flags &= ~RC_DOXXFER;
1549 }
1550 rc->rc_optr = rc->rc_obufend;
1551 rc->rc_tp.t_state &= ~TS_BUSY;
1552 critical_exit();
1553 ttwwakeup(&rc->rc_tp);
1554}
1555
1556static void
1557disc_optim(struct tty *tp, struct termios *t, struct rc_chans *rc)
1558{
1559
1560 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1561 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1562 && (!(t->c_iflag & PARMRK)
1563 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1564 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1565 && linesw[tp->t_line].l_rint == ttyinput)
1566 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1567 else
1568 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1569 rc->rc_hotchar = linesw[tp->t_line].l_hotchar;
1570}
1571
1572static void
1573rc_wait0(struct rc_softc *sc, int chan, int line)
1574{
1575 int rcnt;
1576
1577 for (rcnt = 50; rcnt && rcin(sc, CD180_CCR); rcnt--)
1578 DELAY(30);
1579 if (rcnt == 0)
1580 device_printf(sc->sc_dev,
1581 "channel %d command timeout, rc.c line: %d\n", chan, line);
1582}
1583
1584static device_method_t rc_methods[] = {
1585 /* Device interface */
1586 DEVMETHOD(device_probe, rc_probe),
1587 DEVMETHOD(device_attach, rc_attach),
1588 DEVMETHOD(device_detach, rc_detach),
1589 { 0, 0 }
1590};
1591
1592static driver_t rc_driver = {
1593 "rc",
1594 rc_methods, sizeof(struct rc_softc),
1595};
1596
1597DRIVER_MODULE(rc, isa, rc_driver, rc_devclass, 0, 0);
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