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qlnx_def.h (320164) qlnx_def.h (322851)
1/*
2 * Copyright (c) 2017-2018 Cavium, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

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19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 *
1/*
2 * Copyright (c) 2017-2018 Cavium, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

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19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 *
27 * $FreeBSD: stable/11/sys/dev/qlnx/qlnxe/qlnx_def.h 320164 2017-06-20 19:16:06Z davidcs $
27 * $FreeBSD: stable/11/sys/dev/qlnx/qlnxe/qlnx_def.h 322851 2017-08-24 18:51:55Z davidcs $
28 *
29 */
30
31
32
33/*
34 * File: qlnx_def.h
35 * Author : David C Somayajulu, Cavium Inc., San Jose, CA 95131.

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45 void *ha;
46 struct resource *irq;
47 void *handle;
48 int irq_rid;
49};
50
51typedef struct qlnx_ivec qlnx_ivec_t;
52
28 *
29 */
30
31
32
33/*
34 * File: qlnx_def.h
35 * Author : David C Somayajulu, Cavium Inc., San Jose, CA 95131.

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45 void *ha;
46 struct resource *irq;
47 void *handle;
48 int irq_rid;
49};
50
51typedef struct qlnx_ivec qlnx_ivec_t;
52
53//#define QLNX_MAX_RSS 30
54#define QLNX_MAX_RSS 16
55#define QLNX_MAX_TC 1
53//#define QLNX_MAX_RSS 30
54#define QLNX_MAX_RSS 36
55#define QLNX_DEFAULT_RSS 16
56#define QLNX_MAX_TC 1
56
57enum QLNX_STATE {
58 QLNX_STATE_CLOSED,
59 QLNX_STATE_OPEN,
60};
61
62#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
63

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196 struct task fp_task;
197 struct taskqueue *fp_taskqueue;
198
199 /* transmit statistics */
200 uint64_t tx_pkts_processed;
201 uint64_t tx_pkts_freed;
202 uint64_t tx_pkts_transmitted;
203 uint64_t tx_pkts_completed;
57
58enum QLNX_STATE {
59 QLNX_STATE_CLOSED,
60 QLNX_STATE_OPEN,
61};
62
63#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
64

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197 struct task fp_task;
198 struct taskqueue *fp_taskqueue;
199
200 /* transmit statistics */
201 uint64_t tx_pkts_processed;
202 uint64_t tx_pkts_freed;
203 uint64_t tx_pkts_transmitted;
204 uint64_t tx_pkts_completed;
205 uint64_t tx_tso_pkts;
206 uint64_t tx_non_tso_pkts;
207
208#ifdef QLNX_TRACE_PERF_DATA
209 uint64_t tx_pkts_trans_ctx;
210 uint64_t tx_pkts_compl_ctx;
211 uint64_t tx_pkts_trans_fp;
212 uint64_t tx_pkts_compl_fp;
213 uint64_t tx_pkts_compl_intr;
214#endif
215
204 uint64_t tx_lso_wnd_min_len;
205 uint64_t tx_defrag;
206 uint64_t tx_nsegs_gt_elem_left;
207 uint32_t tx_tso_max_nsegs;
208 uint32_t tx_tso_min_nsegs;
209 uint32_t tx_tso_max_pkt_len;
210 uint32_t tx_tso_min_pkt_len;
211 uint64_t tx_pkts[QLNX_FP_MAX_SEGS];
216 uint64_t tx_lso_wnd_min_len;
217 uint64_t tx_defrag;
218 uint64_t tx_nsegs_gt_elem_left;
219 uint32_t tx_tso_max_nsegs;
220 uint32_t tx_tso_min_nsegs;
221 uint32_t tx_tso_max_pkt_len;
222 uint32_t tx_tso_min_pkt_len;
223 uint64_t tx_pkts[QLNX_FP_MAX_SEGS];
224
225#ifdef QLNX_TRACE_PERF_DATA
226 uint64_t tx_pkts_hist[QLNX_FP_MAX_SEGS];
227 uint64_t tx_comInt[QLNX_FP_MAX_SEGS];
228 uint64_t tx_pkts_q[QLNX_FP_MAX_SEGS];
229#endif
230
212 uint64_t err_tx_nsegs_gt_elem_left;
213 uint64_t err_tx_dmamap_create;
214 uint64_t err_tx_defrag_dmamap_load;
215 uint64_t err_tx_non_tso_max_seg;
216 uint64_t err_tx_dmamap_load;
217 uint64_t err_tx_defrag;
218 uint64_t err_tx_free_pkt_null;
219 uint64_t err_tx_cons_idx_conflict;

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296 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT)
297
298#define RX_COPY_THRESH 92
299#define ETH_MAX_PACKET_SIZE 1500
300
301#define QLNX_MFW_VERSION_LENGTH 32
302#define QLNX_STORMFW_VERSION_LENGTH 32
303
231 uint64_t err_tx_nsegs_gt_elem_left;
232 uint64_t err_tx_dmamap_create;
233 uint64_t err_tx_defrag_dmamap_load;
234 uint64_t err_tx_non_tso_max_seg;
235 uint64_t err_tx_dmamap_load;
236 uint64_t err_tx_defrag;
237 uint64_t err_tx_free_pkt_null;
238 uint64_t err_tx_cons_idx_conflict;

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315 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT)
316
317#define RX_COPY_THRESH 92
318#define ETH_MAX_PACKET_SIZE 1500
319
320#define QLNX_MFW_VERSION_LENGTH 32
321#define QLNX_STORMFW_VERSION_LENGTH 32
322
304#define QLNX_TX_ELEM_RESERVE 2
323#define QLNX_TX_ELEM_RESERVE 2
324#define QLNX_TX_ELEM_THRESH 128
325#define QLNX_TX_ELEM_MAX_THRESH 512
326#define QLNX_TX_ELEM_MIN_THRESH 32
327#define QLNX_TX_COMPL_THRESH 32
305
328
329
306#define QLNX_TPA_MAX_AGG_BUFFERS (20)
307
308#define QLNX_MAX_NUM_MULTICAST_ADDRS ECORE_MAX_MC_ADDRS
309typedef struct _qlnx_mcast {
310 uint16_t rsrvd;
311 uint8_t addr[6];
312} __packed qlnx_mcast_t;
313

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449 void *idle_chk[QLNX_MAX_HW_FUNCS];
450
451 /* storm stats related */
452#define QLNX_STORM_STATS_TOTAL \
453 (QLNX_MAX_HW_FUNCS * QLNX_STORM_STATS_SAMPLES_PER_HWFN)
454 qlnx_storm_stats_t storm_stats[QLNX_STORM_STATS_TOTAL];
455 uint32_t storm_stats_index;
456 uint32_t storm_stats_enable;
330#define QLNX_TPA_MAX_AGG_BUFFERS (20)
331
332#define QLNX_MAX_NUM_MULTICAST_ADDRS ECORE_MAX_MC_ADDRS
333typedef struct _qlnx_mcast {
334 uint16_t rsrvd;
335 uint8_t addr[6];
336} __packed qlnx_mcast_t;
337

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473 void *idle_chk[QLNX_MAX_HW_FUNCS];
474
475 /* storm stats related */
476#define QLNX_STORM_STATS_TOTAL \
477 (QLNX_MAX_HW_FUNCS * QLNX_STORM_STATS_SAMPLES_PER_HWFN)
478 qlnx_storm_stats_t storm_stats[QLNX_STORM_STATS_TOTAL];
479 uint32_t storm_stats_index;
480 uint32_t storm_stats_enable;
481 uint32_t storm_stats_gather;
457
458 uint32_t personality;
459};
460
461typedef struct qlnx_host qlnx_host_t;
462
463/* note that align has to be a power of 2 */
464#define QL_ALIGN(size, align) (size + (align - 1)) & ~(align - 1);
465#define QL_MIN(x, y) ((x < y) ? x : y)
466
467#define QL_RUNNING(ifp) \
468 ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == \
469 IFF_DRV_RUNNING)
470
471#define QLNX_MAX_MTU 9000
472#define QLNX_MAX_SEGMENTS_NON_TSO (ETH_TX_MAX_BDS_PER_NON_LSO_PACKET - 1)
482
483 uint32_t personality;
484};
485
486typedef struct qlnx_host qlnx_host_t;
487
488/* note that align has to be a power of 2 */
489#define QL_ALIGN(size, align) (size + (align - 1)) & ~(align - 1);
490#define QL_MIN(x, y) ((x < y) ? x : y)
491
492#define QL_RUNNING(ifp) \
493 ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == \
494 IFF_DRV_RUNNING)
495
496#define QLNX_MAX_MTU 9000
497#define QLNX_MAX_SEGMENTS_NON_TSO (ETH_TX_MAX_BDS_PER_NON_LSO_PACKET - 1)
473#define QLNX_MAX_TSO_FRAME_SIZE ((64 * 1024 - 1) + 22)
498//#define QLNX_MAX_TSO_FRAME_SIZE ((64 * 1024 - 1) + 22)
499#define QLNX_MAX_TSO_FRAME_SIZE 65536
500#define QLNX_MAX_TX_MBUF_SIZE 65536 /* bytes - bd_len = 16bits */
474
501
502
475#define QL_MAC_CMP(mac1, mac2) \
476 ((((*(uint32_t *) mac1) == (*(uint32_t *) mac2) && \
477 (*(uint16_t *)(mac1 + 4)) == (*(uint16_t *)(mac2 + 4)))) ? 0 : 1)
478#define for_each_rss(i) for (i = 0; i < ha->num_rss; i++)
479
480/*
481 * Debug Related
482 */

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698#define CQE_L4_HAS_CSUM(flags) \
699 ((flags) & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK \
700 << PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT))
701
702#define CQE_HAS_VLAN(flags) \
703 ((flags) & (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK \
704 << PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT))
705
503#define QL_MAC_CMP(mac1, mac2) \
504 ((((*(uint32_t *) mac1) == (*(uint32_t *) mac2) && \
505 (*(uint16_t *)(mac1 + 4)) == (*(uint16_t *)(mac2 + 4)))) ? 0 : 1)
506#define for_each_rss(i) for (i = 0; i < ha->num_rss; i++)
507
508/*
509 * Debug Related
510 */

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726#define CQE_L4_HAS_CSUM(flags) \
727 ((flags) & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK \
728 << PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT))
729
730#define CQE_HAS_VLAN(flags) \
731 ((flags) & (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK \
732 << PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT))
733
734#if defined(__i386__) || defined(__amd64__)
706
735
736static __inline
737void prefetch(void *x)
738{
739 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
740}
741
742#else
743#define prefetch(x)
744#endif
745
746
707#endif /* #ifndef _QLNX_DEF_H_ */
747#endif /* #ifndef _QLNX_DEF_H_ */