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ecore_dev.c (318300) ecore_dev.c (320164)
1/*
2 * Copyright (c) 2017-2018 Cavium, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

--- 15 unchanged lines hidden (view full) ---

24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28/*
29 * File : ecore_dev.c
30 */
31#include <sys/cdefs.h>
1/*
2 * Copyright (c) 2017-2018 Cavium, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

--- 15 unchanged lines hidden (view full) ---

24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28/*
29 * File : ecore_dev.c
30 */
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: stable/11/sys/dev/qlnx/qlnxe/ecore_dev.c 318300 2017-05-15 17:45:05Z davidcs $");
32__FBSDID("$FreeBSD: stable/11/sys/dev/qlnx/qlnxe/ecore_dev.c 320164 2017-06-20 19:16:06Z davidcs $");
33
33
34
35#include "bcm_osal.h"
36#include "reg_addr.h"
37#include "ecore_gtt_reg_addr.h"
38#include "ecore.h"
39#include "ecore_chain.h"
40#include "ecore_status.h"
41#include "ecore_hw.h"
42#include "ecore_rt_defs.h"

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69 * some of the PFs configuration might be lost.
70 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
71 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
72 * there's more than a single compiled ecore component in system].
73 */
74static osal_spinlock_t qm_lock;
75static bool qm_lock_init = false;
76
34#include "bcm_osal.h"
35#include "reg_addr.h"
36#include "ecore_gtt_reg_addr.h"
37#include "ecore.h"
38#include "ecore_chain.h"
39#include "ecore_status.h"
40#include "ecore_hw.h"
41#include "ecore_rt_defs.h"

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68 * some of the PFs configuration might be lost.
69 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
70 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
71 * there's more than a single compiled ecore component in system].
72 */
73static osal_spinlock_t qm_lock;
74static bool qm_lock_init = false;
75
76/******************** Doorbell Recovery *******************/
77/* The doorbell recovery mechanism consists of a list of entries which represent
78 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
79 * entity needs to register with the mechanism and provide the parameters
80 * describing it's doorbell, including a location where last used doorbell data
81 * can be found. The doorbell execute function will traverse the list and
82 * doorbell all of the registered entries.
83 */
84struct ecore_db_recovery_entry {
85 osal_list_entry_t list_entry;
86 void OSAL_IOMEM *db_addr;
87 void *db_data;
88 enum ecore_db_rec_width db_width;
89 enum ecore_db_rec_space db_space;
90 u8 hwfn_idx;
91};
92
93/* display a single doorbell recovery entry */
94static void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
95 struct ecore_db_recovery_entry *db_entry,
96 char *action)
97{
98 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
99 action, db_entry, db_entry->db_addr, db_entry->db_data,
100 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
101 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
102 db_entry->hwfn_idx);
103}
104
105/* doorbell address sanity (address within doorbell bar range) */
106static bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr)
107{
108 if (db_addr < p_dev->doorbells || db_addr >
109 (void OSAL_IOMEM *)((uint8_t *)p_dev->doorbells + p_dev->db_size)) {
110 OSAL_WARN(true,
111 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
112 db_addr, p_dev->doorbells,
113 (void *)((uint8_t *)p_dev->doorbells + p_dev->db_size));
114 return false;
115 } else {
116 return true;
117 }
118}
119
120/* find hwfn according to the doorbell address */
121static struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
122 void OSAL_IOMEM *db_addr)
123{
124 struct ecore_hwfn *p_hwfn;
125
126 /* in CMT doorbell bar is split down the middle between engine 0 and enigne 1 */
127 if (p_dev->num_hwfns > 1)
128 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
129 &p_dev->hwfns[0] : &p_dev->hwfns[1];
130 else
131 p_hwfn = ECORE_LEADING_HWFN(p_dev);
132
133 return p_hwfn;
134}
135
136/* add a new entry to the doorbell recovery mechanism */
137enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
138 void OSAL_IOMEM *db_addr,
139 void *db_data,
140 enum ecore_db_rec_width db_width,
141 enum ecore_db_rec_space db_space)
142{
143 struct ecore_db_recovery_entry *db_entry;
144 struct ecore_hwfn *p_hwfn;
145
146 /* shortcircuit VFs, for now */
147 if (IS_VF(p_dev)) {
148 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
149 return ECORE_SUCCESS;
150 }
151
152 /* sanitize doorbell address */
153 if (!ecore_db_rec_sanity(p_dev, db_addr))
154 return ECORE_INVAL;
155
156 /* obtain hwfn from doorbell address */
157 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
158
159 /* create entry */
160 db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
161 if (!db_entry) {
162 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
163 return ECORE_NOMEM;
164 }
165
166 /* populate entry */
167 db_entry->db_addr = db_addr;
168 db_entry->db_data = db_data;
169 db_entry->db_width = db_width;
170 db_entry->db_space = db_space;
171 db_entry->hwfn_idx = p_hwfn->my_id;
172
173 /* display */
174 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
175
176 /* protect the list */
177 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
178 OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
179 &p_hwfn->db_recovery_info.list);
180 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
181
182 return ECORE_SUCCESS;
183}
184
185/* remove an entry from the doorbell recovery mechanism */
186enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
187 void OSAL_IOMEM *db_addr,
188 void *db_data)
189{
190 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
191 enum _ecore_status_t rc = ECORE_INVAL;
192 struct ecore_hwfn *p_hwfn;
193
194 /* shortcircuit VFs, for now */
195 if (IS_VF(p_dev)) {
196 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
197 return ECORE_SUCCESS;
198 }
199
200 /* sanitize doorbell address */
201 if (!ecore_db_rec_sanity(p_dev, db_addr))
202 return ECORE_INVAL;
203
204 /* obtain hwfn from doorbell address */
205 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
206
207 /* protect the list */
208 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
209 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
210 &p_hwfn->db_recovery_info.list,
211 list_entry,
212 struct ecore_db_recovery_entry) {
213
214 /* search according to db_data addr since db_addr is not unique (roce) */
215 if (db_entry->db_data == db_data) {
216 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Deleting");
217 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
218 &p_hwfn->db_recovery_info.list);
219 rc = ECORE_SUCCESS;
220 break;
221 }
222 }
223
224 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
225
226 if (rc == ECORE_INVAL) {
227 OSAL_WARN(true, "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
228 db_data, db_addr);
229 } else {
230 OSAL_FREE(p_dev, db_entry);
231 }
232
233 return rc;
234}
235
236/* initialize the doorbell recovery mechanism */
237static void ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
238{
239 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
240 OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
241#ifdef CONFIG_ECORE_LOCK_ALLOC
242 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock);
243#endif
244 OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
245 p_hwfn->db_recovery_info.db_recovery_counter = 0;
246}
247
248/* destroy the doorbell recovery mechanism */
249static void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
250{
251 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
252
253 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
254 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
255 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
256 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
257 db_entry = OSAL_LIST_FIRST_ENTRY(&p_hwfn->db_recovery_info.list,
258 struct ecore_db_recovery_entry,
259 list_entry);
260 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
261 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
262 &p_hwfn->db_recovery_info.list);
263 OSAL_FREE(p_hwfn->p_dev, db_entry);
264 }
265 }
266#ifdef CONFIG_ECORE_LOCK_ALLOC
267 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
268#endif
269 p_hwfn->db_recovery_info.db_recovery_counter = 0;
270}
271
272/* print the content of the doorbell recovery mechanism */
273void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
274{
275 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
276
277 DP_NOTICE(p_hwfn, false,
278 "Dispalying doorbell recovery database. Counter was %d\n",
279 p_hwfn->db_recovery_info.db_recovery_counter);
280
281 /* protect the list */
282 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
283 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
284 &p_hwfn->db_recovery_info.list,
285 list_entry,
286 struct ecore_db_recovery_entry) {
287 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
288 }
289
290 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
291}
292
293/* ring the doorbell of a single doorbell recovery entry */
294static void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
295 struct ecore_db_recovery_entry *db_entry,
296 enum ecore_db_rec_exec db_exec)
297{
298 /* Print according to width */
299 if (db_entry->db_width == DB_REC_WIDTH_32B)
300 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
301 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
302 db_entry->db_addr, *(u32 *)db_entry->db_data);
303 else
304 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %llx\n",
305 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
306 db_entry->db_addr, (unsigned long long)*(u64 *)(db_entry->db_data));
307
308 /* Sanity */
309 if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr))
310 return;
311
312 /* Flush the write combined buffer. Since there are multiple doorbelling
313 * entities using the same address, if we don't flush, a transaction
314 * could be lost.
315 */
316 OSAL_WMB(p_hwfn->p_dev);
317
318 /* Ring the doorbell */
319 if (db_exec == DB_REC_REAL_DEAL) {
320 if (db_entry->db_width == DB_REC_WIDTH_32B)
321 DIRECT_REG_WR(p_hwfn, db_entry->db_addr, *(u32 *)(db_entry->db_data));
322 else
323 DIRECT_REG_WR64(p_hwfn, db_entry->db_addr, *(u64 *)(db_entry->db_data));
324 }
325
326 /* Flush the write combined buffer. Next doorbell may come from a
327 * different entity to the same address...
328 */
329 OSAL_WMB(p_hwfn->p_dev);
330}
331
332/* traverse the doorbell recovery entry list and ring all the doorbells */
333void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
334 enum ecore_db_rec_exec db_exec)
335{
336 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
337
338 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
339 p_hwfn->db_recovery_info.db_recovery_counter);
340
341 /* protect the list */
342 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
343 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
344 &p_hwfn->db_recovery_info.list,
345 list_entry,
346 struct ecore_db_recovery_entry)
347 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
348 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
349
350 /* track amount of times recovery was executed */
351 p_hwfn->db_recovery_info.db_recovery_counter++;
352}
353/******************** Doorbell Recovery end ****************/
354
77/* Configurable */
78#define ECORE_MIN_DPIS (4) /* The minimal number of DPIs required to
79 * load the driver. The number was
80 * arbitrarily set.
81 */
82
83/* Derived */
355/* Configurable */
356#define ECORE_MIN_DPIS (4) /* The minimal number of DPIs required to
357 * load the driver. The number was
358 * arbitrarily set.
359 */
360
361/* Derived */
84#define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
362#define ECORE_MIN_PWM_REGION (ECORE_WID_SIZE * ECORE_MIN_DPIS)
85
86enum BAR_ID {
87 BAR_ID_0, /* used for GRC */
88 BAR_ID_1 /* Used for doorbells */
89};
90
363
364enum BAR_ID {
365 BAR_ID_0, /* used for GRC */
366 BAR_ID_1 /* Used for doorbells */
367};
368
91static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
369static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
370 struct ecore_ptt *p_ptt,
371 enum BAR_ID bar_id)
92{
93 u32 bar_reg = (bar_id == BAR_ID_0 ?
94 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
95 u32 val;
96
97 if (IS_VF(p_hwfn->p_dev)) {
98 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
99 * read from actual register, but we're currently not using
100 * it for actual doorbelling.
101 */
102 return 1 << 17;
103 }
104
372{
373 u32 bar_reg = (bar_id == BAR_ID_0 ?
374 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
375 u32 val;
376
377 if (IS_VF(p_hwfn->p_dev)) {
378 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
379 * read from actual register, but we're currently not using
380 * it for actual doorbelling.
381 */
382 return 1 << 17;
383 }
384
105 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
385 val = ecore_rd(p_hwfn, p_ptt, bar_reg);
106 if (val)
107 return 1 << (val + 15);
108
109 /* The above registers were updated in the past only in CMT mode. Since
110 * they were found to be useful MFW started updating them from 8.7.7.0.
111 * In older MFW versions they are set to 0 which means disabled.
112 */
113 if (p_hwfn->p_dev->num_hwfns > 1) {
386 if (val)
387 return 1 << (val + 15);
388
389 /* The above registers were updated in the past only in CMT mode. Since
390 * they were found to be useful MFW started updating them from 8.7.7.0.
391 * In older MFW versions they are set to 0 which means disabled.
392 */
393 if (p_hwfn->p_dev->num_hwfns > 1) {
114 DP_NOTICE(p_hwfn, false,
115 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
394 DP_INFO(p_hwfn,
395 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
116 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
117 } else {
396 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
397 } else {
118 DP_NOTICE(p_hwfn, false,
119 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
398 DP_INFO(p_hwfn,
399 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
120 return 512 * 1024;
121 }
122}
123
124void ecore_init_dp(struct ecore_dev *p_dev,
125 u32 dp_module,
126 u8 dp_level,
127 void *dp_ctx)

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146
147 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
148 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
149
150 p_hwfn->p_dev = p_dev;
151 p_hwfn->my_id = i;
152 p_hwfn->b_active = false;
153
400 return 512 * 1024;
401 }
402}
403
404void ecore_init_dp(struct ecore_dev *p_dev,
405 u32 dp_module,
406 u8 dp_level,
407 void *dp_ctx)

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426
427 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
428 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
429
430 p_hwfn->p_dev = p_dev;
431 p_hwfn->my_id = i;
432 p_hwfn->b_active = false;
433
434#ifdef CONFIG_ECORE_LOCK_ALLOC
154 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
435 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
436#endif
155 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
156 }
157
158 /* hwfn 0 is always active */
159 p_dev->hwfns[0].b_active = true;
160
161 /* set the default cache alignment to 128 (may be overridden later) */
162 p_dev->cache_shift = 7;

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214 ecore_ooo_free(p_hwfn);
215 }
216#endif
217 ecore_iov_free(p_hwfn);
218 ecore_l2_free(p_hwfn);
219 ecore_dmae_info_free(p_hwfn);
220 ecore_dcbx_info_free(p_hwfn);
221 /* @@@TBD Flush work-queue ?*/
437 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
438 }
439
440 /* hwfn 0 is always active */
441 p_dev->hwfns[0].b_active = true;
442
443 /* set the default cache alignment to 128 (may be overridden later) */
444 p_dev->cache_shift = 7;

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496 ecore_ooo_free(p_hwfn);
497 }
498#endif
499 ecore_iov_free(p_hwfn);
500 ecore_l2_free(p_hwfn);
501 ecore_dmae_info_free(p_hwfn);
502 ecore_dcbx_info_free(p_hwfn);
503 /* @@@TBD Flush work-queue ?*/
504
505 /* destroy doorbell recovery mechanism */
506 ecore_db_recovery_teardown(p_hwfn);
222 }
223}
224
225/******************** QM initialization *******************/
507 }
508}
509
510/******************** QM initialization *******************/
226
227/* bitmaps for indicating active traffic classes. Special case for Arrowhead 4 port */
228#define ACTIVE_TCS_BMAP 0x9f /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
229#define ACTIVE_TCS_BMAP_4PORT_K2 0xf /* 0..3 actually used, OOO and high priority stuff all use 3 */
230
231/* determines the physical queue flags for a given PF. */
232static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
233{
234 u32 flags;

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337 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
338 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
339
340 /* rate limiting and weighted fair queueing are always enabled */
341 qm_info->vport_rl_en = 1;
342 qm_info->vport_wfq_en = 1;
343
344 /* TC config is different for AH 4 port */
511/* bitmaps for indicating active traffic classes. Special case for Arrowhead 4 port */
512#define ACTIVE_TCS_BMAP 0x9f /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
513#define ACTIVE_TCS_BMAP_4PORT_K2 0xf /* 0..3 actually used, OOO and high priority stuff all use 3 */
514
515/* determines the physical queue flags for a given PF. */
516static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
517{
518 u32 flags;

--- 102 unchanged lines hidden (view full) ---

621 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
622 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
623
624 /* rate limiting and weighted fair queueing are always enabled */
625 qm_info->vport_rl_en = 1;
626 qm_info->vport_wfq_en = 1;
627
628 /* TC config is different for AH 4 port */
345 four_port = p_hwfn->p_dev->num_ports_in_engines == MAX_NUM_PORTS_K2;
629 four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
346
347 /* in AH 4 port we have fewer TCs per port */
348 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 : NUM_OF_PHYS_TCS;
349
350 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and 4 otherwise */
351 if (!qm_info->ooo_tc)
352 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC : DCBX_TCP_OOO_TC;
353}

--- 8 unchanged lines hidden (view full) ---

362 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
363 qm_info->qm_vport_params[i].vport_wfq = 1;
364}
365
366/* initialize qm port params */
367static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
368{
369 /* Initialize qm port parameters */
630
631 /* in AH 4 port we have fewer TCs per port */
632 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 : NUM_OF_PHYS_TCS;
633
634 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and 4 otherwise */
635 if (!qm_info->ooo_tc)
636 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC : DCBX_TCP_OOO_TC;
637}

--- 8 unchanged lines hidden (view full) ---

646 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
647 qm_info->qm_vport_params[i].vport_wfq = 1;
648}
649
650/* initialize qm port params */
651static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
652{
653 /* Initialize qm port parameters */
370 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engines;
654 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
371
372 /* indicate how ooo and high pri traffic is dealt with */
373 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
374 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
375
376 for (i = 0; i < num_ports; i++) {
377 struct init_qm_port_params *p_qm_port =
378 &p_hwfn->qm_info.qm_port_params[i];
379
380 p_qm_port->active = 1;
381 p_qm_port->active_phys_tcs = active_phys_tcs;
655
656 /* indicate how ooo and high pri traffic is dealt with */
657 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
658 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
659
660 for (i = 0; i < num_ports; i++) {
661 struct init_qm_port_params *p_qm_port =
662 &p_hwfn->qm_info.qm_port_params[i];
663
664 p_qm_port->active = 1;
665 p_qm_port->active_phys_tcs = active_phys_tcs;
382 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
666 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
383 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
384 }
385}
386
387/* Reset the params which must be reset for qm init. QM init may be called as
388 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
389 * params may be affected by the init but would simply recalculate to the same
390 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not

--- 308 unchanged lines hidden (view full) ---

699 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
700 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq, qm_info->offload_pq, qm_info->pure_ack_pq);
701 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
702 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs, qm_info->num_vf_pqs, qm_info->num_vports, qm_info->max_phys_tcs_per_port);
703 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
704 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en, qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl, qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
705
706 /* port table */
667 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
668 }
669}
670
671/* Reset the params which must be reset for qm init. QM init may be called as
672 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
673 * params may be affected by the init but would simply recalculate to the same
674 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not

--- 308 unchanged lines hidden (view full) ---

983 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
984 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq, qm_info->offload_pq, qm_info->pure_ack_pq);
985 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
986 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs, qm_info->num_vf_pqs, qm_info->num_vports, qm_info->max_phys_tcs_per_port);
987 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
988 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en, qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl, qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
989
990 /* port table */
707 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engines; i++) {
991 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
708 port = &(qm_info->qm_port_params[i]);
709 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
710 i, port->active, port->active_phys_tcs, port->num_pbf_cmd_lines, port->num_btb_blocks, port->reserved);
711 }
712
713 /* vport table */
714 for (i = 0; i < qm_info->num_vports; i++) {
715 vport = &(qm_info->qm_vport_params[i]);

--- 58 unchanged lines hidden (view full) ---

774 OSAL_SPIN_UNLOCK(&qm_lock);
775 if (!b_rc)
776 return ECORE_INVAL;
777
778 /* clear the QM_PF runtime phase leftovers from previous init */
779 ecore_init_clear_rt_data(p_hwfn);
780
781 /* prepare QM portion of runtime array */
992 port = &(qm_info->qm_port_params[i]);
993 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
994 i, port->active, port->active_phys_tcs, port->num_pbf_cmd_lines, port->num_btb_blocks, port->reserved);
995 }
996
997 /* vport table */
998 for (i = 0; i < qm_info->num_vports; i++) {
999 vport = &(qm_info->qm_vport_params[i]);

--- 58 unchanged lines hidden (view full) ---

1058 OSAL_SPIN_UNLOCK(&qm_lock);
1059 if (!b_rc)
1060 return ECORE_INVAL;
1061
1062 /* clear the QM_PF runtime phase leftovers from previous init */
1063 ecore_init_clear_rt_data(p_hwfn);
1064
1065 /* prepare QM portion of runtime array */
782 ecore_qm_init_pf(p_hwfn);
1066 ecore_qm_init_pf(p_hwfn, p_ptt);
783
784 /* activate init tool on runtime array */
785 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
786 p_hwfn->hw_info.hw_mode);
787 if (rc != ECORE_SUCCESS)
788 return rc;
789
790 /* start PF's qm queues */

--- 25 unchanged lines hidden (view full) ---

816 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
817 sizeof(struct init_qm_vport_params) *
818 ecore_init_qm_get_num_vports(p_hwfn));
819 if (!qm_info->qm_vport_params)
820 goto alloc_err;
821
822 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
823 sizeof(struct init_qm_port_params) *
1067
1068 /* activate init tool on runtime array */
1069 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1070 p_hwfn->hw_info.hw_mode);
1071 if (rc != ECORE_SUCCESS)
1072 return rc;
1073
1074 /* start PF's qm queues */

--- 25 unchanged lines hidden (view full) ---

1100 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1101 sizeof(struct init_qm_vport_params) *
1102 ecore_init_qm_get_num_vports(p_hwfn));
1103 if (!qm_info->qm_vport_params)
1104 goto alloc_err;
1105
1106 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1107 sizeof(struct init_qm_port_params) *
824 p_hwfn->p_dev->num_ports_in_engines);
1108 p_hwfn->p_dev->num_ports_in_engine);
825 if (!qm_info->qm_port_params)
826 goto alloc_err;
827
828 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
829 sizeof(struct ecore_wfq_data) *
830 ecore_init_qm_get_num_vports(p_hwfn));
831 if (!qm_info->wfq_data)
832 goto alloc_err;

--- 4 unchanged lines hidden (view full) ---

837 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
838 ecore_qm_info_free(p_hwfn);
839 return ECORE_NOMEM;
840}
841/******************** End QM initialization ***************/
842
843enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
844{
1109 if (!qm_info->qm_port_params)
1110 goto alloc_err;
1111
1112 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1113 sizeof(struct ecore_wfq_data) *
1114 ecore_init_qm_get_num_vports(p_hwfn));
1115 if (!qm_info->wfq_data)
1116 goto alloc_err;

--- 4 unchanged lines hidden (view full) ---

1121 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1122 ecore_qm_info_free(p_hwfn);
1123 return ECORE_NOMEM;
1124}
1125/******************** End QM initialization ***************/
1126
1127enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1128{
845 enum _ecore_status_t rc = ECORE_SUCCESS;
846 u32 rdma_tasks, excess_tasks;
847 u32 line_count;
1129 u32 rdma_tasks, excess_tasks;
1130 u32 line_count;
1131 enum _ecore_status_t rc = ECORE_SUCCESS;
848 int i;
849
850 if (IS_VF(p_dev)) {
851 for_each_hwfn(p_dev, i) {
852 rc = ecore_l2_alloc(&p_dev->hwfns[i]);
853 if (rc != ECORE_SUCCESS)
854 return rc;
855 }

--- 173 unchanged lines hidden (view full) ---

1029
1030 /* DCBX initialization */
1031 rc = ecore_dcbx_info_alloc(p_hwfn);
1032 if (rc) {
1033 DP_NOTICE(p_hwfn, true,
1034 "Failed to allocate memory for dcbx structure\n");
1035 goto alloc_err;
1036 }
1132 int i;
1133
1134 if (IS_VF(p_dev)) {
1135 for_each_hwfn(p_dev, i) {
1136 rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1137 if (rc != ECORE_SUCCESS)
1138 return rc;
1139 }

--- 173 unchanged lines hidden (view full) ---

1313
1314 /* DCBX initialization */
1315 rc = ecore_dcbx_info_alloc(p_hwfn);
1316 if (rc) {
1317 DP_NOTICE(p_hwfn, true,
1318 "Failed to allocate memory for dcbx structure\n");
1319 goto alloc_err;
1320 }
1321
1322 /* initialize the doorbell recovery mechanism */
1323 ecore_db_recovery_setup(p_hwfn);
1037 }
1038
1039 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1040 sizeof(*p_dev->reset_stats));
1041 if (!p_dev->reset_stats) {
1042 DP_NOTICE(p_dev, true,
1043 "Failed to allocate reset statistics\n");
1044 goto alloc_no_mem;

--- 30 unchanged lines hidden (view full) ---

1075 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1076 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1077 p_hwfn->mcp_info->mfw_mb_cur,
1078 p_hwfn->mcp_info->mfw_mb_length);
1079
1080 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1081
1082 ecore_l2_setup(p_hwfn);
1324 }
1325
1326 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1327 sizeof(*p_dev->reset_stats));
1328 if (!p_dev->reset_stats) {
1329 DP_NOTICE(p_dev, true,
1330 "Failed to allocate reset statistics\n");
1331 goto alloc_no_mem;

--- 30 unchanged lines hidden (view full) ---

1362 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1363 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1364 p_hwfn->mcp_info->mfw_mb_cur,
1365 p_hwfn->mcp_info->mfw_mb_length);
1366
1367 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1368
1369 ecore_l2_setup(p_hwfn);
1083 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
1370 ecore_iov_setup(p_hwfn);
1084#ifdef CONFIG_ECORE_LL2
1085 if (p_hwfn->using_ll2)
1086 ecore_ll2_setup(p_hwfn);
1087#endif
1088#ifdef CONFIG_ECORE_FCOE
1089 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE)
1090 ecore_fcoe_setup(p_hwfn);
1091#endif

--- 66 unchanged lines hidden (view full) ---

1158static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1159{
1160 int hw_mode = 0;
1161
1162 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1163 hw_mode |= 1 << MODE_BB;
1164 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1165 hw_mode |= 1 << MODE_K2;
1371#ifdef CONFIG_ECORE_LL2
1372 if (p_hwfn->using_ll2)
1373 ecore_ll2_setup(p_hwfn);
1374#endif
1375#ifdef CONFIG_ECORE_FCOE
1376 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE)
1377 ecore_fcoe_setup(p_hwfn);
1378#endif

--- 66 unchanged lines hidden (view full) ---

1445static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1446{
1447 int hw_mode = 0;
1448
1449 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1450 hw_mode |= 1 << MODE_BB;
1451 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1452 hw_mode |= 1 << MODE_K2;
1453 } else if (ECORE_IS_E5(p_hwfn->p_dev)) {
1454 hw_mode |= 1 << MODE_E5;
1166 } else {
1167 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1168 p_hwfn->p_dev->type);
1169 return ECORE_INVAL;
1170 }
1171
1172 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE*/
1455 } else {
1456 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1457 p_hwfn->p_dev->type);
1458 return ECORE_INVAL;
1459 }
1460
1461 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE*/
1173 switch (p_hwfn->p_dev->num_ports_in_engines) {
1462 switch (p_hwfn->p_dev->num_ports_in_engine) {
1174 case 1:
1175 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1176 break;
1177 case 2:
1178 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1179 break;
1180 case 4:
1181 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1182 break;
1183 default:
1184 DP_NOTICE(p_hwfn, true, "num_ports_in_engine = %d not supported\n",
1463 case 1:
1464 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1465 break;
1466 case 2:
1467 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1468 break;
1469 case 4:
1470 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1471 break;
1472 default:
1473 DP_NOTICE(p_hwfn, true, "num_ports_in_engine = %d not supported\n",
1185 p_hwfn->p_dev->num_ports_in_engines);
1474 p_hwfn->p_dev->num_ports_in_engine);
1186 return ECORE_INVAL;
1187 }
1188
1189 switch (p_hwfn->p_dev->mf_mode) {
1190 case ECORE_MF_DEFAULT:
1191 case ECORE_MF_NPAR:
1192 hw_mode |= 1 << MODE_MF_SI;
1193 break;

--- 58 unchanged lines hidden (view full) ---

1252 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1253 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1254 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1255
1256 if (CHIP_REV_IS_EMUL(p_dev)) {
1257 if (ECORE_IS_AH(p_dev)) {
1258 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1259 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1475 return ECORE_INVAL;
1476 }
1477
1478 switch (p_hwfn->p_dev->mf_mode) {
1479 case ECORE_MF_DEFAULT:
1480 case ECORE_MF_NPAR:
1481 hw_mode |= 1 << MODE_MF_SI;
1482 break;

--- 58 unchanged lines hidden (view full) ---

1541 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1542 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1543 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1544
1545 if (CHIP_REV_IS_EMUL(p_dev)) {
1546 if (ECORE_IS_AH(p_dev)) {
1547 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1548 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1260 (p_dev->num_ports_in_engines >> 1));
1549 (p_dev->num_ports_in_engine >> 1));
1261
1262 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1550
1551 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1263 p_dev->num_ports_in_engines == 4 ? 0 : 3);
1552 p_dev->num_ports_in_engine == 4 ? 0 : 3);
1264 } else if (ECORE_IS_E5(p_dev)) {
1265 ECORE_E5_MISSING_CODE;
1266 }
1553 } else if (ECORE_IS_E5(p_dev)) {
1554 ECORE_E5_MISSING_CODE;
1555 }
1267 }
1268
1556
1269 /* Poll on RBC */
1270 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1271 for (i = 0; i < 100; i++) {
1272 OSAL_UDELAY(50);
1273 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1274 break;
1557 /* Poll on RBC */
1558 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1559 for (i = 0; i < 100; i++) {
1560 OSAL_UDELAY(50);
1561 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1562 break;
1563 }
1564 if (i == 100)
1565 DP_NOTICE(p_hwfn, true,
1566 "RBC done failed to complete in PSWRQ2\n");
1275 }
1567 }
1276 if (i == 100)
1277 DP_NOTICE(p_hwfn, true, "RBC done failed to complete in PSWRQ2\n");
1278
1279 return ECORE_SUCCESS;
1280}
1281#endif
1282
1283/* Init run time data for all PFs and their VFs on an engine.
1284 * TBD - for VFs - Once we have parent PF info for each VF in
1285 * shmem available as CAU requires knowledge of parent PF for each VF.

--- 72 unchanged lines hidden (view full) ---

1358 }
1359
1360 if (OSAL_CACHE_LINE_SIZE > wr_mbs)
1361 DP_INFO(p_hwfn,
1362 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1363 OSAL_CACHE_LINE_SIZE, wr_mbs);
1364
1365 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1568
1569 return ECORE_SUCCESS;
1570}
1571#endif
1572
1573/* Init run time data for all PFs and their VFs on an engine.
1574 * TBD - for VFs - Once we have parent PF info for each VF in
1575 * shmem available as CAU requires knowledge of parent PF for each VF.

--- 72 unchanged lines hidden (view full) ---

1648 }
1649
1650 if (OSAL_CACHE_LINE_SIZE > wr_mbs)
1651 DP_INFO(p_hwfn,
1652 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1653 OSAL_CACHE_LINE_SIZE, wr_mbs);
1654
1655 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1656 if (val > 0) {
1657 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1658 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1659 }
1366}
1367
1368static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1369 struct ecore_ptt *p_ptt,
1370 int hw_mode)
1371{
1372 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1373 struct ecore_dev *p_dev = p_hwfn->p_dev;
1374 u8 vf_id, max_num_vfs;
1375 u16 num_pfs, pf_id;
1376 u32 concrete_fid;
1377 enum _ecore_status_t rc = ECORE_SUCCESS;
1378
1379 ecore_init_cau_rt_data(p_dev);
1380
1381 /* Program GTT windows */
1660}
1661
1662static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1663 struct ecore_ptt *p_ptt,
1664 int hw_mode)
1665{
1666 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1667 struct ecore_dev *p_dev = p_hwfn->p_dev;
1668 u8 vf_id, max_num_vfs;
1669 u16 num_pfs, pf_id;
1670 u32 concrete_fid;
1671 enum _ecore_status_t rc = ECORE_SUCCESS;
1672
1673 ecore_init_cau_rt_data(p_dev);
1674
1675 /* Program GTT windows */
1382 ecore_gtt_init(p_hwfn);
1676 ecore_gtt_init(p_hwfn, p_ptt);
1383
1384#ifndef ASIC_ONLY
1385 if (CHIP_REV_IS_EMUL(p_dev)) {
1677
1678#ifndef ASIC_ONLY
1679 if (CHIP_REV_IS_EMUL(p_dev)) {
1386 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
1680 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1387 if (rc != ECORE_SUCCESS)
1388 return rc;
1389 }
1390#endif
1391
1392 if (p_hwfn->mcp_info) {
1393 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1394 qm_info->pf_rl_en = 1;
1395 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1396 qm_info->pf_wfq_en = 1;
1397 }
1398
1399 ecore_qm_common_rt_init(p_hwfn,
1681 if (rc != ECORE_SUCCESS)
1682 return rc;
1683 }
1684#endif
1685
1686 if (p_hwfn->mcp_info) {
1687 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1688 qm_info->pf_rl_en = 1;
1689 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1690 qm_info->pf_wfq_en = 1;
1691 }
1692
1693 ecore_qm_common_rt_init(p_hwfn,
1400 p_dev->num_ports_in_engines,
1694 p_dev->num_ports_in_engine,
1401 qm_info->max_phys_tcs_per_port,
1402 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1403 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1404 qm_info->qm_port_params);
1405
1406 ecore_cxt_hw_init_common(p_hwfn);
1407
1408 ecore_init_cache_line_size(p_hwfn, p_ptt);
1409
1410 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1411 if (rc != ECORE_SUCCESS)
1412 return rc;
1413
1695 qm_info->max_phys_tcs_per_port,
1696 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1697 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1698 qm_info->qm_port_params);
1699
1700 ecore_cxt_hw_init_common(p_hwfn);
1701
1702 ecore_init_cache_line_size(p_hwfn, p_ptt);
1703
1704 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1705 if (rc != ECORE_SUCCESS)
1706 return rc;
1707
1708 /* @@@TBD mask DORQ afull as it is now benign. Init tool should do this */
1709 ecore_wr(p_hwfn, p_ptt, DORQ_REG_INT_MASK,
1710 DORQ_REG_INT_STS_DORQ_FIFO_AFULL);
1711
1414 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1415 * need to decide with which value, maybe runtime
1416 */
1417 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1418 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1419
1420 if (ECORE_IS_BB(p_dev)) {
1421 /* Workaround clears ROCE search for all functions to prevent

--- 229 unchanged lines hidden (view full) ---

1651 *
1652 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1653 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1654 * containing 4 WIDs.
1655 */
1656 dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1657 dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1658 dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1712 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1713 * need to decide with which value, maybe runtime
1714 */
1715 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1716 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1717
1718 if (ECORE_IS_BB(p_dev)) {
1719 /* Workaround clears ROCE search for all functions to prevent

--- 229 unchanged lines hidden (view full) ---

1949 *
1950 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1951 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1952 * containing 4 WIDs.
1953 */
1954 dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1955 dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1956 dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1659 dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1957 dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) & ~(OSAL_PAGE_SIZE - 1);
1660 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1661
1662 dpi_count = pwm_region_size / dpi_page_size;
1663
1664 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1665 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1666
1667 /* Update hwfn */

--- 22 unchanged lines hidden (view full) ---

1690 u32 pwm_regsize, norm_regsize;
1691 u32 non_pwm_conn, min_addr_reg1;
1692 u32 db_bar_size, n_cpus = 1;
1693 u32 roce_edpm_mode;
1694 u32 pf_dems_shift;
1695 enum _ecore_status_t rc = ECORE_SUCCESS;
1696 u8 cond;
1697
1958 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1959
1960 dpi_count = pwm_region_size / dpi_page_size;
1961
1962 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1963 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1964
1965 /* Update hwfn */

--- 22 unchanged lines hidden (view full) ---

1988 u32 pwm_regsize, norm_regsize;
1989 u32 non_pwm_conn, min_addr_reg1;
1990 u32 db_bar_size, n_cpus = 1;
1991 u32 roce_edpm_mode;
1992 u32 pf_dems_shift;
1993 enum _ecore_status_t rc = ECORE_SUCCESS;
1994 u8 cond;
1995
1698 db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1996 db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1699 if (p_hwfn->p_dev->num_hwfns > 1)
1700 db_bar_size /= 2;
1701
1702 /* Calculate doorbell regions
1703 * -----------------------------------
1704 * The doorbell BAR is made of two regions. The first is called normal
1705 * region and the second is called PWM region. In the normal region
1706 * each ICID has its own set of addresses so that writing to that

--- 6 unchanged lines hidden (view full) ---

1713 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1714 * in units of 4,096 bytes.
1715 */
1716 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1717 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1718 OSAL_NULL) +
1719 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1720 OSAL_NULL);
1997 if (p_hwfn->p_dev->num_hwfns > 1)
1998 db_bar_size /= 2;
1999
2000 /* Calculate doorbell regions
2001 * -----------------------------------
2002 * The doorbell BAR is made of two regions. The first is called normal
2003 * region and the second is called PWM region. In the normal region
2004 * each ICID has its own set of addresses so that writing to that

--- 6 unchanged lines hidden (view full) ---

2011 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
2012 * in units of 4,096 bytes.
2013 */
2014 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
2015 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
2016 OSAL_NULL) +
2017 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2018 OSAL_NULL);
1721 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
2019 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, OSAL_PAGE_SIZE);
1722 min_addr_reg1 = norm_regsize / 4096;
1723 pwm_regsize = db_bar_size - norm_regsize;
1724
1725 /* Check that the normal and PWM sizes are valid */
1726 if (db_bar_size < norm_regsize) {
1727 DP_ERR(p_hwfn->p_dev, "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", db_bar_size, norm_regsize);
1728 return ECORE_NORESOURCES;
1729 }

--- 4 unchanged lines hidden (view full) ---

1734
1735 /* Calculate number of DPIs */
1736 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1737 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1738 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1739 /* Either EDPM is mandatory, or we are attempting to allocate a
1740 * WID per CPU.
1741 */
2020 min_addr_reg1 = norm_regsize / 4096;
2021 pwm_regsize = db_bar_size - norm_regsize;
2022
2023 /* Check that the normal and PWM sizes are valid */
2024 if (db_bar_size < norm_regsize) {
2025 DP_ERR(p_hwfn->p_dev, "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", db_bar_size, norm_regsize);
2026 return ECORE_NORESOURCES;
2027 }

--- 4 unchanged lines hidden (view full) ---

2032
2033 /* Calculate number of DPIs */
2034 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
2035 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
2036 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
2037 /* Either EDPM is mandatory, or we are attempting to allocate a
2038 * WID per CPU.
2039 */
1742 n_cpus = OSAL_NUM_ACTIVE_CPU();
2040 n_cpus = OSAL_NUM_CPUS();
1743 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1744 }
1745
1746 cond = ((rc != ECORE_SUCCESS) &&
1747 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1748 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1749 if (cond || p_hwfn->dcbx_no_edpm) {
1750 /* Either EDPM is disabled from user configuration, or it is

--- 16 unchanged lines hidden (view full) ---

1767
1768 DP_INFO(p_hwfn, "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1769 norm_regsize, pwm_regsize, p_hwfn->dpi_size, p_hwfn->dpi_count,
1770 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1771 "disabled" : "enabled");
1772
1773 /* Check return codes from above calls */
1774 if (rc != ECORE_SUCCESS) {
2041 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2042 }
2043
2044 cond = ((rc != ECORE_SUCCESS) &&
2045 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
2046 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
2047 if (cond || p_hwfn->dcbx_no_edpm) {
2048 /* Either EDPM is disabled from user configuration, or it is

--- 16 unchanged lines hidden (view full) ---

2065
2066 DP_INFO(p_hwfn, "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2067 norm_regsize, pwm_regsize, p_hwfn->dpi_size, p_hwfn->dpi_count,
2068 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
2069 "disabled" : "enabled");
2070
2071 /* Check return codes from above calls */
2072 if (rc != ECORE_SUCCESS) {
2073#ifndef LINUX_REMOVE
1775 DP_ERR(p_hwfn,
1776 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d. You can try reducing this down to %d via user configuration n_dpi or by disabling EDPM via user configuration roce_edpm\n",
1777 p_hwfn->dpi_count,
1778 p_hwfn->pf_params.rdma_pf_params.min_dpis,
1779 ECORE_MIN_DPIS);
2074 DP_ERR(p_hwfn,
2075 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d. You can try reducing this down to %d via user configuration n_dpi or by disabling EDPM via user configuration roce_edpm\n",
2076 p_hwfn->dpi_count,
2077 p_hwfn->pf_params.rdma_pf_params.min_dpis,
2078 ECORE_MIN_DPIS);
2079#else
2080 DP_ERR(p_hwfn,
2081 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d. You can try reducing this down to %d via the module parameter min_roce_dpis or by disabling EDPM via the module parameter roce_edpm\n",
2082 p_hwfn->dpi_count,
2083 p_hwfn->pf_params.rdma_pf_params.min_dpis,
2084 ECORE_MIN_DPIS);
2085#endif
1780 return ECORE_NORESOURCES;
1781 }
1782
1783 /* Update hwfn */
1784 p_hwfn->dpi_start_offset = norm_regsize; /* this is later used to
1785 * calculate the doorbell
1786 * address
1787 */

--- 12 unchanged lines hidden (view full) ---

1800 int hw_mode)
1801{
1802 enum _ecore_status_t rc = ECORE_SUCCESS;
1803
1804 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1805 hw_mode);
1806 if (rc != ECORE_SUCCESS)
1807 return rc;
2086 return ECORE_NORESOURCES;
2087 }
2088
2089 /* Update hwfn */
2090 p_hwfn->dpi_start_offset = norm_regsize; /* this is later used to
2091 * calculate the doorbell
2092 * address
2093 */

--- 12 unchanged lines hidden (view full) ---

2106 int hw_mode)
2107{
2108 enum _ecore_status_t rc = ECORE_SUCCESS;
2109
2110 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2111 hw_mode);
2112 if (rc != ECORE_SUCCESS)
2113 return rc;
2114
2115 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2116
1808#if 0
1809 /* FW 8.10.5.0 requires us to configure PF_VECTOR and DUALMODE in LLH.
1810 * This would hopefully be moved to MFW.
1811 */
1812 if (IS_MF_DEFAULT(p_hwfn) || IS_MF_SI(p_hwfn)) {
1813 u8 pf_id = 0;
1814
1815 if (ecore_hw_init_first_eth(p_hwfn, p_ptt, &pf_id) ==
1816 ECORE_SUCCESS) {
1817 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
1818 "PF[%08x] is first eth on engine\n",
1819 pf_id);
1820
1821 /* We should have configured BIT for ppfid, i.e., the
1822 * relative function number in the port. But there's a
1823 * bug in LLH in BB where the ppfid is actually engine
1824 * based, so we need to take this into account.
1825 */
1826 if (!ECORE_IS_BB(p_hwfn->p_dev))
2117#if 0
2118 /* FW 8.10.5.0 requires us to configure PF_VECTOR and DUALMODE in LLH.
2119 * This would hopefully be moved to MFW.
2120 */
2121 if (IS_MF_DEFAULT(p_hwfn) || IS_MF_SI(p_hwfn)) {
2122 u8 pf_id = 0;
2123
2124 if (ecore_hw_init_first_eth(p_hwfn, p_ptt, &pf_id) ==
2125 ECORE_SUCCESS) {
2126 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2127 "PF[%08x] is first eth on engine\n",
2128 pf_id);
2129
2130 /* We should have configured BIT for ppfid, i.e., the
2131 * relative function number in the port. But there's a
2132 * bug in LLH in BB where the ppfid is actually engine
2133 * based, so we need to take this into account.
2134 */
2135 if (!ECORE_IS_BB(p_hwfn->p_dev))
1827 pf_id /= p_hwfn->p_dev->num_ports_in_engines;
2136 pf_id /= p_hwfn->p_dev->num_ports_in_engine;
1828
1829 ecore_wr(p_hwfn, p_ptt,
1830 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 1 << pf_id);
1831 }
1832
1833 /* Take the protocol-based hit vector if there is a hit,
1834 * otherwise take the other vector.
1835 */

--- 59 unchanged lines hidden (view full) ---

1895
1896 p_info = &p_hwfn->mcp_info->func_info;
1897 if (p_info->bandwidth_min)
1898 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1899
1900 /* Update rate limit once we'll actually have a link */
1901 p_hwfn->qm_info.pf_rl = 100000;
1902 }
2137
2138 ecore_wr(p_hwfn, p_ptt,
2139 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 1 << pf_id);
2140 }
2141
2142 /* Take the protocol-based hit vector if there is a hit,
2143 * otherwise take the other vector.
2144 */

--- 59 unchanged lines hidden (view full) ---

2204
2205 p_info = &p_hwfn->mcp_info->func_info;
2206 if (p_info->bandwidth_min)
2207 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2208
2209 /* Update rate limit once we'll actually have a link */
2210 p_hwfn->qm_info.pf_rl = 100000;
2211 }
1903 ecore_cxt_hw_init_pf(p_hwfn);
2212 ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
1904
1905 ecore_int_igu_init_rt(p_hwfn);
1906
1907 /* Set VLAN in NIG if needed */
1908 if (hw_mode & (1 << MODE_MF_SD)) {
1909 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1910 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1911 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,

--- 69 unchanged lines hidden (view full) ---

1981 "PF[%d] is first ETH on engine\n",
1982 pf_id);
1983 val = 1;
1984 }
1985 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, val);
1986 }
1987 }
1988#endif
2213
2214 ecore_int_igu_init_rt(p_hwfn);
2215
2216 /* Set VLAN in NIG if needed */
2217 if (hw_mode & (1 << MODE_MF_SD)) {
2218 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2219 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2220 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,

--- 69 unchanged lines hidden (view full) ---

2290 "PF[%d] is first ETH on engine\n",
2291 pf_id);
2292 val = 1;
2293 }
2294 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, val);
2295 }
2296 }
2297#endif
1989 /* Add an LLH filter with the primary MAC address. */
2298 /* No default PF is configured in 100G NPAR mode, so need add an LLH
2299 * filter with the primary MAC address.
2300 */
1990 if (p_hwfn->p_dev->num_hwfns > 1 && IS_LEAD_HWFN(p_hwfn)) {
1991 rc = ecore_llh_add_mac_filter(p_hwfn, p_ptt,
1992 p_hwfn->hw_info.hw_mac_addr);
1993 if (rc != ECORE_SUCCESS)
1994 DP_NOTICE(p_hwfn, false,
2301 if (p_hwfn->p_dev->num_hwfns > 1 && IS_LEAD_HWFN(p_hwfn)) {
2302 rc = ecore_llh_add_mac_filter(p_hwfn, p_ptt,
2303 p_hwfn->hw_info.hw_mac_addr);
2304 if (rc != ECORE_SUCCESS)
2305 DP_NOTICE(p_hwfn, false,
1995 "Failed to add an LLH filter with the primary MAC\n");
2306 "Failed to add an LLH filter with the primary MAC in 100 NPAR mode\n");
1996 }
1997
1998 if (b_hw_start) {
1999 /* enable interrupts */
2000 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2001 if (rc != ECORE_SUCCESS)
2002 return rc;
2003
2004 /* send function start command */
2307 }
2308
2309 if (b_hw_start) {
2310 /* enable interrupts */
2311 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2312 if (rc != ECORE_SUCCESS)
2313 return rc;
2314
2315 /* send function start command */
2005 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
2316 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2317 p_hwfn->p_dev->mf_mode,
2006 allow_npar_tx_switch);
2007 if (rc) {
2008 DP_NOTICE(p_hwfn, true, "Function start ramrod failed\n");
2009 } else {
2010 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2011 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2012 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2013

--- 83 unchanged lines hidden (view full) ---

2097
2098 return ECORE_SUCCESS;
2099}
2100
2101static void
2102ecore_fill_load_req_params(struct ecore_load_req_params *p_load_req,
2103 struct ecore_drv_load_params *p_drv_load)
2104{
2318 allow_npar_tx_switch);
2319 if (rc) {
2320 DP_NOTICE(p_hwfn, true, "Function start ramrod failed\n");
2321 } else {
2322 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2323 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2324 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2325

--- 83 unchanged lines hidden (view full) ---

2409
2410 return ECORE_SUCCESS;
2411}
2412
2413static void
2414ecore_fill_load_req_params(struct ecore_load_req_params *p_load_req,
2415 struct ecore_drv_load_params *p_drv_load)
2416{
2417 /* Make sure that if ecore-client didn't provide inputs, all the
2418 * expected defaults are indeed zero.
2419 */
2420 OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2421 OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2422 OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2423
2105 OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2106
2107 if (p_drv_load != OSAL_NULL) {
2108 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2109 ECORE_DRV_ROLE_KDUMP :
2110 ECORE_DRV_ROLE_OS;
2111 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2112 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2113 p_load_req->override_force_load =
2114 p_drv_load->override_force_load;
2424 OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2425
2426 if (p_drv_load != OSAL_NULL) {
2427 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2428 ECORE_DRV_ROLE_KDUMP :
2429 ECORE_DRV_ROLE_OS;
2430 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2431 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2432 p_load_req->override_force_load =
2433 p_drv_load->override_force_load;
2115 } else {
2116 p_load_req->drv_role = ECORE_DRV_ROLE_OS;
2117 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
2118 p_load_req->avoid_eng_reset = false;
2119 p_load_req->override_force_load =
2120 ECORE_OVERRIDE_FORCE_LOAD_NONE;
2121 }
2122}
2123
2124enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2125 struct ecore_hw_init_params *p_params)
2126{
2127 struct ecore_load_req_params load_req_params;
2128 u32 load_code, param, drv_mb_param;

--- 134 unchanged lines hidden (view full) ---

2263 DP_NOTICE(p_hwfn, false,
2264 "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
2265
2266 /* send DCBX attention request command */
2267 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2268 "sending phony dcbx set command to trigger DCBx attention handling\n");
2269 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2270 DRV_MSG_CODE_SET_DCBX,
2434 }
2435}
2436
2437enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2438 struct ecore_hw_init_params *p_params)
2439{
2440 struct ecore_load_req_params load_req_params;
2441 u32 load_code, param, drv_mb_param;

--- 134 unchanged lines hidden (view full) ---

2576 DP_NOTICE(p_hwfn, false,
2577 "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
2578
2579 /* send DCBX attention request command */
2580 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2581 "sending phony dcbx set command to trigger DCBx attention handling\n");
2582 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2583 DRV_MSG_CODE_SET_DCBX,
2271 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
2584 1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET,
2272 &load_code, &param);
2273 if (mfw_rc != ECORE_SUCCESS) {
2274 DP_NOTICE(p_hwfn, true,
2275 "Failed to send DCBX attention request\n");
2276 return mfw_rc;
2277 }
2278
2279 p_hwfn->hw_init_done = true;

--- 198 unchanged lines hidden (view full) ---

2478 if (rc != ECORE_SUCCESS) {
2479 DP_NOTICE(p_hwfn, true,
2480 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2481 rc);
2482 rc2 = ECORE_UNKNOWN_ERROR;
2483 }
2484 }
2485
2585 &load_code, &param);
2586 if (mfw_rc != ECORE_SUCCESS) {
2587 DP_NOTICE(p_hwfn, true,
2588 "Failed to send DCBX attention request\n");
2589 return mfw_rc;
2590 }
2591
2592 p_hwfn->hw_init_done = true;

--- 198 unchanged lines hidden (view full) ---

2791 if (rc != ECORE_SUCCESS) {
2792 DP_NOTICE(p_hwfn, true,
2793 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2794 rc);
2795 rc2 = ECORE_UNKNOWN_ERROR;
2796 }
2797 }
2798
2486 /* remove the LLH filter with the primary MAC addres */
2799 /* 100g NPAR mode - remove the LLH filter with the primary MAC
2800 * address.
2801 */
2487 if (p_hwfn->p_dev->num_hwfns > 1 && IS_LEAD_HWFN(p_hwfn))
2488 ecore_llh_remove_mac_filter(p_hwfn, p_ptt,
2802 if (p_hwfn->p_dev->num_hwfns > 1 && IS_LEAD_HWFN(p_hwfn))
2803 ecore_llh_remove_mac_filter(p_hwfn, p_ptt,
2489 p_hwfn->hw_info.hw_mac_addr);
2804 p_hwfn->hw_info.hw_mac_addr);
2490 } /* hwfn loop */
2491
2492 if (IS_PF(p_dev)) {
2493 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2494 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2495
2496 /* Disable DMAE in PXP - in CMT, this should only be done for
2497 * first hw-function, and only after all transactions have

--- 6 unchanged lines hidden (view full) ---

2504 rc);
2505 rc2 = ECORE_UNKNOWN_ERROR;
2506 }
2507 }
2508
2509 return rc2;
2510}
2511
2805 } /* hwfn loop */
2806
2807 if (IS_PF(p_dev)) {
2808 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2809 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2810
2811 /* Disable DMAE in PXP - in CMT, this should only be done for
2812 * first hw-function, and only after all transactions have

--- 6 unchanged lines hidden (view full) ---

2819 rc);
2820 rc2 = ECORE_UNKNOWN_ERROR;
2821 }
2822 }
2823
2824 return rc2;
2825}
2826
2512void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2827enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2513{
2514 int j;
2515
2516 for_each_hwfn(p_dev, j) {
2517 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2828{
2829 int j;
2830
2831 for_each_hwfn(p_dev, j) {
2832 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2518 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2833 struct ecore_ptt *p_ptt;
2519
2520 if (IS_VF(p_dev)) {
2521 ecore_vf_pf_int_cleanup(p_hwfn);
2522 continue;
2523 }
2834
2835 if (IS_VF(p_dev)) {
2836 ecore_vf_pf_int_cleanup(p_hwfn);
2837 continue;
2838 }
2839 p_ptt = ecore_ptt_acquire(p_hwfn);
2840 if (!p_ptt)
2841 return ECORE_AGAIN;
2524
2525 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Shutting down the fastpath\n");
2526
2527 ecore_wr(p_hwfn, p_ptt,
2528 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2529
2530 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2531 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);

--- 4 unchanged lines hidden (view full) ---

2536 /* @@@TBD - clean transmission queues (5.b) */
2537 /* @@@TBD - clean BTB (5.c) */
2538
2539 /* @@@TBD - verify DMAE requests are done (8) */
2540
2541 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2542 /* Need to wait 1ms to guarantee SBs are cleared */
2543 OSAL_MSLEEP(1);
2842
2843 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Shutting down the fastpath\n");
2844
2845 ecore_wr(p_hwfn, p_ptt,
2846 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2847
2848 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2849 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);

--- 4 unchanged lines hidden (view full) ---

2854 /* @@@TBD - clean transmission queues (5.b) */
2855 /* @@@TBD - clean BTB (5.c) */
2856
2857 /* @@@TBD - verify DMAE requests are done (8) */
2858
2859 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2860 /* Need to wait 1ms to guarantee SBs are cleared */
2861 OSAL_MSLEEP(1);
2862 ecore_ptt_release(p_hwfn, p_ptt);
2544 }
2863 }
2864
2865 return ECORE_SUCCESS;
2545}
2546
2866}
2867
2547void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2868enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2548{
2869{
2549 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2870 struct ecore_ptt *p_ptt;
2550
2551 if (IS_VF(p_hwfn->p_dev))
2871
2872 if (IS_VF(p_hwfn->p_dev))
2552 return;
2873 return ECORE_SUCCESS;
2553
2874
2875 p_ptt = ecore_ptt_acquire(p_hwfn);
2876 if (!p_ptt)
2877 return ECORE_AGAIN;
2878
2554 /* If roce info is allocated it means roce is initialized and should
2555 * be enabled in searcher.
2556 */
2557 if (p_hwfn->p_rdma_info) {
2558 if (p_hwfn->b_rdma_enabled_in_prs)
2559 ecore_wr(p_hwfn, p_ptt,
2560 p_hwfn->rdma_prs_search_reg, 0x1);
2561 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2562 }
2563
2564 /* Re-open incoming traffic */
2879 /* If roce info is allocated it means roce is initialized and should
2880 * be enabled in searcher.
2881 */
2882 if (p_hwfn->p_rdma_info) {
2883 if (p_hwfn->b_rdma_enabled_in_prs)
2884 ecore_wr(p_hwfn, p_ptt,
2885 p_hwfn->rdma_prs_search_reg, 0x1);
2886 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2887 }
2888
2889 /* Re-open incoming traffic */
2565 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2890 ecore_wr(p_hwfn, p_ptt,
2566 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2891 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2892 ecore_ptt_release(p_hwfn, p_ptt);
2893
2894 return ECORE_SUCCESS;
2567}
2568/* TEMP macro to be removed when wol code revisted */
2569#define ECORE_WOL_WR(_p_hwfn, _p_ptt, _offset, _val) ECORE_IS_BB(_p_hwfn->p_dev) ? \
2570 ecore_wr(_p_hwfn, _p_ptt, _offset, _val) : \
2571 ecore_mcp_wol_wr(_p_hwfn, _p_ptt, _offset, _val);
2572
2895}
2896/* TEMP macro to be removed when wol code revisted */
2897#define ECORE_WOL_WR(_p_hwfn, _p_ptt, _offset, _val) ECORE_IS_BB(_p_hwfn->p_dev) ? \
2898 ecore_wr(_p_hwfn, _p_ptt, _offset, _val) : \
2899 ecore_mcp_wol_wr(_p_hwfn, _p_ptt, _offset, _val);
2900
2573enum _ecore_status_t ecore_set_nwuf_reg(struct ecore_dev *p_dev,
2574 const bool b_enable,
2575 u32 reg_idx,
2576 u32 pattern_size,
2577 u32 crc)
2901enum _ecore_status_t ecore_set_nwuf_reg(struct ecore_dev *p_dev, u32 reg_idx,
2902 u32 pattern_size, u32 crc)
2578{
2579 struct ecore_hwfn *hwfn = &p_dev->hwfns[0];
2903{
2904 struct ecore_hwfn *hwfn = &p_dev->hwfns[0];
2905 enum _ecore_status_t rc = ECORE_SUCCESS;
2906 struct ecore_ptt *p_ptt;
2580 u32 reg_len = 0;
2581 u32 reg_crc = 0;
2582
2907 u32 reg_len = 0;
2908 u32 reg_crc = 0;
2909
2910 p_ptt = ecore_ptt_acquire(hwfn);
2911 if (!p_ptt)
2912 return ECORE_AGAIN;
2913
2583 /* Get length and CRC register offsets */
2584 switch (reg_idx)
2585 {
2586 case 0:
2587 reg_len = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_0_LEN_BB :
2588 WOL_REG_ACPI_PAT_0_LEN_K2_E5;
2589 reg_crc = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_0_CRC_BB :
2590 WOL_REG_ACPI_PAT_0_CRC_K2_E5;

--- 36 unchanged lines hidden (view full) ---

2627 break;
2628 case 7:
2629 reg_len = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_7_LEN_BB :
2630 WOL_REG_ACPI_PAT_7_LEN_K2_E5;
2631 reg_crc = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_7_CRC_BB :
2632 WOL_REG_ACPI_PAT_7_CRC_K2_E5;
2633 break;
2634 default:
2914 /* Get length and CRC register offsets */
2915 switch (reg_idx)
2916 {
2917 case 0:
2918 reg_len = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_0_LEN_BB :
2919 WOL_REG_ACPI_PAT_0_LEN_K2_E5;
2920 reg_crc = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_0_CRC_BB :
2921 WOL_REG_ACPI_PAT_0_CRC_K2_E5;

--- 36 unchanged lines hidden (view full) ---

2958 break;
2959 case 7:
2960 reg_len = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_7_LEN_BB :
2961 WOL_REG_ACPI_PAT_7_LEN_K2_E5;
2962 reg_crc = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_7_CRC_BB :
2963 WOL_REG_ACPI_PAT_7_CRC_K2_E5;
2964 break;
2965 default:
2635 return ECORE_UNKNOWN_ERROR;
2966 rc = ECORE_UNKNOWN_ERROR;
2967 goto out;
2636 }
2637
2638 /* Allign pattern size to 4 */
2639 while (pattern_size % 4)
2640 {
2641 pattern_size++;
2642 }
2643 /* write pattern length */
2968 }
2969
2970 /* Allign pattern size to 4 */
2971 while (pattern_size % 4)
2972 {
2973 pattern_size++;
2974 }
2975 /* write pattern length */
2644 ECORE_WOL_WR(hwfn, hwfn->p_main_ptt, reg_len, pattern_size);
2976 ECORE_WOL_WR(hwfn, p_ptt, reg_len, pattern_size);
2645
2646 /* write crc value*/
2977
2978 /* write crc value*/
2647 ECORE_WOL_WR(hwfn, hwfn->p_main_ptt, reg_crc, crc);
2979 ECORE_WOL_WR(hwfn, p_ptt, reg_crc, crc);
2648
2649 DP_INFO(p_dev,
2650 "ecore_set_nwuf_reg: idx[%d] reg_crc[0x%x=0x%08x] "
2651 "reg_len[0x%x=0x%x]\n",
2652 reg_idx, reg_crc, crc, reg_len, pattern_size);
2980
2981 DP_INFO(p_dev,
2982 "ecore_set_nwuf_reg: idx[%d] reg_crc[0x%x=0x%08x] "
2983 "reg_len[0x%x=0x%x]\n",
2984 reg_idx, reg_crc, crc, reg_len, pattern_size);
2985out:
2986 ecore_ptt_release(hwfn, p_ptt);
2653
2987
2654 return ECORE_SUCCESS;
2988 return rc;
2655}
2656
2989}
2990
2657void ecore_wol_buffer_clear(struct ecore_dev *p_dev)
2991void ecore_wol_buffer_clear(struct ecore_hwfn *p_hwfn,
2992 struct ecore_ptt *p_ptt)
2658{
2993{
2659 struct ecore_hwfn *hwfn = &p_dev->hwfns[0];
2660 const u32 wake_buffer_clear_offset =
2994 const u32 wake_buffer_clear_offset =
2661 ECORE_IS_BB(p_dev) ?
2995 ECORE_IS_BB(p_hwfn->p_dev) ?
2662 NIG_REG_WAKE_BUFFER_CLEAR_BB : WOL_REG_WAKE_BUFFER_CLEAR_K2_E5;
2663
2996 NIG_REG_WAKE_BUFFER_CLEAR_BB : WOL_REG_WAKE_BUFFER_CLEAR_K2_E5;
2997
2664 DP_INFO(p_dev,
2998 DP_INFO(p_hwfn->p_dev,
2665 "ecore_wol_buffer_clear: reset "
2666 "REG_WAKE_BUFFER_CLEAR offset=0x%08x\n",
2667 wake_buffer_clear_offset);
2668
2999 "ecore_wol_buffer_clear: reset "
3000 "REG_WAKE_BUFFER_CLEAR offset=0x%08x\n",
3001 wake_buffer_clear_offset);
3002
2669 ECORE_WOL_WR(hwfn, hwfn->p_main_ptt, wake_buffer_clear_offset, 1);
2670 ECORE_WOL_WR(hwfn, hwfn->p_main_ptt, wake_buffer_clear_offset, 0);
3003 ECORE_WOL_WR(p_hwfn, p_ptt, wake_buffer_clear_offset, 1);
3004 ECORE_WOL_WR(p_hwfn, p_ptt, wake_buffer_clear_offset, 0);
2671}
2672
3005}
3006
2673enum _ecore_status_t ecore_get_wake_info(struct ecore_dev *p_dev,
2674 struct ecore_wake_info *wake_info)
3007enum _ecore_status_t ecore_get_wake_info(struct ecore_hwfn *p_hwfn,
3008 struct ecore_ptt *p_ptt,
3009 struct ecore_wake_info *wake_info)
2675{
3010{
2676 struct ecore_hwfn *hwfn = &p_dev->hwfns[0];
3011 struct ecore_dev *p_dev = p_hwfn->p_dev;
2677 u32 *buf = OSAL_NULL;
2678 u32 i = 0;
2679 const u32 reg_wake_buffer_offest =
2680 ECORE_IS_BB(p_dev) ? NIG_REG_WAKE_BUFFER_BB :
2681 WOL_REG_WAKE_BUFFER_K2_E5;
2682
3012 u32 *buf = OSAL_NULL;
3013 u32 i = 0;
3014 const u32 reg_wake_buffer_offest =
3015 ECORE_IS_BB(p_dev) ? NIG_REG_WAKE_BUFFER_BB :
3016 WOL_REG_WAKE_BUFFER_K2_E5;
3017
2683 wake_info->wk_info = ecore_rd(hwfn, hwfn->p_main_ptt,
3018 wake_info->wk_info = ecore_rd(p_hwfn, p_ptt,
2684 ECORE_IS_BB(p_dev) ? NIG_REG_WAKE_INFO_BB :
2685 WOL_REG_WAKE_INFO_K2_E5);
3019 ECORE_IS_BB(p_dev) ? NIG_REG_WAKE_INFO_BB :
3020 WOL_REG_WAKE_INFO_K2_E5);
2686 wake_info->wk_details = ecore_rd(hwfn, hwfn->p_main_ptt,
3021 wake_info->wk_details = ecore_rd(p_hwfn, p_ptt,
2687 ECORE_IS_BB(p_dev) ? NIG_REG_WAKE_DETAILS_BB :
2688 WOL_REG_WAKE_DETAILS_K2_E5);
3022 ECORE_IS_BB(p_dev) ? NIG_REG_WAKE_DETAILS_BB :
3023 WOL_REG_WAKE_DETAILS_K2_E5);
2689 wake_info->wk_pkt_len = ecore_rd(hwfn, hwfn->p_main_ptt,
3024 wake_info->wk_pkt_len = ecore_rd(p_hwfn, p_ptt,
2690 ECORE_IS_BB(p_dev) ? NIG_REG_WAKE_PKT_LEN_BB :
2691 WOL_REG_WAKE_PKT_LEN_K2_E5);
2692
2693 DP_INFO(p_dev,
2694 "ecore_get_wake_info: REG_WAKE_INFO=0x%08x "
2695 "REG_WAKE_DETAILS=0x%08x "
2696 "REG_WAKE_PKT_LEN=0x%08x\n",
2697 wake_info->wk_info,

--- 6 unchanged lines hidden (view full) ---

2704 {
2705 if ((i*sizeof(u32)) >= sizeof(wake_info->wk_buffer))
2706 {
2707 DP_INFO(p_dev,
2708 "ecore_get_wake_info: i index to 0 high=%d\n",
2709 i);
2710 break;
2711 }
3025 ECORE_IS_BB(p_dev) ? NIG_REG_WAKE_PKT_LEN_BB :
3026 WOL_REG_WAKE_PKT_LEN_K2_E5);
3027
3028 DP_INFO(p_dev,
3029 "ecore_get_wake_info: REG_WAKE_INFO=0x%08x "
3030 "REG_WAKE_DETAILS=0x%08x "
3031 "REG_WAKE_PKT_LEN=0x%08x\n",
3032 wake_info->wk_info,

--- 6 unchanged lines hidden (view full) ---

3039 {
3040 if ((i*sizeof(u32)) >= sizeof(wake_info->wk_buffer))
3041 {
3042 DP_INFO(p_dev,
3043 "ecore_get_wake_info: i index to 0 high=%d\n",
3044 i);
3045 break;
3046 }
2712 buf[i] = ecore_rd(hwfn, hwfn->p_main_ptt,
3047 buf[i] = ecore_rd(p_hwfn, p_ptt,
2713 reg_wake_buffer_offest + (i * sizeof(u32)));
2714 DP_INFO(p_dev, "ecore_get_wake_info: wk_buffer[%u]: 0x%08x\n",
2715 i, buf[i]);
2716 }
2717
3048 reg_wake_buffer_offest + (i * sizeof(u32)));
3049 DP_INFO(p_dev, "ecore_get_wake_info: wk_buffer[%u]: 0x%08x\n",
3050 i, buf[i]);
3051 }
3052
2718 ecore_wol_buffer_clear(p_dev);
3053 ecore_wol_buffer_clear(p_hwfn, p_ptt);
2719
2720 return ECORE_SUCCESS;
2721}
2722
2723/* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2724static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2725{
2726 ecore_ptt_pool_free(p_hwfn);

--- 159 unchanged lines hidden (view full) ---

2886 return "SB";
2887 default:
2888 return "UNKNOWN_RESOURCE";
2889 }
2890}
2891
2892static enum _ecore_status_t
2893__ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
3054
3055 return ECORE_SUCCESS;
3056}
3057
3058/* Free hwfn memory and resources acquired in hw_hwfn_prepare */
3059static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
3060{
3061 ecore_ptt_pool_free(p_hwfn);

--- 159 unchanged lines hidden (view full) ---

3221 return "SB";
3222 default:
3223 return "UNKNOWN_RESOURCE";
3224 }
3225}
3226
3227static enum _ecore_status_t
3228__ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2894 enum ecore_resources res_id, u32 resc_max_val,
3229 struct ecore_ptt *p_ptt,
3230 enum ecore_resources res_id,
3231 u32 resc_max_val,
2895 u32 *p_mcp_resp)
2896{
2897 enum _ecore_status_t rc;
2898
3232 u32 *p_mcp_resp)
3233{
3234 enum _ecore_status_t rc;
3235
2899 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_hwfn->p_main_ptt, res_id,
3236 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2900 resc_max_val, p_mcp_resp);
2901 if (rc != ECORE_SUCCESS) {
2902 DP_NOTICE(p_hwfn, true,
2903 "MFW response failure for a max value setting of resource %d [%s]\n",
2904 res_id, ecore_hw_get_resc_name(res_id));
2905 return rc;
2906 }
2907
2908 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2909 DP_INFO(p_hwfn,
2910 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2911 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2912
2913 return ECORE_SUCCESS;
2914}
2915
2916static enum _ecore_status_t
3237 resc_max_val, p_mcp_resp);
3238 if (rc != ECORE_SUCCESS) {
3239 DP_NOTICE(p_hwfn, true,
3240 "MFW response failure for a max value setting of resource %d [%s]\n",
3241 res_id, ecore_hw_get_resc_name(res_id));
3242 return rc;
3243 }
3244
3245 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
3246 DP_INFO(p_hwfn,
3247 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
3248 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
3249
3250 return ECORE_SUCCESS;
3251}
3252
3253static enum _ecore_status_t
2917ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn)
3254ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
3255 struct ecore_ptt *p_ptt)
2918{
2919 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2920 u32 resc_max_val, mcp_resp;
2921 u8 res_id;
2922 enum _ecore_status_t rc;
2923
2924 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2925 switch (res_id) {
2926 case ECORE_LL2_QUEUE:
2927 resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2928 break;
2929 case ECORE_RDMA_CNQ_RAM:
2930 /* No need for a case for ECORE_CMDQS_CQS since
2931 * CNQ/CMDQS are the same resource.
2932 */
3256{
3257 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3258 u32 resc_max_val, mcp_resp;
3259 u8 res_id;
3260 enum _ecore_status_t rc;
3261
3262 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3263 switch (res_id) {
3264 case ECORE_LL2_QUEUE:
3265 resc_max_val = MAX_NUM_LL2_RX_QUEUES;
3266 break;
3267 case ECORE_RDMA_CNQ_RAM:
3268 /* No need for a case for ECORE_CMDQS_CQS since
3269 * CNQ/CMDQS are the same resource.
3270 */
2933 resc_max_val = NUM_OF_GLOBAL_QUEUES;
3271 resc_max_val = NUM_OF_CMDQS_CQS;
2934 break;
2935 case ECORE_RDMA_STATS_QUEUE:
2936 resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2937 : RDMA_NUM_STATISTIC_COUNTERS_BB;
2938 break;
2939 case ECORE_BDQ:
2940 resc_max_val = BDQ_NUM_RESOURCES;
2941 break;
2942 default:
2943 continue;
2944 }
2945
3272 break;
3273 case ECORE_RDMA_STATS_QUEUE:
3274 resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
3275 : RDMA_NUM_STATISTIC_COUNTERS_BB;
3276 break;
3277 case ECORE_BDQ:
3278 resc_max_val = BDQ_NUM_RESOURCES;
3279 break;
3280 default:
3281 continue;
3282 }
3283
2946 rc = __ecore_hw_set_soft_resc_size(p_hwfn, res_id,
3284 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2947 resc_max_val, &mcp_resp);
2948 if (rc != ECORE_SUCCESS)
2949 return rc;
2950
2951 /* There's no point to continue to the next resource if the
2952 * command is not supported by the MFW.
2953 * We do continue if the command is supported but the resource
2954 * is unknown to the MFW. Such a resource will be later

--- 45 unchanged lines hidden (view full) ---

3000 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3001 break;
3002 case ECORE_LL2_QUEUE:
3003 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3004 break;
3005 case ECORE_RDMA_CNQ_RAM:
3006 case ECORE_CMDQS_CQS:
3007 /* CNQ/CMDQS are the same resource */
3285 resc_max_val, &mcp_resp);
3286 if (rc != ECORE_SUCCESS)
3287 return rc;
3288
3289 /* There's no point to continue to the next resource if the
3290 * command is not supported by the MFW.
3291 * We do continue if the command is supported but the resource
3292 * is unknown to the MFW. Such a resource will be later

--- 45 unchanged lines hidden (view full) ---

3338 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3339 break;
3340 case ECORE_LL2_QUEUE:
3341 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3342 break;
3343 case ECORE_RDMA_CNQ_RAM:
3344 case ECORE_CMDQS_CQS:
3345 /* CNQ/CMDQS are the same resource */
3008 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
3346 *p_resc_num = NUM_OF_CMDQS_CQS / num_funcs;
3009 break;
3010 case ECORE_RDMA_STATS_QUEUE:
3011 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
3012 RDMA_NUM_STATISTIC_COUNTERS_BB) /
3013 num_funcs;
3014 break;
3015 case ECORE_BDQ:
3016 if (p_hwfn->hw_info.personality != ECORE_PCI_ISCSI &&

--- 11 unchanged lines hidden (view full) ---

3028 default:
3029 return ECORE_INVAL;
3030 }
3031
3032 switch (res_id) {
3033 case ECORE_BDQ:
3034 if (!*p_resc_num)
3035 *p_resc_start = 0;
3347 break;
3348 case ECORE_RDMA_STATS_QUEUE:
3349 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
3350 RDMA_NUM_STATISTIC_COUNTERS_BB) /
3351 num_funcs;
3352 break;
3353 case ECORE_BDQ:
3354 if (p_hwfn->hw_info.personality != ECORE_PCI_ISCSI &&

--- 11 unchanged lines hidden (view full) ---

3366 default:
3367 return ECORE_INVAL;
3368 }
3369
3370 switch (res_id) {
3371 case ECORE_BDQ:
3372 if (!*p_resc_num)
3373 *p_resc_start = 0;
3036 else if (p_hwfn->p_dev->num_ports_in_engines == 4)
3374 else if (p_hwfn->p_dev->num_ports_in_engine == 4)
3037 *p_resc_start = p_hwfn->port_id;
3038 else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI)
3039 *p_resc_start = p_hwfn->port_id;
3040 else if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE)
3041 *p_resc_start = p_hwfn->port_id + 2;
3042 break;
3043 default:
3044 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;

--- 95 unchanged lines hidden (view full) ---

3140 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3141 if (rc != ECORE_SUCCESS)
3142 return rc;
3143 }
3144
3145 return ECORE_SUCCESS;
3146}
3147
3375 *p_resc_start = p_hwfn->port_id;
3376 else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI)
3377 *p_resc_start = p_hwfn->port_id;
3378 else if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE)
3379 *p_resc_start = p_hwfn->port_id + 2;
3380 break;
3381 default:
3382 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;

--- 95 unchanged lines hidden (view full) ---

3478 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3479 if (rc != ECORE_SUCCESS)
3480 return rc;
3481 }
3482
3483 return ECORE_SUCCESS;
3484}
3485
3148#define ECORE_RESC_ALLOC_LOCK_RETRY_CNT 10
3149#define ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US 10000 /* 10 msec */
3150
3151static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3486static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3487 struct ecore_ptt *p_ptt,
3152 bool drv_resc_alloc)
3153{
3154 struct ecore_resc_unlock_params resc_unlock_params;
3155 struct ecore_resc_lock_params resc_lock_params;
3156 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3157 u8 res_id;
3158 enum _ecore_status_t rc;
3159#ifndef ASIC_ONLY

--- 13 unchanged lines hidden (view full) ---

3173 * run in parallel - a resource lock is needed.
3174 * If either the resource lock or resource set value commands are not
3175 * supported - skip the the max values setting, release the lock if
3176 * needed, and proceed to the queries. Other failures, including a
3177 * failure to acquire the lock, will cause this function to fail.
3178 * Old drivers that don't acquire the lock can run in parallel, and
3179 * their allocation values won't be affected by the updated max values.
3180 */
3488 bool drv_resc_alloc)
3489{
3490 struct ecore_resc_unlock_params resc_unlock_params;
3491 struct ecore_resc_lock_params resc_lock_params;
3492 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3493 u8 res_id;
3494 enum _ecore_status_t rc;
3495#ifndef ASIC_ONLY

--- 13 unchanged lines hidden (view full) ---

3509 * run in parallel - a resource lock is needed.
3510 * If either the resource lock or resource set value commands are not
3511 * supported - skip the the max values setting, release the lock if
3512 * needed, and proceed to the queries. Other failures, including a
3513 * failure to acquire the lock, will cause this function to fail.
3514 * Old drivers that don't acquire the lock can run in parallel, and
3515 * their allocation values won't be affected by the updated max values.
3516 */
3181 OSAL_MEM_ZERO(&resc_lock_params, sizeof(resc_lock_params));
3182 resc_lock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
3183 resc_lock_params.retry_num = ECORE_RESC_ALLOC_LOCK_RETRY_CNT;
3184 resc_lock_params.retry_interval = ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US;
3185 resc_lock_params.sleep_b4_retry = true;
3186 OSAL_MEM_ZERO(&resc_unlock_params, sizeof(resc_unlock_params));
3187 resc_unlock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
3517 ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3518 ECORE_RESC_LOCK_RESC_ALLOC, false);
3188
3519
3189 rc = ecore_mcp_resc_lock(p_hwfn, p_hwfn->p_main_ptt, &resc_lock_params);
3520 rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3190 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3191 return rc;
3192 } else if (rc == ECORE_NOTIMPL) {
3193 DP_INFO(p_hwfn,
3194 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3195 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3196 DP_NOTICE(p_hwfn, false,
3197 "Failed to acquire the resource lock for the resource allocation commands\n");
3198 return ECORE_BUSY;
3199 } else {
3521 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3522 return rc;
3523 } else if (rc == ECORE_NOTIMPL) {
3524 DP_INFO(p_hwfn,
3525 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3526 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3527 DP_NOTICE(p_hwfn, false,
3528 "Failed to acquire the resource lock for the resource allocation commands\n");
3529 return ECORE_BUSY;
3530 } else {
3200 rc = ecore_hw_set_soft_resc_size(p_hwfn);
3531 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3201 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3202 DP_NOTICE(p_hwfn, false,
3203 "Failed to set the max values of the soft resources\n");
3204 goto unlock_and_exit;
3205 } else if (rc == ECORE_NOTIMPL) {
3206 DP_INFO(p_hwfn,
3207 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3532 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3533 DP_NOTICE(p_hwfn, false,
3534 "Failed to set the max values of the soft resources\n");
3535 goto unlock_and_exit;
3536 } else if (rc == ECORE_NOTIMPL) {
3537 DP_INFO(p_hwfn,
3538 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3208 rc = ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt,
3539 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3209 &resc_unlock_params);
3210 if (rc != ECORE_SUCCESS)
3211 DP_INFO(p_hwfn,
3212 "Failed to release the resource lock for the resource allocation commands\n");
3213 }
3214 }
3215
3216 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3217 if (rc != ECORE_SUCCESS)
3218 goto unlock_and_exit;
3219
3220 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3540 &resc_unlock_params);
3541 if (rc != ECORE_SUCCESS)
3542 DP_INFO(p_hwfn,
3543 "Failed to release the resource lock for the resource allocation commands\n");
3544 }
3545 }
3546
3547 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3548 if (rc != ECORE_SUCCESS)
3549 goto unlock_and_exit;
3550
3551 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3221 rc = ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt,
3552 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3222 &resc_unlock_params);
3223 if (rc != ECORE_SUCCESS)
3224 DP_INFO(p_hwfn,
3225 "Failed to release the resource lock for the resource allocation commands\n");
3226 }
3227
3228#ifndef ASIC_ONLY
3229 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {

--- 29 unchanged lines hidden (view full) ---

3259 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3260 DP_NOTICE(p_hwfn, true, "Can't assign ILT pages [%08x,...,%08x]\n",
3261 RESC_START(p_hwfn, ECORE_ILT),
3262 RESC_END(p_hwfn, ECORE_ILT) - 1);
3263 return ECORE_INVAL;
3264 }
3265
3266 /* This will also learn the number of SBs from MFW */
3553 &resc_unlock_params);
3554 if (rc != ECORE_SUCCESS)
3555 DP_INFO(p_hwfn,
3556 "Failed to release the resource lock for the resource allocation commands\n");
3557 }
3558
3559#ifndef ASIC_ONLY
3560 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {

--- 29 unchanged lines hidden (view full) ---

3590 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3591 DP_NOTICE(p_hwfn, true, "Can't assign ILT pages [%08x,...,%08x]\n",
3592 RESC_START(p_hwfn, ECORE_ILT),
3593 RESC_END(p_hwfn, ECORE_ILT) - 1);
3594 return ECORE_INVAL;
3595 }
3596
3597 /* This will also learn the number of SBs from MFW */
3267 if (ecore_int_igu_reset_cam(p_hwfn, p_hwfn->p_main_ptt))
3598 if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3268 return ECORE_INVAL;
3269
3270 ecore_hw_set_feat(p_hwfn);
3271
3272 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3273 "The numbers for each resource are:\n");
3274 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3275 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3276 ecore_hw_get_resc_name(res_id),
3277 RESC_NUM(p_hwfn, res_id),
3278 RESC_START(p_hwfn, res_id));
3279
3280 return ECORE_SUCCESS;
3281
3282unlock_and_exit:
3283 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3599 return ECORE_INVAL;
3600
3601 ecore_hw_set_feat(p_hwfn);
3602
3603 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3604 "The numbers for each resource are:\n");
3605 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3606 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3607 ecore_hw_get_resc_name(res_id),
3608 RESC_NUM(p_hwfn, res_id),
3609 RESC_START(p_hwfn, res_id));
3610
3611 return ECORE_SUCCESS;
3612
3613unlock_and_exit:
3614 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3284 ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt,
3615 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3285 &resc_unlock_params);
3286 return rc;
3287}
3288
3289static enum _ecore_status_t
3290ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3291 struct ecore_ptt *p_ptt,
3292 struct ecore_hw_prepare_params *p_params)

--- 323 unchanged lines hidden (view full) ---

3616 (p_hwfn->p_dev->num_hwfns > 1))
3617 /* In CMT on emulation, assume 1 port */
3618 port_mode = 1;
3619 else
3620#endif
3621 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3622
3623 if (port_mode < 3) {
3616 &resc_unlock_params);
3617 return rc;
3618}
3619
3620static enum _ecore_status_t
3621ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3622 struct ecore_ptt *p_ptt,
3623 struct ecore_hw_prepare_params *p_params)

--- 323 unchanged lines hidden (view full) ---

3947 (p_hwfn->p_dev->num_hwfns > 1))
3948 /* In CMT on emulation, assume 1 port */
3949 port_mode = 1;
3950 else
3951#endif
3952 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3953
3954 if (port_mode < 3) {
3624 p_hwfn->p_dev->num_ports_in_engines = 1;
3955 p_hwfn->p_dev->num_ports_in_engine = 1;
3625 } else if (port_mode <= 5) {
3956 } else if (port_mode <= 5) {
3626 p_hwfn->p_dev->num_ports_in_engines = 2;
3957 p_hwfn->p_dev->num_ports_in_engine = 2;
3627 } else {
3628 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3958 } else {
3959 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3629 p_hwfn->p_dev->num_ports_in_engines);
3960 p_hwfn->p_dev->num_ports_in_engine);
3630
3961
3631 /* Default num_ports_in_engines to something */
3632 p_hwfn->p_dev->num_ports_in_engines = 1;
3962 /* Default num_ports_in_engine to something */
3963 p_hwfn->p_dev->num_ports_in_engine = 1;
3633 }
3634}
3635
3636static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3637 struct ecore_ptt *p_ptt)
3638{
3639 u32 port;
3640 int i;
3641
3964 }
3965}
3966
3967static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3968 struct ecore_ptt *p_ptt)
3969{
3970 u32 port;
3971 int i;
3972
3642 p_hwfn->p_dev->num_ports_in_engines = 0;
3973 p_hwfn->p_dev->num_ports_in_engine = 0;
3643
3644#ifndef ASIC_ONLY
3645 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3974
3975#ifndef ASIC_ONLY
3976 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3646 port = ecore_rd(p_hwfn, p_ptt,
3647 MISCS_REG_ECO_RESERVED);
3977 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3648 switch ((port & 0xf000) >> 12) {
3649 case 1:
3978 switch ((port & 0xf000) >> 12) {
3979 case 1:
3650 p_hwfn->p_dev->num_ports_in_engines = 1;
3980 p_hwfn->p_dev->num_ports_in_engine = 1;
3651 break;
3652 case 3:
3981 break;
3982 case 3:
3653 p_hwfn->p_dev->num_ports_in_engines = 2;
3983 p_hwfn->p_dev->num_ports_in_engine = 2;
3654 break;
3655 case 0xf:
3984 break;
3985 case 0xf:
3656 p_hwfn->p_dev->num_ports_in_engines = 4;
3986 p_hwfn->p_dev->num_ports_in_engine = 4;
3657 break;
3658 default:
3659 DP_NOTICE(p_hwfn, false,
3660 "Unknown port mode in ECO_RESERVED %08x\n",
3661 port);
3662 }
3663 } else
3664#endif
3665 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3666 port = ecore_rd(p_hwfn, p_ptt,
3667 CNIG_REG_NIG_PORT0_CONF_K2_E5 + (i * 4));
3668 if (port & 1)
3987 break;
3988 default:
3989 DP_NOTICE(p_hwfn, false,
3990 "Unknown port mode in ECO_RESERVED %08x\n",
3991 port);
3992 }
3993 } else
3994#endif
3995 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3996 port = ecore_rd(p_hwfn, p_ptt,
3997 CNIG_REG_NIG_PORT0_CONF_K2_E5 + (i * 4));
3998 if (port & 1)
3669 p_hwfn->p_dev->num_ports_in_engines++;
3999 p_hwfn->p_dev->num_ports_in_engine++;
3670 }
4000 }
4001
4002 if (!p_hwfn->p_dev->num_ports_in_engine) {
4003 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
4004
4005 /* Default num_ports_in_engine to something */
4006 p_hwfn->p_dev->num_ports_in_engine = 1;
4007 }
3671}
3672
3673static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3674 struct ecore_ptt *p_ptt)
3675{
3676 if (ECORE_IS_BB(p_hwfn->p_dev))
3677 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3678 else

--- 109 unchanged lines hidden (view full) ---

3788 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3789
3790 /* In case of forcing the driver's default resource allocation, calling
3791 * ecore_hw_get_resc() should come after initializing the personality
3792 * and after getting the number of functions, since the calculation of
3793 * the resources/features depends on them.
3794 * This order is not harmful if not forcing.
3795 */
4008}
4009
4010static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
4011 struct ecore_ptt *p_ptt)
4012{
4013 if (ECORE_IS_BB(p_hwfn->p_dev))
4014 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
4015 else

--- 109 unchanged lines hidden (view full) ---

4125 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
4126
4127 /* In case of forcing the driver's default resource allocation, calling
4128 * ecore_hw_get_resc() should come after initializing the personality
4129 * and after getting the number of functions, since the calculation of
4130 * the resources/features depends on them.
4131 * This order is not harmful if not forcing.
4132 */
3796 rc = ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
4133 rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
3797 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3798 rc = ECORE_SUCCESS;
3799 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3800 }
3801
3802 return rc;
3803}
3804
4134 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
4135 rc = ECORE_SUCCESS;
4136 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
4137 }
4138
4139 return rc;
4140}
4141
3805static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
4142static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
4143 struct ecore_ptt *p_ptt)
3806{
4144{
3807 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4145 struct ecore_dev *p_dev = p_hwfn->p_dev;
3808 u16 device_id_mask;
3809 u32 tmp;
3810
3811 /* Read Vendor Id / Device Id */
3812 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3813 &p_dev->vendor_id);
3814 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3815 &p_dev->device_id);
3816
3817 /* Determine type */
3818 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
3819 switch (device_id_mask) {
3820 case ECORE_DEV_ID_MASK_BB:
3821 p_dev->type = ECORE_DEV_TYPE_BB;
3822 break;
3823 case ECORE_DEV_ID_MASK_AH:
3824 p_dev->type = ECORE_DEV_TYPE_AH;
3825 break;
4146 u16 device_id_mask;
4147 u32 tmp;
4148
4149 /* Read Vendor Id / Device Id */
4150 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
4151 &p_dev->vendor_id);
4152 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
4153 &p_dev->device_id);
4154
4155 /* Determine type */
4156 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
4157 switch (device_id_mask) {
4158 case ECORE_DEV_ID_MASK_BB:
4159 p_dev->type = ECORE_DEV_TYPE_BB;
4160 break;
4161 case ECORE_DEV_ID_MASK_AH:
4162 p_dev->type = ECORE_DEV_TYPE_AH;
4163 break;
4164 case ECORE_DEV_ID_MASK_E5:
4165 p_dev->type = ECORE_DEV_TYPE_E5;
4166 break;
3826 default:
3827 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
3828 p_dev->device_id);
3829 return ECORE_ABORTED;
3830 }
3831
4167 default:
4168 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
4169 p_dev->device_id);
4170 return ECORE_ABORTED;
4171 }
4172
3832 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3833 MISCS_REG_CHIP_NUM);
3834 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3835 MISCS_REG_CHIP_REV);
4173 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_ptt,
4174 MISCS_REG_CHIP_NUM);
4175 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_ptt,
4176 MISCS_REG_CHIP_REV);
3836
3837 MASK_FIELD(CHIP_REV, p_dev->chip_rev);
3838
3839 /* Learn number of HW-functions */
4177
4178 MASK_FIELD(CHIP_REV, p_dev->chip_rev);
4179
4180 /* Learn number of HW-functions */
3840 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3841 MISCS_REG_CMT_ENABLED_FOR_PAIR);
4181 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3842
3843 if (tmp & (1 << p_hwfn->rel_pf_id)) {
3844 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3845 p_dev->num_hwfns = 2;
3846 } else {
3847 p_dev->num_hwfns = 1;
3848 }
3849
3850#ifndef ASIC_ONLY
3851 if (CHIP_REV_IS_EMUL(p_dev)) {
3852 /* For some reason we have problems with this register
3853 * in B0 emulation; Simply assume no CMT
3854 */
3855 DP_NOTICE(p_dev->hwfns, false, "device on emul - assume no CMT\n");
3856 p_dev->num_hwfns = 1;
3857 }
3858#endif
3859
4182
4183 if (tmp & (1 << p_hwfn->rel_pf_id)) {
4184 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
4185 p_dev->num_hwfns = 2;
4186 } else {
4187 p_dev->num_hwfns = 1;
4188 }
4189
4190#ifndef ASIC_ONLY
4191 if (CHIP_REV_IS_EMUL(p_dev)) {
4192 /* For some reason we have problems with this register
4193 * in B0 emulation; Simply assume no CMT
4194 */
4195 DP_NOTICE(p_dev->hwfns, false, "device on emul - assume no CMT\n");
4196 p_dev->num_hwfns = 1;
4197 }
4198#endif
4199
3860 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
4200 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_ptt,
3861 MISCS_REG_CHIP_TEST_REG) >> 4;
3862 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
4201 MISCS_REG_CHIP_TEST_REG) >> 4;
4202 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
3863 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
4203 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_ptt,
3864 MISCS_REG_CHIP_METAL);
3865 MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
3866 DP_INFO(p_dev->hwfns,
3867 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3868 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3869 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3870 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3871 p_dev->chip_metal);
3872
3873 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
3874 DP_NOTICE(p_dev->hwfns, false,
3875 "The chip type/rev (BB A0) is not supported!\n");
3876 return ECORE_ABORTED;
3877 }
3878
3879#ifndef ASIC_ONLY
3880 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
4204 MISCS_REG_CHIP_METAL);
4205 MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
4206 DP_INFO(p_dev->hwfns,
4207 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
4208 ECORE_IS_BB(p_dev) ? "BB" : "AH",
4209 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
4210 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
4211 p_dev->chip_metal);
4212
4213 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
4214 DP_NOTICE(p_dev->hwfns, false,
4215 "The chip type/rev (BB A0) is not supported!\n");
4216 return ECORE_ABORTED;
4217 }
4218
4219#ifndef ASIC_ONLY
4220 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3881 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3882 MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
4221 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3883
3884 if (CHIP_REV_IS_EMUL(p_dev)) {
4222
4223 if (CHIP_REV_IS_EMUL(p_dev)) {
3885 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3886 MISCS_REG_ECO_RESERVED);
4224 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3887 if (tmp & (1 << 29)) {
3888 DP_NOTICE(p_hwfn, false, "Emulation: Running on a FULL build\n");
3889 p_dev->b_is_emul_full = true;
3890 } else {
3891 DP_NOTICE(p_hwfn, false, "Emulation: Running on a REDUCED build\n");
3892 }
3893 }
3894#endif

--- 79 unchanged lines hidden (view full) ---

3974 goto err0;
3975 }
3976
3977 /* Allocate the main PTT */
3978 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3979
3980 /* First hwfn learns basic information, e.g., number of hwfns */
3981 if (!p_hwfn->my_id) {
4225 if (tmp & (1 << 29)) {
4226 DP_NOTICE(p_hwfn, false, "Emulation: Running on a FULL build\n");
4227 p_dev->b_is_emul_full = true;
4228 } else {
4229 DP_NOTICE(p_hwfn, false, "Emulation: Running on a REDUCED build\n");
4230 }
4231 }
4232#endif

--- 79 unchanged lines hidden (view full) ---

4312 goto err0;
4313 }
4314
4315 /* Allocate the main PTT */
4316 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4317
4318 /* First hwfn learns basic information, e.g., number of hwfns */
4319 if (!p_hwfn->my_id) {
3982 rc = ecore_get_dev_info(p_dev);
4320 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
3983 if (rc != ECORE_SUCCESS) {
3984 if (p_params->b_relaxed_probe)
3985 p_params->p_relaxed_res =
3986 ECORE_HW_PREPARE_FAILED_DEV;
3987 goto err1;
3988 }
3989 }
3990

--- 107 unchanged lines hidden (view full) ---

4098
4099 /* initilalize 2nd hwfn if necessary */
4100 if (p_dev->num_hwfns > 1) {
4101 void OSAL_IOMEM *p_regview, *p_doorbell;
4102 u8 OSAL_IOMEM *addr;
4103
4104 /* adjust bar offset for second engine */
4105 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4321 if (rc != ECORE_SUCCESS) {
4322 if (p_params->b_relaxed_probe)
4323 p_params->p_relaxed_res =
4324 ECORE_HW_PREPARE_FAILED_DEV;
4325 goto err1;
4326 }
4327 }
4328

--- 107 unchanged lines hidden (view full) ---

4436
4437 /* initilalize 2nd hwfn if necessary */
4438 if (p_dev->num_hwfns > 1) {
4439 void OSAL_IOMEM *p_regview, *p_doorbell;
4440 u8 OSAL_IOMEM *addr;
4441
4442 /* adjust bar offset for second engine */
4443 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4106 ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
4444 ecore_hw_bar_size(p_hwfn,
4445 p_hwfn->p_main_ptt,
4446 BAR_ID_0) / 2;
4107 p_regview = (void OSAL_IOMEM *)addr;
4108
4109 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4447 p_regview = (void OSAL_IOMEM *)addr;
4448
4449 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4110 ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
4450 ecore_hw_bar_size(p_hwfn,
4451 p_hwfn->p_main_ptt,
4452 BAR_ID_1) / 2;
4111 p_doorbell = (void OSAL_IOMEM *)addr;
4112
4113 /* prepare second hw function */
4114 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4115 p_doorbell, p_params);
4116
4117 /* in case of error, need to free the previously
4118 * initiliazed hwfn 0.

--- 33 unchanged lines hidden (view full) ---

4152 ecore_vf_pf_release(p_hwfn);
4153 continue;
4154 }
4155
4156 ecore_init_free(p_hwfn);
4157 ecore_hw_hwfn_free(p_hwfn);
4158 ecore_mcp_free(p_hwfn);
4159
4453 p_doorbell = (void OSAL_IOMEM *)addr;
4454
4455 /* prepare second hw function */
4456 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4457 p_doorbell, p_params);
4458
4459 /* in case of error, need to free the previously
4460 * initiliazed hwfn 0.

--- 33 unchanged lines hidden (view full) ---

4494 ecore_vf_pf_release(p_hwfn);
4495 continue;
4496 }
4497
4498 ecore_init_free(p_hwfn);
4499 ecore_hw_hwfn_free(p_hwfn);
4500 ecore_mcp_free(p_hwfn);
4501
4502#ifdef CONFIG_ECORE_LOCK_ALLOC
4160 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
4503 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
4504#endif
4161 }
4162
4163 ecore_iov_free_hw_info(p_dev);
4164}
4165
4166static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4167 struct ecore_chain *p_chain)
4168{

--- 164 unchanged lines hidden (view full) ---

4333 return ECORE_SUCCESS;
4334}
4335
4336static enum _ecore_status_t
4337ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4338 struct ecore_chain *p_chain,
4339 struct ecore_chain_ext_pbl *ext_pbl)
4340{
4505 }
4506
4507 ecore_iov_free_hw_info(p_dev);
4508}
4509
4510static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4511 struct ecore_chain *p_chain)
4512{

--- 164 unchanged lines hidden (view full) ---

4677 return ECORE_SUCCESS;
4678}
4679
4680static enum _ecore_status_t
4681ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4682 struct ecore_chain *p_chain,
4683 struct ecore_chain_ext_pbl *ext_pbl)
4684{
4341 void *p_virt = OSAL_NULL;
4342 u8 *p_pbl_virt = OSAL_NULL;
4343 void **pp_virt_addr_tbl = OSAL_NULL;
4344 dma_addr_t p_phys = 0, p_pbl_phys = 0;
4345 u32 page_cnt = p_chain->page_cnt, size, i;
4685 u32 page_cnt = p_chain->page_cnt, size, i;
4686 dma_addr_t p_phys = 0, p_pbl_phys = 0;
4687 void **pp_virt_addr_tbl = OSAL_NULL;
4688 u8 *p_pbl_virt = OSAL_NULL;
4689 void *p_virt = OSAL_NULL;
4346
4347 size = page_cnt * sizeof(*pp_virt_addr_tbl);
4348 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4349 if (!pp_virt_addr_tbl) {
4350 DP_NOTICE(p_dev, true,
4351 "Failed to allocate memory for the chain virtual addresses table\n");
4352 return ECORE_NOMEM;
4353 }

--- 189 unchanged lines hidden (view full) ---

4543 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4544 return ECORE_NORESOURCES;
4545
4546 *p_entry_num = i;
4547
4548 return ECORE_SUCCESS;
4549}
4550
4690
4691 size = page_cnt * sizeof(*pp_virt_addr_tbl);
4692 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4693 if (!pp_virt_addr_tbl) {
4694 DP_NOTICE(p_dev, true,
4695 "Failed to allocate memory for the chain virtual addresses table\n");
4696 return ECORE_NOMEM;
4697 }

--- 189 unchanged lines hidden (view full) ---

4887 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4888 return ECORE_NORESOURCES;
4889
4890 *p_entry_num = i;
4891
4892 return ECORE_SUCCESS;
4893}
4894
4895/* OSAL_UNUSED is temporary used to avoid unused-parameter compilation warnings.
4896 * Should be removed when the function is implemented.
4897 */
4551static enum _ecore_status_t
4898static enum _ecore_status_t
4552ecore_llh_add_mac_filter_e5(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
4553 u32 high, u32 low, u32 *p_entry_num)
4899ecore_llh_add_mac_filter_e5(struct ecore_hwfn OSAL_UNUSED *p_hwfn,
4900 struct ecore_ptt OSAL_UNUSED *p_ptt,
4901 u32 OSAL_UNUSED high, u32 OSAL_UNUSED low,
4902 u32 OSAL_UNUSED *p_entry_num)
4554{
4555 ECORE_E5_MISSING_CODE;
4556
4557 return ECORE_NOTIMPL;
4558}
4559
4560enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4561 struct ecore_ptt *p_ptt, u8 *p_filter)

--- 60 unchanged lines hidden (view full) ---

4622 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4623 return ECORE_INVAL;
4624
4625 *p_entry_num = i;
4626
4627 return ECORE_SUCCESS;
4628}
4629
4903{
4904 ECORE_E5_MISSING_CODE;
4905
4906 return ECORE_NOTIMPL;
4907}
4908
4909enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4910 struct ecore_ptt *p_ptt, u8 *p_filter)

--- 60 unchanged lines hidden (view full) ---

4971 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4972 return ECORE_INVAL;
4973
4974 *p_entry_num = i;
4975
4976 return ECORE_SUCCESS;
4977}
4978
4979/* OSAL_UNUSED is temporary used to avoid unused-parameter compilation warnings.
4980 * Should be removed when the function is implemented.
4981 */
4630static enum _ecore_status_t
4982static enum _ecore_status_t
4631ecore_llh_remove_mac_filter_e5(struct ecore_hwfn *p_hwfn,
4632 struct ecore_ptt *p_ptt, u32 high, u32 low,
4633 u32 *p_entry_num)
4983ecore_llh_remove_mac_filter_e5(struct ecore_hwfn OSAL_UNUSED *p_hwfn,
4984 struct ecore_ptt OSAL_UNUSED *p_ptt,
4985 u32 OSAL_UNUSED high, u32 OSAL_UNUSED low,
4986 u32 OSAL_UNUSED *p_entry_num)
4634{
4635 ECORE_E5_MISSING_CODE;
4636
4637 return ECORE_NOTIMPL;
4638}
4639
4640void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4641 struct ecore_ptt *p_ptt, u8 *p_filter)

--- 64 unchanged lines hidden (view full) ---

4706 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4707 return ECORE_NORESOURCES;
4708
4709 *p_entry_num = i;
4710
4711 return ECORE_SUCCESS;
4712}
4713
4987{
4988 ECORE_E5_MISSING_CODE;
4989
4990 return ECORE_NOTIMPL;
4991}
4992
4993void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4994 struct ecore_ptt *p_ptt, u8 *p_filter)

--- 64 unchanged lines hidden (view full) ---

5059 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
5060 return ECORE_NORESOURCES;
5061
5062 *p_entry_num = i;
5063
5064 return ECORE_SUCCESS;
5065}
5066
5067/* OSAL_UNUSED is temporary used to avoid unused-parameter compilation warnings.
5068 * Should be removed when the function is implemented.
5069 */
4714static enum _ecore_status_t
5070static enum _ecore_status_t
4715ecore_llh_add_protocol_filter_e5(struct ecore_hwfn *p_hwfn,
4716 struct ecore_ptt *p_ptt,
4717 enum ecore_llh_port_filter_type_t type,
4718 u32 high, u32 low, u32 *p_entry_num)
5071ecore_llh_add_protocol_filter_e5(struct ecore_hwfn OSAL_UNUSED *p_hwfn,
5072 struct ecore_ptt OSAL_UNUSED *p_ptt,
5073 enum ecore_llh_port_filter_type_t OSAL_UNUSED type,
5074 u32 OSAL_UNUSED high, u32 OSAL_UNUSED low,
5075 u32 OSAL_UNUSED *p_entry_num)
4719{
4720 ECORE_E5_MISSING_CODE;
4721
4722 return ECORE_NOTIMPL;
4723}
4724
4725enum _ecore_status_t
4726ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,

--- 136 unchanged lines hidden (view full) ---

4863 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4864 return ECORE_INVAL;
4865
4866 *p_entry_num = i;
4867
4868 return ECORE_SUCCESS;
4869}
4870
5076{
5077 ECORE_E5_MISSING_CODE;
5078
5079 return ECORE_NOTIMPL;
5080}
5081
5082enum _ecore_status_t
5083ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,

--- 136 unchanged lines hidden (view full) ---

5220 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
5221 return ECORE_INVAL;
5222
5223 *p_entry_num = i;
5224
5225 return ECORE_SUCCESS;
5226}
5227
5228/* OSAL_UNUSED is temporary used to avoid unused-parameter compilation warnings.
5229 * Should be removed when the function is implemented.
5230 */
4871static enum _ecore_status_t
5231static enum _ecore_status_t
4872ecore_llh_remove_protocol_filter_e5(struct ecore_hwfn *p_hwfn,
4873 struct ecore_ptt *p_ptt,
4874 enum ecore_llh_port_filter_type_t type,
4875 u32 high, u32 low, u32 *p_entry_num)
5232ecore_llh_remove_protocol_filter_e5(struct ecore_hwfn OSAL_UNUSED *p_hwfn,
5233 struct ecore_ptt OSAL_UNUSED *p_ptt,
5234 enum ecore_llh_port_filter_type_t OSAL_UNUSED type,
5235 u32 OSAL_UNUSED high, u32 OSAL_UNUSED low,
5236 u32 OSAL_UNUSED *p_entry_num)
4876{
4877 ECORE_E5_MISSING_CODE;
4878
4879 return ECORE_NOTIMPL;
4880}
4881
4882void
4883ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,

--- 64 unchanged lines hidden (view full) ---

4948 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4949 2 * i * sizeof(u32), 0);
4950 ecore_wr(p_hwfn, p_ptt,
4951 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4952 (2 * i + 1) * sizeof(u32), 0);
4953 }
4954}
4955
5237{
5238 ECORE_E5_MISSING_CODE;
5239
5240 return ECORE_NOTIMPL;
5241}
5242
5243void
5244ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,

--- 64 unchanged lines hidden (view full) ---

5309 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5310 2 * i * sizeof(u32), 0);
5311 ecore_wr(p_hwfn, p_ptt,
5312 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5313 (2 * i + 1) * sizeof(u32), 0);
5314 }
5315}
5316
4956static void ecore_llh_clear_all_filters_e5(struct ecore_hwfn *p_hwfn,
4957 struct ecore_ptt *p_ptt)
5317/* OSAL_UNUSED is temporary used to avoid unused-parameter compilation warnings.
5318 * Should be removed when the function is implemented.
5319 */
5320static void ecore_llh_clear_all_filters_e5(struct ecore_hwfn OSAL_UNUSED *p_hwfn,
5321 struct ecore_ptt OSAL_UNUSED *p_ptt)
4958{
4959 ECORE_E5_MISSING_CODE;
4960}
4961
4962void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4963 struct ecore_ptt *p_ptt)
4964{
4965 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))

--- 183 unchanged lines hidden (view full) ---

5149 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5150 min_pf_rate;
5151 ecore_init_vport_wfq(p_hwfn, p_ptt,
5152 vport_params[i].first_tx_pq_id,
5153 vport_params[i].vport_wfq);
5154 }
5155}
5156
5322{
5323 ECORE_E5_MISSING_CODE;
5324}
5325
5326void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
5327 struct ecore_ptt *p_ptt)
5328{
5329 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))

--- 183 unchanged lines hidden (view full) ---

5513 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5514 min_pf_rate;
5515 ecore_init_vport_wfq(p_hwfn, p_ptt,
5516 vport_params[i].first_tx_pq_id,
5517 vport_params[i].vport_wfq);
5518 }
5519}
5520
5157static void
5158ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
5521static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
5159
5160{
5161 int i;
5162
5163 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5164 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5165}
5166
5167static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5522
5523{
5524 int i;
5525
5526 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5527 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5528}
5529
5530static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5168 struct ecore_ptt *p_ptt,
5169 u32 min_pf_rate)
5531 struct ecore_ptt *p_ptt)
5170{
5171 struct init_qm_vport_params *vport_params;
5172 int i;
5173
5174 vport_params = p_hwfn->qm_info.qm_vport_params;
5175
5176 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5532{
5533 struct init_qm_vport_params *vport_params;
5534 int i;
5535
5536 vport_params = p_hwfn->qm_info.qm_vport_params;
5537
5538 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5177 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
5539 ecore_init_wfq_default_param(p_hwfn);
5178 ecore_init_vport_wfq(p_hwfn, p_ptt,
5179 vport_params[i].first_tx_pq_id,
5180 vport_params[i].vport_wfq);
5181 }
5182}
5183
5184/* This function performs several validations for WFQ
5185 * configuration and required min rate for a given vport

--- 23 unchanged lines hidden (view full) ---

5209 }
5210
5211 /* Include current vport data as well */
5212 req_count++;
5213 total_req_min_rate += req_rate;
5214 non_requested_count = num_vports - req_count;
5215
5216 /* validate possible error cases */
5540 ecore_init_vport_wfq(p_hwfn, p_ptt,
5541 vport_params[i].first_tx_pq_id,
5542 vport_params[i].vport_wfq);
5543 }
5544}
5545
5546/* This function performs several validations for WFQ
5547 * configuration and required min rate for a given vport

--- 23 unchanged lines hidden (view full) ---

5571 }
5572
5573 /* Include current vport data as well */
5574 req_count++;
5575 total_req_min_rate += req_rate;
5576 non_requested_count = num_vports - req_count;
5577
5578 /* validate possible error cases */
5217 if (req_rate > min_pf_rate) {
5218 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5219 "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5220 vport_id, req_rate, min_pf_rate);
5221 return ECORE_INVAL;
5222 }
5223
5224 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5225 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5226 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5227 vport_id, req_rate, min_pf_rate);
5228 return ECORE_INVAL;
5229 }
5230
5231 /* TBD - for number of vports greater than 100 */

--- 90 unchanged lines hidden (view full) ---

5322 "WFQ validation failed while configuring min rate\n");
5323 break;
5324 }
5325 }
5326
5327 if (rc == ECORE_SUCCESS && use_wfq)
5328 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5329 else
5579 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5580 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5581 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5582 vport_id, req_rate, min_pf_rate);
5583 return ECORE_INVAL;
5584 }
5585
5586 /* TBD - for number of vports greater than 100 */

--- 90 unchanged lines hidden (view full) ---

5677 "WFQ validation failed while configuring min rate\n");
5678 break;
5679 }
5680 }
5681
5682 if (rc == ECORE_SUCCESS && use_wfq)
5683 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5684 else
5330 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5685 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5331
5332 return rc;
5333}
5334
5335/* Main API for ecore clients to configure vport min rate.
5336 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5337 * rate - Speed in Mbps needs to be assigned to a given vport.
5338 */

--- 186 unchanged lines hidden (view full) ---

5525
5526void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5527{
5528 struct ecore_mcp_link_state *p_link;
5529
5530 p_link = &p_hwfn->mcp_info->link_output;
5531
5532 if (p_link->min_pf_rate)
5686
5687 return rc;
5688}
5689
5690/* Main API for ecore clients to configure vport min rate.
5691 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5692 * rate - Speed in Mbps needs to be assigned to a given vport.
5693 */

--- 186 unchanged lines hidden (view full) ---

5880
5881void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5882{
5883 struct ecore_mcp_link_state *p_link;
5884
5885 p_link = &p_hwfn->mcp_info->link_output;
5886
5887 if (p_link->min_pf_rate)
5533 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
5534 p_link->min_pf_rate);
5888 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5535
5536 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5537 sizeof(*p_hwfn->qm_info.wfq_data) *
5538 p_hwfn->qm_info.num_vports);
5539}
5540
5541int ecore_device_num_engines(struct ecore_dev *p_dev)
5542{
5543 return ECORE_IS_BB(p_dev) ? 2 : 1;
5544}
5545
5546int ecore_device_num_ports(struct ecore_dev *p_dev)
5547{
5548 /* in CMT always only one port */
5549 if (p_dev->num_hwfns > 1)
5550 return 1;
5551
5889
5890 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5891 sizeof(*p_hwfn->qm_info.wfq_data) *
5892 p_hwfn->qm_info.num_vports);
5893}
5894
5895int ecore_device_num_engines(struct ecore_dev *p_dev)
5896{
5897 return ECORE_IS_BB(p_dev) ? 2 : 1;
5898}
5899
5900int ecore_device_num_ports(struct ecore_dev *p_dev)
5901{
5902 /* in CMT always only one port */
5903 if (p_dev->num_hwfns > 1)
5904 return 1;
5905
5552 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
5906 return p_dev->num_ports_in_engine * ecore_device_num_engines(p_dev);
5553}
5554
5907}
5908
5909int ecore_device_get_port_id(struct ecore_dev *p_dev)
5910{
5911 return (ECORE_LEADING_HWFN(p_dev)->abs_pf_id) %
5912 ecore_device_num_ports(p_dev);
5913}
5914
5555void ecore_set_fw_mac_addr(__le16 *fw_msb,
5556 __le16 *fw_mid,
5557 __le16 *fw_lsb,
5558 u8 *mac)
5559{
5560 ((u8 *)fw_msb)[0] = mac[1];
5561 ((u8 *)fw_msb)[1] = mac[0];
5562 ((u8 *)fw_mid)[0] = mac[3];
5563 ((u8 *)fw_mid)[1] = mac[2];
5564 ((u8 *)fw_lsb)[0] = mac[5];
5565 ((u8 *)fw_lsb)[1] = mac[4];
5566}
5915void ecore_set_fw_mac_addr(__le16 *fw_msb,
5916 __le16 *fw_mid,
5917 __le16 *fw_lsb,
5918 u8 *mac)
5919{
5920 ((u8 *)fw_msb)[0] = mac[1];
5921 ((u8 *)fw_msb)[1] = mac[0];
5922 ((u8 *)fw_mid)[0] = mac[3];
5923 ((u8 *)fw_mid)[1] = mac[2];
5924 ((u8 *)fw_lsb)[0] = mac[5];
5925 ((u8 *)fw_lsb)[1] = mac[4];
5926}