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ppc.c (183053) ppc.c (184130)
1/*-
2 * Copyright (c) 1997-2000 Nicolas Souchu
3 * Copyright (c) 2001 Alcove - Nicolas Souchu
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1997-2000 Nicolas Souchu
3 * Copyright (c) 2001 Alcove - Nicolas Souchu
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/dev/ppc/ppc.c 183053 2008-09-15 22:26:32Z jhb $");
29__FBSDID("$FreeBSD: head/sys/dev/ppc/ppc.c 184130 2008-10-21 18:30:10Z jhb $");
30
31#include "opt_ppc.h"
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/kernel.h>
37#include <sys/interrupt.h>

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128
129 for (i = 0; i < 100; i++) {
130 r = r_ecr(ppc);
131 if (r & 0x1)
132 return;
133 DELAY(100);
134 }
135
30
31#include "opt_ppc.h"
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/kernel.h>
37#include <sys/interrupt.h>

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128
129 for (i = 0; i < 100; i++) {
130 r = r_ecr(ppc);
131 if (r & 0x1)
132 return;
133 DELAY(100);
134 }
135
136 printf("ppc%d: ECP sync failed as data still " \
137 "present in FIFO.\n", ppc->ppc_unit);
136 device_printf(dev, "ECP sync failed as data still present in FIFO.\n");
138
139 return;
140}
141
142/*
143 * ppc_detect_fifo()
144 *
145 * Detect parallel port FIFO

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747
748 /*
749 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
750 * If SPP mode is detected, try to set ECP+EPP mode
751 */
752
753 if (bootverbose) {
754 outb(csr, 0x1);
137
138 return;
139}
140
141/*
142 * ppc_detect_fifo()
143 *
144 * Detect parallel port FIFO

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746
747 /*
748 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
749 * If SPP mode is detected, try to set ECP+EPP mode
750 */
751
752 if (bootverbose) {
753 outb(csr, 0x1);
755 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit,
756 inb(cio) & 0xff);
754 device_printf(dev, "SMC registers CR1=0x%x", inb(cio) & 0xff);
757
758 outb(csr, 0x4);
759 printf(" CR4=0x%x", inb(cio) & 0xff);
760 }
761
762 /* select CR1 */
763 outb(csr, 0x1);
764

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1041 break;
1042
1043 default:
1044 ppc->ppc_model = WINB_UNKNOWN;
1045 }
1046
1047 if (bootverbose) {
1048 /* dump of registers */
755
756 outb(csr, 0x4);
757 printf(" CR4=0x%x", inb(cio) & 0xff);
758 }
759
760 /* select CR1 */
761 outb(csr, 0x1);
762

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1039 break;
1040
1041 default:
1042 ppc->ppc_model = WINB_UNKNOWN;
1043 }
1044
1045 if (bootverbose) {
1046 /* dump of registers */
1049 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]);
1047 device_printf(dev, "0x%x - ", w83877f_keys[i]);
1050 for (i = 0; i <= 0xd; i ++) {
1051 outb(efir, i);
1052 printf("0x%x ", inb(efdr));
1053 }
1054 for (i = 0x10; i <= 0x17; i ++) {
1055 outb(efir, i);
1056 printf("0x%x ", inb(efdr));
1057 }
1058 outb(efir, 0x1e);
1059 printf("0x%x ", inb(efdr));
1060 for (i = 0x20; i <= 0x29; i ++) {
1061 outb(efir, i);
1062 printf("0x%x ", inb(efdr));
1063 }
1064 printf("\n");
1048 for (i = 0; i <= 0xd; i ++) {
1049 outb(efir, i);
1050 printf("0x%x ", inb(efdr));
1051 }
1052 for (i = 0x10; i <= 0x17; i ++) {
1053 outb(efir, i);
1054 printf("0x%x ", inb(efdr));
1055 }
1056 outb(efir, 0x1e);
1057 printf("0x%x ", inb(efdr));
1058 for (i = 0x20; i <= 0x29; i ++) {
1059 outb(efir, i);
1060 printf("0x%x ", inb(efdr));
1061 }
1062 printf("\n");
1065 printf("ppc%d:", ppc->ppc_unit);
1066 }
1067
1068 ppc->ppc_type = PPC_TYPE_GENERIC;
1069
1070 if (!chipset_mode) {
1071 /* autodetect mode */
1072
1073 /* select CR0 */
1074 outb(efir, 0x0);
1075 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1076
1077 /* select CR9 */
1078 outb(efir, 0x9);
1079 r |= (inb(efdr) & WINB_PRTMODS2);
1080
1081 switch (r) {
1082 case WINB_W83757:
1083 if (bootverbose)
1063 }
1064
1065 ppc->ppc_type = PPC_TYPE_GENERIC;
1066
1067 if (!chipset_mode) {
1068 /* autodetect mode */
1069
1070 /* select CR0 */
1071 outb(efir, 0x0);
1072 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1073
1074 /* select CR9 */
1075 outb(efir, 0x9);
1076 r |= (inb(efdr) & WINB_PRTMODS2);
1077
1078 switch (r) {
1079 case WINB_W83757:
1080 if (bootverbose)
1084 printf("ppc%d: W83757 compatible mode\n",
1085 ppc->ppc_unit);
1081 device_printf(dev, "W83757 compatible mode\n");
1086 return (-1); /* generic or SMC-like */
1087
1088 case WINB_EXTFDC:
1089 case WINB_EXTADP:
1090 case WINB_EXT2FDD:
1091 case WINB_JOYSTICK:
1092 if (bootverbose)
1082 return (-1); /* generic or SMC-like */
1083
1084 case WINB_EXTFDC:
1085 case WINB_EXTADP:
1086 case WINB_EXT2FDD:
1087 case WINB_JOYSTICK:
1088 if (bootverbose)
1093 printf(" not in parallel port mode\n");
1089 device_printf(dev,
1090 "not in parallel port mode\n");
1094 return (-1);
1095
1096 case (WINB_PARALLEL | WINB_EPP_SPP):
1097 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1098 if (bootverbose)
1091 return (-1);
1092
1093 case (WINB_PARALLEL | WINB_EPP_SPP):
1094 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1095 if (bootverbose)
1099 printf(" EPP SPP");
1096 device_printf(dev, "EPP SPP\n");
1100 break;
1101
1102 case (WINB_PARALLEL | WINB_ECP):
1103 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1104 if (bootverbose)
1097 break;
1098
1099 case (WINB_PARALLEL | WINB_ECP):
1100 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1101 if (bootverbose)
1105 printf(" ECP SPP");
1102 device_printf(dev, "ECP SPP\n");
1106 break;
1107
1108 case (WINB_PARALLEL | WINB_ECP_EPP):
1109 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1110 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1111
1112 if (bootverbose)
1103 break;
1104
1105 case (WINB_PARALLEL | WINB_ECP_EPP):
1106 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1107 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1108
1109 if (bootverbose)
1113 printf(" ECP+EPP SPP");
1110 device_printf(dev, "ECP+EPP SPP\n");
1114 break;
1115 default:
1116 printf("%s: unknown case (0x%x)!\n", __func__, r);
1117 }
1118
1119 } else {
1120 /* mode forced */
1121

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1126 /* select CR0 and reset PRTMODSx bits */
1127 outb(efir, 0x0);
1128 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1129
1130 if (chipset_mode & PPB_ECP) {
1131 if (chipset_mode & PPB_EPP) {
1132 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1133 if (bootverbose)
1111 break;
1112 default:
1113 printf("%s: unknown case (0x%x)!\n", __func__, r);
1114 }
1115
1116 } else {
1117 /* mode forced */
1118

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1123 /* select CR0 and reset PRTMODSx bits */
1124 outb(efir, 0x0);
1125 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1126
1127 if (chipset_mode & PPB_ECP) {
1128 if (chipset_mode & PPB_EPP) {
1129 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1130 if (bootverbose)
1134 printf(" ECP+EPP");
1131 device_printf(dev, "ECP+EPP\n");
1135
1136 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1137
1138 } else {
1139 outb(efdr, inb(efdr) | WINB_ECP);
1140 if (bootverbose)
1132
1133 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1134
1135 } else {
1136 outb(efdr, inb(efdr) | WINB_ECP);
1137 if (bootverbose)
1141 printf(" ECP");
1138 device_printf(dev, "ECP\n");
1142 }
1143 } else {
1144 /* select EPP_SPP otherwise */
1145 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1146 if (bootverbose)
1139 }
1140 } else {
1141 /* select EPP_SPP otherwise */
1142 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1143 if (bootverbose)
1147 printf(" EPP SPP");
1144 device_printf(dev, "EPP SPP\n");
1148 }
1149 ppc->ppc_avm = chipset_mode;
1150 }
1151
1145 }
1146 ppc->ppc_avm = chipset_mode;
1147 }
1148
1152 if (bootverbose)
1153 printf("\n");
1154
1155 /* exit configuration mode */
1156 outb(efer, 0xaa);
1157
1158 switch (ppc->ppc_type) {
1159 case PPC_TYPE_SMCLIKE:
1160 ppc_smclike_setmode(ppc, chipset_mode);
1161 break;
1162 default:

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1173 */
1174static int
1175ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1176{
1177 /* default to generic */
1178 ppc->ppc_type = PPC_TYPE_GENERIC;
1179
1180 if (bootverbose)
1149 /* exit configuration mode */
1150 outb(efer, 0xaa);
1151
1152 switch (ppc->ppc_type) {
1153 case PPC_TYPE_SMCLIKE:
1154 ppc_smclike_setmode(ppc, chipset_mode);
1155 break;
1156 default:

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1167 */
1168static int
1169ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1170{
1171 /* default to generic */
1172 ppc->ppc_type = PPC_TYPE_GENERIC;
1173
1174 if (bootverbose)
1181 printf("ppc%d:", ppc->ppc_unit);
1175 device_printf(ppc->ppc_dev, "SPP");
1182
1183 /* first, check for ECP */
1184 w_ecr(ppc, PPC_ECR_PS2);
1185 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1186 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1187 if (bootverbose)
1176
1177 /* first, check for ECP */
1178 w_ecr(ppc, PPC_ECR_PS2);
1179 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1180 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1181 if (bootverbose)
1188 printf(" ECP SPP");
1182 printf(" ECP ");
1189
1190 /* search for SMC style ECP+EPP mode */
1191 w_ecr(ppc, PPC_ECR_EPP);
1192 }
1193
1194 /* try to reset EPP timeout bit */
1195 if (ppc_check_epp_timeout(ppc)) {
1196 ppc->ppc_dtm |= PPB_EPP;

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1209 } else {
1210 /* restore to standard mode */
1211 w_ecr(ppc, PPC_ECR_STD);
1212 }
1213
1214 /* XXX try to detect NIBBLE and PS2 modes */
1215 ppc->ppc_dtm |= PPB_NIBBLE;
1216
1183
1184 /* search for SMC style ECP+EPP mode */
1185 w_ecr(ppc, PPC_ECR_EPP);
1186 }
1187
1188 /* try to reset EPP timeout bit */
1189 if (ppc_check_epp_timeout(ppc)) {
1190 ppc->ppc_dtm |= PPB_EPP;

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1203 } else {
1204 /* restore to standard mode */
1205 w_ecr(ppc, PPC_ECR_STD);
1206 }
1207
1208 /* XXX try to detect NIBBLE and PS2 modes */
1209 ppc->ppc_dtm |= PPB_NIBBLE;
1210
1217 if (bootverbose)
1218 printf(" SPP");
1219
1220 if (chipset_mode)
1221 ppc->ppc_avm = chipset_mode;
1222 else
1223 ppc->ppc_avm = ppc->ppc_dtm;
1224
1225 if (bootverbose)
1226 printf("\n");
1227

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1732 RF_ACTIVE);
1733 }
1734
1735 if (ppc->res_irq)
1736 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1737 if (ppc->res_drq)
1738 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1739
1211 if (chipset_mode)
1212 ppc->ppc_avm = chipset_mode;
1213 else
1214 ppc->ppc_avm = ppc->ppc_dtm;
1215
1216 if (bootverbose)
1217 printf("\n");
1218

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1723 RF_ACTIVE);
1724 }
1725
1726 if (ppc->res_irq)
1727 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1728 if (ppc->res_drq)
1729 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1730
1740 ppc->ppc_unit = device_get_unit(dev);
1731 ppc->ppc_dev = dev;
1741 ppc->ppc_model = GENERIC;
1742
1743 ppc->ppc_mode = PPB_COMPATIBLE;
1744 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1745
1746 ppc->ppc_type = PPC_TYPE_GENERIC;
1747
1748#if defined(__i386__) && defined(PC98)

--- 305 unchanged lines hidden --- 		1732 ppc->ppc_model = GENERIC;
1733
1734 ppc->ppc_mode = PPB_COMPATIBLE;
1735 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1736
1737 ppc->ppc_type = PPC_TYPE_GENERIC;
1738
1739#if defined(__i386__) && defined(PC98)

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