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pci.c (281874) pci.c (283735)
1/*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 13 unchanged lines hidden (view full) ---

22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD: head/sys/dev/pci/pci.c 281874 2015-04-22 22:02:27Z jhb $");
30__FBSDID("$FreeBSD: head/sys/dev/pci/pci.c 283735 2015-05-29 13:24:17Z kib $");
31
32#include "opt_bus.h"
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/malloc.h>
37#include <sys/module.h>
38#include <sys/limits.h>

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2384 * PCI power manangement
2385 */
2386int
2387pci_set_powerstate_method(device_t dev, device_t child, int state)
2388{
2389 struct pci_devinfo *dinfo = device_get_ivars(child);
2390 pcicfgregs *cfg = &dinfo->cfg;
2391 uint16_t status;
31
32#include "opt_bus.h"
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/malloc.h>
37#include <sys/module.h>
38#include <sys/limits.h>

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2384 * PCI power manangement
2385 */
2386int
2387pci_set_powerstate_method(device_t dev, device_t child, int state)
2388{
2389 struct pci_devinfo *dinfo = device_get_ivars(child);
2390 pcicfgregs *cfg = &dinfo->cfg;
2391 uint16_t status;
2392 int result, oldstate, highest, delay;
2392 int oldstate, highest, delay;
2393
2394 if (cfg->pp.pp_cap == 0)
2395 return (EOPNOTSUPP);
2396
2397 /*
2398 * Optimize a no state change request away. While it would be OK to
2399 * write to the hardware in theory, some devices have shown odd
2400 * behavior when going from D3 -> D3.

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2419 if (highest == PCI_POWERSTATE_D3)
2420 delay = 10000;
2421 else if (highest == PCI_POWERSTATE_D2)
2422 delay = 200;
2423 else
2424 delay = 0;
2425 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2426 & ~PCIM_PSTAT_DMASK;
2393
2394 if (cfg->pp.pp_cap == 0)
2395 return (EOPNOTSUPP);
2396
2397 /*
2398 * Optimize a no state change request away. While it would be OK to
2399 * write to the hardware in theory, some devices have shown odd
2400 * behavior when going from D3 -> D3.

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2419 if (highest == PCI_POWERSTATE_D3)
2420 delay = 10000;
2421 else if (highest == PCI_POWERSTATE_D2)
2422 delay = 200;
2423 else
2424 delay = 0;
2425 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2426 & ~PCIM_PSTAT_DMASK;
2427 result = 0;
2428 switch (state) {
2429 case PCI_POWERSTATE_D0:
2430 status |= PCIM_PSTAT_D0;
2431 break;
2432 case PCI_POWERSTATE_D1:
2433 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2434 return (EOPNOTSUPP);
2435 status |= PCIM_PSTAT_D1;

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2984 * same addresses that old ISA hardware did. This dictates that we use
2985 * those addresses and ignore the BAR's if we cannot set PCI native
2986 * addressing mode.
2987 */
2988static void
2989pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
2990 uint32_t prefetchmask)
2991{
2427 switch (state) {
2428 case PCI_POWERSTATE_D0:
2429 status |= PCIM_PSTAT_D0;
2430 break;
2431 case PCI_POWERSTATE_D1:
2432 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2433 return (EOPNOTSUPP);
2434 status |= PCIM_PSTAT_D1;

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2983 * same addresses that old ISA hardware did. This dictates that we use
2984 * those addresses and ignore the BAR's if we cannot set PCI native
2985 * addressing mode.
2986 */
2987static void
2988pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
2989 uint32_t prefetchmask)
2990{
2992 struct resource *r;
2993 int rid, type, progif;
2994#if 0
2995 /* if this device supports PCI native addressing use it */
2996 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2997 if ((progif & 0x8a) == 0x8a) {
2998 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2999 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
3000 printf("Trying ATA native PCI addressing mode\n");

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3007 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
3008 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
3009 prefetchmask & (1 << 0));
3010 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
3011 prefetchmask & (1 << 1));
3012 } else {
3013 rid = PCIR_BAR(0);
3014 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2991 int rid, type, progif;
2992#if 0
2993 /* if this device supports PCI native addressing use it */
2994 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2995 if ((progif & 0x8a) == 0x8a) {
2996 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2997 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2998 printf("Trying ATA native PCI addressing mode\n");

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3005 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
3006 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
3007 prefetchmask & (1 << 0));
3008 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
3009 prefetchmask & (1 << 1));
3010 } else {
3011 rid = PCIR_BAR(0);
3012 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
3015 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0,
3013 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0,
3016 0x1f7, 8, 0);
3017 rid = PCIR_BAR(1);
3018 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
3014 0x1f7, 8, 0);
3015 rid = PCIR_BAR(1);
3016 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
3019 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6,
3017 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6,
3020 0x3f6, 1, 0);
3021 }
3022 if (progif & PCIP_STORAGE_IDE_MODESEC) {
3023 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
3024 prefetchmask & (1 << 2));
3025 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
3026 prefetchmask & (1 << 3));
3027 } else {
3028 rid = PCIR_BAR(2);
3029 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
3018 0x3f6, 1, 0);
3019 }
3020 if (progif & PCIP_STORAGE_IDE_MODESEC) {
3021 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
3022 prefetchmask & (1 << 2));
3023 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
3024 prefetchmask & (1 << 3));
3025 } else {
3026 rid = PCIR_BAR(2);
3027 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
3030 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x170,
3028 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170,
3031 0x177, 8, 0);
3032 rid = PCIR_BAR(3);
3033 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
3029 0x177, 8, 0);
3030 rid = PCIR_BAR(3);
3031 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
3034 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x376,
3032 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376,
3035 0x376, 1, 0);
3036 }
3037 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
3038 prefetchmask & (1 << 4));
3039 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
3040 prefetchmask & (1 << 5));
3041}
3042

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3722 sc = device_get_softc(dev);
3723 return (bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus));
3724}
3725#endif
3726
3727static void
3728pci_set_power_child(device_t dev, device_t child, int state)
3729{
3033 0x376, 1, 0);
3034 }
3035 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
3036 prefetchmask & (1 << 4));
3037 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
3038 prefetchmask & (1 << 5));
3039}
3040

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3720 sc = device_get_softc(dev);
3721 return (bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus));
3722}
3723#endif
3724
3725static void
3726pci_set_power_child(device_t dev, device_t child, int state)
3727{
3730 struct pci_devinfo *dinfo;
3731 device_t pcib;
3732 int dstate;
3733
3734 /*
3735 * Set the device to the given state. If the firmware suggests
3736 * a different power state, use it instead. If power management
3737 * is not present, the firmware is responsible for managing
3738 * device power. Skip children who aren't attached since they
3739 * are handled separately.
3740 */
3741 pcib = device_get_parent(dev);
3728 device_t pcib;
3729 int dstate;
3730
3731 /*
3732 * Set the device to the given state. If the firmware suggests
3733 * a different power state, use it instead. If power management
3734 * is not present, the firmware is responsible for managing
3735 * device power. Skip children who aren't attached since they
3736 * are handled separately.
3737 */
3738 pcib = device_get_parent(dev);
3742 dinfo = device_get_ivars(child);
3743 dstate = state;
3744 if (device_is_attached(child) &&
3745 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0)
3746 pci_set_powerstate(child, dstate);
3747}
3748
3749int
3750pci_suspend_child(device_t dev, device_t child)

--- 1630 unchanged lines hidden --- 		3739 dstate = state;
3740 if (device_is_attached(child) &&
3741 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0)
3742 pci_set_powerstate(child, dstate);
3743}
3744
3745int
3746pci_suspend_child(device_t dev, device_t child)

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