1/*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
|
30__FBSDID("$FreeBSD: head/sys/dev/pci/pci.c 261527 2014-02-05 20:52:12Z jhb $");
| 30__FBSDID("$FreeBSD: head/sys/dev/pci/pci.c 261790 2014-02-12 04:30:37Z jhb $");
|
31
32#include "opt_bus.h"
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/malloc.h>
37#include <sys/module.h>
38#include <sys/linker.h>
39#include <sys/fcntl.h>
40#include <sys/conf.h>
41#include <sys/kernel.h>
42#include <sys/queue.h>
43#include <sys/sysctl.h>
44#include <sys/endian.h>
45
46#include <vm/vm.h>
47#include <vm/pmap.h>
48#include <vm/vm_extern.h>
49
50#include <sys/bus.h>
51#include <machine/bus.h>
52#include <sys/rman.h>
53#include <machine/resource.h>
54#include <machine/stdarg.h>
55
56#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
57#include <machine/intr_machdep.h>
58#endif
59
60#include <sys/pciio.h>
61#include <dev/pci/pcireg.h>
62#include <dev/pci/pcivar.h>
63#include <dev/pci/pci_private.h>
64
65#include <dev/usb/controller/xhcireg.h>
66#include <dev/usb/controller/ehcireg.h>
67#include <dev/usb/controller/ohcireg.h>
68#include <dev/usb/controller/uhcireg.h>
69
70#include "pcib_if.h"
71#include "pci_if.h"
72
73#define PCIR_IS_BIOS(cfg, reg) \
74 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
75 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
76
77static int pci_has_quirk(uint32_t devid, int quirk);
78static pci_addr_t pci_mapbase(uint64_t mapreg);
79static const char *pci_maptype(uint64_t mapreg);
80static int pci_mapsize(uint64_t testval);
81static int pci_maprange(uint64_t mapreg);
82static pci_addr_t pci_rombase(uint64_t mapreg);
83static int pci_romsize(uint64_t testval);
84static void pci_fixancient(pcicfgregs *cfg);
85static int pci_printf(pcicfgregs *cfg, const char *fmt, ...);
86
87static int pci_porten(device_t dev);
88static int pci_memen(device_t dev);
89static void pci_assign_interrupt(device_t bus, device_t dev,
90 int force_route);
91static int pci_add_map(device_t bus, device_t dev, int reg,
92 struct resource_list *rl, int force, int prefetch);
93static int pci_probe(device_t dev);
94static int pci_attach(device_t dev);
| 31
32#include "opt_bus.h"
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/malloc.h>
37#include <sys/module.h>
38#include <sys/linker.h>
39#include <sys/fcntl.h>
40#include <sys/conf.h>
41#include <sys/kernel.h>
42#include <sys/queue.h>
43#include <sys/sysctl.h>
44#include <sys/endian.h>
45
46#include <vm/vm.h>
47#include <vm/pmap.h>
48#include <vm/vm_extern.h>
49
50#include <sys/bus.h>
51#include <machine/bus.h>
52#include <sys/rman.h>
53#include <machine/resource.h>
54#include <machine/stdarg.h>
55
56#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
57#include <machine/intr_machdep.h>
58#endif
59
60#include <sys/pciio.h>
61#include <dev/pci/pcireg.h>
62#include <dev/pci/pcivar.h>
63#include <dev/pci/pci_private.h>
64
65#include <dev/usb/controller/xhcireg.h>
66#include <dev/usb/controller/ehcireg.h>
67#include <dev/usb/controller/ohcireg.h>
68#include <dev/usb/controller/uhcireg.h>
69
70#include "pcib_if.h"
71#include "pci_if.h"
72
73#define PCIR_IS_BIOS(cfg, reg) \
74 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
75 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
76
77static int pci_has_quirk(uint32_t devid, int quirk);
78static pci_addr_t pci_mapbase(uint64_t mapreg);
79static const char *pci_maptype(uint64_t mapreg);
80static int pci_mapsize(uint64_t testval);
81static int pci_maprange(uint64_t mapreg);
82static pci_addr_t pci_rombase(uint64_t mapreg);
83static int pci_romsize(uint64_t testval);
84static void pci_fixancient(pcicfgregs *cfg);
85static int pci_printf(pcicfgregs *cfg, const char *fmt, ...);
86
87static int pci_porten(device_t dev);
88static int pci_memen(device_t dev);
89static void pci_assign_interrupt(device_t bus, device_t dev,
90 int force_route);
91static int pci_add_map(device_t bus, device_t dev, int reg,
92 struct resource_list *rl, int force, int prefetch);
93static int pci_probe(device_t dev);
94static int pci_attach(device_t dev);
|
| 95#ifdef PCI_RES_BUS
96static int pci_detach(device_t dev);
97#endif
|
95static void pci_load_vendor_data(void);
96static int pci_describe_parse_line(char **ptr, int *vendor,
97 int *device, char **desc);
98static char *pci_describe_device(device_t dev);
99static int pci_modevent(module_t mod, int what, void *arg);
100static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
101 pcicfgregs *cfg);
102static void pci_read_cap(device_t pcib, pcicfgregs *cfg);
103static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
104 int reg, uint32_t *data);
105#if 0
106static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
107 int reg, uint32_t data);
108#endif
109static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
110static void pci_disable_msi(device_t dev);
111static void pci_enable_msi(device_t dev, uint64_t address,
112 uint16_t data);
113static void pci_enable_msix(device_t dev, u_int index,
114 uint64_t address, uint32_t data);
115static void pci_mask_msix(device_t dev, u_int index);
116static void pci_unmask_msix(device_t dev, u_int index);
117static int pci_msi_blacklisted(void);
118static int pci_msix_blacklisted(void);
119static void pci_resume_msi(device_t dev);
120static void pci_resume_msix(device_t dev);
121static int pci_remap_intr_method(device_t bus, device_t dev,
122 u_int irq);
123
124static device_method_t pci_methods[] = {
125 /* Device interface */
126 DEVMETHOD(device_probe, pci_probe),
127 DEVMETHOD(device_attach, pci_attach),
| 98static void pci_load_vendor_data(void);
99static int pci_describe_parse_line(char **ptr, int *vendor,
100 int *device, char **desc);
101static char *pci_describe_device(device_t dev);
102static int pci_modevent(module_t mod, int what, void *arg);
103static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
104 pcicfgregs *cfg);
105static void pci_read_cap(device_t pcib, pcicfgregs *cfg);
106static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
107 int reg, uint32_t *data);
108#if 0
109static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
110 int reg, uint32_t data);
111#endif
112static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
113static void pci_disable_msi(device_t dev);
114static void pci_enable_msi(device_t dev, uint64_t address,
115 uint16_t data);
116static void pci_enable_msix(device_t dev, u_int index,
117 uint64_t address, uint32_t data);
118static void pci_mask_msix(device_t dev, u_int index);
119static void pci_unmask_msix(device_t dev, u_int index);
120static int pci_msi_blacklisted(void);
121static int pci_msix_blacklisted(void);
122static void pci_resume_msi(device_t dev);
123static void pci_resume_msix(device_t dev);
124static int pci_remap_intr_method(device_t bus, device_t dev,
125 u_int irq);
126
127static device_method_t pci_methods[] = {
128 /* Device interface */
129 DEVMETHOD(device_probe, pci_probe),
130 DEVMETHOD(device_attach, pci_attach),
|
| 131#ifdef PCI_RES_BUS
132 DEVMETHOD(device_detach, pci_detach),
133#else
|
128 DEVMETHOD(device_detach, bus_generic_detach),
| 134 DEVMETHOD(device_detach, bus_generic_detach),
|
| 135#endif
|
129 DEVMETHOD(device_shutdown, bus_generic_shutdown),
130 DEVMETHOD(device_suspend, pci_suspend),
131 DEVMETHOD(device_resume, pci_resume),
132
133 /* Bus interface */
134 DEVMETHOD(bus_print_child, pci_print_child),
135 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
136 DEVMETHOD(bus_read_ivar, pci_read_ivar),
137 DEVMETHOD(bus_write_ivar, pci_write_ivar),
138 DEVMETHOD(bus_driver_added, pci_driver_added),
139 DEVMETHOD(bus_setup_intr, pci_setup_intr),
140 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
141
142 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag),
143 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
144 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
145 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
146 DEVMETHOD(bus_delete_resource, pci_delete_resource),
147 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
148 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
149 DEVMETHOD(bus_release_resource, pci_release_resource),
150 DEVMETHOD(bus_activate_resource, pci_activate_resource),
151 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
152 DEVMETHOD(bus_child_detached, pci_child_detached),
153 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
154 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
155 DEVMETHOD(bus_remap_intr, pci_remap_intr_method),
156
157 /* PCI interface */
158 DEVMETHOD(pci_read_config, pci_read_config_method),
159 DEVMETHOD(pci_write_config, pci_write_config_method),
160 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
161 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
162 DEVMETHOD(pci_enable_io, pci_enable_io_method),
163 DEVMETHOD(pci_disable_io, pci_disable_io_method),
164 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
165 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
166 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
167 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
168 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
169 DEVMETHOD(pci_find_cap, pci_find_cap_method),
170 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
171 DEVMETHOD(pci_find_htcap, pci_find_htcap_method),
172 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
173 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
174 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
175 DEVMETHOD(pci_release_msi, pci_release_msi_method),
176 DEVMETHOD(pci_msi_count, pci_msi_count_method),
177 DEVMETHOD(pci_msix_count, pci_msix_count_method),
178
179 DEVMETHOD_END
180};
181
182DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc));
183
184static devclass_t pci_devclass;
185DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL);
186MODULE_VERSION(pci, 1);
187
188static char *pci_vendordata;
189static size_t pci_vendordata_size;
190
191struct pci_quirk {
192 uint32_t devid; /* Vendor/device of the card */
193 int type;
194#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
195#define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
196#define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */
197#define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */
198#define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
199 int arg1;
200 int arg2;
201};
202
203static const struct pci_quirk pci_quirks[] = {
204 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
205 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
206 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
207 /* As does the Serverworks OSB4 (the SMBus mapping register) */
208 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
209
210 /*
211 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
212 * or the CMIC-SL (AKA ServerWorks GC_LE).
213 */
214 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
215 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
216
217 /*
218 * MSI doesn't work on earlier Intel chipsets including
219 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
220 */
221 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
222 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
223 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
224 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
225 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
226 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
227 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
228
229 /*
230 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
231 * bridge.
232 */
233 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
234
235 /*
236 * MSI-X allocation doesn't work properly for devices passed through
237 * by VMware up to at least ESXi 5.1.
238 */
239 { 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCI/PCI-X */
240 { 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCIe */
241
242 /*
243 * Some virtualization environments emulate an older chipset
244 * but support MSI just fine. QEMU uses the Intel 82440.
245 */
246 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 },
247
248 /*
249 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus
250 * controller depending on SoftPciRst register (PM_IO 0x55 [7]).
251 * It prevents us from attaching hpet(4) when the bit is unset.
252 * Note this quirk only affects SB600 revision A13 and earlier.
253 * For SB600 A21 and later, firmware must set the bit to hide it.
254 * For SB700 and later, it is unused and hardcoded to zero.
255 */
256 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 },
257
258 { 0 }
259};
260
261/* map register information */
262#define PCI_MAPMEM 0x01 /* memory map */
263#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
264#define PCI_MAPPORT 0x04 /* port map */
265
266struct devlist pci_devq;
267uint32_t pci_generation;
268uint32_t pci_numdevs = 0;
269static int pcie_chipset, pcix_chipset;
270
271/* sysctl vars */
272SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
273
274static int pci_enable_io_modes = 1;
275TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
276SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
277 &pci_enable_io_modes, 1,
278 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
279enable these bits correctly. We'd like to do this all the time, but there\n\
280are some peripherals that this causes problems with.");
281
282static int pci_do_realloc_bars = 0;
283TUNABLE_INT("hw.pci.realloc_bars", &pci_do_realloc_bars);
284SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RW,
285 &pci_do_realloc_bars, 0,
286 "Attempt to allocate a new range for any BARs whose original firmware-assigned ranges fail to allocate during the initial device scan.");
287
288static int pci_do_power_nodriver = 0;
289TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
290SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
291 &pci_do_power_nodriver, 0,
292 "Place a function into D3 state when no driver attaches to it. 0 means\n\
293disable. 1 means conservatively place devices into D3 state. 2 means\n\
294agressively place devices into D3 state. 3 means put absolutely everything\n\
295in D3 state.");
296
297int pci_do_power_resume = 1;
298TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
299SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
300 &pci_do_power_resume, 1,
301 "Transition from D3 -> D0 on resume.");
302
303int pci_do_power_suspend = 1;
304TUNABLE_INT("hw.pci.do_power_suspend", &pci_do_power_suspend);
305SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RW,
306 &pci_do_power_suspend, 1,
307 "Transition from D0 -> D3 on suspend.");
308
309static int pci_do_msi = 1;
310TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
311SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
312 "Enable support for MSI interrupts");
313
314static int pci_do_msix = 1;
315TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
316SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
317 "Enable support for MSI-X interrupts");
318
319static int pci_honor_msi_blacklist = 1;
320TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
321SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
322 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X");
323
324#if defined(__i386__) || defined(__amd64__)
325static int pci_usb_takeover = 1;
326#else
327static int pci_usb_takeover = 0;
328#endif
329TUNABLE_INT("hw.pci.usb_early_takeover", &pci_usb_takeover);
330SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN,
331 &pci_usb_takeover, 1, "Enable early takeover of USB controllers.\n\
332Disable this if you depend on BIOS emulation of USB devices, that is\n\
333you use USB devices (like keyboard or mouse) but do not load USB drivers");
334
335static int pci_clear_bars;
336TUNABLE_INT("hw.pci.clear_bars", &pci_clear_bars);
337SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0,
338 "Ignore firmware-assigned resources for BARs.");
339
| 136 DEVMETHOD(device_shutdown, bus_generic_shutdown),
137 DEVMETHOD(device_suspend, pci_suspend),
138 DEVMETHOD(device_resume, pci_resume),
139
140 /* Bus interface */
141 DEVMETHOD(bus_print_child, pci_print_child),
142 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
143 DEVMETHOD(bus_read_ivar, pci_read_ivar),
144 DEVMETHOD(bus_write_ivar, pci_write_ivar),
145 DEVMETHOD(bus_driver_added, pci_driver_added),
146 DEVMETHOD(bus_setup_intr, pci_setup_intr),
147 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
148
149 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag),
150 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
151 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
152 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
153 DEVMETHOD(bus_delete_resource, pci_delete_resource),
154 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
155 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
156 DEVMETHOD(bus_release_resource, pci_release_resource),
157 DEVMETHOD(bus_activate_resource, pci_activate_resource),
158 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
159 DEVMETHOD(bus_child_detached, pci_child_detached),
160 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
161 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
162 DEVMETHOD(bus_remap_intr, pci_remap_intr_method),
163
164 /* PCI interface */
165 DEVMETHOD(pci_read_config, pci_read_config_method),
166 DEVMETHOD(pci_write_config, pci_write_config_method),
167 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
168 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
169 DEVMETHOD(pci_enable_io, pci_enable_io_method),
170 DEVMETHOD(pci_disable_io, pci_disable_io_method),
171 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
172 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
173 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
174 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
175 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
176 DEVMETHOD(pci_find_cap, pci_find_cap_method),
177 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
178 DEVMETHOD(pci_find_htcap, pci_find_htcap_method),
179 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
180 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
181 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
182 DEVMETHOD(pci_release_msi, pci_release_msi_method),
183 DEVMETHOD(pci_msi_count, pci_msi_count_method),
184 DEVMETHOD(pci_msix_count, pci_msix_count_method),
185
186 DEVMETHOD_END
187};
188
189DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc));
190
191static devclass_t pci_devclass;
192DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL);
193MODULE_VERSION(pci, 1);
194
195static char *pci_vendordata;
196static size_t pci_vendordata_size;
197
198struct pci_quirk {
199 uint32_t devid; /* Vendor/device of the card */
200 int type;
201#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
202#define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
203#define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */
204#define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */
205#define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
206 int arg1;
207 int arg2;
208};
209
210static const struct pci_quirk pci_quirks[] = {
211 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
212 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
213 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
214 /* As does the Serverworks OSB4 (the SMBus mapping register) */
215 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
216
217 /*
218 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
219 * or the CMIC-SL (AKA ServerWorks GC_LE).
220 */
221 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
222 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
223
224 /*
225 * MSI doesn't work on earlier Intel chipsets including
226 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
227 */
228 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
229 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
230 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
231 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
232 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
233 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
234 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
235
236 /*
237 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
238 * bridge.
239 */
240 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
241
242 /*
243 * MSI-X allocation doesn't work properly for devices passed through
244 * by VMware up to at least ESXi 5.1.
245 */
246 { 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCI/PCI-X */
247 { 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCIe */
248
249 /*
250 * Some virtualization environments emulate an older chipset
251 * but support MSI just fine. QEMU uses the Intel 82440.
252 */
253 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 },
254
255 /*
256 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus
257 * controller depending on SoftPciRst register (PM_IO 0x55 [7]).
258 * It prevents us from attaching hpet(4) when the bit is unset.
259 * Note this quirk only affects SB600 revision A13 and earlier.
260 * For SB600 A21 and later, firmware must set the bit to hide it.
261 * For SB700 and later, it is unused and hardcoded to zero.
262 */
263 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 },
264
265 { 0 }
266};
267
268/* map register information */
269#define PCI_MAPMEM 0x01 /* memory map */
270#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
271#define PCI_MAPPORT 0x04 /* port map */
272
273struct devlist pci_devq;
274uint32_t pci_generation;
275uint32_t pci_numdevs = 0;
276static int pcie_chipset, pcix_chipset;
277
278/* sysctl vars */
279SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
280
281static int pci_enable_io_modes = 1;
282TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
283SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
284 &pci_enable_io_modes, 1,
285 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
286enable these bits correctly. We'd like to do this all the time, but there\n\
287are some peripherals that this causes problems with.");
288
289static int pci_do_realloc_bars = 0;
290TUNABLE_INT("hw.pci.realloc_bars", &pci_do_realloc_bars);
291SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RW,
292 &pci_do_realloc_bars, 0,
293 "Attempt to allocate a new range for any BARs whose original firmware-assigned ranges fail to allocate during the initial device scan.");
294
295static int pci_do_power_nodriver = 0;
296TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
297SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
298 &pci_do_power_nodriver, 0,
299 "Place a function into D3 state when no driver attaches to it. 0 means\n\
300disable. 1 means conservatively place devices into D3 state. 2 means\n\
301agressively place devices into D3 state. 3 means put absolutely everything\n\
302in D3 state.");
303
304int pci_do_power_resume = 1;
305TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
306SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
307 &pci_do_power_resume, 1,
308 "Transition from D3 -> D0 on resume.");
309
310int pci_do_power_suspend = 1;
311TUNABLE_INT("hw.pci.do_power_suspend", &pci_do_power_suspend);
312SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RW,
313 &pci_do_power_suspend, 1,
314 "Transition from D0 -> D3 on suspend.");
315
316static int pci_do_msi = 1;
317TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
318SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
319 "Enable support for MSI interrupts");
320
321static int pci_do_msix = 1;
322TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
323SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
324 "Enable support for MSI-X interrupts");
325
326static int pci_honor_msi_blacklist = 1;
327TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
328SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
329 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X");
330
331#if defined(__i386__) || defined(__amd64__)
332static int pci_usb_takeover = 1;
333#else
334static int pci_usb_takeover = 0;
335#endif
336TUNABLE_INT("hw.pci.usb_early_takeover", &pci_usb_takeover);
337SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN,
338 &pci_usb_takeover, 1, "Enable early takeover of USB controllers.\n\
339Disable this if you depend on BIOS emulation of USB devices, that is\n\
340you use USB devices (like keyboard or mouse) but do not load USB drivers");
341
342static int pci_clear_bars;
343TUNABLE_INT("hw.pci.clear_bars", &pci_clear_bars);
344SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0,
345 "Ignore firmware-assigned resources for BARs.");
346
|
| 347#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
348static int pci_clear_buses;
349TUNABLE_INT("hw.pci.clear_buses", &pci_clear_buses);
350SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0,
351 "Ignore firmware-assigned bus numbers.");
352#endif
353
|
340static int
341pci_has_quirk(uint32_t devid, int quirk)
342{
343 const struct pci_quirk *q;
344
345 for (q = &pci_quirks[0]; q->devid; q++) {
346 if (q->devid == devid && q->type == quirk)
347 return (1);
348 }
349 return (0);
350}
351
352/* Find a device_t by bus/slot/function in domain 0 */
353
354device_t
355pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
356{
357
358 return (pci_find_dbsf(0, bus, slot, func));
359}
360
361/* Find a device_t by domain/bus/slot/function */
362
363device_t
364pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
365{
366 struct pci_devinfo *dinfo;
367
368 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
369 if ((dinfo->cfg.domain == domain) &&
370 (dinfo->cfg.bus == bus) &&
371 (dinfo->cfg.slot == slot) &&
372 (dinfo->cfg.func == func)) {
373 return (dinfo->cfg.dev);
374 }
375 }
376
377 return (NULL);
378}
379
380/* Find a device_t by vendor/device ID */
381
382device_t
383pci_find_device(uint16_t vendor, uint16_t device)
384{
385 struct pci_devinfo *dinfo;
386
387 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
388 if ((dinfo->cfg.vendor == vendor) &&
389 (dinfo->cfg.device == device)) {
390 return (dinfo->cfg.dev);
391 }
392 }
393
394 return (NULL);
395}
396
397device_t
398pci_find_class(uint8_t class, uint8_t subclass)
399{
400 struct pci_devinfo *dinfo;
401
402 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
403 if (dinfo->cfg.baseclass == class &&
404 dinfo->cfg.subclass == subclass) {
405 return (dinfo->cfg.dev);
406 }
407 }
408
409 return (NULL);
410}
411
412static int
413pci_printf(pcicfgregs *cfg, const char *fmt, ...)
414{
415 va_list ap;
416 int retval;
417
418 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot,
419 cfg->func);
420 va_start(ap, fmt);
421 retval += vprintf(fmt, ap);
422 va_end(ap);
423 return (retval);
424}
425
426/* return base address of memory or port map */
427
428static pci_addr_t
429pci_mapbase(uint64_t mapreg)
430{
431
432 if (PCI_BAR_MEM(mapreg))
433 return (mapreg & PCIM_BAR_MEM_BASE);
434 else
435 return (mapreg & PCIM_BAR_IO_BASE);
436}
437
438/* return map type of memory or port map */
439
440static const char *
441pci_maptype(uint64_t mapreg)
442{
443
444 if (PCI_BAR_IO(mapreg))
445 return ("I/O Port");
446 if (mapreg & PCIM_BAR_MEM_PREFETCH)
447 return ("Prefetchable Memory");
448 return ("Memory");
449}
450
451/* return log2 of map size decoded for memory or port map */
452
453static int
454pci_mapsize(uint64_t testval)
455{
456 int ln2size;
457
458 testval = pci_mapbase(testval);
459 ln2size = 0;
460 if (testval != 0) {
461 while ((testval & 1) == 0)
462 {
463 ln2size++;
464 testval >>= 1;
465 }
466 }
467 return (ln2size);
468}
469
470/* return base address of device ROM */
471
472static pci_addr_t
473pci_rombase(uint64_t mapreg)
474{
475
476 return (mapreg & PCIM_BIOS_ADDR_MASK);
477}
478
479/* return log2 of map size decided for device ROM */
480
481static int
482pci_romsize(uint64_t testval)
483{
484 int ln2size;
485
486 testval = pci_rombase(testval);
487 ln2size = 0;
488 if (testval != 0) {
489 while ((testval & 1) == 0)
490 {
491 ln2size++;
492 testval >>= 1;
493 }
494 }
495 return (ln2size);
496}
497
498/* return log2 of address range supported by map register */
499
500static int
501pci_maprange(uint64_t mapreg)
502{
503 int ln2range = 0;
504
505 if (PCI_BAR_IO(mapreg))
506 ln2range = 32;
507 else
508 switch (mapreg & PCIM_BAR_MEM_TYPE) {
509 case PCIM_BAR_MEM_32:
510 ln2range = 32;
511 break;
512 case PCIM_BAR_MEM_1MB:
513 ln2range = 20;
514 break;
515 case PCIM_BAR_MEM_64:
516 ln2range = 64;
517 break;
518 }
519 return (ln2range);
520}
521
522/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
523
524static void
525pci_fixancient(pcicfgregs *cfg)
526{
527 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
528 return;
529
530 /* PCI to PCI bridges use header type 1 */
531 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
532 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
533}
534
535/* extract header type specific config data */
536
537static void
538pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
539{
540#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
541 switch (cfg->hdrtype & PCIM_HDRTYPE) {
542 case PCIM_HDRTYPE_NORMAL:
543 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
544 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
545 cfg->nummaps = PCI_MAXMAPS_0;
546 break;
547 case PCIM_HDRTYPE_BRIDGE:
548 cfg->nummaps = PCI_MAXMAPS_1;
549 break;
550 case PCIM_HDRTYPE_CARDBUS:
551 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
552 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
553 cfg->nummaps = PCI_MAXMAPS_2;
554 break;
555 }
556#undef REG
557}
558
559/* read configuration header into pcicfgregs structure */
560struct pci_devinfo *
561pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
562{
563#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
564 pcicfgregs *cfg = NULL;
565 struct pci_devinfo *devlist_entry;
566 struct devlist *devlist_head;
567
568 devlist_head = &pci_devq;
569
570 devlist_entry = NULL;
571
572 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) {
573 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
574 if (devlist_entry == NULL)
575 return (NULL);
576
577 cfg = &devlist_entry->cfg;
578
579 cfg->domain = d;
580 cfg->bus = b;
581 cfg->slot = s;
582 cfg->func = f;
583 cfg->vendor = REG(PCIR_VENDOR, 2);
584 cfg->device = REG(PCIR_DEVICE, 2);
585 cfg->cmdreg = REG(PCIR_COMMAND, 2);
586 cfg->statreg = REG(PCIR_STATUS, 2);
587 cfg->baseclass = REG(PCIR_CLASS, 1);
588 cfg->subclass = REG(PCIR_SUBCLASS, 1);
589 cfg->progif = REG(PCIR_PROGIF, 1);
590 cfg->revid = REG(PCIR_REVID, 1);
591 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
592 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
593 cfg->lattimer = REG(PCIR_LATTIMER, 1);
594 cfg->intpin = REG(PCIR_INTPIN, 1);
595 cfg->intline = REG(PCIR_INTLINE, 1);
596
597 cfg->mingnt = REG(PCIR_MINGNT, 1);
598 cfg->maxlat = REG(PCIR_MAXLAT, 1);
599
600 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
601 cfg->hdrtype &= ~PCIM_MFDEV;
602 STAILQ_INIT(&cfg->maps);
603
604 pci_fixancient(cfg);
605 pci_hdrtypedata(pcib, b, s, f, cfg);
606
607 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
608 pci_read_cap(pcib, cfg);
609
610 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
611
612 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
613 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
614 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
615 devlist_entry->conf.pc_sel.pc_func = cfg->func;
616 devlist_entry->conf.pc_hdr = cfg->hdrtype;
617
618 devlist_entry->conf.pc_subvendor = cfg->subvendor;
619 devlist_entry->conf.pc_subdevice = cfg->subdevice;
620 devlist_entry->conf.pc_vendor = cfg->vendor;
621 devlist_entry->conf.pc_device = cfg->device;
622
623 devlist_entry->conf.pc_class = cfg->baseclass;
624 devlist_entry->conf.pc_subclass = cfg->subclass;
625 devlist_entry->conf.pc_progif = cfg->progif;
626 devlist_entry->conf.pc_revid = cfg->revid;
627
628 pci_numdevs++;
629 pci_generation++;
630 }
631 return (devlist_entry);
632#undef REG
633}
634
635static void
636pci_read_cap(device_t pcib, pcicfgregs *cfg)
637{
638#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
639#define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
640#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
641 uint64_t addr;
642#endif
643 uint32_t val;
644 int ptr, nextptr, ptrptr;
645
646 switch (cfg->hdrtype & PCIM_HDRTYPE) {
647 case PCIM_HDRTYPE_NORMAL:
648 case PCIM_HDRTYPE_BRIDGE:
649 ptrptr = PCIR_CAP_PTR;
650 break;
651 case PCIM_HDRTYPE_CARDBUS:
652 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
653 break;
654 default:
655 return; /* no extended capabilities support */
656 }
657 nextptr = REG(ptrptr, 1); /* sanity check? */
658
659 /*
660 * Read capability entries.
661 */
662 while (nextptr != 0) {
663 /* Sanity check */
664 if (nextptr > 255) {
665 printf("illegal PCI extended capability offset %d\n",
666 nextptr);
667 return;
668 }
669 /* Find the next entry */
670 ptr = nextptr;
671 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
672
673 /* Process this entry */
674 switch (REG(ptr + PCICAP_ID, 1)) {
675 case PCIY_PMG: /* PCI power management */
676 if (cfg->pp.pp_cap == 0) {
677 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
678 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
679 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE;
680 if ((nextptr - ptr) > PCIR_POWER_DATA)
681 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
682 }
683 break;
684 case PCIY_HT: /* HyperTransport */
685 /* Determine HT-specific capability type. */
686 val = REG(ptr + PCIR_HT_COMMAND, 2);
687
688 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
689 cfg->ht.ht_slave = ptr;
690
691#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
692 switch (val & PCIM_HTCMD_CAP_MASK) {
693 case PCIM_HTCAP_MSI_MAPPING:
694 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
695 /* Sanity check the mapping window. */
696 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
697 4);
698 addr <<= 32;
699 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
700 4);
701 if (addr != MSI_INTEL_ADDR_BASE)
702 device_printf(pcib,
703 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
704 cfg->domain, cfg->bus,
705 cfg->slot, cfg->func,
706 (long long)addr);
707 } else
708 addr = MSI_INTEL_ADDR_BASE;
709
710 cfg->ht.ht_msimap = ptr;
711 cfg->ht.ht_msictrl = val;
712 cfg->ht.ht_msiaddr = addr;
713 break;
714 }
715#endif
716 break;
717 case PCIY_MSI: /* PCI MSI */
718 cfg->msi.msi_location = ptr;
719 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
720 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
721 PCIM_MSICTRL_MMC_MASK)>>1);
722 break;
723 case PCIY_MSIX: /* PCI MSI-X */
724 cfg->msix.msix_location = ptr;
725 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
726 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
727 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
728 val = REG(ptr + PCIR_MSIX_TABLE, 4);
729 cfg->msix.msix_table_bar = PCIR_BAR(val &
730 PCIM_MSIX_BIR_MASK);
731 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
732 val = REG(ptr + PCIR_MSIX_PBA, 4);
733 cfg->msix.msix_pba_bar = PCIR_BAR(val &
734 PCIM_MSIX_BIR_MASK);
735 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
736 break;
737 case PCIY_VPD: /* PCI Vital Product Data */
738 cfg->vpd.vpd_reg = ptr;
739 break;
740 case PCIY_SUBVENDOR:
741 /* Should always be true. */
742 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
743 PCIM_HDRTYPE_BRIDGE) {
744 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
745 cfg->subvendor = val & 0xffff;
746 cfg->subdevice = val >> 16;
747 }
748 break;
749 case PCIY_PCIX: /* PCI-X */
750 /*
751 * Assume we have a PCI-X chipset if we have
752 * at least one PCI-PCI bridge with a PCI-X
753 * capability. Note that some systems with
754 * PCI-express or HT chipsets might match on
755 * this check as well.
756 */
757 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
758 PCIM_HDRTYPE_BRIDGE)
759 pcix_chipset = 1;
760 cfg->pcix.pcix_location = ptr;
761 break;
762 case PCIY_EXPRESS: /* PCI-express */
763 /*
764 * Assume we have a PCI-express chipset if we have
765 * at least one PCI-express device.
766 */
767 pcie_chipset = 1;
768 cfg->pcie.pcie_location = ptr;
769 val = REG(ptr + PCIER_FLAGS, 2);
770 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE;
771 break;
772 default:
773 break;
774 }
775 }
776
777#if defined(__powerpc__)
778 /*
779 * Enable the MSI mapping window for all HyperTransport
780 * slaves. PCI-PCI bridges have their windows enabled via
781 * PCIB_MAP_MSI().
782 */
783 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
784 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
785 device_printf(pcib,
786 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
787 cfg->domain, cfg->bus, cfg->slot, cfg->func);
788 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
789 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
790 2);
791 }
792#endif
793/* REG and WREG use carry through to next functions */
794}
795
796/*
797 * PCI Vital Product Data
798 */
799
800#define PCI_VPD_TIMEOUT 1000000
801
802static int
803pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
804{
805 int count = PCI_VPD_TIMEOUT;
806
807 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
808
809 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
810
811 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
812 if (--count < 0)
813 return (ENXIO);
814 DELAY(1); /* limit looping */
815 }
816 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
817
818 return (0);
819}
820
821#if 0
822static int
823pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
824{
825 int count = PCI_VPD_TIMEOUT;
826
827 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
828
829 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
830 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
831 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
832 if (--count < 0)
833 return (ENXIO);
834 DELAY(1); /* limit looping */
835 }
836
837 return (0);
838}
839#endif
840
841#undef PCI_VPD_TIMEOUT
842
843struct vpd_readstate {
844 device_t pcib;
845 pcicfgregs *cfg;
846 uint32_t val;
847 int bytesinval;
848 int off;
849 uint8_t cksum;
850};
851
852static int
853vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
854{
855 uint32_t reg;
856 uint8_t byte;
857
858 if (vrs->bytesinval == 0) {
859 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
860 return (ENXIO);
861 vrs->val = le32toh(reg);
862 vrs->off += 4;
863 byte = vrs->val & 0xff;
864 vrs->bytesinval = 3;
865 } else {
866 vrs->val = vrs->val >> 8;
867 byte = vrs->val & 0xff;
868 vrs->bytesinval--;
869 }
870
871 vrs->cksum += byte;
872 *data = byte;
873 return (0);
874}
875
876static void
877pci_read_vpd(device_t pcib, pcicfgregs *cfg)
878{
879 struct vpd_readstate vrs;
880 int state;
881 int name;
882 int remain;
883 int i;
884 int alloc, off; /* alloc/off for RO/W arrays */
885 int cksumvalid;
886 int dflen;
887 uint8_t byte;
888 uint8_t byte2;
889
890 /* init vpd reader */
891 vrs.bytesinval = 0;
892 vrs.off = 0;
893 vrs.pcib = pcib;
894 vrs.cfg = cfg;
895 vrs.cksum = 0;
896
897 state = 0;
898 name = remain = i = 0; /* shut up stupid gcc */
899 alloc = off = 0; /* shut up stupid gcc */
900 dflen = 0; /* shut up stupid gcc */
901 cksumvalid = -1;
902 while (state >= 0) {
903 if (vpd_nextbyte(&vrs, &byte)) {
904 state = -2;
905 break;
906 }
907#if 0
908 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
909 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
910 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
911#endif
912 switch (state) {
913 case 0: /* item name */
914 if (byte & 0x80) {
915 if (vpd_nextbyte(&vrs, &byte2)) {
916 state = -2;
917 break;
918 }
919 remain = byte2;
920 if (vpd_nextbyte(&vrs, &byte2)) {
921 state = -2;
922 break;
923 }
924 remain |= byte2 << 8;
925 if (remain > (0x7f*4 - vrs.off)) {
926 state = -1;
927 pci_printf(cfg,
928 "invalid VPD data, remain %#x\n",
929 remain);
930 }
931 name = byte & 0x7f;
932 } else {
933 remain = byte & 0x7;
934 name = (byte >> 3) & 0xf;
935 }
936 switch (name) {
937 case 0x2: /* String */
938 cfg->vpd.vpd_ident = malloc(remain + 1,
939 M_DEVBUF, M_WAITOK);
940 i = 0;
941 state = 1;
942 break;
943 case 0xf: /* End */
944 state = -1;
945 break;
946 case 0x10: /* VPD-R */
947 alloc = 8;
948 off = 0;
949 cfg->vpd.vpd_ros = malloc(alloc *
950 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
951 M_WAITOK | M_ZERO);
952 state = 2;
953 break;
954 case 0x11: /* VPD-W */
955 alloc = 8;
956 off = 0;
957 cfg->vpd.vpd_w = malloc(alloc *
958 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
959 M_WAITOK | M_ZERO);
960 state = 5;
961 break;
962 default: /* Invalid data, abort */
963 state = -1;
964 break;
965 }
966 break;
967
968 case 1: /* Identifier String */
969 cfg->vpd.vpd_ident[i++] = byte;
970 remain--;
971 if (remain == 0) {
972 cfg->vpd.vpd_ident[i] = '\0';
973 state = 0;
974 }
975 break;
976
977 case 2: /* VPD-R Keyword Header */
978 if (off == alloc) {
979 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
980 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
981 M_DEVBUF, M_WAITOK | M_ZERO);
982 }
983 cfg->vpd.vpd_ros[off].keyword[0] = byte;
984 if (vpd_nextbyte(&vrs, &byte2)) {
985 state = -2;
986 break;
987 }
988 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
989 if (vpd_nextbyte(&vrs, &byte2)) {
990 state = -2;
991 break;
992 }
993 cfg->vpd.vpd_ros[off].len = dflen = byte2;
994 if (dflen == 0 &&
995 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
996 2) == 0) {
997 /*
998 * if this happens, we can't trust the rest
999 * of the VPD.
1000 */
1001 pci_printf(cfg, "bad keyword length: %d\n",
1002 dflen);
1003 cksumvalid = 0;
1004 state = -1;
1005 break;
1006 } else if (dflen == 0) {
1007 cfg->vpd.vpd_ros[off].value = malloc(1 *
1008 sizeof(*cfg->vpd.vpd_ros[off].value),
1009 M_DEVBUF, M_WAITOK);
1010 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1011 } else
1012 cfg->vpd.vpd_ros[off].value = malloc(
1013 (dflen + 1) *
1014 sizeof(*cfg->vpd.vpd_ros[off].value),
1015 M_DEVBUF, M_WAITOK);
1016 remain -= 3;
1017 i = 0;
1018 /* keep in sync w/ state 3's transistions */
1019 if (dflen == 0 && remain == 0)
1020 state = 0;
1021 else if (dflen == 0)
1022 state = 2;
1023 else
1024 state = 3;
1025 break;
1026
1027 case 3: /* VPD-R Keyword Value */
1028 cfg->vpd.vpd_ros[off].value[i++] = byte;
1029 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1030 "RV", 2) == 0 && cksumvalid == -1) {
1031 if (vrs.cksum == 0)
1032 cksumvalid = 1;
1033 else {
1034 if (bootverbose)
1035 pci_printf(cfg,
1036 "bad VPD cksum, remain %hhu\n",
1037 vrs.cksum);
1038 cksumvalid = 0;
1039 state = -1;
1040 break;
1041 }
1042 }
1043 dflen--;
1044 remain--;
1045 /* keep in sync w/ state 2's transistions */
1046 if (dflen == 0)
1047 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1048 if (dflen == 0 && remain == 0) {
1049 cfg->vpd.vpd_rocnt = off;
1050 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
1051 off * sizeof(*cfg->vpd.vpd_ros),
1052 M_DEVBUF, M_WAITOK | M_ZERO);
1053 state = 0;
1054 } else if (dflen == 0)
1055 state = 2;
1056 break;
1057
1058 case 4:
1059 remain--;
1060 if (remain == 0)
1061 state = 0;
1062 break;
1063
1064 case 5: /* VPD-W Keyword Header */
1065 if (off == alloc) {
1066 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1067 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1068 M_DEVBUF, M_WAITOK | M_ZERO);
1069 }
1070 cfg->vpd.vpd_w[off].keyword[0] = byte;
1071 if (vpd_nextbyte(&vrs, &byte2)) {
1072 state = -2;
1073 break;
1074 }
1075 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1076 if (vpd_nextbyte(&vrs, &byte2)) {
1077 state = -2;
1078 break;
1079 }
1080 cfg->vpd.vpd_w[off].len = dflen = byte2;
1081 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1082 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
1083 sizeof(*cfg->vpd.vpd_w[off].value),
1084 M_DEVBUF, M_WAITOK);
1085 remain -= 3;
1086 i = 0;
1087 /* keep in sync w/ state 6's transistions */
1088 if (dflen == 0 && remain == 0)
1089 state = 0;
1090 else if (dflen == 0)
1091 state = 5;
1092 else
1093 state = 6;
1094 break;
1095
1096 case 6: /* VPD-W Keyword Value */
1097 cfg->vpd.vpd_w[off].value[i++] = byte;
1098 dflen--;
1099 remain--;
1100 /* keep in sync w/ state 5's transistions */
1101 if (dflen == 0)
1102 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1103 if (dflen == 0 && remain == 0) {
1104 cfg->vpd.vpd_wcnt = off;
1105 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1106 off * sizeof(*cfg->vpd.vpd_w),
1107 M_DEVBUF, M_WAITOK | M_ZERO);
1108 state = 0;
1109 } else if (dflen == 0)
1110 state = 5;
1111 break;
1112
1113 default:
1114 pci_printf(cfg, "invalid state: %d\n", state);
1115 state = -1;
1116 break;
1117 }
1118 }
1119
1120 if (cksumvalid == 0 || state < -1) {
1121 /* read-only data bad, clean up */
1122 if (cfg->vpd.vpd_ros != NULL) {
1123 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1124 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1125 free(cfg->vpd.vpd_ros, M_DEVBUF);
1126 cfg->vpd.vpd_ros = NULL;
1127 }
1128 }
1129 if (state < -1) {
1130 /* I/O error, clean up */
1131 pci_printf(cfg, "failed to read VPD data.\n");
1132 if (cfg->vpd.vpd_ident != NULL) {
1133 free(cfg->vpd.vpd_ident, M_DEVBUF);
1134 cfg->vpd.vpd_ident = NULL;
1135 }
1136 if (cfg->vpd.vpd_w != NULL) {
1137 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1138 free(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1139 free(cfg->vpd.vpd_w, M_DEVBUF);
1140 cfg->vpd.vpd_w = NULL;
1141 }
1142 }
1143 cfg->vpd.vpd_cached = 1;
1144#undef REG
1145#undef WREG
1146}
1147
1148int
1149pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1150{
1151 struct pci_devinfo *dinfo = device_get_ivars(child);
1152 pcicfgregs *cfg = &dinfo->cfg;
1153
1154 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1155 pci_read_vpd(device_get_parent(dev), cfg);
1156
1157 *identptr = cfg->vpd.vpd_ident;
1158
1159 if (*identptr == NULL)
1160 return (ENXIO);
1161
1162 return (0);
1163}
1164
1165int
1166pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1167 const char **vptr)
1168{
1169 struct pci_devinfo *dinfo = device_get_ivars(child);
1170 pcicfgregs *cfg = &dinfo->cfg;
1171 int i;
1172
1173 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1174 pci_read_vpd(device_get_parent(dev), cfg);
1175
1176 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1177 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1178 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1179 *vptr = cfg->vpd.vpd_ros[i].value;
1180 return (0);
1181 }
1182
1183 *vptr = NULL;
1184 return (ENXIO);
1185}
1186
1187struct pcicfg_vpd *
1188pci_fetch_vpd_list(device_t dev)
1189{
1190 struct pci_devinfo *dinfo = device_get_ivars(dev);
1191 pcicfgregs *cfg = &dinfo->cfg;
1192
1193 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1194 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg);
1195 return (&cfg->vpd);
1196}
1197
1198/*
1199 * Find the requested HyperTransport capability and return the offset
1200 * in configuration space via the pointer provided. The function
1201 * returns 0 on success and an error code otherwise.
1202 */
1203int
1204pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg)
1205{
1206 int ptr, error;
1207 uint16_t val;
1208
1209 error = pci_find_cap(child, PCIY_HT, &ptr);
1210 if (error)
1211 return (error);
1212
1213 /*
1214 * Traverse the capabilities list checking each HT capability
1215 * to see if it matches the requested HT capability.
1216 */
1217 while (ptr != 0) {
1218 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2);
1219 if (capability == PCIM_HTCAP_SLAVE ||
1220 capability == PCIM_HTCAP_HOST)
1221 val &= 0xe000;
1222 else
1223 val &= PCIM_HTCMD_CAP_MASK;
1224 if (val == capability) {
1225 if (capreg != NULL)
1226 *capreg = ptr;
1227 return (0);
1228 }
1229
1230 /* Skip to the next HT capability. */
1231 while (ptr != 0) {
1232 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1233 if (pci_read_config(child, ptr + PCICAP_ID, 1) ==
1234 PCIY_HT)
1235 break;
1236 }
1237 }
1238 return (ENOENT);
1239}
1240
1241/*
1242 * Find the requested capability and return the offset in
1243 * configuration space via the pointer provided. The function returns
1244 * 0 on success and an error code otherwise.
1245 */
1246int
1247pci_find_cap_method(device_t dev, device_t child, int capability,
1248 int *capreg)
1249{
1250 struct pci_devinfo *dinfo = device_get_ivars(child);
1251 pcicfgregs *cfg = &dinfo->cfg;
1252 u_int32_t status;
1253 u_int8_t ptr;
1254
1255 /*
1256 * Check the CAP_LIST bit of the PCI status register first.
1257 */
1258 status = pci_read_config(child, PCIR_STATUS, 2);
1259 if (!(status & PCIM_STATUS_CAPPRESENT))
1260 return (ENXIO);
1261
1262 /*
1263 * Determine the start pointer of the capabilities list.
1264 */
1265 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1266 case PCIM_HDRTYPE_NORMAL:
1267 case PCIM_HDRTYPE_BRIDGE:
1268 ptr = PCIR_CAP_PTR;
1269 break;
1270 case PCIM_HDRTYPE_CARDBUS:
1271 ptr = PCIR_CAP_PTR_2;
1272 break;
1273 default:
1274 /* XXX: panic? */
1275 return (ENXIO); /* no extended capabilities support */
1276 }
1277 ptr = pci_read_config(child, ptr, 1);
1278
1279 /*
1280 * Traverse the capabilities list.
1281 */
1282 while (ptr != 0) {
1283 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1284 if (capreg != NULL)
1285 *capreg = ptr;
1286 return (0);
1287 }
1288 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1289 }
1290
1291 return (ENOENT);
1292}
1293
1294/*
1295 * Find the requested extended capability and return the offset in
1296 * configuration space via the pointer provided. The function returns
1297 * 0 on success and an error code otherwise.
1298 */
1299int
1300pci_find_extcap_method(device_t dev, device_t child, int capability,
1301 int *capreg)
1302{
1303 struct pci_devinfo *dinfo = device_get_ivars(child);
1304 pcicfgregs *cfg = &dinfo->cfg;
1305 uint32_t ecap;
1306 uint16_t ptr;
1307
1308 /* Only supported for PCI-express devices. */
1309 if (cfg->pcie.pcie_location == 0)
1310 return (ENXIO);
1311
1312 ptr = PCIR_EXTCAP;
1313 ecap = pci_read_config(child, ptr, 4);
1314 if (ecap == 0xffffffff || ecap == 0)
1315 return (ENOENT);
1316 for (;;) {
1317 if (PCI_EXTCAP_ID(ecap) == capability) {
1318 if (capreg != NULL)
1319 *capreg = ptr;
1320 return (0);
1321 }
1322 ptr = PCI_EXTCAP_NEXTPTR(ecap);
1323 if (ptr == 0)
1324 break;
1325 ecap = pci_read_config(child, ptr, 4);
1326 }
1327
1328 return (ENOENT);
1329}
1330
1331/*
1332 * Support for MSI-X message interrupts.
1333 */
1334void
1335pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1336{
1337 struct pci_devinfo *dinfo = device_get_ivars(dev);
1338 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1339 uint32_t offset;
1340
1341 KASSERT(msix->msix_table_len > index, ("bogus index"));
1342 offset = msix->msix_table_offset + index * 16;
1343 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1344 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1345 bus_write_4(msix->msix_table_res, offset + 8, data);
1346
1347 /* Enable MSI -> HT mapping. */
1348 pci_ht_map_msi(dev, address);
1349}
1350
1351void
1352pci_mask_msix(device_t dev, u_int index)
1353{
1354 struct pci_devinfo *dinfo = device_get_ivars(dev);
1355 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1356 uint32_t offset, val;
1357
1358 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1359 offset = msix->msix_table_offset + index * 16 + 12;
1360 val = bus_read_4(msix->msix_table_res, offset);
1361 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1362 val |= PCIM_MSIX_VCTRL_MASK;
1363 bus_write_4(msix->msix_table_res, offset, val);
1364 }
1365}
1366
1367void
1368pci_unmask_msix(device_t dev, u_int index)
1369{
1370 struct pci_devinfo *dinfo = device_get_ivars(dev);
1371 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1372 uint32_t offset, val;
1373
1374 KASSERT(msix->msix_table_len > index, ("bogus index"));
1375 offset = msix->msix_table_offset + index * 16 + 12;
1376 val = bus_read_4(msix->msix_table_res, offset);
1377 if (val & PCIM_MSIX_VCTRL_MASK) {
1378 val &= ~PCIM_MSIX_VCTRL_MASK;
1379 bus_write_4(msix->msix_table_res, offset, val);
1380 }
1381}
1382
1383int
1384pci_pending_msix(device_t dev, u_int index)
1385{
1386 struct pci_devinfo *dinfo = device_get_ivars(dev);
1387 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1388 uint32_t offset, bit;
1389
1390 KASSERT(msix->msix_table_len > index, ("bogus index"));
1391 offset = msix->msix_pba_offset + (index / 32) * 4;
1392 bit = 1 << index % 32;
1393 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1394}
1395
1396/*
1397 * Restore MSI-X registers and table during resume. If MSI-X is
1398 * enabled then walk the virtual table to restore the actual MSI-X
1399 * table.
1400 */
1401static void
1402pci_resume_msix(device_t dev)
1403{
1404 struct pci_devinfo *dinfo = device_get_ivars(dev);
1405 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1406 struct msix_table_entry *mte;
1407 struct msix_vector *mv;
1408 int i;
1409
1410 if (msix->msix_alloc > 0) {
1411 /* First, mask all vectors. */
1412 for (i = 0; i < msix->msix_msgnum; i++)
1413 pci_mask_msix(dev, i);
1414
1415 /* Second, program any messages with at least one handler. */
1416 for (i = 0; i < msix->msix_table_len; i++) {
1417 mte = &msix->msix_table[i];
1418 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1419 continue;
1420 mv = &msix->msix_vectors[mte->mte_vector - 1];
1421 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1422 pci_unmask_msix(dev, i);
1423 }
1424 }
1425 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1426 msix->msix_ctrl, 2);
1427}
1428
1429/*
1430 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1431 * returned in *count. After this function returns, each message will be
1432 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1433 */
1434int
1435pci_alloc_msix_method(device_t dev, device_t child, int *count)
1436{
1437 struct pci_devinfo *dinfo = device_get_ivars(child);
1438 pcicfgregs *cfg = &dinfo->cfg;
1439 struct resource_list_entry *rle;
1440 int actual, error, i, irq, max;
1441
1442 /* Don't let count == 0 get us into trouble. */
1443 if (*count == 0)
1444 return (EINVAL);
1445
1446 /* If rid 0 is allocated, then fail. */
1447 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1448 if (rle != NULL && rle->res != NULL)
1449 return (ENXIO);
1450
1451 /* Already have allocated messages? */
1452 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1453 return (ENXIO);
1454
1455 /* If MSI-X is blacklisted for this system, fail. */
1456 if (pci_msix_blacklisted())
1457 return (ENXIO);
1458
1459 /* MSI-X capability present? */
1460 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1461 return (ENODEV);
1462
1463 /* Make sure the appropriate BARs are mapped. */
1464 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1465 cfg->msix.msix_table_bar);
1466 if (rle == NULL || rle->res == NULL ||
1467 !(rman_get_flags(rle->res) & RF_ACTIVE))
1468 return (ENXIO);
1469 cfg->msix.msix_table_res = rle->res;
1470 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1471 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1472 cfg->msix.msix_pba_bar);
1473 if (rle == NULL || rle->res == NULL ||
1474 !(rman_get_flags(rle->res) & RF_ACTIVE))
1475 return (ENXIO);
1476 }
1477 cfg->msix.msix_pba_res = rle->res;
1478
1479 if (bootverbose)
1480 device_printf(child,
1481 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1482 *count, cfg->msix.msix_msgnum);
1483 max = min(*count, cfg->msix.msix_msgnum);
1484 for (i = 0; i < max; i++) {
1485 /* Allocate a message. */
1486 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1487 if (error) {
1488 if (i == 0)
1489 return (error);
1490 break;
1491 }
1492 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1493 irq, 1);
1494 }
1495 actual = i;
1496
1497 if (bootverbose) {
1498 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1499 if (actual == 1)
1500 device_printf(child, "using IRQ %lu for MSI-X\n",
1501 rle->start);
1502 else {
1503 int run;
1504
1505 /*
1506 * Be fancy and try to print contiguous runs of
1507 * IRQ values as ranges. 'irq' is the previous IRQ.
1508 * 'run' is true if we are in a range.
1509 */
1510 device_printf(child, "using IRQs %lu", rle->start);
1511 irq = rle->start;
1512 run = 0;
1513 for (i = 1; i < actual; i++) {
1514 rle = resource_list_find(&dinfo->resources,
1515 SYS_RES_IRQ, i + 1);
1516
1517 /* Still in a run? */
1518 if (rle->start == irq + 1) {
1519 run = 1;
1520 irq++;
1521 continue;
1522 }
1523
1524 /* Finish previous range. */
1525 if (run) {
1526 printf("-%d", irq);
1527 run = 0;
1528 }
1529
1530 /* Start new range. */
1531 printf(",%lu", rle->start);
1532 irq = rle->start;
1533 }
1534
1535 /* Unfinished range? */
1536 if (run)
1537 printf("-%d", irq);
1538 printf(" for MSI-X\n");
1539 }
1540 }
1541
1542 /* Mask all vectors. */
1543 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1544 pci_mask_msix(child, i);
1545
1546 /* Allocate and initialize vector data and virtual table. */
1547 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
1548 M_DEVBUF, M_WAITOK | M_ZERO);
1549 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
1550 M_DEVBUF, M_WAITOK | M_ZERO);
1551 for (i = 0; i < actual; i++) {
1552 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1553 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1554 cfg->msix.msix_table[i].mte_vector = i + 1;
1555 }
1556
1557 /* Update control register to enable MSI-X. */
1558 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1559 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1560 cfg->msix.msix_ctrl, 2);
1561
1562 /* Update counts of alloc'd messages. */
1563 cfg->msix.msix_alloc = actual;
1564 cfg->msix.msix_table_len = actual;
1565 *count = actual;
1566 return (0);
1567}
1568
1569/*
1570 * By default, pci_alloc_msix() will assign the allocated IRQ
1571 * resources consecutively to the first N messages in the MSI-X table.
1572 * However, device drivers may want to use different layouts if they
1573 * either receive fewer messages than they asked for, or they wish to
1574 * populate the MSI-X table sparsely. This method allows the driver
1575 * to specify what layout it wants. It must be called after a
1576 * successful pci_alloc_msix() but before any of the associated
1577 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1578 *
1579 * The 'vectors' array contains 'count' message vectors. The array
1580 * maps directly to the MSI-X table in that index 0 in the array
1581 * specifies the vector for the first message in the MSI-X table, etc.
1582 * The vector value in each array index can either be 0 to indicate
1583 * that no vector should be assigned to a message slot, or it can be a
1584 * number from 1 to N (where N is the count returned from a
1585 * succcessful call to pci_alloc_msix()) to indicate which message
1586 * vector (IRQ) to be used for the corresponding message.
1587 *
1588 * On successful return, each message with a non-zero vector will have
1589 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1590 * 1. Additionally, if any of the IRQs allocated via the previous
1591 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1592 * will be freed back to the system automatically.
1593 *
1594 * For example, suppose a driver has a MSI-X table with 6 messages and
1595 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1596 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1597 * C. After the call to pci_alloc_msix(), the device will be setup to
1598 * have an MSI-X table of ABC--- (where - means no vector assigned).
1599 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 },
1600 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1601 * be freed back to the system. This device will also have valid
1602 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1603 *
1604 * In any case, the SYS_RES_IRQ rid X will always map to the message
1605 * at MSI-X table index X - 1 and will only be valid if a vector is
1606 * assigned to that table entry.
1607 */
1608int
1609pci_remap_msix_method(device_t dev, device_t child, int count,
1610 const u_int *vectors)
1611{
1612 struct pci_devinfo *dinfo = device_get_ivars(child);
1613 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1614 struct resource_list_entry *rle;
1615 int i, irq, j, *used;
1616
1617 /*
1618 * Have to have at least one message in the table but the
1619 * table can't be bigger than the actual MSI-X table in the
1620 * device.
1621 */
1622 if (count == 0 || count > msix->msix_msgnum)
1623 return (EINVAL);
1624
1625 /* Sanity check the vectors. */
1626 for (i = 0; i < count; i++)
1627 if (vectors[i] > msix->msix_alloc)
1628 return (EINVAL);
1629
1630 /*
1631 * Make sure there aren't any holes in the vectors to be used.
1632 * It's a big pain to support it, and it doesn't really make
1633 * sense anyway. Also, at least one vector must be used.
1634 */
1635 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1636 M_ZERO);
1637 for (i = 0; i < count; i++)
1638 if (vectors[i] != 0)
1639 used[vectors[i] - 1] = 1;
1640 for (i = 0; i < msix->msix_alloc - 1; i++)
1641 if (used[i] == 0 && used[i + 1] == 1) {
1642 free(used, M_DEVBUF);
1643 return (EINVAL);
1644 }
1645 if (used[0] != 1) {
1646 free(used, M_DEVBUF);
1647 return (EINVAL);
1648 }
1649
1650 /* Make sure none of the resources are allocated. */
1651 for (i = 0; i < msix->msix_table_len; i++) {
1652 if (msix->msix_table[i].mte_vector == 0)
1653 continue;
1654 if (msix->msix_table[i].mte_handlers > 0)
1655 return (EBUSY);
1656 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1657 KASSERT(rle != NULL, ("missing resource"));
1658 if (rle->res != NULL)
1659 return (EBUSY);
1660 }
1661
1662 /* Free the existing resource list entries. */
1663 for (i = 0; i < msix->msix_table_len; i++) {
1664 if (msix->msix_table[i].mte_vector == 0)
1665 continue;
1666 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1667 }
1668
1669 /*
1670 * Build the new virtual table keeping track of which vectors are
1671 * used.
1672 */
1673 free(msix->msix_table, M_DEVBUF);
1674 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count,
1675 M_DEVBUF, M_WAITOK | M_ZERO);
1676 for (i = 0; i < count; i++)
1677 msix->msix_table[i].mte_vector = vectors[i];
1678 msix->msix_table_len = count;
1679
1680 /* Free any unused IRQs and resize the vectors array if necessary. */
1681 j = msix->msix_alloc - 1;
1682 if (used[j] == 0) {
1683 struct msix_vector *vec;
1684
1685 while (used[j] == 0) {
1686 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1687 msix->msix_vectors[j].mv_irq);
1688 j--;
1689 }
1690 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1691 M_WAITOK);
1692 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1693 (j + 1));
1694 free(msix->msix_vectors, M_DEVBUF);
1695 msix->msix_vectors = vec;
1696 msix->msix_alloc = j + 1;
1697 }
1698 free(used, M_DEVBUF);
1699
1700 /* Map the IRQs onto the rids. */
1701 for (i = 0; i < count; i++) {
1702 if (vectors[i] == 0)
1703 continue;
1704 irq = msix->msix_vectors[vectors[i]].mv_irq;
1705 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1706 irq, 1);
1707 }
1708
1709 if (bootverbose) {
1710 device_printf(child, "Remapped MSI-X IRQs as: ");
1711 for (i = 0; i < count; i++) {
1712 if (i != 0)
1713 printf(", ");
1714 if (vectors[i] == 0)
1715 printf("---");
1716 else
1717 printf("%d",
1718 msix->msix_vectors[vectors[i]].mv_irq);
1719 }
1720 printf("\n");
1721 }
1722
1723 return (0);
1724}
1725
1726static int
1727pci_release_msix(device_t dev, device_t child)
1728{
1729 struct pci_devinfo *dinfo = device_get_ivars(child);
1730 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1731 struct resource_list_entry *rle;
1732 int i;
1733
1734 /* Do we have any messages to release? */
1735 if (msix->msix_alloc == 0)
1736 return (ENODEV);
1737
1738 /* Make sure none of the resources are allocated. */
1739 for (i = 0; i < msix->msix_table_len; i++) {
1740 if (msix->msix_table[i].mte_vector == 0)
1741 continue;
1742 if (msix->msix_table[i].mte_handlers > 0)
1743 return (EBUSY);
1744 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1745 KASSERT(rle != NULL, ("missing resource"));
1746 if (rle->res != NULL)
1747 return (EBUSY);
1748 }
1749
1750 /* Update control register to disable MSI-X. */
1751 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1752 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1753 msix->msix_ctrl, 2);
1754
1755 /* Free the resource list entries. */
1756 for (i = 0; i < msix->msix_table_len; i++) {
1757 if (msix->msix_table[i].mte_vector == 0)
1758 continue;
1759 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1760 }
1761 free(msix->msix_table, M_DEVBUF);
1762 msix->msix_table_len = 0;
1763
1764 /* Release the IRQs. */
1765 for (i = 0; i < msix->msix_alloc; i++)
1766 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1767 msix->msix_vectors[i].mv_irq);
1768 free(msix->msix_vectors, M_DEVBUF);
1769 msix->msix_alloc = 0;
1770 return (0);
1771}
1772
1773/*
1774 * Return the max supported MSI-X messages this device supports.
1775 * Basically, assuming the MD code can alloc messages, this function
1776 * should return the maximum value that pci_alloc_msix() can return.
1777 * Thus, it is subject to the tunables, etc.
1778 */
1779int
1780pci_msix_count_method(device_t dev, device_t child)
1781{
1782 struct pci_devinfo *dinfo = device_get_ivars(child);
1783 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1784
1785 if (pci_do_msix && msix->msix_location != 0)
1786 return (msix->msix_msgnum);
1787 return (0);
1788}
1789
1790/*
1791 * HyperTransport MSI mapping control
1792 */
1793void
1794pci_ht_map_msi(device_t dev, uint64_t addr)
1795{
1796 struct pci_devinfo *dinfo = device_get_ivars(dev);
1797 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1798
1799 if (!ht->ht_msimap)
1800 return;
1801
1802 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1803 ht->ht_msiaddr >> 20 == addr >> 20) {
1804 /* Enable MSI -> HT mapping. */
1805 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1806 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1807 ht->ht_msictrl, 2);
1808 }
1809
1810 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1811 /* Disable MSI -> HT mapping. */
1812 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1813 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1814 ht->ht_msictrl, 2);
1815 }
1816}
1817
1818int
1819pci_get_max_read_req(device_t dev)
1820{
1821 struct pci_devinfo *dinfo = device_get_ivars(dev);
1822 int cap;
1823 uint16_t val;
1824
1825 cap = dinfo->cfg.pcie.pcie_location;
1826 if (cap == 0)
1827 return (0);
1828 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
1829 val &= PCIEM_CTL_MAX_READ_REQUEST;
1830 val >>= 12;
1831 return (1 << (val + 7));
1832}
1833
1834int
1835pci_set_max_read_req(device_t dev, int size)
1836{
1837 struct pci_devinfo *dinfo = device_get_ivars(dev);
1838 int cap;
1839 uint16_t val;
1840
1841 cap = dinfo->cfg.pcie.pcie_location;
1842 if (cap == 0)
1843 return (0);
1844 if (size < 128)
1845 size = 128;
1846 if (size > 4096)
1847 size = 4096;
1848 size = (1 << (fls(size) - 1));
1849 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
1850 val &= ~PCIEM_CTL_MAX_READ_REQUEST;
1851 val |= (fls(size) - 8) << 12;
1852 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2);
1853 return (size);
1854}
1855
1856/*
1857 * Support for MSI message signalled interrupts.
1858 */
1859void
1860pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1861{
1862 struct pci_devinfo *dinfo = device_get_ivars(dev);
1863 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1864
1865 /* Write data and address values. */
1866 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1867 address & 0xffffffff, 4);
1868 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1869 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1870 address >> 32, 4);
1871 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1872 data, 2);
1873 } else
1874 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1875 2);
1876
1877 /* Enable MSI in the control register. */
1878 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1879 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1880 2);
1881
1882 /* Enable MSI -> HT mapping. */
1883 pci_ht_map_msi(dev, address);
1884}
1885
1886void
1887pci_disable_msi(device_t dev)
1888{
1889 struct pci_devinfo *dinfo = device_get_ivars(dev);
1890 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1891
1892 /* Disable MSI -> HT mapping. */
1893 pci_ht_map_msi(dev, 0);
1894
1895 /* Disable MSI in the control register. */
1896 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1897 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1898 2);
1899}
1900
1901/*
1902 * Restore MSI registers during resume. If MSI is enabled then
1903 * restore the data and address registers in addition to the control
1904 * register.
1905 */
1906static void
1907pci_resume_msi(device_t dev)
1908{
1909 struct pci_devinfo *dinfo = device_get_ivars(dev);
1910 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1911 uint64_t address;
1912 uint16_t data;
1913
1914 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1915 address = msi->msi_addr;
1916 data = msi->msi_data;
1917 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1918 address & 0xffffffff, 4);
1919 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1920 pci_write_config(dev, msi->msi_location +
1921 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1922 pci_write_config(dev, msi->msi_location +
1923 PCIR_MSI_DATA_64BIT, data, 2);
1924 } else
1925 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1926 data, 2);
1927 }
1928 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1929 2);
1930}
1931
1932static int
1933pci_remap_intr_method(device_t bus, device_t dev, u_int irq)
1934{
1935 struct pci_devinfo *dinfo = device_get_ivars(dev);
1936 pcicfgregs *cfg = &dinfo->cfg;
1937 struct resource_list_entry *rle;
1938 struct msix_table_entry *mte;
1939 struct msix_vector *mv;
1940 uint64_t addr;
1941 uint32_t data;
1942 int error, i, j;
1943
1944 /*
1945 * Handle MSI first. We try to find this IRQ among our list
1946 * of MSI IRQs. If we find it, we request updated address and
1947 * data registers and apply the results.
1948 */
1949 if (cfg->msi.msi_alloc > 0) {
1950
1951 /* If we don't have any active handlers, nothing to do. */
1952 if (cfg->msi.msi_handlers == 0)
1953 return (0);
1954 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1955 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1956 i + 1);
1957 if (rle->start == irq) {
1958 error = PCIB_MAP_MSI(device_get_parent(bus),
1959 dev, irq, &addr, &data);
1960 if (error)
1961 return (error);
1962 pci_disable_msi(dev);
1963 dinfo->cfg.msi.msi_addr = addr;
1964 dinfo->cfg.msi.msi_data = data;
1965 pci_enable_msi(dev, addr, data);
1966 return (0);
1967 }
1968 }
1969 return (ENOENT);
1970 }
1971
1972 /*
1973 * For MSI-X, we check to see if we have this IRQ. If we do,
1974 * we request the updated mapping info. If that works, we go
1975 * through all the slots that use this IRQ and update them.
1976 */
1977 if (cfg->msix.msix_alloc > 0) {
1978 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1979 mv = &cfg->msix.msix_vectors[i];
1980 if (mv->mv_irq == irq) {
1981 error = PCIB_MAP_MSI(device_get_parent(bus),
1982 dev, irq, &addr, &data);
1983 if (error)
1984 return (error);
1985 mv->mv_address = addr;
1986 mv->mv_data = data;
1987 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1988 mte = &cfg->msix.msix_table[j];
1989 if (mte->mte_vector != i + 1)
1990 continue;
1991 if (mte->mte_handlers == 0)
1992 continue;
1993 pci_mask_msix(dev, j);
1994 pci_enable_msix(dev, j, addr, data);
1995 pci_unmask_msix(dev, j);
1996 }
1997 }
1998 }
1999 return (ENOENT);
2000 }
2001
2002 return (ENOENT);
2003}
2004
2005/*
2006 * Returns true if the specified device is blacklisted because MSI
2007 * doesn't work.
2008 */
2009int
2010pci_msi_device_blacklisted(device_t dev)
2011{
2012
2013 if (!pci_honor_msi_blacklist)
2014 return (0);
2015
2016 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI));
2017}
2018
2019/*
2020 * Determine if MSI is blacklisted globally on this system. Currently,
2021 * we just check for blacklisted chipsets as represented by the
2022 * host-PCI bridge at device 0:0:0. In the future, it may become
2023 * necessary to check other system attributes, such as the kenv values
2024 * that give the motherboard manufacturer and model number.
2025 */
2026static int
2027pci_msi_blacklisted(void)
2028{
2029 device_t dev;
2030
2031 if (!pci_honor_msi_blacklist)
2032 return (0);
2033
2034 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2035 if (!(pcie_chipset || pcix_chipset)) {
2036 if (vm_guest != VM_GUEST_NO) {
2037 /*
2038 * Whitelist older chipsets in virtual
2039 * machines known to support MSI.
2040 */
2041 dev = pci_find_bsf(0, 0, 0);
2042 if (dev != NULL)
2043 return (!pci_has_quirk(pci_get_devid(dev),
2044 PCI_QUIRK_ENABLE_MSI_VM));
2045 }
2046 return (1);
2047 }
2048
2049 dev = pci_find_bsf(0, 0, 0);
2050 if (dev != NULL)
2051 return (pci_msi_device_blacklisted(dev));
2052 return (0);
2053}
2054
2055/*
2056 * Returns true if the specified device is blacklisted because MSI-X
2057 * doesn't work. Note that this assumes that if MSI doesn't work,
2058 * MSI-X doesn't either.
2059 */
2060int
2061pci_msix_device_blacklisted(device_t dev)
2062{
2063
2064 if (!pci_honor_msi_blacklist)
2065 return (0);
2066
2067 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX))
2068 return (1);
2069
2070 return (pci_msi_device_blacklisted(dev));
2071}
2072
2073/*
2074 * Determine if MSI-X is blacklisted globally on this system. If MSI
2075 * is blacklisted, assume that MSI-X is as well. Check for additional
2076 * chipsets where MSI works but MSI-X does not.
2077 */
2078static int
2079pci_msix_blacklisted(void)
2080{
2081 device_t dev;
2082
2083 if (!pci_honor_msi_blacklist)
2084 return (0);
2085
2086 dev = pci_find_bsf(0, 0, 0);
2087 if (dev != NULL && pci_has_quirk(pci_get_devid(dev),
2088 PCI_QUIRK_DISABLE_MSIX))
2089 return (1);
2090
2091 return (pci_msi_blacklisted());
2092}
2093
2094/*
2095 * Attempt to allocate *count MSI messages. The actual number allocated is
2096 * returned in *count. After this function returns, each message will be
2097 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2098 */
2099int
2100pci_alloc_msi_method(device_t dev, device_t child, int *count)
2101{
2102 struct pci_devinfo *dinfo = device_get_ivars(child);
2103 pcicfgregs *cfg = &dinfo->cfg;
2104 struct resource_list_entry *rle;
2105 int actual, error, i, irqs[32];
2106 uint16_t ctrl;
2107
2108 /* Don't let count == 0 get us into trouble. */
2109 if (*count == 0)
2110 return (EINVAL);
2111
2112 /* If rid 0 is allocated, then fail. */
2113 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2114 if (rle != NULL && rle->res != NULL)
2115 return (ENXIO);
2116
2117 /* Already have allocated messages? */
2118 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2119 return (ENXIO);
2120
2121 /* If MSI is blacklisted for this system, fail. */
2122 if (pci_msi_blacklisted())
2123 return (ENXIO);
2124
2125 /* MSI capability present? */
2126 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2127 return (ENODEV);
2128
2129 if (bootverbose)
2130 device_printf(child,
2131 "attempting to allocate %d MSI vectors (%d supported)\n",
2132 *count, cfg->msi.msi_msgnum);
2133
2134 /* Don't ask for more than the device supports. */
2135 actual = min(*count, cfg->msi.msi_msgnum);
2136
2137 /* Don't ask for more than 32 messages. */
2138 actual = min(actual, 32);
2139
2140 /* MSI requires power of 2 number of messages. */
2141 if (!powerof2(actual))
2142 return (EINVAL);
2143
2144 for (;;) {
2145 /* Try to allocate N messages. */
2146 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2147 actual, irqs);
2148 if (error == 0)
2149 break;
2150 if (actual == 1)
2151 return (error);
2152
2153 /* Try N / 2. */
2154 actual >>= 1;
2155 }
2156
2157 /*
2158 * We now have N actual messages mapped onto SYS_RES_IRQ
2159 * resources in the irqs[] array, so add new resources
2160 * starting at rid 1.
2161 */
2162 for (i = 0; i < actual; i++)
2163 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2164 irqs[i], irqs[i], 1);
2165
2166 if (bootverbose) {
2167 if (actual == 1)
2168 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2169 else {
2170 int run;
2171
2172 /*
2173 * Be fancy and try to print contiguous runs
2174 * of IRQ values as ranges. 'run' is true if
2175 * we are in a range.
2176 */
2177 device_printf(child, "using IRQs %d", irqs[0]);
2178 run = 0;
2179 for (i = 1; i < actual; i++) {
2180
2181 /* Still in a run? */
2182 if (irqs[i] == irqs[i - 1] + 1) {
2183 run = 1;
2184 continue;
2185 }
2186
2187 /* Finish previous range. */
2188 if (run) {
2189 printf("-%d", irqs[i - 1]);
2190 run = 0;
2191 }
2192
2193 /* Start new range. */
2194 printf(",%d", irqs[i]);
2195 }
2196
2197 /* Unfinished range? */
2198 if (run)
2199 printf("-%d", irqs[actual - 1]);
2200 printf(" for MSI\n");
2201 }
2202 }
2203
2204 /* Update control register with actual count. */
2205 ctrl = cfg->msi.msi_ctrl;
2206 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2207 ctrl |= (ffs(actual) - 1) << 4;
2208 cfg->msi.msi_ctrl = ctrl;
2209 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2210
2211 /* Update counts of alloc'd messages. */
2212 cfg->msi.msi_alloc = actual;
2213 cfg->msi.msi_handlers = 0;
2214 *count = actual;
2215 return (0);
2216}
2217
2218/* Release the MSI messages associated with this device. */
2219int
2220pci_release_msi_method(device_t dev, device_t child)
2221{
2222 struct pci_devinfo *dinfo = device_get_ivars(child);
2223 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2224 struct resource_list_entry *rle;
2225 int error, i, irqs[32];
2226
2227 /* Try MSI-X first. */
2228 error = pci_release_msix(dev, child);
2229 if (error != ENODEV)
2230 return (error);
2231
2232 /* Do we have any messages to release? */
2233 if (msi->msi_alloc == 0)
2234 return (ENODEV);
2235 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2236
2237 /* Make sure none of the resources are allocated. */
2238 if (msi->msi_handlers > 0)
2239 return (EBUSY);
2240 for (i = 0; i < msi->msi_alloc; i++) {
2241 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2242 KASSERT(rle != NULL, ("missing MSI resource"));
2243 if (rle->res != NULL)
2244 return (EBUSY);
2245 irqs[i] = rle->start;
2246 }
2247
2248 /* Update control register with 0 count. */
2249 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2250 ("%s: MSI still enabled", __func__));
2251 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2252 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2253 msi->msi_ctrl, 2);
2254
2255 /* Release the messages. */
2256 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2257 for (i = 0; i < msi->msi_alloc; i++)
2258 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2259
2260 /* Update alloc count. */
2261 msi->msi_alloc = 0;
2262 msi->msi_addr = 0;
2263 msi->msi_data = 0;
2264 return (0);
2265}
2266
2267/*
2268 * Return the max supported MSI messages this device supports.
2269 * Basically, assuming the MD code can alloc messages, this function
2270 * should return the maximum value that pci_alloc_msi() can return.
2271 * Thus, it is subject to the tunables, etc.
2272 */
2273int
2274pci_msi_count_method(device_t dev, device_t child)
2275{
2276 struct pci_devinfo *dinfo = device_get_ivars(child);
2277 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2278
2279 if (pci_do_msi && msi->msi_location != 0)
2280 return (msi->msi_msgnum);
2281 return (0);
2282}
2283
2284/* free pcicfgregs structure and all depending data structures */
2285
2286int
2287pci_freecfg(struct pci_devinfo *dinfo)
2288{
2289 struct devlist *devlist_head;
2290 struct pci_map *pm, *next;
2291 int i;
2292
2293 devlist_head = &pci_devq;
2294
2295 if (dinfo->cfg.vpd.vpd_reg) {
2296 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2297 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2298 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2299 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2300 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2301 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2302 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2303 }
2304 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) {
2305 free(pm, M_DEVBUF);
2306 }
2307 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2308 free(dinfo, M_DEVBUF);
2309
2310 /* increment the generation count */
2311 pci_generation++;
2312
2313 /* we're losing one device */
2314 pci_numdevs--;
2315 return (0);
2316}
2317
2318/*
2319 * PCI power manangement
2320 */
2321int
2322pci_set_powerstate_method(device_t dev, device_t child, int state)
2323{
2324 struct pci_devinfo *dinfo = device_get_ivars(child);
2325 pcicfgregs *cfg = &dinfo->cfg;
2326 uint16_t status;
2327 int result, oldstate, highest, delay;
2328
2329 if (cfg->pp.pp_cap == 0)
2330 return (EOPNOTSUPP);
2331
2332 /*
2333 * Optimize a no state change request away. While it would be OK to
2334 * write to the hardware in theory, some devices have shown odd
2335 * behavior when going from D3 -> D3.
2336 */
2337 oldstate = pci_get_powerstate(child);
2338 if (oldstate == state)
2339 return (0);
2340
2341 /*
2342 * The PCI power management specification states that after a state
2343 * transition between PCI power states, system software must
2344 * guarantee a minimal delay before the function accesses the device.
2345 * Compute the worst case delay that we need to guarantee before we
2346 * access the device. Many devices will be responsive much more
2347 * quickly than this delay, but there are some that don't respond
2348 * instantly to state changes. Transitions to/from D3 state require
2349 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2350 * is done below with DELAY rather than a sleeper function because
2351 * this function can be called from contexts where we cannot sleep.
2352 */
2353 highest = (oldstate > state) ? oldstate : state;
2354 if (highest == PCI_POWERSTATE_D3)
2355 delay = 10000;
2356 else if (highest == PCI_POWERSTATE_D2)
2357 delay = 200;
2358 else
2359 delay = 0;
2360 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2361 & ~PCIM_PSTAT_DMASK;
2362 result = 0;
2363 switch (state) {
2364 case PCI_POWERSTATE_D0:
2365 status |= PCIM_PSTAT_D0;
2366 break;
2367 case PCI_POWERSTATE_D1:
2368 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2369 return (EOPNOTSUPP);
2370 status |= PCIM_PSTAT_D1;
2371 break;
2372 case PCI_POWERSTATE_D2:
2373 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2374 return (EOPNOTSUPP);
2375 status |= PCIM_PSTAT_D2;
2376 break;
2377 case PCI_POWERSTATE_D3:
2378 status |= PCIM_PSTAT_D3;
2379 break;
2380 default:
2381 return (EINVAL);
2382 }
2383
2384 if (bootverbose)
2385 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate,
2386 state);
2387
2388 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2389 if (delay)
2390 DELAY(delay);
2391 return (0);
2392}
2393
2394int
2395pci_get_powerstate_method(device_t dev, device_t child)
2396{
2397 struct pci_devinfo *dinfo = device_get_ivars(child);
2398 pcicfgregs *cfg = &dinfo->cfg;
2399 uint16_t status;
2400 int result;
2401
2402 if (cfg->pp.pp_cap != 0) {
2403 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2404 switch (status & PCIM_PSTAT_DMASK) {
2405 case PCIM_PSTAT_D0:
2406 result = PCI_POWERSTATE_D0;
2407 break;
2408 case PCIM_PSTAT_D1:
2409 result = PCI_POWERSTATE_D1;
2410 break;
2411 case PCIM_PSTAT_D2:
2412 result = PCI_POWERSTATE_D2;
2413 break;
2414 case PCIM_PSTAT_D3:
2415 result = PCI_POWERSTATE_D3;
2416 break;
2417 default:
2418 result = PCI_POWERSTATE_UNKNOWN;
2419 break;
2420 }
2421 } else {
2422 /* No support, device is always at D0 */
2423 result = PCI_POWERSTATE_D0;
2424 }
2425 return (result);
2426}
2427
2428/*
2429 * Some convenience functions for PCI device drivers.
2430 */
2431
2432static __inline void
2433pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2434{
2435 uint16_t command;
2436
2437 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2438 command |= bit;
2439 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2440}
2441
2442static __inline void
2443pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2444{
2445 uint16_t command;
2446
2447 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2448 command &= ~bit;
2449 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2450}
2451
2452int
2453pci_enable_busmaster_method(device_t dev, device_t child)
2454{
2455 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2456 return (0);
2457}
2458
2459int
2460pci_disable_busmaster_method(device_t dev, device_t child)
2461{
2462 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2463 return (0);
2464}
2465
2466int
2467pci_enable_io_method(device_t dev, device_t child, int space)
2468{
2469 uint16_t bit;
2470
2471 switch(space) {
2472 case SYS_RES_IOPORT:
2473 bit = PCIM_CMD_PORTEN;
2474 break;
2475 case SYS_RES_MEMORY:
2476 bit = PCIM_CMD_MEMEN;
2477 break;
2478 default:
2479 return (EINVAL);
2480 }
2481 pci_set_command_bit(dev, child, bit);
2482 return (0);
2483}
2484
2485int
2486pci_disable_io_method(device_t dev, device_t child, int space)
2487{
2488 uint16_t bit;
2489
2490 switch(space) {
2491 case SYS_RES_IOPORT:
2492 bit = PCIM_CMD_PORTEN;
2493 break;
2494 case SYS_RES_MEMORY:
2495 bit = PCIM_CMD_MEMEN;
2496 break;
2497 default:
2498 return (EINVAL);
2499 }
2500 pci_clear_command_bit(dev, child, bit);
2501 return (0);
2502}
2503
2504/*
2505 * New style pci driver. Parent device is either a pci-host-bridge or a
2506 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2507 */
2508
2509void
2510pci_print_verbose(struct pci_devinfo *dinfo)
2511{
2512
2513 if (bootverbose) {
2514 pcicfgregs *cfg = &dinfo->cfg;
2515
2516 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2517 cfg->vendor, cfg->device, cfg->revid);
2518 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2519 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2520 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2521 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2522 cfg->mfdev);
2523 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2524 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2525 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2526 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2527 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2528 if (cfg->intpin > 0)
2529 printf("\tintpin=%c, irq=%d\n",
2530 cfg->intpin +'a' -1, cfg->intline);
2531 if (cfg->pp.pp_cap) {
2532 uint16_t status;
2533
2534 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2535 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2536 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2537 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2538 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2539 status & PCIM_PSTAT_DMASK);
2540 }
2541 if (cfg->msi.msi_location) {
2542 int ctrl;
2543
2544 ctrl = cfg->msi.msi_ctrl;
2545 printf("\tMSI supports %d message%s%s%s\n",
2546 cfg->msi.msi_msgnum,
2547 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2548 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2549 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2550 }
2551 if (cfg->msix.msix_location) {
2552 printf("\tMSI-X supports %d message%s ",
2553 cfg->msix.msix_msgnum,
2554 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2555 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2556 printf("in map 0x%x\n",
2557 cfg->msix.msix_table_bar);
2558 else
2559 printf("in maps 0x%x and 0x%x\n",
2560 cfg->msix.msix_table_bar,
2561 cfg->msix.msix_pba_bar);
2562 }
2563 }
2564}
2565
2566static int
2567pci_porten(device_t dev)
2568{
2569 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
2570}
2571
2572static int
2573pci_memen(device_t dev)
2574{
2575 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
2576}
2577
2578static void
2579pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp)
2580{
2581 struct pci_devinfo *dinfo;
2582 pci_addr_t map, testval;
2583 int ln2range;
2584 uint16_t cmd;
2585
2586 /*
2587 * The device ROM BAR is special. It is always a 32-bit
2588 * memory BAR. Bit 0 is special and should not be set when
2589 * sizing the BAR.
2590 */
2591 dinfo = device_get_ivars(dev);
2592 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) {
2593 map = pci_read_config(dev, reg, 4);
2594 pci_write_config(dev, reg, 0xfffffffe, 4);
2595 testval = pci_read_config(dev, reg, 4);
2596 pci_write_config(dev, reg, map, 4);
2597 *mapp = map;
2598 *testvalp = testval;
2599 return;
2600 }
2601
2602 map = pci_read_config(dev, reg, 4);
2603 ln2range = pci_maprange(map);
2604 if (ln2range == 64)
2605 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2606
2607 /*
2608 * Disable decoding via the command register before
2609 * determining the BAR's length since we will be placing it in
2610 * a weird state.
2611 */
2612 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2613 pci_write_config(dev, PCIR_COMMAND,
2614 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
2615
2616 /*
2617 * Determine the BAR's length by writing all 1's. The bottom
2618 * log_2(size) bits of the BAR will stick as 0 when we read
2619 * the value back.
2620 */
2621 pci_write_config(dev, reg, 0xffffffff, 4);
2622 testval = pci_read_config(dev, reg, 4);
2623 if (ln2range == 64) {
2624 pci_write_config(dev, reg + 4, 0xffffffff, 4);
2625 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2626 }
2627
2628 /*
2629 * Restore the original value of the BAR. We may have reprogrammed
2630 * the BAR of the low-level console device and when booting verbose,
2631 * we need the console device addressable.
2632 */
2633 pci_write_config(dev, reg, map, 4);
2634 if (ln2range == 64)
2635 pci_write_config(dev, reg + 4, map >> 32, 4);
2636 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2637
2638 *mapp = map;
2639 *testvalp = testval;
2640}
2641
2642static void
2643pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base)
2644{
2645 struct pci_devinfo *dinfo;
2646 int ln2range;
2647
2648 /* The device ROM BAR is always a 32-bit memory BAR. */
2649 dinfo = device_get_ivars(dev);
2650 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
2651 ln2range = 32;
2652 else
2653 ln2range = pci_maprange(pm->pm_value);
2654 pci_write_config(dev, pm->pm_reg, base, 4);
2655 if (ln2range == 64)
2656 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4);
2657 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4);
2658 if (ln2range == 64)
2659 pm->pm_value |= (pci_addr_t)pci_read_config(dev,
2660 pm->pm_reg + 4, 4) << 32;
2661}
2662
2663struct pci_map *
2664pci_find_bar(device_t dev, int reg)
2665{
2666 struct pci_devinfo *dinfo;
2667 struct pci_map *pm;
2668
2669 dinfo = device_get_ivars(dev);
2670 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
2671 if (pm->pm_reg == reg)
2672 return (pm);
2673 }
2674 return (NULL);
2675}
2676
2677int
2678pci_bar_enabled(device_t dev, struct pci_map *pm)
2679{
2680 struct pci_devinfo *dinfo;
2681 uint16_t cmd;
2682
2683 dinfo = device_get_ivars(dev);
2684 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) &&
2685 !(pm->pm_value & PCIM_BIOS_ENABLE))
2686 return (0);
2687 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2688 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value))
2689 return ((cmd & PCIM_CMD_MEMEN) != 0);
2690 else
2691 return ((cmd & PCIM_CMD_PORTEN) != 0);
2692}
2693
2694static struct pci_map *
2695pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size)
2696{
2697 struct pci_devinfo *dinfo;
2698 struct pci_map *pm, *prev;
2699
2700 dinfo = device_get_ivars(dev);
2701 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO);
2702 pm->pm_reg = reg;
2703 pm->pm_value = value;
2704 pm->pm_size = size;
2705 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) {
2706 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x",
2707 reg));
2708 if (STAILQ_NEXT(prev, pm_link) == NULL ||
2709 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg)
2710 break;
2711 }
2712 if (prev != NULL)
2713 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link);
2714 else
2715 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link);
2716 return (pm);
2717}
2718
2719static void
2720pci_restore_bars(device_t dev)
2721{
2722 struct pci_devinfo *dinfo;
2723 struct pci_map *pm;
2724 int ln2range;
2725
2726 dinfo = device_get_ivars(dev);
2727 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
2728 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
2729 ln2range = 32;
2730 else
2731 ln2range = pci_maprange(pm->pm_value);
2732 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4);
2733 if (ln2range == 64)
2734 pci_write_config(dev, pm->pm_reg + 4,
2735 pm->pm_value >> 32, 4);
2736 }
2737}
2738
2739/*
2740 * Add a resource based on a pci map register. Return 1 if the map
2741 * register is a 32bit map register or 2 if it is a 64bit register.
2742 */
2743static int
2744pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
2745 int force, int prefetch)
2746{
2747 struct pci_map *pm;
2748 pci_addr_t base, map, testval;
2749 pci_addr_t start, end, count;
2750 int barlen, basezero, flags, maprange, mapsize, type;
2751 uint16_t cmd;
2752 struct resource *res;
2753
2754 /*
2755 * The BAR may already exist if the device is a CardBus card
2756 * whose CIS is stored in this BAR.
2757 */
2758 pm = pci_find_bar(dev, reg);
2759 if (pm != NULL) {
2760 maprange = pci_maprange(pm->pm_value);
2761 barlen = maprange == 64 ? 2 : 1;
2762 return (barlen);
2763 }
2764
2765 pci_read_bar(dev, reg, &map, &testval);
2766 if (PCI_BAR_MEM(map)) {
2767 type = SYS_RES_MEMORY;
2768 if (map & PCIM_BAR_MEM_PREFETCH)
2769 prefetch = 1;
2770 } else
2771 type = SYS_RES_IOPORT;
2772 mapsize = pci_mapsize(testval);
2773 base = pci_mapbase(map);
2774#ifdef __PCI_BAR_ZERO_VALID
2775 basezero = 0;
2776#else
2777 basezero = base == 0;
2778#endif
2779 maprange = pci_maprange(map);
2780 barlen = maprange == 64 ? 2 : 1;
2781
2782 /*
2783 * For I/O registers, if bottom bit is set, and the next bit up
2784 * isn't clear, we know we have a BAR that doesn't conform to the
2785 * spec, so ignore it. Also, sanity check the size of the data
2786 * areas to the type of memory involved. Memory must be at least
2787 * 16 bytes in size, while I/O ranges must be at least 4.
2788 */
2789 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2790 return (barlen);
2791 if ((type == SYS_RES_MEMORY && mapsize < 4) ||
2792 (type == SYS_RES_IOPORT && mapsize < 2))
2793 return (barlen);
2794
2795 /* Save a record of this BAR. */
2796 pm = pci_add_bar(dev, reg, map, mapsize);
2797 if (bootverbose) {
2798 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2799 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
2800 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2801 printf(", port disabled\n");
2802 else if (type == SYS_RES_MEMORY && !pci_memen(dev))
2803 printf(", memory disabled\n");
2804 else
2805 printf(", enabled\n");
2806 }
2807
2808 /*
2809 * If base is 0, then we have problems if this architecture does
2810 * not allow that. It is best to ignore such entries for the
2811 * moment. These will be allocated later if the driver specifically
2812 * requests them. However, some removable busses look better when
2813 * all resources are allocated, so allow '0' to be overriden.
2814 *
2815 * Similarly treat maps whose values is the same as the test value
2816 * read back. These maps have had all f's written to them by the
2817 * BIOS in an attempt to disable the resources.
2818 */
2819 if (!force && (basezero || map == testval))
2820 return (barlen);
2821 if ((u_long)base != base) {
2822 device_printf(bus,
2823 "pci%d:%d:%d:%d bar %#x too many address bits",
2824 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
2825 pci_get_function(dev), reg);
2826 return (barlen);
2827 }
2828
2829 /*
2830 * This code theoretically does the right thing, but has
2831 * undesirable side effects in some cases where peripherals
2832 * respond oddly to having these bits enabled. Let the user
2833 * be able to turn them off (since pci_enable_io_modes is 1 by
2834 * default).
2835 */
2836 if (pci_enable_io_modes) {
2837 /* Turn on resources that have been left off by a lazy BIOS */
2838 if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
2839 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2840 cmd |= PCIM_CMD_PORTEN;
2841 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2842 }
2843 if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
2844 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2845 cmd |= PCIM_CMD_MEMEN;
2846 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2847 }
2848 } else {
2849 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2850 return (barlen);
2851 if (type == SYS_RES_MEMORY && !pci_memen(dev))
2852 return (barlen);
2853 }
2854
2855 count = (pci_addr_t)1 << mapsize;
2856 flags = RF_ALIGNMENT_LOG2(mapsize);
2857 if (prefetch)
2858 flags |= RF_PREFETCHABLE;
2859 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) {
2860 start = 0; /* Let the parent decide. */
2861 end = ~0ul;
2862 } else {
2863 start = base;
2864 end = base + count - 1;
2865 }
2866 resource_list_add(rl, type, reg, start, end, count);
2867
2868 /*
2869 * Try to allocate the resource for this BAR from our parent
2870 * so that this resource range is already reserved. The
2871 * driver for this device will later inherit this resource in
2872 * pci_alloc_resource().
2873 */
2874 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count,
2875 flags);
2876 if (pci_do_realloc_bars && res == NULL && (start != 0 || end != ~0ul)) {
2877 /*
2878 * If the allocation fails, try to allocate a resource for
2879 * this BAR using any available range. The firmware felt
2880 * it was important enough to assign a resource, so don't
2881 * disable decoding if we can help it.
2882 */
2883 resource_list_delete(rl, type, reg);
2884 resource_list_add(rl, type, reg, 0, ~0ul, count);
2885 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0ul,
2886 count, flags);
2887 }
2888 if (res == NULL) {
2889 /*
2890 * If the allocation fails, delete the resource list entry
2891 * and disable decoding for this device.
2892 *
2893 * If the driver requests this resource in the future,
2894 * pci_reserve_map() will try to allocate a fresh
2895 * resource range.
2896 */
2897 resource_list_delete(rl, type, reg);
2898 pci_disable_io(dev, type);
2899 if (bootverbose)
2900 device_printf(bus,
2901 "pci%d:%d:%d:%d bar %#x failed to allocate\n",
2902 pci_get_domain(dev), pci_get_bus(dev),
2903 pci_get_slot(dev), pci_get_function(dev), reg);
2904 } else {
2905 start = rman_get_start(res);
2906 pci_write_bar(dev, pm, start);
2907 }
2908 return (barlen);
2909}
2910
2911/*
2912 * For ATA devices we need to decide early what addressing mode to use.
2913 * Legacy demands that the primary and secondary ATA ports sits on the
2914 * same addresses that old ISA hardware did. This dictates that we use
2915 * those addresses and ignore the BAR's if we cannot set PCI native
2916 * addressing mode.
2917 */
2918static void
2919pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
2920 uint32_t prefetchmask)
2921{
2922 struct resource *r;
2923 int rid, type, progif;
2924#if 0
2925 /* if this device supports PCI native addressing use it */
2926 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2927 if ((progif & 0x8a) == 0x8a) {
2928 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2929 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2930 printf("Trying ATA native PCI addressing mode\n");
2931 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2932 }
2933 }
2934#endif
2935 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2936 type = SYS_RES_IOPORT;
2937 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2938 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
2939 prefetchmask & (1 << 0));
2940 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
2941 prefetchmask & (1 << 1));
2942 } else {
2943 rid = PCIR_BAR(0);
2944 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2945 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0,
2946 0x1f7, 8, 0);
2947 rid = PCIR_BAR(1);
2948 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2949 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6,
2950 0x3f6, 1, 0);
2951 }
2952 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2953 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
2954 prefetchmask & (1 << 2));
2955 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
2956 prefetchmask & (1 << 3));
2957 } else {
2958 rid = PCIR_BAR(2);
2959 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2960 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x170,
2961 0x177, 8, 0);
2962 rid = PCIR_BAR(3);
2963 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2964 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x376,
2965 0x376, 1, 0);
2966 }
2967 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
2968 prefetchmask & (1 << 4));
2969 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
2970 prefetchmask & (1 << 5));
2971}
2972
2973static void
2974pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2975{
2976 struct pci_devinfo *dinfo = device_get_ivars(dev);
2977 pcicfgregs *cfg = &dinfo->cfg;
2978 char tunable_name[64];
2979 int irq;
2980
2981 /* Has to have an intpin to have an interrupt. */
2982 if (cfg->intpin == 0)
2983 return;
2984
2985 /* Let the user override the IRQ with a tunable. */
2986 irq = PCI_INVALID_IRQ;
2987 snprintf(tunable_name, sizeof(tunable_name),
2988 "hw.pci%d.%d.%d.INT%c.irq",
2989 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2990 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2991 irq = PCI_INVALID_IRQ;
2992
2993 /*
2994 * If we didn't get an IRQ via the tunable, then we either use the
2995 * IRQ value in the intline register or we ask the bus to route an
2996 * interrupt for us. If force_route is true, then we only use the
2997 * value in the intline register if the bus was unable to assign an
2998 * IRQ.
2999 */
3000 if (!PCI_INTERRUPT_VALID(irq)) {
3001 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
3002 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
3003 if (!PCI_INTERRUPT_VALID(irq))
3004 irq = cfg->intline;
3005 }
3006
3007 /* If after all that we don't have an IRQ, just bail. */
3008 if (!PCI_INTERRUPT_VALID(irq))
3009 return;
3010
3011 /* Update the config register if it changed. */
3012 if (irq != cfg->intline) {
3013 cfg->intline = irq;
3014 pci_write_config(dev, PCIR_INTLINE, irq, 1);
3015 }
3016
3017 /* Add this IRQ as rid 0 interrupt resource. */
3018 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
3019}
3020
3021/* Perform early OHCI takeover from SMM. */
3022static void
3023ohci_early_takeover(device_t self)
3024{
3025 struct resource *res;
3026 uint32_t ctl;
3027 int rid;
3028 int i;
3029
3030 rid = PCIR_BAR(0);
3031 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3032 if (res == NULL)
3033 return;
3034
3035 ctl = bus_read_4(res, OHCI_CONTROL);
3036 if (ctl & OHCI_IR) {
3037 if (bootverbose)
3038 printf("ohci early: "
3039 "SMM active, request owner change\n");
3040 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);
3041 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) {
3042 DELAY(1000);
3043 ctl = bus_read_4(res, OHCI_CONTROL);
3044 }
3045 if (ctl & OHCI_IR) {
3046 if (bootverbose)
3047 printf("ohci early: "
3048 "SMM does not respond, resetting\n");
3049 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);
3050 }
3051 /* Disable interrupts */
3052 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
3053 }
3054
3055 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3056}
3057
3058/* Perform early UHCI takeover from SMM. */
3059static void
3060uhci_early_takeover(device_t self)
3061{
3062 struct resource *res;
3063 int rid;
3064
3065 /*
3066 * Set the PIRQD enable bit and switch off all the others. We don't
3067 * want legacy support to interfere with us XXX Does this also mean
3068 * that the BIOS won't touch the keyboard anymore if it is connected
3069 * to the ports of the root hub?
3070 */
3071 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2);
3072
3073 /* Disable interrupts */
3074 rid = PCI_UHCI_BASE_REG;
3075 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE);
3076 if (res != NULL) {
3077 bus_write_2(res, UHCI_INTR, 0);
3078 bus_release_resource(self, SYS_RES_IOPORT, rid, res);
3079 }
3080}
3081
3082/* Perform early EHCI takeover from SMM. */
3083static void
3084ehci_early_takeover(device_t self)
3085{
3086 struct resource *res;
3087 uint32_t cparams;
3088 uint32_t eec;
3089 uint8_t eecp;
3090 uint8_t bios_sem;
3091 uint8_t offs;
3092 int rid;
3093 int i;
3094
3095 rid = PCIR_BAR(0);
3096 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3097 if (res == NULL)
3098 return;
3099
3100 cparams = bus_read_4(res, EHCI_HCCPARAMS);
3101
3102 /* Synchronise with the BIOS if it owns the controller. */
3103 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0;
3104 eecp = EHCI_EECP_NEXT(eec)) {
3105 eec = pci_read_config(self, eecp, 4);
3106 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) {
3107 continue;
3108 }
3109 bios_sem = pci_read_config(self, eecp +
3110 EHCI_LEGSUP_BIOS_SEM, 1);
3111 if (bios_sem == 0) {
3112 continue;
3113 }
3114 if (bootverbose)
3115 printf("ehci early: "
3116 "SMM active, request owner change\n");
3117
3118 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1);
3119
3120 for (i = 0; (i < 100) && (bios_sem != 0); i++) {
3121 DELAY(1000);
3122 bios_sem = pci_read_config(self, eecp +
3123 EHCI_LEGSUP_BIOS_SEM, 1);
3124 }
3125
3126 if (bios_sem != 0) {
3127 if (bootverbose)
3128 printf("ehci early: "
3129 "SMM does not respond\n");
3130 }
3131 /* Disable interrupts */
3132 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION));
3133 bus_write_4(res, offs + EHCI_USBINTR, 0);
3134 }
3135 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3136}
3137
3138/* Perform early XHCI takeover from SMM. */
3139static void
3140xhci_early_takeover(device_t self)
3141{
3142 struct resource *res;
3143 uint32_t cparams;
3144 uint32_t eec;
3145 uint8_t eecp;
3146 uint8_t bios_sem;
3147 uint8_t offs;
3148 int rid;
3149 int i;
3150
3151 rid = PCIR_BAR(0);
3152 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3153 if (res == NULL)
3154 return;
3155
3156 cparams = bus_read_4(res, XHCI_HCSPARAMS0);
3157
3158 eec = -1;
3159
3160 /* Synchronise with the BIOS if it owns the controller. */
3161 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
3162 eecp += XHCI_XECP_NEXT(eec) << 2) {
3163 eec = bus_read_4(res, eecp);
3164
3165 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
3166 continue;
3167
3168 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM);
3169 if (bios_sem == 0)
3170 continue;
3171
3172 if (bootverbose)
3173 printf("xhci early: "
3174 "SMM active, request owner change\n");
3175
3176 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1);
3177
3178 /* wait a maximum of 5 second */
3179
3180 for (i = 0; (i < 5000) && (bios_sem != 0); i++) {
3181 DELAY(1000);
3182 bios_sem = bus_read_1(res, eecp +
3183 XHCI_XECP_BIOS_SEM);
3184 }
3185
3186 if (bios_sem != 0) {
3187 if (bootverbose)
3188 printf("xhci early: "
3189 "SMM does not respond\n");
3190 }
3191
3192 /* Disable interrupts */
3193 offs = bus_read_1(res, XHCI_CAPLENGTH);
3194 bus_write_4(res, offs + XHCI_USBCMD, 0);
3195 bus_read_4(res, offs + XHCI_USBSTS);
3196 }
3197 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3198}
3199
| 354static int
355pci_has_quirk(uint32_t devid, int quirk)
356{
357 const struct pci_quirk *q;
358
359 for (q = &pci_quirks[0]; q->devid; q++) {
360 if (q->devid == devid && q->type == quirk)
361 return (1);
362 }
363 return (0);
364}
365
366/* Find a device_t by bus/slot/function in domain 0 */
367
368device_t
369pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
370{
371
372 return (pci_find_dbsf(0, bus, slot, func));
373}
374
375/* Find a device_t by domain/bus/slot/function */
376
377device_t
378pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
379{
380 struct pci_devinfo *dinfo;
381
382 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
383 if ((dinfo->cfg.domain == domain) &&
384 (dinfo->cfg.bus == bus) &&
385 (dinfo->cfg.slot == slot) &&
386 (dinfo->cfg.func == func)) {
387 return (dinfo->cfg.dev);
388 }
389 }
390
391 return (NULL);
392}
393
394/* Find a device_t by vendor/device ID */
395
396device_t
397pci_find_device(uint16_t vendor, uint16_t device)
398{
399 struct pci_devinfo *dinfo;
400
401 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
402 if ((dinfo->cfg.vendor == vendor) &&
403 (dinfo->cfg.device == device)) {
404 return (dinfo->cfg.dev);
405 }
406 }
407
408 return (NULL);
409}
410
411device_t
412pci_find_class(uint8_t class, uint8_t subclass)
413{
414 struct pci_devinfo *dinfo;
415
416 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
417 if (dinfo->cfg.baseclass == class &&
418 dinfo->cfg.subclass == subclass) {
419 return (dinfo->cfg.dev);
420 }
421 }
422
423 return (NULL);
424}
425
426static int
427pci_printf(pcicfgregs *cfg, const char *fmt, ...)
428{
429 va_list ap;
430 int retval;
431
432 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot,
433 cfg->func);
434 va_start(ap, fmt);
435 retval += vprintf(fmt, ap);
436 va_end(ap);
437 return (retval);
438}
439
440/* return base address of memory or port map */
441
442static pci_addr_t
443pci_mapbase(uint64_t mapreg)
444{
445
446 if (PCI_BAR_MEM(mapreg))
447 return (mapreg & PCIM_BAR_MEM_BASE);
448 else
449 return (mapreg & PCIM_BAR_IO_BASE);
450}
451
452/* return map type of memory or port map */
453
454static const char *
455pci_maptype(uint64_t mapreg)
456{
457
458 if (PCI_BAR_IO(mapreg))
459 return ("I/O Port");
460 if (mapreg & PCIM_BAR_MEM_PREFETCH)
461 return ("Prefetchable Memory");
462 return ("Memory");
463}
464
465/* return log2 of map size decoded for memory or port map */
466
467static int
468pci_mapsize(uint64_t testval)
469{
470 int ln2size;
471
472 testval = pci_mapbase(testval);
473 ln2size = 0;
474 if (testval != 0) {
475 while ((testval & 1) == 0)
476 {
477 ln2size++;
478 testval >>= 1;
479 }
480 }
481 return (ln2size);
482}
483
484/* return base address of device ROM */
485
486static pci_addr_t
487pci_rombase(uint64_t mapreg)
488{
489
490 return (mapreg & PCIM_BIOS_ADDR_MASK);
491}
492
493/* return log2 of map size decided for device ROM */
494
495static int
496pci_romsize(uint64_t testval)
497{
498 int ln2size;
499
500 testval = pci_rombase(testval);
501 ln2size = 0;
502 if (testval != 0) {
503 while ((testval & 1) == 0)
504 {
505 ln2size++;
506 testval >>= 1;
507 }
508 }
509 return (ln2size);
510}
511
512/* return log2 of address range supported by map register */
513
514static int
515pci_maprange(uint64_t mapreg)
516{
517 int ln2range = 0;
518
519 if (PCI_BAR_IO(mapreg))
520 ln2range = 32;
521 else
522 switch (mapreg & PCIM_BAR_MEM_TYPE) {
523 case PCIM_BAR_MEM_32:
524 ln2range = 32;
525 break;
526 case PCIM_BAR_MEM_1MB:
527 ln2range = 20;
528 break;
529 case PCIM_BAR_MEM_64:
530 ln2range = 64;
531 break;
532 }
533 return (ln2range);
534}
535
536/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
537
538static void
539pci_fixancient(pcicfgregs *cfg)
540{
541 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
542 return;
543
544 /* PCI to PCI bridges use header type 1 */
545 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
546 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
547}
548
549/* extract header type specific config data */
550
551static void
552pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
553{
554#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
555 switch (cfg->hdrtype & PCIM_HDRTYPE) {
556 case PCIM_HDRTYPE_NORMAL:
557 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
558 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
559 cfg->nummaps = PCI_MAXMAPS_0;
560 break;
561 case PCIM_HDRTYPE_BRIDGE:
562 cfg->nummaps = PCI_MAXMAPS_1;
563 break;
564 case PCIM_HDRTYPE_CARDBUS:
565 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
566 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
567 cfg->nummaps = PCI_MAXMAPS_2;
568 break;
569 }
570#undef REG
571}
572
573/* read configuration header into pcicfgregs structure */
574struct pci_devinfo *
575pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
576{
577#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
578 pcicfgregs *cfg = NULL;
579 struct pci_devinfo *devlist_entry;
580 struct devlist *devlist_head;
581
582 devlist_head = &pci_devq;
583
584 devlist_entry = NULL;
585
586 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) {
587 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
588 if (devlist_entry == NULL)
589 return (NULL);
590
591 cfg = &devlist_entry->cfg;
592
593 cfg->domain = d;
594 cfg->bus = b;
595 cfg->slot = s;
596 cfg->func = f;
597 cfg->vendor = REG(PCIR_VENDOR, 2);
598 cfg->device = REG(PCIR_DEVICE, 2);
599 cfg->cmdreg = REG(PCIR_COMMAND, 2);
600 cfg->statreg = REG(PCIR_STATUS, 2);
601 cfg->baseclass = REG(PCIR_CLASS, 1);
602 cfg->subclass = REG(PCIR_SUBCLASS, 1);
603 cfg->progif = REG(PCIR_PROGIF, 1);
604 cfg->revid = REG(PCIR_REVID, 1);
605 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
606 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
607 cfg->lattimer = REG(PCIR_LATTIMER, 1);
608 cfg->intpin = REG(PCIR_INTPIN, 1);
609 cfg->intline = REG(PCIR_INTLINE, 1);
610
611 cfg->mingnt = REG(PCIR_MINGNT, 1);
612 cfg->maxlat = REG(PCIR_MAXLAT, 1);
613
614 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
615 cfg->hdrtype &= ~PCIM_MFDEV;
616 STAILQ_INIT(&cfg->maps);
617
618 pci_fixancient(cfg);
619 pci_hdrtypedata(pcib, b, s, f, cfg);
620
621 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
622 pci_read_cap(pcib, cfg);
623
624 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
625
626 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
627 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
628 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
629 devlist_entry->conf.pc_sel.pc_func = cfg->func;
630 devlist_entry->conf.pc_hdr = cfg->hdrtype;
631
632 devlist_entry->conf.pc_subvendor = cfg->subvendor;
633 devlist_entry->conf.pc_subdevice = cfg->subdevice;
634 devlist_entry->conf.pc_vendor = cfg->vendor;
635 devlist_entry->conf.pc_device = cfg->device;
636
637 devlist_entry->conf.pc_class = cfg->baseclass;
638 devlist_entry->conf.pc_subclass = cfg->subclass;
639 devlist_entry->conf.pc_progif = cfg->progif;
640 devlist_entry->conf.pc_revid = cfg->revid;
641
642 pci_numdevs++;
643 pci_generation++;
644 }
645 return (devlist_entry);
646#undef REG
647}
648
649static void
650pci_read_cap(device_t pcib, pcicfgregs *cfg)
651{
652#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
653#define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
654#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
655 uint64_t addr;
656#endif
657 uint32_t val;
658 int ptr, nextptr, ptrptr;
659
660 switch (cfg->hdrtype & PCIM_HDRTYPE) {
661 case PCIM_HDRTYPE_NORMAL:
662 case PCIM_HDRTYPE_BRIDGE:
663 ptrptr = PCIR_CAP_PTR;
664 break;
665 case PCIM_HDRTYPE_CARDBUS:
666 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
667 break;
668 default:
669 return; /* no extended capabilities support */
670 }
671 nextptr = REG(ptrptr, 1); /* sanity check? */
672
673 /*
674 * Read capability entries.
675 */
676 while (nextptr != 0) {
677 /* Sanity check */
678 if (nextptr > 255) {
679 printf("illegal PCI extended capability offset %d\n",
680 nextptr);
681 return;
682 }
683 /* Find the next entry */
684 ptr = nextptr;
685 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
686
687 /* Process this entry */
688 switch (REG(ptr + PCICAP_ID, 1)) {
689 case PCIY_PMG: /* PCI power management */
690 if (cfg->pp.pp_cap == 0) {
691 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
692 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
693 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE;
694 if ((nextptr - ptr) > PCIR_POWER_DATA)
695 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
696 }
697 break;
698 case PCIY_HT: /* HyperTransport */
699 /* Determine HT-specific capability type. */
700 val = REG(ptr + PCIR_HT_COMMAND, 2);
701
702 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
703 cfg->ht.ht_slave = ptr;
704
705#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
706 switch (val & PCIM_HTCMD_CAP_MASK) {
707 case PCIM_HTCAP_MSI_MAPPING:
708 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
709 /* Sanity check the mapping window. */
710 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
711 4);
712 addr <<= 32;
713 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
714 4);
715 if (addr != MSI_INTEL_ADDR_BASE)
716 device_printf(pcib,
717 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
718 cfg->domain, cfg->bus,
719 cfg->slot, cfg->func,
720 (long long)addr);
721 } else
722 addr = MSI_INTEL_ADDR_BASE;
723
724 cfg->ht.ht_msimap = ptr;
725 cfg->ht.ht_msictrl = val;
726 cfg->ht.ht_msiaddr = addr;
727 break;
728 }
729#endif
730 break;
731 case PCIY_MSI: /* PCI MSI */
732 cfg->msi.msi_location = ptr;
733 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
734 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
735 PCIM_MSICTRL_MMC_MASK)>>1);
736 break;
737 case PCIY_MSIX: /* PCI MSI-X */
738 cfg->msix.msix_location = ptr;
739 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
740 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
741 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
742 val = REG(ptr + PCIR_MSIX_TABLE, 4);
743 cfg->msix.msix_table_bar = PCIR_BAR(val &
744 PCIM_MSIX_BIR_MASK);
745 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
746 val = REG(ptr + PCIR_MSIX_PBA, 4);
747 cfg->msix.msix_pba_bar = PCIR_BAR(val &
748 PCIM_MSIX_BIR_MASK);
749 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
750 break;
751 case PCIY_VPD: /* PCI Vital Product Data */
752 cfg->vpd.vpd_reg = ptr;
753 break;
754 case PCIY_SUBVENDOR:
755 /* Should always be true. */
756 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
757 PCIM_HDRTYPE_BRIDGE) {
758 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
759 cfg->subvendor = val & 0xffff;
760 cfg->subdevice = val >> 16;
761 }
762 break;
763 case PCIY_PCIX: /* PCI-X */
764 /*
765 * Assume we have a PCI-X chipset if we have
766 * at least one PCI-PCI bridge with a PCI-X
767 * capability. Note that some systems with
768 * PCI-express or HT chipsets might match on
769 * this check as well.
770 */
771 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
772 PCIM_HDRTYPE_BRIDGE)
773 pcix_chipset = 1;
774 cfg->pcix.pcix_location = ptr;
775 break;
776 case PCIY_EXPRESS: /* PCI-express */
777 /*
778 * Assume we have a PCI-express chipset if we have
779 * at least one PCI-express device.
780 */
781 pcie_chipset = 1;
782 cfg->pcie.pcie_location = ptr;
783 val = REG(ptr + PCIER_FLAGS, 2);
784 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE;
785 break;
786 default:
787 break;
788 }
789 }
790
791#if defined(__powerpc__)
792 /*
793 * Enable the MSI mapping window for all HyperTransport
794 * slaves. PCI-PCI bridges have their windows enabled via
795 * PCIB_MAP_MSI().
796 */
797 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
798 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
799 device_printf(pcib,
800 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
801 cfg->domain, cfg->bus, cfg->slot, cfg->func);
802 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
803 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
804 2);
805 }
806#endif
807/* REG and WREG use carry through to next functions */
808}
809
810/*
811 * PCI Vital Product Data
812 */
813
814#define PCI_VPD_TIMEOUT 1000000
815
816static int
817pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
818{
819 int count = PCI_VPD_TIMEOUT;
820
821 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
822
823 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
824
825 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
826 if (--count < 0)
827 return (ENXIO);
828 DELAY(1); /* limit looping */
829 }
830 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
831
832 return (0);
833}
834
835#if 0
836static int
837pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
838{
839 int count = PCI_VPD_TIMEOUT;
840
841 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
842
843 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
844 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
845 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
846 if (--count < 0)
847 return (ENXIO);
848 DELAY(1); /* limit looping */
849 }
850
851 return (0);
852}
853#endif
854
855#undef PCI_VPD_TIMEOUT
856
857struct vpd_readstate {
858 device_t pcib;
859 pcicfgregs *cfg;
860 uint32_t val;
861 int bytesinval;
862 int off;
863 uint8_t cksum;
864};
865
866static int
867vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
868{
869 uint32_t reg;
870 uint8_t byte;
871
872 if (vrs->bytesinval == 0) {
873 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
874 return (ENXIO);
875 vrs->val = le32toh(reg);
876 vrs->off += 4;
877 byte = vrs->val & 0xff;
878 vrs->bytesinval = 3;
879 } else {
880 vrs->val = vrs->val >> 8;
881 byte = vrs->val & 0xff;
882 vrs->bytesinval--;
883 }
884
885 vrs->cksum += byte;
886 *data = byte;
887 return (0);
888}
889
890static void
891pci_read_vpd(device_t pcib, pcicfgregs *cfg)
892{
893 struct vpd_readstate vrs;
894 int state;
895 int name;
896 int remain;
897 int i;
898 int alloc, off; /* alloc/off for RO/W arrays */
899 int cksumvalid;
900 int dflen;
901 uint8_t byte;
902 uint8_t byte2;
903
904 /* init vpd reader */
905 vrs.bytesinval = 0;
906 vrs.off = 0;
907 vrs.pcib = pcib;
908 vrs.cfg = cfg;
909 vrs.cksum = 0;
910
911 state = 0;
912 name = remain = i = 0; /* shut up stupid gcc */
913 alloc = off = 0; /* shut up stupid gcc */
914 dflen = 0; /* shut up stupid gcc */
915 cksumvalid = -1;
916 while (state >= 0) {
917 if (vpd_nextbyte(&vrs, &byte)) {
918 state = -2;
919 break;
920 }
921#if 0
922 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
923 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
924 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
925#endif
926 switch (state) {
927 case 0: /* item name */
928 if (byte & 0x80) {
929 if (vpd_nextbyte(&vrs, &byte2)) {
930 state = -2;
931 break;
932 }
933 remain = byte2;
934 if (vpd_nextbyte(&vrs, &byte2)) {
935 state = -2;
936 break;
937 }
938 remain |= byte2 << 8;
939 if (remain > (0x7f*4 - vrs.off)) {
940 state = -1;
941 pci_printf(cfg,
942 "invalid VPD data, remain %#x\n",
943 remain);
944 }
945 name = byte & 0x7f;
946 } else {
947 remain = byte & 0x7;
948 name = (byte >> 3) & 0xf;
949 }
950 switch (name) {
951 case 0x2: /* String */
952 cfg->vpd.vpd_ident = malloc(remain + 1,
953 M_DEVBUF, M_WAITOK);
954 i = 0;
955 state = 1;
956 break;
957 case 0xf: /* End */
958 state = -1;
959 break;
960 case 0x10: /* VPD-R */
961 alloc = 8;
962 off = 0;
963 cfg->vpd.vpd_ros = malloc(alloc *
964 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
965 M_WAITOK | M_ZERO);
966 state = 2;
967 break;
968 case 0x11: /* VPD-W */
969 alloc = 8;
970 off = 0;
971 cfg->vpd.vpd_w = malloc(alloc *
972 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
973 M_WAITOK | M_ZERO);
974 state = 5;
975 break;
976 default: /* Invalid data, abort */
977 state = -1;
978 break;
979 }
980 break;
981
982 case 1: /* Identifier String */
983 cfg->vpd.vpd_ident[i++] = byte;
984 remain--;
985 if (remain == 0) {
986 cfg->vpd.vpd_ident[i] = '\0';
987 state = 0;
988 }
989 break;
990
991 case 2: /* VPD-R Keyword Header */
992 if (off == alloc) {
993 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
994 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
995 M_DEVBUF, M_WAITOK | M_ZERO);
996 }
997 cfg->vpd.vpd_ros[off].keyword[0] = byte;
998 if (vpd_nextbyte(&vrs, &byte2)) {
999 state = -2;
1000 break;
1001 }
1002 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1003 if (vpd_nextbyte(&vrs, &byte2)) {
1004 state = -2;
1005 break;
1006 }
1007 cfg->vpd.vpd_ros[off].len = dflen = byte2;
1008 if (dflen == 0 &&
1009 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1010 2) == 0) {
1011 /*
1012 * if this happens, we can't trust the rest
1013 * of the VPD.
1014 */
1015 pci_printf(cfg, "bad keyword length: %d\n",
1016 dflen);
1017 cksumvalid = 0;
1018 state = -1;
1019 break;
1020 } else if (dflen == 0) {
1021 cfg->vpd.vpd_ros[off].value = malloc(1 *
1022 sizeof(*cfg->vpd.vpd_ros[off].value),
1023 M_DEVBUF, M_WAITOK);
1024 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1025 } else
1026 cfg->vpd.vpd_ros[off].value = malloc(
1027 (dflen + 1) *
1028 sizeof(*cfg->vpd.vpd_ros[off].value),
1029 M_DEVBUF, M_WAITOK);
1030 remain -= 3;
1031 i = 0;
1032 /* keep in sync w/ state 3's transistions */
1033 if (dflen == 0 && remain == 0)
1034 state = 0;
1035 else if (dflen == 0)
1036 state = 2;
1037 else
1038 state = 3;
1039 break;
1040
1041 case 3: /* VPD-R Keyword Value */
1042 cfg->vpd.vpd_ros[off].value[i++] = byte;
1043 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1044 "RV", 2) == 0 && cksumvalid == -1) {
1045 if (vrs.cksum == 0)
1046 cksumvalid = 1;
1047 else {
1048 if (bootverbose)
1049 pci_printf(cfg,
1050 "bad VPD cksum, remain %hhu\n",
1051 vrs.cksum);
1052 cksumvalid = 0;
1053 state = -1;
1054 break;
1055 }
1056 }
1057 dflen--;
1058 remain--;
1059 /* keep in sync w/ state 2's transistions */
1060 if (dflen == 0)
1061 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1062 if (dflen == 0 && remain == 0) {
1063 cfg->vpd.vpd_rocnt = off;
1064 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
1065 off * sizeof(*cfg->vpd.vpd_ros),
1066 M_DEVBUF, M_WAITOK | M_ZERO);
1067 state = 0;
1068 } else if (dflen == 0)
1069 state = 2;
1070 break;
1071
1072 case 4:
1073 remain--;
1074 if (remain == 0)
1075 state = 0;
1076 break;
1077
1078 case 5: /* VPD-W Keyword Header */
1079 if (off == alloc) {
1080 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1081 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1082 M_DEVBUF, M_WAITOK | M_ZERO);
1083 }
1084 cfg->vpd.vpd_w[off].keyword[0] = byte;
1085 if (vpd_nextbyte(&vrs, &byte2)) {
1086 state = -2;
1087 break;
1088 }
1089 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1090 if (vpd_nextbyte(&vrs, &byte2)) {
1091 state = -2;
1092 break;
1093 }
1094 cfg->vpd.vpd_w[off].len = dflen = byte2;
1095 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1096 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
1097 sizeof(*cfg->vpd.vpd_w[off].value),
1098 M_DEVBUF, M_WAITOK);
1099 remain -= 3;
1100 i = 0;
1101 /* keep in sync w/ state 6's transistions */
1102 if (dflen == 0 && remain == 0)
1103 state = 0;
1104 else if (dflen == 0)
1105 state = 5;
1106 else
1107 state = 6;
1108 break;
1109
1110 case 6: /* VPD-W Keyword Value */
1111 cfg->vpd.vpd_w[off].value[i++] = byte;
1112 dflen--;
1113 remain--;
1114 /* keep in sync w/ state 5's transistions */
1115 if (dflen == 0)
1116 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1117 if (dflen == 0 && remain == 0) {
1118 cfg->vpd.vpd_wcnt = off;
1119 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1120 off * sizeof(*cfg->vpd.vpd_w),
1121 M_DEVBUF, M_WAITOK | M_ZERO);
1122 state = 0;
1123 } else if (dflen == 0)
1124 state = 5;
1125 break;
1126
1127 default:
1128 pci_printf(cfg, "invalid state: %d\n", state);
1129 state = -1;
1130 break;
1131 }
1132 }
1133
1134 if (cksumvalid == 0 || state < -1) {
1135 /* read-only data bad, clean up */
1136 if (cfg->vpd.vpd_ros != NULL) {
1137 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1138 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1139 free(cfg->vpd.vpd_ros, M_DEVBUF);
1140 cfg->vpd.vpd_ros = NULL;
1141 }
1142 }
1143 if (state < -1) {
1144 /* I/O error, clean up */
1145 pci_printf(cfg, "failed to read VPD data.\n");
1146 if (cfg->vpd.vpd_ident != NULL) {
1147 free(cfg->vpd.vpd_ident, M_DEVBUF);
1148 cfg->vpd.vpd_ident = NULL;
1149 }
1150 if (cfg->vpd.vpd_w != NULL) {
1151 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1152 free(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1153 free(cfg->vpd.vpd_w, M_DEVBUF);
1154 cfg->vpd.vpd_w = NULL;
1155 }
1156 }
1157 cfg->vpd.vpd_cached = 1;
1158#undef REG
1159#undef WREG
1160}
1161
1162int
1163pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1164{
1165 struct pci_devinfo *dinfo = device_get_ivars(child);
1166 pcicfgregs *cfg = &dinfo->cfg;
1167
1168 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1169 pci_read_vpd(device_get_parent(dev), cfg);
1170
1171 *identptr = cfg->vpd.vpd_ident;
1172
1173 if (*identptr == NULL)
1174 return (ENXIO);
1175
1176 return (0);
1177}
1178
1179int
1180pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1181 const char **vptr)
1182{
1183 struct pci_devinfo *dinfo = device_get_ivars(child);
1184 pcicfgregs *cfg = &dinfo->cfg;
1185 int i;
1186
1187 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1188 pci_read_vpd(device_get_parent(dev), cfg);
1189
1190 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1191 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1192 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1193 *vptr = cfg->vpd.vpd_ros[i].value;
1194 return (0);
1195 }
1196
1197 *vptr = NULL;
1198 return (ENXIO);
1199}
1200
1201struct pcicfg_vpd *
1202pci_fetch_vpd_list(device_t dev)
1203{
1204 struct pci_devinfo *dinfo = device_get_ivars(dev);
1205 pcicfgregs *cfg = &dinfo->cfg;
1206
1207 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1208 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg);
1209 return (&cfg->vpd);
1210}
1211
1212/*
1213 * Find the requested HyperTransport capability and return the offset
1214 * in configuration space via the pointer provided. The function
1215 * returns 0 on success and an error code otherwise.
1216 */
1217int
1218pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg)
1219{
1220 int ptr, error;
1221 uint16_t val;
1222
1223 error = pci_find_cap(child, PCIY_HT, &ptr);
1224 if (error)
1225 return (error);
1226
1227 /*
1228 * Traverse the capabilities list checking each HT capability
1229 * to see if it matches the requested HT capability.
1230 */
1231 while (ptr != 0) {
1232 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2);
1233 if (capability == PCIM_HTCAP_SLAVE ||
1234 capability == PCIM_HTCAP_HOST)
1235 val &= 0xe000;
1236 else
1237 val &= PCIM_HTCMD_CAP_MASK;
1238 if (val == capability) {
1239 if (capreg != NULL)
1240 *capreg = ptr;
1241 return (0);
1242 }
1243
1244 /* Skip to the next HT capability. */
1245 while (ptr != 0) {
1246 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1247 if (pci_read_config(child, ptr + PCICAP_ID, 1) ==
1248 PCIY_HT)
1249 break;
1250 }
1251 }
1252 return (ENOENT);
1253}
1254
1255/*
1256 * Find the requested capability and return the offset in
1257 * configuration space via the pointer provided. The function returns
1258 * 0 on success and an error code otherwise.
1259 */
1260int
1261pci_find_cap_method(device_t dev, device_t child, int capability,
1262 int *capreg)
1263{
1264 struct pci_devinfo *dinfo = device_get_ivars(child);
1265 pcicfgregs *cfg = &dinfo->cfg;
1266 u_int32_t status;
1267 u_int8_t ptr;
1268
1269 /*
1270 * Check the CAP_LIST bit of the PCI status register first.
1271 */
1272 status = pci_read_config(child, PCIR_STATUS, 2);
1273 if (!(status & PCIM_STATUS_CAPPRESENT))
1274 return (ENXIO);
1275
1276 /*
1277 * Determine the start pointer of the capabilities list.
1278 */
1279 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1280 case PCIM_HDRTYPE_NORMAL:
1281 case PCIM_HDRTYPE_BRIDGE:
1282 ptr = PCIR_CAP_PTR;
1283 break;
1284 case PCIM_HDRTYPE_CARDBUS:
1285 ptr = PCIR_CAP_PTR_2;
1286 break;
1287 default:
1288 /* XXX: panic? */
1289 return (ENXIO); /* no extended capabilities support */
1290 }
1291 ptr = pci_read_config(child, ptr, 1);
1292
1293 /*
1294 * Traverse the capabilities list.
1295 */
1296 while (ptr != 0) {
1297 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1298 if (capreg != NULL)
1299 *capreg = ptr;
1300 return (0);
1301 }
1302 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1303 }
1304
1305 return (ENOENT);
1306}
1307
1308/*
1309 * Find the requested extended capability and return the offset in
1310 * configuration space via the pointer provided. The function returns
1311 * 0 on success and an error code otherwise.
1312 */
1313int
1314pci_find_extcap_method(device_t dev, device_t child, int capability,
1315 int *capreg)
1316{
1317 struct pci_devinfo *dinfo = device_get_ivars(child);
1318 pcicfgregs *cfg = &dinfo->cfg;
1319 uint32_t ecap;
1320 uint16_t ptr;
1321
1322 /* Only supported for PCI-express devices. */
1323 if (cfg->pcie.pcie_location == 0)
1324 return (ENXIO);
1325
1326 ptr = PCIR_EXTCAP;
1327 ecap = pci_read_config(child, ptr, 4);
1328 if (ecap == 0xffffffff || ecap == 0)
1329 return (ENOENT);
1330 for (;;) {
1331 if (PCI_EXTCAP_ID(ecap) == capability) {
1332 if (capreg != NULL)
1333 *capreg = ptr;
1334 return (0);
1335 }
1336 ptr = PCI_EXTCAP_NEXTPTR(ecap);
1337 if (ptr == 0)
1338 break;
1339 ecap = pci_read_config(child, ptr, 4);
1340 }
1341
1342 return (ENOENT);
1343}
1344
1345/*
1346 * Support for MSI-X message interrupts.
1347 */
1348void
1349pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1350{
1351 struct pci_devinfo *dinfo = device_get_ivars(dev);
1352 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1353 uint32_t offset;
1354
1355 KASSERT(msix->msix_table_len > index, ("bogus index"));
1356 offset = msix->msix_table_offset + index * 16;
1357 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1358 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1359 bus_write_4(msix->msix_table_res, offset + 8, data);
1360
1361 /* Enable MSI -> HT mapping. */
1362 pci_ht_map_msi(dev, address);
1363}
1364
1365void
1366pci_mask_msix(device_t dev, u_int index)
1367{
1368 struct pci_devinfo *dinfo = device_get_ivars(dev);
1369 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1370 uint32_t offset, val;
1371
1372 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1373 offset = msix->msix_table_offset + index * 16 + 12;
1374 val = bus_read_4(msix->msix_table_res, offset);
1375 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1376 val |= PCIM_MSIX_VCTRL_MASK;
1377 bus_write_4(msix->msix_table_res, offset, val);
1378 }
1379}
1380
1381void
1382pci_unmask_msix(device_t dev, u_int index)
1383{
1384 struct pci_devinfo *dinfo = device_get_ivars(dev);
1385 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1386 uint32_t offset, val;
1387
1388 KASSERT(msix->msix_table_len > index, ("bogus index"));
1389 offset = msix->msix_table_offset + index * 16 + 12;
1390 val = bus_read_4(msix->msix_table_res, offset);
1391 if (val & PCIM_MSIX_VCTRL_MASK) {
1392 val &= ~PCIM_MSIX_VCTRL_MASK;
1393 bus_write_4(msix->msix_table_res, offset, val);
1394 }
1395}
1396
1397int
1398pci_pending_msix(device_t dev, u_int index)
1399{
1400 struct pci_devinfo *dinfo = device_get_ivars(dev);
1401 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1402 uint32_t offset, bit;
1403
1404 KASSERT(msix->msix_table_len > index, ("bogus index"));
1405 offset = msix->msix_pba_offset + (index / 32) * 4;
1406 bit = 1 << index % 32;
1407 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1408}
1409
1410/*
1411 * Restore MSI-X registers and table during resume. If MSI-X is
1412 * enabled then walk the virtual table to restore the actual MSI-X
1413 * table.
1414 */
1415static void
1416pci_resume_msix(device_t dev)
1417{
1418 struct pci_devinfo *dinfo = device_get_ivars(dev);
1419 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1420 struct msix_table_entry *mte;
1421 struct msix_vector *mv;
1422 int i;
1423
1424 if (msix->msix_alloc > 0) {
1425 /* First, mask all vectors. */
1426 for (i = 0; i < msix->msix_msgnum; i++)
1427 pci_mask_msix(dev, i);
1428
1429 /* Second, program any messages with at least one handler. */
1430 for (i = 0; i < msix->msix_table_len; i++) {
1431 mte = &msix->msix_table[i];
1432 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1433 continue;
1434 mv = &msix->msix_vectors[mte->mte_vector - 1];
1435 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1436 pci_unmask_msix(dev, i);
1437 }
1438 }
1439 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1440 msix->msix_ctrl, 2);
1441}
1442
1443/*
1444 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1445 * returned in *count. After this function returns, each message will be
1446 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1447 */
1448int
1449pci_alloc_msix_method(device_t dev, device_t child, int *count)
1450{
1451 struct pci_devinfo *dinfo = device_get_ivars(child);
1452 pcicfgregs *cfg = &dinfo->cfg;
1453 struct resource_list_entry *rle;
1454 int actual, error, i, irq, max;
1455
1456 /* Don't let count == 0 get us into trouble. */
1457 if (*count == 0)
1458 return (EINVAL);
1459
1460 /* If rid 0 is allocated, then fail. */
1461 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1462 if (rle != NULL && rle->res != NULL)
1463 return (ENXIO);
1464
1465 /* Already have allocated messages? */
1466 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1467 return (ENXIO);
1468
1469 /* If MSI-X is blacklisted for this system, fail. */
1470 if (pci_msix_blacklisted())
1471 return (ENXIO);
1472
1473 /* MSI-X capability present? */
1474 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1475 return (ENODEV);
1476
1477 /* Make sure the appropriate BARs are mapped. */
1478 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1479 cfg->msix.msix_table_bar);
1480 if (rle == NULL || rle->res == NULL ||
1481 !(rman_get_flags(rle->res) & RF_ACTIVE))
1482 return (ENXIO);
1483 cfg->msix.msix_table_res = rle->res;
1484 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1485 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1486 cfg->msix.msix_pba_bar);
1487 if (rle == NULL || rle->res == NULL ||
1488 !(rman_get_flags(rle->res) & RF_ACTIVE))
1489 return (ENXIO);
1490 }
1491 cfg->msix.msix_pba_res = rle->res;
1492
1493 if (bootverbose)
1494 device_printf(child,
1495 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1496 *count, cfg->msix.msix_msgnum);
1497 max = min(*count, cfg->msix.msix_msgnum);
1498 for (i = 0; i < max; i++) {
1499 /* Allocate a message. */
1500 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1501 if (error) {
1502 if (i == 0)
1503 return (error);
1504 break;
1505 }
1506 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1507 irq, 1);
1508 }
1509 actual = i;
1510
1511 if (bootverbose) {
1512 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1513 if (actual == 1)
1514 device_printf(child, "using IRQ %lu for MSI-X\n",
1515 rle->start);
1516 else {
1517 int run;
1518
1519 /*
1520 * Be fancy and try to print contiguous runs of
1521 * IRQ values as ranges. 'irq' is the previous IRQ.
1522 * 'run' is true if we are in a range.
1523 */
1524 device_printf(child, "using IRQs %lu", rle->start);
1525 irq = rle->start;
1526 run = 0;
1527 for (i = 1; i < actual; i++) {
1528 rle = resource_list_find(&dinfo->resources,
1529 SYS_RES_IRQ, i + 1);
1530
1531 /* Still in a run? */
1532 if (rle->start == irq + 1) {
1533 run = 1;
1534 irq++;
1535 continue;
1536 }
1537
1538 /* Finish previous range. */
1539 if (run) {
1540 printf("-%d", irq);
1541 run = 0;
1542 }
1543
1544 /* Start new range. */
1545 printf(",%lu", rle->start);
1546 irq = rle->start;
1547 }
1548
1549 /* Unfinished range? */
1550 if (run)
1551 printf("-%d", irq);
1552 printf(" for MSI-X\n");
1553 }
1554 }
1555
1556 /* Mask all vectors. */
1557 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1558 pci_mask_msix(child, i);
1559
1560 /* Allocate and initialize vector data and virtual table. */
1561 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
1562 M_DEVBUF, M_WAITOK | M_ZERO);
1563 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
1564 M_DEVBUF, M_WAITOK | M_ZERO);
1565 for (i = 0; i < actual; i++) {
1566 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1567 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1568 cfg->msix.msix_table[i].mte_vector = i + 1;
1569 }
1570
1571 /* Update control register to enable MSI-X. */
1572 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1573 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1574 cfg->msix.msix_ctrl, 2);
1575
1576 /* Update counts of alloc'd messages. */
1577 cfg->msix.msix_alloc = actual;
1578 cfg->msix.msix_table_len = actual;
1579 *count = actual;
1580 return (0);
1581}
1582
1583/*
1584 * By default, pci_alloc_msix() will assign the allocated IRQ
1585 * resources consecutively to the first N messages in the MSI-X table.
1586 * However, device drivers may want to use different layouts if they
1587 * either receive fewer messages than they asked for, or they wish to
1588 * populate the MSI-X table sparsely. This method allows the driver
1589 * to specify what layout it wants. It must be called after a
1590 * successful pci_alloc_msix() but before any of the associated
1591 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1592 *
1593 * The 'vectors' array contains 'count' message vectors. The array
1594 * maps directly to the MSI-X table in that index 0 in the array
1595 * specifies the vector for the first message in the MSI-X table, etc.
1596 * The vector value in each array index can either be 0 to indicate
1597 * that no vector should be assigned to a message slot, or it can be a
1598 * number from 1 to N (where N is the count returned from a
1599 * succcessful call to pci_alloc_msix()) to indicate which message
1600 * vector (IRQ) to be used for the corresponding message.
1601 *
1602 * On successful return, each message with a non-zero vector will have
1603 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1604 * 1. Additionally, if any of the IRQs allocated via the previous
1605 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1606 * will be freed back to the system automatically.
1607 *
1608 * For example, suppose a driver has a MSI-X table with 6 messages and
1609 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1610 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1611 * C. After the call to pci_alloc_msix(), the device will be setup to
1612 * have an MSI-X table of ABC--- (where - means no vector assigned).
1613 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 },
1614 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1615 * be freed back to the system. This device will also have valid
1616 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1617 *
1618 * In any case, the SYS_RES_IRQ rid X will always map to the message
1619 * at MSI-X table index X - 1 and will only be valid if a vector is
1620 * assigned to that table entry.
1621 */
1622int
1623pci_remap_msix_method(device_t dev, device_t child, int count,
1624 const u_int *vectors)
1625{
1626 struct pci_devinfo *dinfo = device_get_ivars(child);
1627 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1628 struct resource_list_entry *rle;
1629 int i, irq, j, *used;
1630
1631 /*
1632 * Have to have at least one message in the table but the
1633 * table can't be bigger than the actual MSI-X table in the
1634 * device.
1635 */
1636 if (count == 0 || count > msix->msix_msgnum)
1637 return (EINVAL);
1638
1639 /* Sanity check the vectors. */
1640 for (i = 0; i < count; i++)
1641 if (vectors[i] > msix->msix_alloc)
1642 return (EINVAL);
1643
1644 /*
1645 * Make sure there aren't any holes in the vectors to be used.
1646 * It's a big pain to support it, and it doesn't really make
1647 * sense anyway. Also, at least one vector must be used.
1648 */
1649 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1650 M_ZERO);
1651 for (i = 0; i < count; i++)
1652 if (vectors[i] != 0)
1653 used[vectors[i] - 1] = 1;
1654 for (i = 0; i < msix->msix_alloc - 1; i++)
1655 if (used[i] == 0 && used[i + 1] == 1) {
1656 free(used, M_DEVBUF);
1657 return (EINVAL);
1658 }
1659 if (used[0] != 1) {
1660 free(used, M_DEVBUF);
1661 return (EINVAL);
1662 }
1663
1664 /* Make sure none of the resources are allocated. */
1665 for (i = 0; i < msix->msix_table_len; i++) {
1666 if (msix->msix_table[i].mte_vector == 0)
1667 continue;
1668 if (msix->msix_table[i].mte_handlers > 0)
1669 return (EBUSY);
1670 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1671 KASSERT(rle != NULL, ("missing resource"));
1672 if (rle->res != NULL)
1673 return (EBUSY);
1674 }
1675
1676 /* Free the existing resource list entries. */
1677 for (i = 0; i < msix->msix_table_len; i++) {
1678 if (msix->msix_table[i].mte_vector == 0)
1679 continue;
1680 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1681 }
1682
1683 /*
1684 * Build the new virtual table keeping track of which vectors are
1685 * used.
1686 */
1687 free(msix->msix_table, M_DEVBUF);
1688 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count,
1689 M_DEVBUF, M_WAITOK | M_ZERO);
1690 for (i = 0; i < count; i++)
1691 msix->msix_table[i].mte_vector = vectors[i];
1692 msix->msix_table_len = count;
1693
1694 /* Free any unused IRQs and resize the vectors array if necessary. */
1695 j = msix->msix_alloc - 1;
1696 if (used[j] == 0) {
1697 struct msix_vector *vec;
1698
1699 while (used[j] == 0) {
1700 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1701 msix->msix_vectors[j].mv_irq);
1702 j--;
1703 }
1704 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1705 M_WAITOK);
1706 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1707 (j + 1));
1708 free(msix->msix_vectors, M_DEVBUF);
1709 msix->msix_vectors = vec;
1710 msix->msix_alloc = j + 1;
1711 }
1712 free(used, M_DEVBUF);
1713
1714 /* Map the IRQs onto the rids. */
1715 for (i = 0; i < count; i++) {
1716 if (vectors[i] == 0)
1717 continue;
1718 irq = msix->msix_vectors[vectors[i]].mv_irq;
1719 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1720 irq, 1);
1721 }
1722
1723 if (bootverbose) {
1724 device_printf(child, "Remapped MSI-X IRQs as: ");
1725 for (i = 0; i < count; i++) {
1726 if (i != 0)
1727 printf(", ");
1728 if (vectors[i] == 0)
1729 printf("---");
1730 else
1731 printf("%d",
1732 msix->msix_vectors[vectors[i]].mv_irq);
1733 }
1734 printf("\n");
1735 }
1736
1737 return (0);
1738}
1739
1740static int
1741pci_release_msix(device_t dev, device_t child)
1742{
1743 struct pci_devinfo *dinfo = device_get_ivars(child);
1744 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1745 struct resource_list_entry *rle;
1746 int i;
1747
1748 /* Do we have any messages to release? */
1749 if (msix->msix_alloc == 0)
1750 return (ENODEV);
1751
1752 /* Make sure none of the resources are allocated. */
1753 for (i = 0; i < msix->msix_table_len; i++) {
1754 if (msix->msix_table[i].mte_vector == 0)
1755 continue;
1756 if (msix->msix_table[i].mte_handlers > 0)
1757 return (EBUSY);
1758 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1759 KASSERT(rle != NULL, ("missing resource"));
1760 if (rle->res != NULL)
1761 return (EBUSY);
1762 }
1763
1764 /* Update control register to disable MSI-X. */
1765 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1766 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1767 msix->msix_ctrl, 2);
1768
1769 /* Free the resource list entries. */
1770 for (i = 0; i < msix->msix_table_len; i++) {
1771 if (msix->msix_table[i].mte_vector == 0)
1772 continue;
1773 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1774 }
1775 free(msix->msix_table, M_DEVBUF);
1776 msix->msix_table_len = 0;
1777
1778 /* Release the IRQs. */
1779 for (i = 0; i < msix->msix_alloc; i++)
1780 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1781 msix->msix_vectors[i].mv_irq);
1782 free(msix->msix_vectors, M_DEVBUF);
1783 msix->msix_alloc = 0;
1784 return (0);
1785}
1786
1787/*
1788 * Return the max supported MSI-X messages this device supports.
1789 * Basically, assuming the MD code can alloc messages, this function
1790 * should return the maximum value that pci_alloc_msix() can return.
1791 * Thus, it is subject to the tunables, etc.
1792 */
1793int
1794pci_msix_count_method(device_t dev, device_t child)
1795{
1796 struct pci_devinfo *dinfo = device_get_ivars(child);
1797 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1798
1799 if (pci_do_msix && msix->msix_location != 0)
1800 return (msix->msix_msgnum);
1801 return (0);
1802}
1803
1804/*
1805 * HyperTransport MSI mapping control
1806 */
1807void
1808pci_ht_map_msi(device_t dev, uint64_t addr)
1809{
1810 struct pci_devinfo *dinfo = device_get_ivars(dev);
1811 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1812
1813 if (!ht->ht_msimap)
1814 return;
1815
1816 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1817 ht->ht_msiaddr >> 20 == addr >> 20) {
1818 /* Enable MSI -> HT mapping. */
1819 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1820 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1821 ht->ht_msictrl, 2);
1822 }
1823
1824 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1825 /* Disable MSI -> HT mapping. */
1826 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1827 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1828 ht->ht_msictrl, 2);
1829 }
1830}
1831
1832int
1833pci_get_max_read_req(device_t dev)
1834{
1835 struct pci_devinfo *dinfo = device_get_ivars(dev);
1836 int cap;
1837 uint16_t val;
1838
1839 cap = dinfo->cfg.pcie.pcie_location;
1840 if (cap == 0)
1841 return (0);
1842 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
1843 val &= PCIEM_CTL_MAX_READ_REQUEST;
1844 val >>= 12;
1845 return (1 << (val + 7));
1846}
1847
1848int
1849pci_set_max_read_req(device_t dev, int size)
1850{
1851 struct pci_devinfo *dinfo = device_get_ivars(dev);
1852 int cap;
1853 uint16_t val;
1854
1855 cap = dinfo->cfg.pcie.pcie_location;
1856 if (cap == 0)
1857 return (0);
1858 if (size < 128)
1859 size = 128;
1860 if (size > 4096)
1861 size = 4096;
1862 size = (1 << (fls(size) - 1));
1863 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
1864 val &= ~PCIEM_CTL_MAX_READ_REQUEST;
1865 val |= (fls(size) - 8) << 12;
1866 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2);
1867 return (size);
1868}
1869
1870/*
1871 * Support for MSI message signalled interrupts.
1872 */
1873void
1874pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1875{
1876 struct pci_devinfo *dinfo = device_get_ivars(dev);
1877 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1878
1879 /* Write data and address values. */
1880 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1881 address & 0xffffffff, 4);
1882 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1883 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1884 address >> 32, 4);
1885 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1886 data, 2);
1887 } else
1888 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1889 2);
1890
1891 /* Enable MSI in the control register. */
1892 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1893 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1894 2);
1895
1896 /* Enable MSI -> HT mapping. */
1897 pci_ht_map_msi(dev, address);
1898}
1899
1900void
1901pci_disable_msi(device_t dev)
1902{
1903 struct pci_devinfo *dinfo = device_get_ivars(dev);
1904 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1905
1906 /* Disable MSI -> HT mapping. */
1907 pci_ht_map_msi(dev, 0);
1908
1909 /* Disable MSI in the control register. */
1910 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1911 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1912 2);
1913}
1914
1915/*
1916 * Restore MSI registers during resume. If MSI is enabled then
1917 * restore the data and address registers in addition to the control
1918 * register.
1919 */
1920static void
1921pci_resume_msi(device_t dev)
1922{
1923 struct pci_devinfo *dinfo = device_get_ivars(dev);
1924 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1925 uint64_t address;
1926 uint16_t data;
1927
1928 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1929 address = msi->msi_addr;
1930 data = msi->msi_data;
1931 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1932 address & 0xffffffff, 4);
1933 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1934 pci_write_config(dev, msi->msi_location +
1935 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1936 pci_write_config(dev, msi->msi_location +
1937 PCIR_MSI_DATA_64BIT, data, 2);
1938 } else
1939 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1940 data, 2);
1941 }
1942 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1943 2);
1944}
1945
1946static int
1947pci_remap_intr_method(device_t bus, device_t dev, u_int irq)
1948{
1949 struct pci_devinfo *dinfo = device_get_ivars(dev);
1950 pcicfgregs *cfg = &dinfo->cfg;
1951 struct resource_list_entry *rle;
1952 struct msix_table_entry *mte;
1953 struct msix_vector *mv;
1954 uint64_t addr;
1955 uint32_t data;
1956 int error, i, j;
1957
1958 /*
1959 * Handle MSI first. We try to find this IRQ among our list
1960 * of MSI IRQs. If we find it, we request updated address and
1961 * data registers and apply the results.
1962 */
1963 if (cfg->msi.msi_alloc > 0) {
1964
1965 /* If we don't have any active handlers, nothing to do. */
1966 if (cfg->msi.msi_handlers == 0)
1967 return (0);
1968 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1969 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1970 i + 1);
1971 if (rle->start == irq) {
1972 error = PCIB_MAP_MSI(device_get_parent(bus),
1973 dev, irq, &addr, &data);
1974 if (error)
1975 return (error);
1976 pci_disable_msi(dev);
1977 dinfo->cfg.msi.msi_addr = addr;
1978 dinfo->cfg.msi.msi_data = data;
1979 pci_enable_msi(dev, addr, data);
1980 return (0);
1981 }
1982 }
1983 return (ENOENT);
1984 }
1985
1986 /*
1987 * For MSI-X, we check to see if we have this IRQ. If we do,
1988 * we request the updated mapping info. If that works, we go
1989 * through all the slots that use this IRQ and update them.
1990 */
1991 if (cfg->msix.msix_alloc > 0) {
1992 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1993 mv = &cfg->msix.msix_vectors[i];
1994 if (mv->mv_irq == irq) {
1995 error = PCIB_MAP_MSI(device_get_parent(bus),
1996 dev, irq, &addr, &data);
1997 if (error)
1998 return (error);
1999 mv->mv_address = addr;
2000 mv->mv_data = data;
2001 for (j = 0; j < cfg->msix.msix_table_len; j++) {
2002 mte = &cfg->msix.msix_table[j];
2003 if (mte->mte_vector != i + 1)
2004 continue;
2005 if (mte->mte_handlers == 0)
2006 continue;
2007 pci_mask_msix(dev, j);
2008 pci_enable_msix(dev, j, addr, data);
2009 pci_unmask_msix(dev, j);
2010 }
2011 }
2012 }
2013 return (ENOENT);
2014 }
2015
2016 return (ENOENT);
2017}
2018
2019/*
2020 * Returns true if the specified device is blacklisted because MSI
2021 * doesn't work.
2022 */
2023int
2024pci_msi_device_blacklisted(device_t dev)
2025{
2026
2027 if (!pci_honor_msi_blacklist)
2028 return (0);
2029
2030 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI));
2031}
2032
2033/*
2034 * Determine if MSI is blacklisted globally on this system. Currently,
2035 * we just check for blacklisted chipsets as represented by the
2036 * host-PCI bridge at device 0:0:0. In the future, it may become
2037 * necessary to check other system attributes, such as the kenv values
2038 * that give the motherboard manufacturer and model number.
2039 */
2040static int
2041pci_msi_blacklisted(void)
2042{
2043 device_t dev;
2044
2045 if (!pci_honor_msi_blacklist)
2046 return (0);
2047
2048 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2049 if (!(pcie_chipset || pcix_chipset)) {
2050 if (vm_guest != VM_GUEST_NO) {
2051 /*
2052 * Whitelist older chipsets in virtual
2053 * machines known to support MSI.
2054 */
2055 dev = pci_find_bsf(0, 0, 0);
2056 if (dev != NULL)
2057 return (!pci_has_quirk(pci_get_devid(dev),
2058 PCI_QUIRK_ENABLE_MSI_VM));
2059 }
2060 return (1);
2061 }
2062
2063 dev = pci_find_bsf(0, 0, 0);
2064 if (dev != NULL)
2065 return (pci_msi_device_blacklisted(dev));
2066 return (0);
2067}
2068
2069/*
2070 * Returns true if the specified device is blacklisted because MSI-X
2071 * doesn't work. Note that this assumes that if MSI doesn't work,
2072 * MSI-X doesn't either.
2073 */
2074int
2075pci_msix_device_blacklisted(device_t dev)
2076{
2077
2078 if (!pci_honor_msi_blacklist)
2079 return (0);
2080
2081 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX))
2082 return (1);
2083
2084 return (pci_msi_device_blacklisted(dev));
2085}
2086
2087/*
2088 * Determine if MSI-X is blacklisted globally on this system. If MSI
2089 * is blacklisted, assume that MSI-X is as well. Check for additional
2090 * chipsets where MSI works but MSI-X does not.
2091 */
2092static int
2093pci_msix_blacklisted(void)
2094{
2095 device_t dev;
2096
2097 if (!pci_honor_msi_blacklist)
2098 return (0);
2099
2100 dev = pci_find_bsf(0, 0, 0);
2101 if (dev != NULL && pci_has_quirk(pci_get_devid(dev),
2102 PCI_QUIRK_DISABLE_MSIX))
2103 return (1);
2104
2105 return (pci_msi_blacklisted());
2106}
2107
2108/*
2109 * Attempt to allocate *count MSI messages. The actual number allocated is
2110 * returned in *count. After this function returns, each message will be
2111 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2112 */
2113int
2114pci_alloc_msi_method(device_t dev, device_t child, int *count)
2115{
2116 struct pci_devinfo *dinfo = device_get_ivars(child);
2117 pcicfgregs *cfg = &dinfo->cfg;
2118 struct resource_list_entry *rle;
2119 int actual, error, i, irqs[32];
2120 uint16_t ctrl;
2121
2122 /* Don't let count == 0 get us into trouble. */
2123 if (*count == 0)
2124 return (EINVAL);
2125
2126 /* If rid 0 is allocated, then fail. */
2127 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2128 if (rle != NULL && rle->res != NULL)
2129 return (ENXIO);
2130
2131 /* Already have allocated messages? */
2132 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2133 return (ENXIO);
2134
2135 /* If MSI is blacklisted for this system, fail. */
2136 if (pci_msi_blacklisted())
2137 return (ENXIO);
2138
2139 /* MSI capability present? */
2140 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2141 return (ENODEV);
2142
2143 if (bootverbose)
2144 device_printf(child,
2145 "attempting to allocate %d MSI vectors (%d supported)\n",
2146 *count, cfg->msi.msi_msgnum);
2147
2148 /* Don't ask for more than the device supports. */
2149 actual = min(*count, cfg->msi.msi_msgnum);
2150
2151 /* Don't ask for more than 32 messages. */
2152 actual = min(actual, 32);
2153
2154 /* MSI requires power of 2 number of messages. */
2155 if (!powerof2(actual))
2156 return (EINVAL);
2157
2158 for (;;) {
2159 /* Try to allocate N messages. */
2160 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2161 actual, irqs);
2162 if (error == 0)
2163 break;
2164 if (actual == 1)
2165 return (error);
2166
2167 /* Try N / 2. */
2168 actual >>= 1;
2169 }
2170
2171 /*
2172 * We now have N actual messages mapped onto SYS_RES_IRQ
2173 * resources in the irqs[] array, so add new resources
2174 * starting at rid 1.
2175 */
2176 for (i = 0; i < actual; i++)
2177 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2178 irqs[i], irqs[i], 1);
2179
2180 if (bootverbose) {
2181 if (actual == 1)
2182 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2183 else {
2184 int run;
2185
2186 /*
2187 * Be fancy and try to print contiguous runs
2188 * of IRQ values as ranges. 'run' is true if
2189 * we are in a range.
2190 */
2191 device_printf(child, "using IRQs %d", irqs[0]);
2192 run = 0;
2193 for (i = 1; i < actual; i++) {
2194
2195 /* Still in a run? */
2196 if (irqs[i] == irqs[i - 1] + 1) {
2197 run = 1;
2198 continue;
2199 }
2200
2201 /* Finish previous range. */
2202 if (run) {
2203 printf("-%d", irqs[i - 1]);
2204 run = 0;
2205 }
2206
2207 /* Start new range. */
2208 printf(",%d", irqs[i]);
2209 }
2210
2211 /* Unfinished range? */
2212 if (run)
2213 printf("-%d", irqs[actual - 1]);
2214 printf(" for MSI\n");
2215 }
2216 }
2217
2218 /* Update control register with actual count. */
2219 ctrl = cfg->msi.msi_ctrl;
2220 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2221 ctrl |= (ffs(actual) - 1) << 4;
2222 cfg->msi.msi_ctrl = ctrl;
2223 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2224
2225 /* Update counts of alloc'd messages. */
2226 cfg->msi.msi_alloc = actual;
2227 cfg->msi.msi_handlers = 0;
2228 *count = actual;
2229 return (0);
2230}
2231
2232/* Release the MSI messages associated with this device. */
2233int
2234pci_release_msi_method(device_t dev, device_t child)
2235{
2236 struct pci_devinfo *dinfo = device_get_ivars(child);
2237 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2238 struct resource_list_entry *rle;
2239 int error, i, irqs[32];
2240
2241 /* Try MSI-X first. */
2242 error = pci_release_msix(dev, child);
2243 if (error != ENODEV)
2244 return (error);
2245
2246 /* Do we have any messages to release? */
2247 if (msi->msi_alloc == 0)
2248 return (ENODEV);
2249 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2250
2251 /* Make sure none of the resources are allocated. */
2252 if (msi->msi_handlers > 0)
2253 return (EBUSY);
2254 for (i = 0; i < msi->msi_alloc; i++) {
2255 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2256 KASSERT(rle != NULL, ("missing MSI resource"));
2257 if (rle->res != NULL)
2258 return (EBUSY);
2259 irqs[i] = rle->start;
2260 }
2261
2262 /* Update control register with 0 count. */
2263 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2264 ("%s: MSI still enabled", __func__));
2265 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2266 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2267 msi->msi_ctrl, 2);
2268
2269 /* Release the messages. */
2270 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2271 for (i = 0; i < msi->msi_alloc; i++)
2272 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2273
2274 /* Update alloc count. */
2275 msi->msi_alloc = 0;
2276 msi->msi_addr = 0;
2277 msi->msi_data = 0;
2278 return (0);
2279}
2280
2281/*
2282 * Return the max supported MSI messages this device supports.
2283 * Basically, assuming the MD code can alloc messages, this function
2284 * should return the maximum value that pci_alloc_msi() can return.
2285 * Thus, it is subject to the tunables, etc.
2286 */
2287int
2288pci_msi_count_method(device_t dev, device_t child)
2289{
2290 struct pci_devinfo *dinfo = device_get_ivars(child);
2291 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2292
2293 if (pci_do_msi && msi->msi_location != 0)
2294 return (msi->msi_msgnum);
2295 return (0);
2296}
2297
2298/* free pcicfgregs structure and all depending data structures */
2299
2300int
2301pci_freecfg(struct pci_devinfo *dinfo)
2302{
2303 struct devlist *devlist_head;
2304 struct pci_map *pm, *next;
2305 int i;
2306
2307 devlist_head = &pci_devq;
2308
2309 if (dinfo->cfg.vpd.vpd_reg) {
2310 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2311 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2312 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2313 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2314 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2315 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2316 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2317 }
2318 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) {
2319 free(pm, M_DEVBUF);
2320 }
2321 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2322 free(dinfo, M_DEVBUF);
2323
2324 /* increment the generation count */
2325 pci_generation++;
2326
2327 /* we're losing one device */
2328 pci_numdevs--;
2329 return (0);
2330}
2331
2332/*
2333 * PCI power manangement
2334 */
2335int
2336pci_set_powerstate_method(device_t dev, device_t child, int state)
2337{
2338 struct pci_devinfo *dinfo = device_get_ivars(child);
2339 pcicfgregs *cfg = &dinfo->cfg;
2340 uint16_t status;
2341 int result, oldstate, highest, delay;
2342
2343 if (cfg->pp.pp_cap == 0)
2344 return (EOPNOTSUPP);
2345
2346 /*
2347 * Optimize a no state change request away. While it would be OK to
2348 * write to the hardware in theory, some devices have shown odd
2349 * behavior when going from D3 -> D3.
2350 */
2351 oldstate = pci_get_powerstate(child);
2352 if (oldstate == state)
2353 return (0);
2354
2355 /*
2356 * The PCI power management specification states that after a state
2357 * transition between PCI power states, system software must
2358 * guarantee a minimal delay before the function accesses the device.
2359 * Compute the worst case delay that we need to guarantee before we
2360 * access the device. Many devices will be responsive much more
2361 * quickly than this delay, but there are some that don't respond
2362 * instantly to state changes. Transitions to/from D3 state require
2363 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2364 * is done below with DELAY rather than a sleeper function because
2365 * this function can be called from contexts where we cannot sleep.
2366 */
2367 highest = (oldstate > state) ? oldstate : state;
2368 if (highest == PCI_POWERSTATE_D3)
2369 delay = 10000;
2370 else if (highest == PCI_POWERSTATE_D2)
2371 delay = 200;
2372 else
2373 delay = 0;
2374 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2375 & ~PCIM_PSTAT_DMASK;
2376 result = 0;
2377 switch (state) {
2378 case PCI_POWERSTATE_D0:
2379 status |= PCIM_PSTAT_D0;
2380 break;
2381 case PCI_POWERSTATE_D1:
2382 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2383 return (EOPNOTSUPP);
2384 status |= PCIM_PSTAT_D1;
2385 break;
2386 case PCI_POWERSTATE_D2:
2387 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2388 return (EOPNOTSUPP);
2389 status |= PCIM_PSTAT_D2;
2390 break;
2391 case PCI_POWERSTATE_D3:
2392 status |= PCIM_PSTAT_D3;
2393 break;
2394 default:
2395 return (EINVAL);
2396 }
2397
2398 if (bootverbose)
2399 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate,
2400 state);
2401
2402 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2403 if (delay)
2404 DELAY(delay);
2405 return (0);
2406}
2407
2408int
2409pci_get_powerstate_method(device_t dev, device_t child)
2410{
2411 struct pci_devinfo *dinfo = device_get_ivars(child);
2412 pcicfgregs *cfg = &dinfo->cfg;
2413 uint16_t status;
2414 int result;
2415
2416 if (cfg->pp.pp_cap != 0) {
2417 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2418 switch (status & PCIM_PSTAT_DMASK) {
2419 case PCIM_PSTAT_D0:
2420 result = PCI_POWERSTATE_D0;
2421 break;
2422 case PCIM_PSTAT_D1:
2423 result = PCI_POWERSTATE_D1;
2424 break;
2425 case PCIM_PSTAT_D2:
2426 result = PCI_POWERSTATE_D2;
2427 break;
2428 case PCIM_PSTAT_D3:
2429 result = PCI_POWERSTATE_D3;
2430 break;
2431 default:
2432 result = PCI_POWERSTATE_UNKNOWN;
2433 break;
2434 }
2435 } else {
2436 /* No support, device is always at D0 */
2437 result = PCI_POWERSTATE_D0;
2438 }
2439 return (result);
2440}
2441
2442/*
2443 * Some convenience functions for PCI device drivers.
2444 */
2445
2446static __inline void
2447pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2448{
2449 uint16_t command;
2450
2451 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2452 command |= bit;
2453 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2454}
2455
2456static __inline void
2457pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2458{
2459 uint16_t command;
2460
2461 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2462 command &= ~bit;
2463 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2464}
2465
2466int
2467pci_enable_busmaster_method(device_t dev, device_t child)
2468{
2469 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2470 return (0);
2471}
2472
2473int
2474pci_disable_busmaster_method(device_t dev, device_t child)
2475{
2476 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2477 return (0);
2478}
2479
2480int
2481pci_enable_io_method(device_t dev, device_t child, int space)
2482{
2483 uint16_t bit;
2484
2485 switch(space) {
2486 case SYS_RES_IOPORT:
2487 bit = PCIM_CMD_PORTEN;
2488 break;
2489 case SYS_RES_MEMORY:
2490 bit = PCIM_CMD_MEMEN;
2491 break;
2492 default:
2493 return (EINVAL);
2494 }
2495 pci_set_command_bit(dev, child, bit);
2496 return (0);
2497}
2498
2499int
2500pci_disable_io_method(device_t dev, device_t child, int space)
2501{
2502 uint16_t bit;
2503
2504 switch(space) {
2505 case SYS_RES_IOPORT:
2506 bit = PCIM_CMD_PORTEN;
2507 break;
2508 case SYS_RES_MEMORY:
2509 bit = PCIM_CMD_MEMEN;
2510 break;
2511 default:
2512 return (EINVAL);
2513 }
2514 pci_clear_command_bit(dev, child, bit);
2515 return (0);
2516}
2517
2518/*
2519 * New style pci driver. Parent device is either a pci-host-bridge or a
2520 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2521 */
2522
2523void
2524pci_print_verbose(struct pci_devinfo *dinfo)
2525{
2526
2527 if (bootverbose) {
2528 pcicfgregs *cfg = &dinfo->cfg;
2529
2530 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2531 cfg->vendor, cfg->device, cfg->revid);
2532 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2533 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2534 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2535 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2536 cfg->mfdev);
2537 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2538 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2539 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2540 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2541 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2542 if (cfg->intpin > 0)
2543 printf("\tintpin=%c, irq=%d\n",
2544 cfg->intpin +'a' -1, cfg->intline);
2545 if (cfg->pp.pp_cap) {
2546 uint16_t status;
2547
2548 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2549 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2550 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2551 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2552 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2553 status & PCIM_PSTAT_DMASK);
2554 }
2555 if (cfg->msi.msi_location) {
2556 int ctrl;
2557
2558 ctrl = cfg->msi.msi_ctrl;
2559 printf("\tMSI supports %d message%s%s%s\n",
2560 cfg->msi.msi_msgnum,
2561 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2562 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2563 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2564 }
2565 if (cfg->msix.msix_location) {
2566 printf("\tMSI-X supports %d message%s ",
2567 cfg->msix.msix_msgnum,
2568 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2569 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2570 printf("in map 0x%x\n",
2571 cfg->msix.msix_table_bar);
2572 else
2573 printf("in maps 0x%x and 0x%x\n",
2574 cfg->msix.msix_table_bar,
2575 cfg->msix.msix_pba_bar);
2576 }
2577 }
2578}
2579
2580static int
2581pci_porten(device_t dev)
2582{
2583 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
2584}
2585
2586static int
2587pci_memen(device_t dev)
2588{
2589 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
2590}
2591
2592static void
2593pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp)
2594{
2595 struct pci_devinfo *dinfo;
2596 pci_addr_t map, testval;
2597 int ln2range;
2598 uint16_t cmd;
2599
2600 /*
2601 * The device ROM BAR is special. It is always a 32-bit
2602 * memory BAR. Bit 0 is special and should not be set when
2603 * sizing the BAR.
2604 */
2605 dinfo = device_get_ivars(dev);
2606 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) {
2607 map = pci_read_config(dev, reg, 4);
2608 pci_write_config(dev, reg, 0xfffffffe, 4);
2609 testval = pci_read_config(dev, reg, 4);
2610 pci_write_config(dev, reg, map, 4);
2611 *mapp = map;
2612 *testvalp = testval;
2613 return;
2614 }
2615
2616 map = pci_read_config(dev, reg, 4);
2617 ln2range = pci_maprange(map);
2618 if (ln2range == 64)
2619 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2620
2621 /*
2622 * Disable decoding via the command register before
2623 * determining the BAR's length since we will be placing it in
2624 * a weird state.
2625 */
2626 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2627 pci_write_config(dev, PCIR_COMMAND,
2628 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
2629
2630 /*
2631 * Determine the BAR's length by writing all 1's. The bottom
2632 * log_2(size) bits of the BAR will stick as 0 when we read
2633 * the value back.
2634 */
2635 pci_write_config(dev, reg, 0xffffffff, 4);
2636 testval = pci_read_config(dev, reg, 4);
2637 if (ln2range == 64) {
2638 pci_write_config(dev, reg + 4, 0xffffffff, 4);
2639 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2640 }
2641
2642 /*
2643 * Restore the original value of the BAR. We may have reprogrammed
2644 * the BAR of the low-level console device and when booting verbose,
2645 * we need the console device addressable.
2646 */
2647 pci_write_config(dev, reg, map, 4);
2648 if (ln2range == 64)
2649 pci_write_config(dev, reg + 4, map >> 32, 4);
2650 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2651
2652 *mapp = map;
2653 *testvalp = testval;
2654}
2655
2656static void
2657pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base)
2658{
2659 struct pci_devinfo *dinfo;
2660 int ln2range;
2661
2662 /* The device ROM BAR is always a 32-bit memory BAR. */
2663 dinfo = device_get_ivars(dev);
2664 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
2665 ln2range = 32;
2666 else
2667 ln2range = pci_maprange(pm->pm_value);
2668 pci_write_config(dev, pm->pm_reg, base, 4);
2669 if (ln2range == 64)
2670 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4);
2671 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4);
2672 if (ln2range == 64)
2673 pm->pm_value |= (pci_addr_t)pci_read_config(dev,
2674 pm->pm_reg + 4, 4) << 32;
2675}
2676
2677struct pci_map *
2678pci_find_bar(device_t dev, int reg)
2679{
2680 struct pci_devinfo *dinfo;
2681 struct pci_map *pm;
2682
2683 dinfo = device_get_ivars(dev);
2684 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
2685 if (pm->pm_reg == reg)
2686 return (pm);
2687 }
2688 return (NULL);
2689}
2690
2691int
2692pci_bar_enabled(device_t dev, struct pci_map *pm)
2693{
2694 struct pci_devinfo *dinfo;
2695 uint16_t cmd;
2696
2697 dinfo = device_get_ivars(dev);
2698 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) &&
2699 !(pm->pm_value & PCIM_BIOS_ENABLE))
2700 return (0);
2701 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2702 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value))
2703 return ((cmd & PCIM_CMD_MEMEN) != 0);
2704 else
2705 return ((cmd & PCIM_CMD_PORTEN) != 0);
2706}
2707
2708static struct pci_map *
2709pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size)
2710{
2711 struct pci_devinfo *dinfo;
2712 struct pci_map *pm, *prev;
2713
2714 dinfo = device_get_ivars(dev);
2715 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO);
2716 pm->pm_reg = reg;
2717 pm->pm_value = value;
2718 pm->pm_size = size;
2719 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) {
2720 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x",
2721 reg));
2722 if (STAILQ_NEXT(prev, pm_link) == NULL ||
2723 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg)
2724 break;
2725 }
2726 if (prev != NULL)
2727 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link);
2728 else
2729 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link);
2730 return (pm);
2731}
2732
2733static void
2734pci_restore_bars(device_t dev)
2735{
2736 struct pci_devinfo *dinfo;
2737 struct pci_map *pm;
2738 int ln2range;
2739
2740 dinfo = device_get_ivars(dev);
2741 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
2742 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
2743 ln2range = 32;
2744 else
2745 ln2range = pci_maprange(pm->pm_value);
2746 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4);
2747 if (ln2range == 64)
2748 pci_write_config(dev, pm->pm_reg + 4,
2749 pm->pm_value >> 32, 4);
2750 }
2751}
2752
2753/*
2754 * Add a resource based on a pci map register. Return 1 if the map
2755 * register is a 32bit map register or 2 if it is a 64bit register.
2756 */
2757static int
2758pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
2759 int force, int prefetch)
2760{
2761 struct pci_map *pm;
2762 pci_addr_t base, map, testval;
2763 pci_addr_t start, end, count;
2764 int barlen, basezero, flags, maprange, mapsize, type;
2765 uint16_t cmd;
2766 struct resource *res;
2767
2768 /*
2769 * The BAR may already exist if the device is a CardBus card
2770 * whose CIS is stored in this BAR.
2771 */
2772 pm = pci_find_bar(dev, reg);
2773 if (pm != NULL) {
2774 maprange = pci_maprange(pm->pm_value);
2775 barlen = maprange == 64 ? 2 : 1;
2776 return (barlen);
2777 }
2778
2779 pci_read_bar(dev, reg, &map, &testval);
2780 if (PCI_BAR_MEM(map)) {
2781 type = SYS_RES_MEMORY;
2782 if (map & PCIM_BAR_MEM_PREFETCH)
2783 prefetch = 1;
2784 } else
2785 type = SYS_RES_IOPORT;
2786 mapsize = pci_mapsize(testval);
2787 base = pci_mapbase(map);
2788#ifdef __PCI_BAR_ZERO_VALID
2789 basezero = 0;
2790#else
2791 basezero = base == 0;
2792#endif
2793 maprange = pci_maprange(map);
2794 barlen = maprange == 64 ? 2 : 1;
2795
2796 /*
2797 * For I/O registers, if bottom bit is set, and the next bit up
2798 * isn't clear, we know we have a BAR that doesn't conform to the
2799 * spec, so ignore it. Also, sanity check the size of the data
2800 * areas to the type of memory involved. Memory must be at least
2801 * 16 bytes in size, while I/O ranges must be at least 4.
2802 */
2803 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2804 return (barlen);
2805 if ((type == SYS_RES_MEMORY && mapsize < 4) ||
2806 (type == SYS_RES_IOPORT && mapsize < 2))
2807 return (barlen);
2808
2809 /* Save a record of this BAR. */
2810 pm = pci_add_bar(dev, reg, map, mapsize);
2811 if (bootverbose) {
2812 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2813 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
2814 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2815 printf(", port disabled\n");
2816 else if (type == SYS_RES_MEMORY && !pci_memen(dev))
2817 printf(", memory disabled\n");
2818 else
2819 printf(", enabled\n");
2820 }
2821
2822 /*
2823 * If base is 0, then we have problems if this architecture does
2824 * not allow that. It is best to ignore such entries for the
2825 * moment. These will be allocated later if the driver specifically
2826 * requests them. However, some removable busses look better when
2827 * all resources are allocated, so allow '0' to be overriden.
2828 *
2829 * Similarly treat maps whose values is the same as the test value
2830 * read back. These maps have had all f's written to them by the
2831 * BIOS in an attempt to disable the resources.
2832 */
2833 if (!force && (basezero || map == testval))
2834 return (barlen);
2835 if ((u_long)base != base) {
2836 device_printf(bus,
2837 "pci%d:%d:%d:%d bar %#x too many address bits",
2838 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
2839 pci_get_function(dev), reg);
2840 return (barlen);
2841 }
2842
2843 /*
2844 * This code theoretically does the right thing, but has
2845 * undesirable side effects in some cases where peripherals
2846 * respond oddly to having these bits enabled. Let the user
2847 * be able to turn them off (since pci_enable_io_modes is 1 by
2848 * default).
2849 */
2850 if (pci_enable_io_modes) {
2851 /* Turn on resources that have been left off by a lazy BIOS */
2852 if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
2853 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2854 cmd |= PCIM_CMD_PORTEN;
2855 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2856 }
2857 if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
2858 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2859 cmd |= PCIM_CMD_MEMEN;
2860 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2861 }
2862 } else {
2863 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2864 return (barlen);
2865 if (type == SYS_RES_MEMORY && !pci_memen(dev))
2866 return (barlen);
2867 }
2868
2869 count = (pci_addr_t)1 << mapsize;
2870 flags = RF_ALIGNMENT_LOG2(mapsize);
2871 if (prefetch)
2872 flags |= RF_PREFETCHABLE;
2873 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) {
2874 start = 0; /* Let the parent decide. */
2875 end = ~0ul;
2876 } else {
2877 start = base;
2878 end = base + count - 1;
2879 }
2880 resource_list_add(rl, type, reg, start, end, count);
2881
2882 /*
2883 * Try to allocate the resource for this BAR from our parent
2884 * so that this resource range is already reserved. The
2885 * driver for this device will later inherit this resource in
2886 * pci_alloc_resource().
2887 */
2888 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count,
2889 flags);
2890 if (pci_do_realloc_bars && res == NULL && (start != 0 || end != ~0ul)) {
2891 /*
2892 * If the allocation fails, try to allocate a resource for
2893 * this BAR using any available range. The firmware felt
2894 * it was important enough to assign a resource, so don't
2895 * disable decoding if we can help it.
2896 */
2897 resource_list_delete(rl, type, reg);
2898 resource_list_add(rl, type, reg, 0, ~0ul, count);
2899 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0ul,
2900 count, flags);
2901 }
2902 if (res == NULL) {
2903 /*
2904 * If the allocation fails, delete the resource list entry
2905 * and disable decoding for this device.
2906 *
2907 * If the driver requests this resource in the future,
2908 * pci_reserve_map() will try to allocate a fresh
2909 * resource range.
2910 */
2911 resource_list_delete(rl, type, reg);
2912 pci_disable_io(dev, type);
2913 if (bootverbose)
2914 device_printf(bus,
2915 "pci%d:%d:%d:%d bar %#x failed to allocate\n",
2916 pci_get_domain(dev), pci_get_bus(dev),
2917 pci_get_slot(dev), pci_get_function(dev), reg);
2918 } else {
2919 start = rman_get_start(res);
2920 pci_write_bar(dev, pm, start);
2921 }
2922 return (barlen);
2923}
2924
2925/*
2926 * For ATA devices we need to decide early what addressing mode to use.
2927 * Legacy demands that the primary and secondary ATA ports sits on the
2928 * same addresses that old ISA hardware did. This dictates that we use
2929 * those addresses and ignore the BAR's if we cannot set PCI native
2930 * addressing mode.
2931 */
2932static void
2933pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
2934 uint32_t prefetchmask)
2935{
2936 struct resource *r;
2937 int rid, type, progif;
2938#if 0
2939 /* if this device supports PCI native addressing use it */
2940 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2941 if ((progif & 0x8a) == 0x8a) {
2942 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2943 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2944 printf("Trying ATA native PCI addressing mode\n");
2945 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2946 }
2947 }
2948#endif
2949 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2950 type = SYS_RES_IOPORT;
2951 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2952 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
2953 prefetchmask & (1 << 0));
2954 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
2955 prefetchmask & (1 << 1));
2956 } else {
2957 rid = PCIR_BAR(0);
2958 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2959 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0,
2960 0x1f7, 8, 0);
2961 rid = PCIR_BAR(1);
2962 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2963 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6,
2964 0x3f6, 1, 0);
2965 }
2966 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2967 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
2968 prefetchmask & (1 << 2));
2969 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
2970 prefetchmask & (1 << 3));
2971 } else {
2972 rid = PCIR_BAR(2);
2973 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2974 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x170,
2975 0x177, 8, 0);
2976 rid = PCIR_BAR(3);
2977 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2978 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x376,
2979 0x376, 1, 0);
2980 }
2981 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
2982 prefetchmask & (1 << 4));
2983 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
2984 prefetchmask & (1 << 5));
2985}
2986
2987static void
2988pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2989{
2990 struct pci_devinfo *dinfo = device_get_ivars(dev);
2991 pcicfgregs *cfg = &dinfo->cfg;
2992 char tunable_name[64];
2993 int irq;
2994
2995 /* Has to have an intpin to have an interrupt. */
2996 if (cfg->intpin == 0)
2997 return;
2998
2999 /* Let the user override the IRQ with a tunable. */
3000 irq = PCI_INVALID_IRQ;
3001 snprintf(tunable_name, sizeof(tunable_name),
3002 "hw.pci%d.%d.%d.INT%c.irq",
3003 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
3004 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
3005 irq = PCI_INVALID_IRQ;
3006
3007 /*
3008 * If we didn't get an IRQ via the tunable, then we either use the
3009 * IRQ value in the intline register or we ask the bus to route an
3010 * interrupt for us. If force_route is true, then we only use the
3011 * value in the intline register if the bus was unable to assign an
3012 * IRQ.
3013 */
3014 if (!PCI_INTERRUPT_VALID(irq)) {
3015 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
3016 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
3017 if (!PCI_INTERRUPT_VALID(irq))
3018 irq = cfg->intline;
3019 }
3020
3021 /* If after all that we don't have an IRQ, just bail. */
3022 if (!PCI_INTERRUPT_VALID(irq))
3023 return;
3024
3025 /* Update the config register if it changed. */
3026 if (irq != cfg->intline) {
3027 cfg->intline = irq;
3028 pci_write_config(dev, PCIR_INTLINE, irq, 1);
3029 }
3030
3031 /* Add this IRQ as rid 0 interrupt resource. */
3032 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
3033}
3034
3035/* Perform early OHCI takeover from SMM. */
3036static void
3037ohci_early_takeover(device_t self)
3038{
3039 struct resource *res;
3040 uint32_t ctl;
3041 int rid;
3042 int i;
3043
3044 rid = PCIR_BAR(0);
3045 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3046 if (res == NULL)
3047 return;
3048
3049 ctl = bus_read_4(res, OHCI_CONTROL);
3050 if (ctl & OHCI_IR) {
3051 if (bootverbose)
3052 printf("ohci early: "
3053 "SMM active, request owner change\n");
3054 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);
3055 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) {
3056 DELAY(1000);
3057 ctl = bus_read_4(res, OHCI_CONTROL);
3058 }
3059 if (ctl & OHCI_IR) {
3060 if (bootverbose)
3061 printf("ohci early: "
3062 "SMM does not respond, resetting\n");
3063 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);
3064 }
3065 /* Disable interrupts */
3066 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
3067 }
3068
3069 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3070}
3071
3072/* Perform early UHCI takeover from SMM. */
3073static void
3074uhci_early_takeover(device_t self)
3075{
3076 struct resource *res;
3077 int rid;
3078
3079 /*
3080 * Set the PIRQD enable bit and switch off all the others. We don't
3081 * want legacy support to interfere with us XXX Does this also mean
3082 * that the BIOS won't touch the keyboard anymore if it is connected
3083 * to the ports of the root hub?
3084 */
3085 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2);
3086
3087 /* Disable interrupts */
3088 rid = PCI_UHCI_BASE_REG;
3089 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE);
3090 if (res != NULL) {
3091 bus_write_2(res, UHCI_INTR, 0);
3092 bus_release_resource(self, SYS_RES_IOPORT, rid, res);
3093 }
3094}
3095
3096/* Perform early EHCI takeover from SMM. */
3097static void
3098ehci_early_takeover(device_t self)
3099{
3100 struct resource *res;
3101 uint32_t cparams;
3102 uint32_t eec;
3103 uint8_t eecp;
3104 uint8_t bios_sem;
3105 uint8_t offs;
3106 int rid;
3107 int i;
3108
3109 rid = PCIR_BAR(0);
3110 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3111 if (res == NULL)
3112 return;
3113
3114 cparams = bus_read_4(res, EHCI_HCCPARAMS);
3115
3116 /* Synchronise with the BIOS if it owns the controller. */
3117 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0;
3118 eecp = EHCI_EECP_NEXT(eec)) {
3119 eec = pci_read_config(self, eecp, 4);
3120 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) {
3121 continue;
3122 }
3123 bios_sem = pci_read_config(self, eecp +
3124 EHCI_LEGSUP_BIOS_SEM, 1);
3125 if (bios_sem == 0) {
3126 continue;
3127 }
3128 if (bootverbose)
3129 printf("ehci early: "
3130 "SMM active, request owner change\n");
3131
3132 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1);
3133
3134 for (i = 0; (i < 100) && (bios_sem != 0); i++) {
3135 DELAY(1000);
3136 bios_sem = pci_read_config(self, eecp +
3137 EHCI_LEGSUP_BIOS_SEM, 1);
3138 }
3139
3140 if (bios_sem != 0) {
3141 if (bootverbose)
3142 printf("ehci early: "
3143 "SMM does not respond\n");
3144 }
3145 /* Disable interrupts */
3146 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION));
3147 bus_write_4(res, offs + EHCI_USBINTR, 0);
3148 }
3149 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3150}
3151
3152/* Perform early XHCI takeover from SMM. */
3153static void
3154xhci_early_takeover(device_t self)
3155{
3156 struct resource *res;
3157 uint32_t cparams;
3158 uint32_t eec;
3159 uint8_t eecp;
3160 uint8_t bios_sem;
3161 uint8_t offs;
3162 int rid;
3163 int i;
3164
3165 rid = PCIR_BAR(0);
3166 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3167 if (res == NULL)
3168 return;
3169
3170 cparams = bus_read_4(res, XHCI_HCSPARAMS0);
3171
3172 eec = -1;
3173
3174 /* Synchronise with the BIOS if it owns the controller. */
3175 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
3176 eecp += XHCI_XECP_NEXT(eec) << 2) {
3177 eec = bus_read_4(res, eecp);
3178
3179 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
3180 continue;
3181
3182 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM);
3183 if (bios_sem == 0)
3184 continue;
3185
3186 if (bootverbose)
3187 printf("xhci early: "
3188 "SMM active, request owner change\n");
3189
3190 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1);
3191
3192 /* wait a maximum of 5 second */
3193
3194 for (i = 0; (i < 5000) && (bios_sem != 0); i++) {
3195 DELAY(1000);
3196 bios_sem = bus_read_1(res, eecp +
3197 XHCI_XECP_BIOS_SEM);
3198 }
3199
3200 if (bios_sem != 0) {
3201 if (bootverbose)
3202 printf("xhci early: "
3203 "SMM does not respond\n");
3204 }
3205
3206 /* Disable interrupts */
3207 offs = bus_read_1(res, XHCI_CAPLENGTH);
3208 bus_write_4(res, offs + XHCI_USBCMD, 0);
3209 bus_read_4(res, offs + XHCI_USBSTS);
3210 }
3211 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3212}
3213
|
| 3214#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
3215static void
3216pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg,
3217 struct resource_list *rl)
3218{
3219 struct resource *res;
3220 char *cp;
3221 u_long start, end, count;
3222 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus;
3223
3224 switch (cfg->hdrtype & PCIM_HDRTYPE) {
3225 case PCIM_HDRTYPE_BRIDGE:
3226 sec_reg = PCIR_SECBUS_1;
3227 sub_reg = PCIR_SUBBUS_1;
3228 break;
3229 case PCIM_HDRTYPE_CARDBUS:
3230 sec_reg = PCIR_SECBUS_2;
3231 sub_reg = PCIR_SUBBUS_2;
3232 break;
3233 default:
3234 return;
3235 }
3236
3237 /*
3238 * If the existing bus range is valid, attempt to reserve it
3239 * from our parent. If this fails for any reason, clear the
3240 * secbus and subbus registers.
3241 *
3242 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus?
3243 * This would at least preserve the existing sec_bus if it is
3244 * valid.
3245 */
3246 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1);
3247 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1);
3248
3249 /* Quirk handling. */
3250 switch (pci_get_devid(dev)) {
3251 case 0x12258086: /* Intel 82454KX/GX (Orion) */
3252 sup_bus = pci_read_config(dev, 0x41, 1);
3253 if (sup_bus != 0xff) {
3254 sec_bus = sup_bus + 1;
3255 sub_bus = sup_bus + 1;
3256 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1);
3257 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1);
3258 }
3259 break;
3260
3261 case 0x00dd10de:
3262 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
3263 if ((cp = getenv("smbios.planar.maker")) == NULL)
3264 break;
3265 if (strncmp(cp, "Compal", 6) != 0) {
3266 freeenv(cp);
3267 break;
3268 }
3269 freeenv(cp);
3270 if ((cp = getenv("smbios.planar.product")) == NULL)
3271 break;
3272 if (strncmp(cp, "08A0", 4) != 0) {
3273 freeenv(cp);
3274 break;
3275 }
3276 freeenv(cp);
3277 if (sub_bus < 0xa) {
3278 sub_bus = 0xa;
3279 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1);
3280 }
3281 break;
3282 }
3283
3284 if (bootverbose)
3285 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus);
3286 if (sec_bus > 0 && sub_bus >= sec_bus) {
3287 start = sec_bus;
3288 end = sub_bus;
3289 count = end - start + 1;
3290
3291 resource_list_add(rl, PCI_RES_BUS, 0, 0ul, ~0ul, count);
3292
3293 /*
3294 * If requested, clear secondary bus registers in
3295 * bridge devices to force a complete renumbering
3296 * rather than reserving the existing range. However,
3297 * preserve the existing size.
3298 */
3299 if (pci_clear_buses)
3300 goto clear;
3301
3302 rid = 0;
3303 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid,
3304 start, end, count, 0);
3305 if (res != NULL)
3306 return;
3307
3308 if (bootverbose)
3309 device_printf(bus,
3310 "pci%d:%d:%d:%d secbus failed to allocate\n",
3311 pci_get_domain(dev), pci_get_bus(dev),
3312 pci_get_slot(dev), pci_get_function(dev));
3313 }
3314
3315clear:
3316 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1);
3317 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1);
3318}
3319
3320static struct resource *
3321pci_alloc_secbus(device_t dev, device_t child, int *rid, u_long start,
3322 u_long end, u_long count, u_int flags)
3323{
3324 struct pci_devinfo *dinfo;
3325 pcicfgregs *cfg;
3326 struct resource_list *rl;
3327 struct resource *res;
3328 int sec_reg, sub_reg;
3329
3330 dinfo = device_get_ivars(child);
3331 cfg = &dinfo->cfg;
3332 rl = &dinfo->resources;
3333 switch (cfg->hdrtype & PCIM_HDRTYPE) {
3334 case PCIM_HDRTYPE_BRIDGE:
3335 sec_reg = PCIR_SECBUS_1;
3336 sub_reg = PCIR_SUBBUS_1;
3337 break;
3338 case PCIM_HDRTYPE_CARDBUS:
3339 sec_reg = PCIR_SECBUS_2;
3340 sub_reg = PCIR_SUBBUS_2;
3341 break;
3342 default:
3343 return (NULL);
3344 }
3345
3346 if (*rid != 0)
3347 return (NULL);
3348
3349 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL)
3350 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count);
3351 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) {
3352 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid,
3353 start, end, count, flags & ~RF_ACTIVE);
3354 if (res == NULL) {
3355 resource_list_delete(rl, PCI_RES_BUS, *rid);
3356 device_printf(child, "allocating %lu bus%s failed\n",
3357 count, count == 1 ? "" : "es");
3358 return (NULL);
3359 }
3360 if (bootverbose)
3361 device_printf(child,
3362 "Lazy allocation of %lu bus%s at %lu\n", count,
3363 count == 1 ? "" : "es", rman_get_start(res));
3364 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1);
3365 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1);
3366 }
3367 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start,
3368 end, count, flags));
3369}
3370#endif
3371
|
3200void
3201pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
3202{
3203 struct pci_devinfo *dinfo;
3204 pcicfgregs *cfg;
3205 struct resource_list *rl;
3206 const struct pci_quirk *q;
3207 uint32_t devid;
3208 int i;
3209
3210 dinfo = device_get_ivars(dev);
3211 cfg = &dinfo->cfg;
3212 rl = &dinfo->resources;
3213 devid = (cfg->device << 16) | cfg->vendor;
3214
3215 /* ATA devices needs special map treatment */
3216 if ((pci_get_class(dev) == PCIC_STORAGE) &&
3217 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
3218 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
3219 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
3220 !pci_read_config(dev, PCIR_BAR(2), 4))) )
3221 pci_ata_maps(bus, dev, rl, force, prefetchmask);
3222 else
3223 for (i = 0; i < cfg->nummaps;) {
3224 /*
3225 * Skip quirked resources.
3226 */
3227 for (q = &pci_quirks[0]; q->devid != 0; q++)
3228 if (q->devid == devid &&
3229 q->type == PCI_QUIRK_UNMAP_REG &&
3230 q->arg1 == PCIR_BAR(i))
3231 break;
3232 if (q->devid != 0) {
3233 i++;
3234 continue;
3235 }
3236 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
3237 prefetchmask & (1 << i));
3238 }
3239
3240 /*
3241 * Add additional, quirked resources.
3242 */
3243 for (q = &pci_quirks[0]; q->devid != 0; q++)
3244 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG)
3245 pci_add_map(bus, dev, q->arg1, rl, force, 0);
3246
3247 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
3248#ifdef __PCI_REROUTE_INTERRUPT
3249 /*
3250 * Try to re-route interrupts. Sometimes the BIOS or
3251 * firmware may leave bogus values in these registers.
3252 * If the re-route fails, then just stick with what we
3253 * have.
3254 */
3255 pci_assign_interrupt(bus, dev, 1);
3256#else
3257 pci_assign_interrupt(bus, dev, 0);
3258#endif
3259 }
3260
3261 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
3262 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
3263 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI)
3264 xhci_early_takeover(dev);
3265 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
3266 ehci_early_takeover(dev);
3267 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
3268 ohci_early_takeover(dev);
3269 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
3270 uhci_early_takeover(dev);
3271 }
| 3372void
3373pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
3374{
3375 struct pci_devinfo *dinfo;
3376 pcicfgregs *cfg;
3377 struct resource_list *rl;
3378 const struct pci_quirk *q;
3379 uint32_t devid;
3380 int i;
3381
3382 dinfo = device_get_ivars(dev);
3383 cfg = &dinfo->cfg;
3384 rl = &dinfo->resources;
3385 devid = (cfg->device << 16) | cfg->vendor;
3386
3387 /* ATA devices needs special map treatment */
3388 if ((pci_get_class(dev) == PCIC_STORAGE) &&
3389 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
3390 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
3391 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
3392 !pci_read_config(dev, PCIR_BAR(2), 4))) )
3393 pci_ata_maps(bus, dev, rl, force, prefetchmask);
3394 else
3395 for (i = 0; i < cfg->nummaps;) {
3396 /*
3397 * Skip quirked resources.
3398 */
3399 for (q = &pci_quirks[0]; q->devid != 0; q++)
3400 if (q->devid == devid &&
3401 q->type == PCI_QUIRK_UNMAP_REG &&
3402 q->arg1 == PCIR_BAR(i))
3403 break;
3404 if (q->devid != 0) {
3405 i++;
3406 continue;
3407 }
3408 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
3409 prefetchmask & (1 << i));
3410 }
3411
3412 /*
3413 * Add additional, quirked resources.
3414 */
3415 for (q = &pci_quirks[0]; q->devid != 0; q++)
3416 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG)
3417 pci_add_map(bus, dev, q->arg1, rl, force, 0);
3418
3419 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
3420#ifdef __PCI_REROUTE_INTERRUPT
3421 /*
3422 * Try to re-route interrupts. Sometimes the BIOS or
3423 * firmware may leave bogus values in these registers.
3424 * If the re-route fails, then just stick with what we
3425 * have.
3426 */
3427 pci_assign_interrupt(bus, dev, 1);
3428#else
3429 pci_assign_interrupt(bus, dev, 0);
3430#endif
3431 }
3432
3433 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
3434 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
3435 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI)
3436 xhci_early_takeover(dev);
3437 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
3438 ehci_early_takeover(dev);
3439 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
3440 ohci_early_takeover(dev);
3441 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
3442 uhci_early_takeover(dev);
3443 }
|
| 3444
3445#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
3446 /*
3447 * Reserve resources for secondary bus ranges behind bridge
3448 * devices.
3449 */
3450 pci_reserve_secbus(bus, dev, cfg, rl);
3451#endif
|
3272}
3273
3274void
3275pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
3276{
3277#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
3278 device_t pcib = device_get_parent(dev);
3279 struct pci_devinfo *dinfo;
3280 int maxslots;
3281 int s, f, pcifunchigh;
3282 uint8_t hdrtype;
3283
3284 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
3285 ("dinfo_size too small"));
3286 maxslots = PCIB_MAXSLOTS(pcib);
3287 for (s = 0; s <= maxslots; s++) {
3288 pcifunchigh = 0;
3289 f = 0;
3290 DELAY(1);
3291 hdrtype = REG(PCIR_HDRTYPE, 1);
3292 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
3293 continue;
3294 if (hdrtype & PCIM_MFDEV)
3295 pcifunchigh = PCI_FUNCMAX;
3296 for (f = 0; f <= pcifunchigh; f++) {
3297 dinfo = pci_read_device(pcib, domain, busno, s, f,
3298 dinfo_size);
3299 if (dinfo != NULL) {
3300 pci_add_child(dev, dinfo);
3301 }
3302 }
3303 }
3304#undef REG
3305}
3306
3307void
3308pci_add_child(device_t bus, struct pci_devinfo *dinfo)
3309{
3310 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
3311 device_set_ivars(dinfo->cfg.dev, dinfo);
3312 resource_list_init(&dinfo->resources);
3313 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
3314 pci_cfg_restore(dinfo->cfg.dev, dinfo);
3315 pci_print_verbose(dinfo);
3316 pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
3317}
3318
3319static int
3320pci_probe(device_t dev)
3321{
3322
3323 device_set_desc(dev, "PCI bus");
3324
3325 /* Allow other subclasses to override this driver. */
3326 return (BUS_PROBE_GENERIC);
3327}
3328
3329int
3330pci_attach_common(device_t dev)
3331{
3332 struct pci_softc *sc;
3333 int busno, domain;
3334#ifdef PCI_DMA_BOUNDARY
3335 int error, tag_valid;
3336#endif
| 3452}
3453
3454void
3455pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
3456{
3457#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
3458 device_t pcib = device_get_parent(dev);
3459 struct pci_devinfo *dinfo;
3460 int maxslots;
3461 int s, f, pcifunchigh;
3462 uint8_t hdrtype;
3463
3464 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
3465 ("dinfo_size too small"));
3466 maxslots = PCIB_MAXSLOTS(pcib);
3467 for (s = 0; s <= maxslots; s++) {
3468 pcifunchigh = 0;
3469 f = 0;
3470 DELAY(1);
3471 hdrtype = REG(PCIR_HDRTYPE, 1);
3472 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
3473 continue;
3474 if (hdrtype & PCIM_MFDEV)
3475 pcifunchigh = PCI_FUNCMAX;
3476 for (f = 0; f <= pcifunchigh; f++) {
3477 dinfo = pci_read_device(pcib, domain, busno, s, f,
3478 dinfo_size);
3479 if (dinfo != NULL) {
3480 pci_add_child(dev, dinfo);
3481 }
3482 }
3483 }
3484#undef REG
3485}
3486
3487void
3488pci_add_child(device_t bus, struct pci_devinfo *dinfo)
3489{
3490 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
3491 device_set_ivars(dinfo->cfg.dev, dinfo);
3492 resource_list_init(&dinfo->resources);
3493 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
3494 pci_cfg_restore(dinfo->cfg.dev, dinfo);
3495 pci_print_verbose(dinfo);
3496 pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
3497}
3498
3499static int
3500pci_probe(device_t dev)
3501{
3502
3503 device_set_desc(dev, "PCI bus");
3504
3505 /* Allow other subclasses to override this driver. */
3506 return (BUS_PROBE_GENERIC);
3507}
3508
3509int
3510pci_attach_common(device_t dev)
3511{
3512 struct pci_softc *sc;
3513 int busno, domain;
3514#ifdef PCI_DMA_BOUNDARY
3515 int error, tag_valid;
3516#endif
|
| 3517#ifdef PCI_RES_BUS
3518 int rid;
3519#endif
|
3337
3338 sc = device_get_softc(dev);
3339 domain = pcib_get_domain(dev);
3340 busno = pcib_get_bus(dev);
| 3520
3521 sc = device_get_softc(dev);
3522 domain = pcib_get_domain(dev);
3523 busno = pcib_get_bus(dev);
|
| 3524#ifdef PCI_RES_BUS
3525 rid = 0;
3526 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno,
3527 1, 0);
3528 if (sc->sc_bus == NULL) {
3529 device_printf(dev, "failed to allocate bus number\n");
3530 return (ENXIO);
3531 }
3532#endif
|
3341 if (bootverbose)
3342 device_printf(dev, "domain=%d, physical bus=%d\n",
3343 domain, busno);
3344#ifdef PCI_DMA_BOUNDARY
3345 tag_valid = 0;
3346 if (device_get_devclass(device_get_parent(device_get_parent(dev))) !=
3347 devclass_find("pci")) {
3348 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1,
3349 PCI_DMA_BOUNDARY, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3350 NULL, NULL, BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED,
3351 BUS_SPACE_MAXSIZE, 0, NULL, NULL, &sc->sc_dma_tag);
3352 if (error)
3353 device_printf(dev, "Failed to create DMA tag: %d\n",
3354 error);
3355 else
3356 tag_valid = 1;
3357 }
3358 if (!tag_valid)
3359#endif
3360 sc->sc_dma_tag = bus_get_dma_tag(dev);
3361 return (0);
3362}
3363
3364static int
3365pci_attach(device_t dev)
3366{
3367 int busno, domain, error;
3368
3369 error = pci_attach_common(dev);
3370 if (error)
3371 return (error);
3372
3373 /*
3374 * Since there can be multiple independantly numbered PCI
3375 * busses on systems with multiple PCI domains, we can't use
3376 * the unit number to decide which bus we are probing. We ask
3377 * the parent pcib what our domain and bus numbers are.
3378 */
3379 domain = pcib_get_domain(dev);
3380 busno = pcib_get_bus(dev);
3381 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
3382 return (bus_generic_attach(dev));
3383}
3384
| 3533 if (bootverbose)
3534 device_printf(dev, "domain=%d, physical bus=%d\n",
3535 domain, busno);
3536#ifdef PCI_DMA_BOUNDARY
3537 tag_valid = 0;
3538 if (device_get_devclass(device_get_parent(device_get_parent(dev))) !=
3539 devclass_find("pci")) {
3540 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1,
3541 PCI_DMA_BOUNDARY, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3542 NULL, NULL, BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED,
3543 BUS_SPACE_MAXSIZE, 0, NULL, NULL, &sc->sc_dma_tag);
3544 if (error)
3545 device_printf(dev, "Failed to create DMA tag: %d\n",
3546 error);
3547 else
3548 tag_valid = 1;
3549 }
3550 if (!tag_valid)
3551#endif
3552 sc->sc_dma_tag = bus_get_dma_tag(dev);
3553 return (0);
3554}
3555
3556static int
3557pci_attach(device_t dev)
3558{
3559 int busno, domain, error;
3560
3561 error = pci_attach_common(dev);
3562 if (error)
3563 return (error);
3564
3565 /*
3566 * Since there can be multiple independantly numbered PCI
3567 * busses on systems with multiple PCI domains, we can't use
3568 * the unit number to decide which bus we are probing. We ask
3569 * the parent pcib what our domain and bus numbers are.
3570 */
3571 domain = pcib_get_domain(dev);
3572 busno = pcib_get_bus(dev);
3573 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
3574 return (bus_generic_attach(dev));
3575}
3576
|
| 3577#ifdef PCI_RES_BUS
3578static int
3579pci_detach(device_t dev)
3580{
3581 struct pci_softc *sc;
3582 int error;
3583
3584 error = bus_generic_detach(dev);
3585 if (error)
3586 return (error);
3587 sc = device_get_softc(dev);
3588 return (bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus));
3589}
3590#endif
3591
|
3385static void
3386pci_set_power_children(device_t dev, device_t *devlist, int numdevs,
3387 int state)
3388{
3389 device_t child, pcib;
3390 struct pci_devinfo *dinfo;
3391 int dstate, i;
3392
3393 /*
3394 * Set the device to the given state. If the firmware suggests
3395 * a different power state, use it instead. If power management
3396 * is not present, the firmware is responsible for managing
3397 * device power. Skip children who aren't attached since they
3398 * are handled separately.
3399 */
3400 pcib = device_get_parent(dev);
3401 for (i = 0; i < numdevs; i++) {
3402 child = devlist[i];
3403 dinfo = device_get_ivars(child);
3404 dstate = state;
3405 if (device_is_attached(child) &&
3406 PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0)
3407 pci_set_powerstate(child, dstate);
3408 }
3409}
3410
3411int
3412pci_suspend(device_t dev)
3413{
3414 device_t child, *devlist;
3415 struct pci_devinfo *dinfo;
3416 int error, i, numdevs;
3417
3418 /*
3419 * Save the PCI configuration space for each child and set the
3420 * device in the appropriate power state for this sleep state.
3421 */
3422 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
3423 return (error);
3424 for (i = 0; i < numdevs; i++) {
3425 child = devlist[i];
3426 dinfo = device_get_ivars(child);
3427 pci_cfg_save(child, dinfo, 0);
3428 }
3429
3430 /* Suspend devices before potentially powering them down. */
3431 error = bus_generic_suspend(dev);
3432 if (error) {
3433 free(devlist, M_TEMP);
3434 return (error);
3435 }
3436 if (pci_do_power_suspend)
3437 pci_set_power_children(dev, devlist, numdevs,
3438 PCI_POWERSTATE_D3);
3439 free(devlist, M_TEMP);
3440 return (0);
3441}
3442
3443int
3444pci_resume(device_t dev)
3445{
3446 device_t child, *devlist;
3447 struct pci_devinfo *dinfo;
3448 int error, i, numdevs;
3449
3450 /*
3451 * Set each child to D0 and restore its PCI configuration space.
3452 */
3453 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
3454 return (error);
3455 if (pci_do_power_resume)
3456 pci_set_power_children(dev, devlist, numdevs,
3457 PCI_POWERSTATE_D0);
3458
3459 /* Now the device is powered up, restore its config space. */
3460 for (i = 0; i < numdevs; i++) {
3461 child = devlist[i];
3462 dinfo = device_get_ivars(child);
3463
3464 pci_cfg_restore(child, dinfo);
3465 if (!device_is_attached(child))
3466 pci_cfg_save(child, dinfo, 1);
3467 }
3468
3469 /*
3470 * Resume critical devices first, then everything else later.
3471 */
3472 for (i = 0; i < numdevs; i++) {
3473 child = devlist[i];
3474 switch (pci_get_class(child)) {
3475 case PCIC_DISPLAY:
3476 case PCIC_MEMORY:
3477 case PCIC_BRIDGE:
3478 case PCIC_BASEPERIPH:
3479 DEVICE_RESUME(child);
3480 break;
3481 }
3482 }
3483 for (i = 0; i < numdevs; i++) {
3484 child = devlist[i];
3485 switch (pci_get_class(child)) {
3486 case PCIC_DISPLAY:
3487 case PCIC_MEMORY:
3488 case PCIC_BRIDGE:
3489 case PCIC_BASEPERIPH:
3490 break;
3491 default:
3492 DEVICE_RESUME(child);
3493 }
3494 }
3495 free(devlist, M_TEMP);
3496 return (0);
3497}
3498
3499static void
3500pci_load_vendor_data(void)
3501{
3502 caddr_t data;
3503 void *ptr;
3504 size_t sz;
3505
3506 data = preload_search_by_type("pci_vendor_data");
3507 if (data != NULL) {
3508 ptr = preload_fetch_addr(data);
3509 sz = preload_fetch_size(data);
3510 if (ptr != NULL && sz != 0) {
3511 pci_vendordata = ptr;
3512 pci_vendordata_size = sz;
3513 /* terminate the database */
3514 pci_vendordata[pci_vendordata_size] = '\n';
3515 }
3516 }
3517}
3518
3519void
3520pci_driver_added(device_t dev, driver_t *driver)
3521{
3522 int numdevs;
3523 device_t *devlist;
3524 device_t child;
3525 struct pci_devinfo *dinfo;
3526 int i;
3527
3528 if (bootverbose)
3529 device_printf(dev, "driver added\n");
3530 DEVICE_IDENTIFY(driver, dev);
3531 if (device_get_children(dev, &devlist, &numdevs) != 0)
3532 return;
3533 for (i = 0; i < numdevs; i++) {
3534 child = devlist[i];
3535 if (device_get_state(child) != DS_NOTPRESENT)
3536 continue;
3537 dinfo = device_get_ivars(child);
3538 pci_print_verbose(dinfo);
3539 if (bootverbose)
3540 pci_printf(&dinfo->cfg, "reprobing on driver added\n");
3541 pci_cfg_restore(child, dinfo);
3542 if (device_probe_and_attach(child) != 0)
3543 pci_child_detached(dev, child);
3544 }
3545 free(devlist, M_TEMP);
3546}
3547
3548int
3549pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3550 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep)
3551{
3552 struct pci_devinfo *dinfo;
3553 struct msix_table_entry *mte;
3554 struct msix_vector *mv;
3555 uint64_t addr;
3556 uint32_t data;
3557 void *cookie;
3558 int error, rid;
3559
3560 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
3561 arg, &cookie);
3562 if (error)
3563 return (error);
3564
3565 /* If this is not a direct child, just bail out. */
3566 if (device_get_parent(child) != dev) {
3567 *cookiep = cookie;
3568 return(0);
3569 }
3570
3571 rid = rman_get_rid(irq);
3572 if (rid == 0) {
3573 /* Make sure that INTx is enabled */
3574 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3575 } else {
3576 /*
3577 * Check to see if the interrupt is MSI or MSI-X.
3578 * Ask our parent to map the MSI and give
3579 * us the address and data register values.
3580 * If we fail for some reason, teardown the
3581 * interrupt handler.
3582 */
3583 dinfo = device_get_ivars(child);
3584 if (dinfo->cfg.msi.msi_alloc > 0) {
3585 if (dinfo->cfg.msi.msi_addr == 0) {
3586 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3587 ("MSI has handlers, but vectors not mapped"));
3588 error = PCIB_MAP_MSI(device_get_parent(dev),
3589 child, rman_get_start(irq), &addr, &data);
3590 if (error)
3591 goto bad;
3592 dinfo->cfg.msi.msi_addr = addr;
3593 dinfo->cfg.msi.msi_data = data;
3594 }
3595 if (dinfo->cfg.msi.msi_handlers == 0)
3596 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
3597 dinfo->cfg.msi.msi_data);
3598 dinfo->cfg.msi.msi_handlers++;
3599 } else {
3600 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3601 ("No MSI or MSI-X interrupts allocated"));
3602 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3603 ("MSI-X index too high"));
3604 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3605 KASSERT(mte->mte_vector != 0, ("no message vector"));
3606 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3607 KASSERT(mv->mv_irq == rman_get_start(irq),
3608 ("IRQ mismatch"));
3609 if (mv->mv_address == 0) {
3610 KASSERT(mte->mte_handlers == 0,
3611 ("MSI-X table entry has handlers, but vector not mapped"));
3612 error = PCIB_MAP_MSI(device_get_parent(dev),
3613 child, rman_get_start(irq), &addr, &data);
3614 if (error)
3615 goto bad;
3616 mv->mv_address = addr;
3617 mv->mv_data = data;
3618 }
3619 if (mte->mte_handlers == 0) {
3620 pci_enable_msix(child, rid - 1, mv->mv_address,
3621 mv->mv_data);
3622 pci_unmask_msix(child, rid - 1);
3623 }
3624 mte->mte_handlers++;
3625 }
3626
3627 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3628 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3629 bad:
3630 if (error) {
3631 (void)bus_generic_teardown_intr(dev, child, irq,
3632 cookie);
3633 return (error);
3634 }
3635 }
3636 *cookiep = cookie;
3637 return (0);
3638}
3639
3640int
3641pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3642 void *cookie)
3643{
3644 struct msix_table_entry *mte;
3645 struct resource_list_entry *rle;
3646 struct pci_devinfo *dinfo;
3647 int error, rid;
3648
3649 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3650 return (EINVAL);
3651
3652 /* If this isn't a direct child, just bail out */
3653 if (device_get_parent(child) != dev)
3654 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3655
3656 rid = rman_get_rid(irq);
3657 if (rid == 0) {
3658 /* Mask INTx */
3659 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3660 } else {
3661 /*
3662 * Check to see if the interrupt is MSI or MSI-X. If so,
3663 * decrement the appropriate handlers count and mask the
3664 * MSI-X message, or disable MSI messages if the count
3665 * drops to 0.
3666 */
3667 dinfo = device_get_ivars(child);
3668 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3669 if (rle->res != irq)
3670 return (EINVAL);
3671 if (dinfo->cfg.msi.msi_alloc > 0) {
3672 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3673 ("MSI-X index too high"));
3674 if (dinfo->cfg.msi.msi_handlers == 0)
3675 return (EINVAL);
3676 dinfo->cfg.msi.msi_handlers--;
3677 if (dinfo->cfg.msi.msi_handlers == 0)
3678 pci_disable_msi(child);
3679 } else {
3680 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3681 ("No MSI or MSI-X interrupts allocated"));
3682 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3683 ("MSI-X index too high"));
3684 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3685 if (mte->mte_handlers == 0)
3686 return (EINVAL);
3687 mte->mte_handlers--;
3688 if (mte->mte_handlers == 0)
3689 pci_mask_msix(child, rid - 1);
3690 }
3691 }
3692 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3693 if (rid > 0)
3694 KASSERT(error == 0,
3695 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3696 return (error);
3697}
3698
3699int
3700pci_print_child(device_t dev, device_t child)
3701{
3702 struct pci_devinfo *dinfo;
3703 struct resource_list *rl;
3704 int retval = 0;
3705
3706 dinfo = device_get_ivars(child);
3707 rl = &dinfo->resources;
3708
3709 retval += bus_print_child_header(dev, child);
3710
3711 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3712 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3713 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3714 if (device_get_flags(dev))
3715 retval += printf(" flags %#x", device_get_flags(dev));
3716
3717 retval += printf(" at device %d.%d", pci_get_slot(child),
3718 pci_get_function(child));
3719
3720 retval += bus_print_child_footer(dev, child);
3721
3722 return (retval);
3723}
3724
3725static const struct
3726{
3727 int class;
3728 int subclass;
3729 const char *desc;
3730} pci_nomatch_tab[] = {
3731 {PCIC_OLD, -1, "old"},
3732 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3733 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3734 {PCIC_STORAGE, -1, "mass storage"},
3735 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3736 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3737 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3738 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3739 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3740 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3741 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3742 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3743 {PCIC_STORAGE, PCIS_STORAGE_NVM, "NVM"},
3744 {PCIC_NETWORK, -1, "network"},
3745 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3746 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3747 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3748 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3749 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3750 {PCIC_DISPLAY, -1, "display"},
3751 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3752 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3753 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3754 {PCIC_MULTIMEDIA, -1, "multimedia"},
3755 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3756 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3757 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3758 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3759 {PCIC_MEMORY, -1, "memory"},
3760 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3761 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3762 {PCIC_BRIDGE, -1, "bridge"},
3763 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3764 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3765 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3766 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3767 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3768 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3769 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3770 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3771 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3772 {PCIC_SIMPLECOMM, -1, "simple comms"},
3773 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3774 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3775 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3776 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3777 {PCIC_BASEPERIPH, -1, "base peripheral"},
3778 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3779 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3780 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3781 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3782 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3783 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3784 {PCIC_INPUTDEV, -1, "input device"},
3785 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3786 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3787 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3788 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3789 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3790 {PCIC_DOCKING, -1, "docking station"},
3791 {PCIC_PROCESSOR, -1, "processor"},
3792 {PCIC_SERIALBUS, -1, "serial bus"},
3793 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3794 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3795 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3796 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3797 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3798 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3799 {PCIC_WIRELESS, -1, "wireless controller"},
3800 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3801 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3802 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3803 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3804 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3805 {PCIC_SATCOM, -1, "satellite communication"},
3806 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3807 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3808 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3809 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3810 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3811 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3812 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3813 {PCIC_DASP, -1, "dasp"},
3814 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3815 {0, 0, NULL}
3816};
3817
3818void
3819pci_probe_nomatch(device_t dev, device_t child)
3820{
3821 int i;
3822 const char *cp, *scp;
3823 char *device;
3824
3825 /*
3826 * Look for a listing for this device in a loaded device database.
3827 */
3828 if ((device = pci_describe_device(child)) != NULL) {
3829 device_printf(dev, "<%s>", device);
3830 free(device, M_DEVBUF);
3831 } else {
3832 /*
3833 * Scan the class/subclass descriptions for a general
3834 * description.
3835 */
3836 cp = "unknown";
3837 scp = NULL;
3838 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3839 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3840 if (pci_nomatch_tab[i].subclass == -1) {
3841 cp = pci_nomatch_tab[i].desc;
3842 } else if (pci_nomatch_tab[i].subclass ==
3843 pci_get_subclass(child)) {
3844 scp = pci_nomatch_tab[i].desc;
3845 }
3846 }
3847 }
3848 device_printf(dev, "<%s%s%s>",
3849 cp ? cp : "",
3850 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3851 scp ? scp : "");
3852 }
3853 printf(" at device %d.%d (no driver attached)\n",
3854 pci_get_slot(child), pci_get_function(child));
3855 pci_cfg_save(child, device_get_ivars(child), 1);
3856}
3857
3858void
3859pci_child_detached(device_t dev, device_t child)
3860{
3861 struct pci_devinfo *dinfo;
3862 struct resource_list *rl;
3863
3864 dinfo = device_get_ivars(child);
3865 rl = &dinfo->resources;
3866
3867 /*
3868 * Have to deallocate IRQs before releasing any MSI messages and
3869 * have to release MSI messages before deallocating any memory
3870 * BARs.
3871 */
3872 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0)
3873 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n");
3874 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) {
3875 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n");
3876 (void)pci_release_msi(child);
3877 }
3878 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0)
3879 pci_printf(&dinfo->cfg, "Device leaked memory resources\n");
3880 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0)
3881 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n");
| 3592static void
3593pci_set_power_children(device_t dev, device_t *devlist, int numdevs,
3594 int state)
3595{
3596 device_t child, pcib;
3597 struct pci_devinfo *dinfo;
3598 int dstate, i;
3599
3600 /*
3601 * Set the device to the given state. If the firmware suggests
3602 * a different power state, use it instead. If power management
3603 * is not present, the firmware is responsible for managing
3604 * device power. Skip children who aren't attached since they
3605 * are handled separately.
3606 */
3607 pcib = device_get_parent(dev);
3608 for (i = 0; i < numdevs; i++) {
3609 child = devlist[i];
3610 dinfo = device_get_ivars(child);
3611 dstate = state;
3612 if (device_is_attached(child) &&
3613 PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0)
3614 pci_set_powerstate(child, dstate);
3615 }
3616}
3617
3618int
3619pci_suspend(device_t dev)
3620{
3621 device_t child, *devlist;
3622 struct pci_devinfo *dinfo;
3623 int error, i, numdevs;
3624
3625 /*
3626 * Save the PCI configuration space for each child and set the
3627 * device in the appropriate power state for this sleep state.
3628 */
3629 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
3630 return (error);
3631 for (i = 0; i < numdevs; i++) {
3632 child = devlist[i];
3633 dinfo = device_get_ivars(child);
3634 pci_cfg_save(child, dinfo, 0);
3635 }
3636
3637 /* Suspend devices before potentially powering them down. */
3638 error = bus_generic_suspend(dev);
3639 if (error) {
3640 free(devlist, M_TEMP);
3641 return (error);
3642 }
3643 if (pci_do_power_suspend)
3644 pci_set_power_children(dev, devlist, numdevs,
3645 PCI_POWERSTATE_D3);
3646 free(devlist, M_TEMP);
3647 return (0);
3648}
3649
3650int
3651pci_resume(device_t dev)
3652{
3653 device_t child, *devlist;
3654 struct pci_devinfo *dinfo;
3655 int error, i, numdevs;
3656
3657 /*
3658 * Set each child to D0 and restore its PCI configuration space.
3659 */
3660 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
3661 return (error);
3662 if (pci_do_power_resume)
3663 pci_set_power_children(dev, devlist, numdevs,
3664 PCI_POWERSTATE_D0);
3665
3666 /* Now the device is powered up, restore its config space. */
3667 for (i = 0; i < numdevs; i++) {
3668 child = devlist[i];
3669 dinfo = device_get_ivars(child);
3670
3671 pci_cfg_restore(child, dinfo);
3672 if (!device_is_attached(child))
3673 pci_cfg_save(child, dinfo, 1);
3674 }
3675
3676 /*
3677 * Resume critical devices first, then everything else later.
3678 */
3679 for (i = 0; i < numdevs; i++) {
3680 child = devlist[i];
3681 switch (pci_get_class(child)) {
3682 case PCIC_DISPLAY:
3683 case PCIC_MEMORY:
3684 case PCIC_BRIDGE:
3685 case PCIC_BASEPERIPH:
3686 DEVICE_RESUME(child);
3687 break;
3688 }
3689 }
3690 for (i = 0; i < numdevs; i++) {
3691 child = devlist[i];
3692 switch (pci_get_class(child)) {
3693 case PCIC_DISPLAY:
3694 case PCIC_MEMORY:
3695 case PCIC_BRIDGE:
3696 case PCIC_BASEPERIPH:
3697 break;
3698 default:
3699 DEVICE_RESUME(child);
3700 }
3701 }
3702 free(devlist, M_TEMP);
3703 return (0);
3704}
3705
3706static void
3707pci_load_vendor_data(void)
3708{
3709 caddr_t data;
3710 void *ptr;
3711 size_t sz;
3712
3713 data = preload_search_by_type("pci_vendor_data");
3714 if (data != NULL) {
3715 ptr = preload_fetch_addr(data);
3716 sz = preload_fetch_size(data);
3717 if (ptr != NULL && sz != 0) {
3718 pci_vendordata = ptr;
3719 pci_vendordata_size = sz;
3720 /* terminate the database */
3721 pci_vendordata[pci_vendordata_size] = '\n';
3722 }
3723 }
3724}
3725
3726void
3727pci_driver_added(device_t dev, driver_t *driver)
3728{
3729 int numdevs;
3730 device_t *devlist;
3731 device_t child;
3732 struct pci_devinfo *dinfo;
3733 int i;
3734
3735 if (bootverbose)
3736 device_printf(dev, "driver added\n");
3737 DEVICE_IDENTIFY(driver, dev);
3738 if (device_get_children(dev, &devlist, &numdevs) != 0)
3739 return;
3740 for (i = 0; i < numdevs; i++) {
3741 child = devlist[i];
3742 if (device_get_state(child) != DS_NOTPRESENT)
3743 continue;
3744 dinfo = device_get_ivars(child);
3745 pci_print_verbose(dinfo);
3746 if (bootverbose)
3747 pci_printf(&dinfo->cfg, "reprobing on driver added\n");
3748 pci_cfg_restore(child, dinfo);
3749 if (device_probe_and_attach(child) != 0)
3750 pci_child_detached(dev, child);
3751 }
3752 free(devlist, M_TEMP);
3753}
3754
3755int
3756pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3757 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep)
3758{
3759 struct pci_devinfo *dinfo;
3760 struct msix_table_entry *mte;
3761 struct msix_vector *mv;
3762 uint64_t addr;
3763 uint32_t data;
3764 void *cookie;
3765 int error, rid;
3766
3767 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
3768 arg, &cookie);
3769 if (error)
3770 return (error);
3771
3772 /* If this is not a direct child, just bail out. */
3773 if (device_get_parent(child) != dev) {
3774 *cookiep = cookie;
3775 return(0);
3776 }
3777
3778 rid = rman_get_rid(irq);
3779 if (rid == 0) {
3780 /* Make sure that INTx is enabled */
3781 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3782 } else {
3783 /*
3784 * Check to see if the interrupt is MSI or MSI-X.
3785 * Ask our parent to map the MSI and give
3786 * us the address and data register values.
3787 * If we fail for some reason, teardown the
3788 * interrupt handler.
3789 */
3790 dinfo = device_get_ivars(child);
3791 if (dinfo->cfg.msi.msi_alloc > 0) {
3792 if (dinfo->cfg.msi.msi_addr == 0) {
3793 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3794 ("MSI has handlers, but vectors not mapped"));
3795 error = PCIB_MAP_MSI(device_get_parent(dev),
3796 child, rman_get_start(irq), &addr, &data);
3797 if (error)
3798 goto bad;
3799 dinfo->cfg.msi.msi_addr = addr;
3800 dinfo->cfg.msi.msi_data = data;
3801 }
3802 if (dinfo->cfg.msi.msi_handlers == 0)
3803 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
3804 dinfo->cfg.msi.msi_data);
3805 dinfo->cfg.msi.msi_handlers++;
3806 } else {
3807 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3808 ("No MSI or MSI-X interrupts allocated"));
3809 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3810 ("MSI-X index too high"));
3811 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3812 KASSERT(mte->mte_vector != 0, ("no message vector"));
3813 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3814 KASSERT(mv->mv_irq == rman_get_start(irq),
3815 ("IRQ mismatch"));
3816 if (mv->mv_address == 0) {
3817 KASSERT(mte->mte_handlers == 0,
3818 ("MSI-X table entry has handlers, but vector not mapped"));
3819 error = PCIB_MAP_MSI(device_get_parent(dev),
3820 child, rman_get_start(irq), &addr, &data);
3821 if (error)
3822 goto bad;
3823 mv->mv_address = addr;
3824 mv->mv_data = data;
3825 }
3826 if (mte->mte_handlers == 0) {
3827 pci_enable_msix(child, rid - 1, mv->mv_address,
3828 mv->mv_data);
3829 pci_unmask_msix(child, rid - 1);
3830 }
3831 mte->mte_handlers++;
3832 }
3833
3834 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3835 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3836 bad:
3837 if (error) {
3838 (void)bus_generic_teardown_intr(dev, child, irq,
3839 cookie);
3840 return (error);
3841 }
3842 }
3843 *cookiep = cookie;
3844 return (0);
3845}
3846
3847int
3848pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3849 void *cookie)
3850{
3851 struct msix_table_entry *mte;
3852 struct resource_list_entry *rle;
3853 struct pci_devinfo *dinfo;
3854 int error, rid;
3855
3856 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3857 return (EINVAL);
3858
3859 /* If this isn't a direct child, just bail out */
3860 if (device_get_parent(child) != dev)
3861 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3862
3863 rid = rman_get_rid(irq);
3864 if (rid == 0) {
3865 /* Mask INTx */
3866 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3867 } else {
3868 /*
3869 * Check to see if the interrupt is MSI or MSI-X. If so,
3870 * decrement the appropriate handlers count and mask the
3871 * MSI-X message, or disable MSI messages if the count
3872 * drops to 0.
3873 */
3874 dinfo = device_get_ivars(child);
3875 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3876 if (rle->res != irq)
3877 return (EINVAL);
3878 if (dinfo->cfg.msi.msi_alloc > 0) {
3879 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3880 ("MSI-X index too high"));
3881 if (dinfo->cfg.msi.msi_handlers == 0)
3882 return (EINVAL);
3883 dinfo->cfg.msi.msi_handlers--;
3884 if (dinfo->cfg.msi.msi_handlers == 0)
3885 pci_disable_msi(child);
3886 } else {
3887 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3888 ("No MSI or MSI-X interrupts allocated"));
3889 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3890 ("MSI-X index too high"));
3891 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3892 if (mte->mte_handlers == 0)
3893 return (EINVAL);
3894 mte->mte_handlers--;
3895 if (mte->mte_handlers == 0)
3896 pci_mask_msix(child, rid - 1);
3897 }
3898 }
3899 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3900 if (rid > 0)
3901 KASSERT(error == 0,
3902 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3903 return (error);
3904}
3905
3906int
3907pci_print_child(device_t dev, device_t child)
3908{
3909 struct pci_devinfo *dinfo;
3910 struct resource_list *rl;
3911 int retval = 0;
3912
3913 dinfo = device_get_ivars(child);
3914 rl = &dinfo->resources;
3915
3916 retval += bus_print_child_header(dev, child);
3917
3918 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3919 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3920 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3921 if (device_get_flags(dev))
3922 retval += printf(" flags %#x", device_get_flags(dev));
3923
3924 retval += printf(" at device %d.%d", pci_get_slot(child),
3925 pci_get_function(child));
3926
3927 retval += bus_print_child_footer(dev, child);
3928
3929 return (retval);
3930}
3931
3932static const struct
3933{
3934 int class;
3935 int subclass;
3936 const char *desc;
3937} pci_nomatch_tab[] = {
3938 {PCIC_OLD, -1, "old"},
3939 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3940 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3941 {PCIC_STORAGE, -1, "mass storage"},
3942 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3943 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3944 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3945 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3946 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3947 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3948 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3949 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3950 {PCIC_STORAGE, PCIS_STORAGE_NVM, "NVM"},
3951 {PCIC_NETWORK, -1, "network"},
3952 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3953 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3954 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3955 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3956 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3957 {PCIC_DISPLAY, -1, "display"},
3958 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3959 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3960 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3961 {PCIC_MULTIMEDIA, -1, "multimedia"},
3962 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3963 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3964 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3965 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3966 {PCIC_MEMORY, -1, "memory"},
3967 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3968 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3969 {PCIC_BRIDGE, -1, "bridge"},
3970 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3971 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3972 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3973 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3974 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3975 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3976 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3977 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3978 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3979 {PCIC_SIMPLECOMM, -1, "simple comms"},
3980 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3981 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3982 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3983 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3984 {PCIC_BASEPERIPH, -1, "base peripheral"},
3985 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3986 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3987 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3988 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3989 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3990 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3991 {PCIC_INPUTDEV, -1, "input device"},
3992 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3993 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3994 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3995 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3996 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3997 {PCIC_DOCKING, -1, "docking station"},
3998 {PCIC_PROCESSOR, -1, "processor"},
3999 {PCIC_SERIALBUS, -1, "serial bus"},
4000 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
4001 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
4002 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
4003 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
4004 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
4005 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
4006 {PCIC_WIRELESS, -1, "wireless controller"},
4007 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
4008 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
4009 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
4010 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
4011 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
4012 {PCIC_SATCOM, -1, "satellite communication"},
4013 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
4014 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
4015 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
4016 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
4017 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
4018 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
4019 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
4020 {PCIC_DASP, -1, "dasp"},
4021 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
4022 {0, 0, NULL}
4023};
4024
4025void
4026pci_probe_nomatch(device_t dev, device_t child)
4027{
4028 int i;
4029 const char *cp, *scp;
4030 char *device;
4031
4032 /*
4033 * Look for a listing for this device in a loaded device database.
4034 */
4035 if ((device = pci_describe_device(child)) != NULL) {
4036 device_printf(dev, "<%s>", device);
4037 free(device, M_DEVBUF);
4038 } else {
4039 /*
4040 * Scan the class/subclass descriptions for a general
4041 * description.
4042 */
4043 cp = "unknown";
4044 scp = NULL;
4045 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
4046 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
4047 if (pci_nomatch_tab[i].subclass == -1) {
4048 cp = pci_nomatch_tab[i].desc;
4049 } else if (pci_nomatch_tab[i].subclass ==
4050 pci_get_subclass(child)) {
4051 scp = pci_nomatch_tab[i].desc;
4052 }
4053 }
4054 }
4055 device_printf(dev, "<%s%s%s>",
4056 cp ? cp : "",
4057 ((cp != NULL) && (scp != NULL)) ? ", " : "",
4058 scp ? scp : "");
4059 }
4060 printf(" at device %d.%d (no driver attached)\n",
4061 pci_get_slot(child), pci_get_function(child));
4062 pci_cfg_save(child, device_get_ivars(child), 1);
4063}
4064
4065void
4066pci_child_detached(device_t dev, device_t child)
4067{
4068 struct pci_devinfo *dinfo;
4069 struct resource_list *rl;
4070
4071 dinfo = device_get_ivars(child);
4072 rl = &dinfo->resources;
4073
4074 /*
4075 * Have to deallocate IRQs before releasing any MSI messages and
4076 * have to release MSI messages before deallocating any memory
4077 * BARs.
4078 */
4079 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0)
4080 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n");
4081 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) {
4082 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n");
4083 (void)pci_release_msi(child);
4084 }
4085 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0)
4086 pci_printf(&dinfo->cfg, "Device leaked memory resources\n");
4087 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0)
4088 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n");
|
| 4089#ifdef PCI_RES_BUS
4090 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0)
4091 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n");
4092#endif
|
3882
3883 pci_cfg_save(child, dinfo, 1);
3884}
3885
3886/*
3887 * Parse the PCI device database, if loaded, and return a pointer to a
3888 * description of the device.
3889 *
3890 * The database is flat text formatted as follows:
3891 *
3892 * Any line not in a valid format is ignored.
3893 * Lines are terminated with newline '\n' characters.
3894 *
3895 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3896 * the vendor name.
3897 *
3898 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3899 * - devices cannot be listed without a corresponding VENDOR line.
3900 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3901 * another TAB, then the device name.
3902 */
3903
3904/*
3905 * Assuming (ptr) points to the beginning of a line in the database,
3906 * return the vendor or device and description of the next entry.
3907 * The value of (vendor) or (device) inappropriate for the entry type
3908 * is set to -1. Returns nonzero at the end of the database.
3909 *
3910 * Note that this is slightly unrobust in the face of corrupt data;
3911 * we attempt to safeguard against this by spamming the end of the
3912 * database with a newline when we initialise.
3913 */
3914static int
3915pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3916{
3917 char *cp = *ptr;
3918 int left;
3919
3920 *device = -1;
3921 *vendor = -1;
3922 **desc = '\0';
3923 for (;;) {
3924 left = pci_vendordata_size - (cp - pci_vendordata);
3925 if (left <= 0) {
3926 *ptr = cp;
3927 return(1);
3928 }
3929
3930 /* vendor entry? */
3931 if (*cp != '\t' &&
3932 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3933 break;
3934 /* device entry? */
3935 if (*cp == '\t' &&
3936 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3937 break;
3938
3939 /* skip to next line */
3940 while (*cp != '\n' && left > 0) {
3941 cp++;
3942 left--;
3943 }
3944 if (*cp == '\n') {
3945 cp++;
3946 left--;
3947 }
3948 }
3949 /* skip to next line */
3950 while (*cp != '\n' && left > 0) {
3951 cp++;
3952 left--;
3953 }
3954 if (*cp == '\n' && left > 0)
3955 cp++;
3956 *ptr = cp;
3957 return(0);
3958}
3959
3960static char *
3961pci_describe_device(device_t dev)
3962{
3963 int vendor, device;
3964 char *desc, *vp, *dp, *line;
3965
3966 desc = vp = dp = NULL;
3967
3968 /*
3969 * If we have no vendor data, we can't do anything.
3970 */
3971 if (pci_vendordata == NULL)
3972 goto out;
3973
3974 /*
3975 * Scan the vendor data looking for this device
3976 */
3977 line = pci_vendordata;
3978 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3979 goto out;
3980 for (;;) {
3981 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3982 goto out;
3983 if (vendor == pci_get_vendor(dev))
3984 break;
3985 }
3986 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3987 goto out;
3988 for (;;) {
3989 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3990 *dp = 0;
3991 break;
3992 }
3993 if (vendor != -1) {
3994 *dp = 0;
3995 break;
3996 }
3997 if (device == pci_get_device(dev))
3998 break;
3999 }
4000 if (dp[0] == '\0')
4001 snprintf(dp, 80, "0x%x", pci_get_device(dev));
4002 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
4003 NULL)
4004 sprintf(desc, "%s, %s", vp, dp);
4005out:
4006 if (vp != NULL)
4007 free(vp, M_DEVBUF);
4008 if (dp != NULL)
4009 free(dp, M_DEVBUF);
4010 return(desc);
4011}
4012
4013int
4014pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
4015{
4016 struct pci_devinfo *dinfo;
4017 pcicfgregs *cfg;
4018
4019 dinfo = device_get_ivars(child);
4020 cfg = &dinfo->cfg;
4021
4022 switch (which) {
4023 case PCI_IVAR_ETHADDR:
4024 /*
4025 * The generic accessor doesn't deal with failure, so
4026 * we set the return value, then return an error.
4027 */
4028 *((uint8_t **) result) = NULL;
4029 return (EINVAL);
4030 case PCI_IVAR_SUBVENDOR:
4031 *result = cfg->subvendor;
4032 break;
4033 case PCI_IVAR_SUBDEVICE:
4034 *result = cfg->subdevice;
4035 break;
4036 case PCI_IVAR_VENDOR:
4037 *result = cfg->vendor;
4038 break;
4039 case PCI_IVAR_DEVICE:
4040 *result = cfg->device;
4041 break;
4042 case PCI_IVAR_DEVID:
4043 *result = (cfg->device << 16) | cfg->vendor;
4044 break;
4045 case PCI_IVAR_CLASS:
4046 *result = cfg->baseclass;
4047 break;
4048 case PCI_IVAR_SUBCLASS:
4049 *result = cfg->subclass;
4050 break;
4051 case PCI_IVAR_PROGIF:
4052 *result = cfg->progif;
4053 break;
4054 case PCI_IVAR_REVID:
4055 *result = cfg->revid;
4056 break;
4057 case PCI_IVAR_INTPIN:
4058 *result = cfg->intpin;
4059 break;
4060 case PCI_IVAR_IRQ:
4061 *result = cfg->intline;
4062 break;
4063 case PCI_IVAR_DOMAIN:
4064 *result = cfg->domain;
4065 break;
4066 case PCI_IVAR_BUS:
4067 *result = cfg->bus;
4068 break;
4069 case PCI_IVAR_SLOT:
4070 *result = cfg->slot;
4071 break;
4072 case PCI_IVAR_FUNCTION:
4073 *result = cfg->func;
4074 break;
4075 case PCI_IVAR_CMDREG:
4076 *result = cfg->cmdreg;
4077 break;
4078 case PCI_IVAR_CACHELNSZ:
4079 *result = cfg->cachelnsz;
4080 break;
4081 case PCI_IVAR_MINGNT:
4082 *result = cfg->mingnt;
4083 break;
4084 case PCI_IVAR_MAXLAT:
4085 *result = cfg->maxlat;
4086 break;
4087 case PCI_IVAR_LATTIMER:
4088 *result = cfg->lattimer;
4089 break;
4090 default:
4091 return (ENOENT);
4092 }
4093 return (0);
4094}
4095
4096int
4097pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
4098{
4099 struct pci_devinfo *dinfo;
4100
4101 dinfo = device_get_ivars(child);
4102
4103 switch (which) {
4104 case PCI_IVAR_INTPIN:
4105 dinfo->cfg.intpin = value;
4106 return (0);
4107 case PCI_IVAR_ETHADDR:
4108 case PCI_IVAR_SUBVENDOR:
4109 case PCI_IVAR_SUBDEVICE:
4110 case PCI_IVAR_VENDOR:
4111 case PCI_IVAR_DEVICE:
4112 case PCI_IVAR_DEVID:
4113 case PCI_IVAR_CLASS:
4114 case PCI_IVAR_SUBCLASS:
4115 case PCI_IVAR_PROGIF:
4116 case PCI_IVAR_REVID:
4117 case PCI_IVAR_IRQ:
4118 case PCI_IVAR_DOMAIN:
4119 case PCI_IVAR_BUS:
4120 case PCI_IVAR_SLOT:
4121 case PCI_IVAR_FUNCTION:
4122 return (EINVAL); /* disallow for now */
4123
4124 default:
4125 return (ENOENT);
4126 }
4127}
4128
4129#include "opt_ddb.h"
4130#ifdef DDB
4131#include <ddb/ddb.h>
4132#include <sys/cons.h>
4133
4134/*
4135 * List resources based on pci map registers, used for within ddb
4136 */
4137
4138DB_SHOW_COMMAND(pciregs, db_pci_dump)
4139{
4140 struct pci_devinfo *dinfo;
4141 struct devlist *devlist_head;
4142 struct pci_conf *p;
4143 const char *name;
4144 int i, error, none_count;
4145
4146 none_count = 0;
4147 /* get the head of the device queue */
4148 devlist_head = &pci_devq;
4149
4150 /*
4151 * Go through the list of devices and print out devices
4152 */
4153 for (error = 0, i = 0,
4154 dinfo = STAILQ_FIRST(devlist_head);
4155 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
4156 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4157
4158 /* Populate pd_name and pd_unit */
4159 name = NULL;
4160 if (dinfo->cfg.dev)
4161 name = device_get_name(dinfo->cfg.dev);
4162
4163 p = &dinfo->conf;
4164 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
4165 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
4166 (name && *name) ? name : "none",
4167 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
4168 none_count++,
4169 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
4170 p->pc_sel.pc_func, (p->pc_class << 16) |
4171 (p->pc_subclass << 8) | p->pc_progif,
4172 (p->pc_subdevice << 16) | p->pc_subvendor,
4173 (p->pc_device << 16) | p->pc_vendor,
4174 p->pc_revid, p->pc_hdr);
4175 }
4176}
4177#endif /* DDB */
4178
4179static struct resource *
4180pci_reserve_map(device_t dev, device_t child, int type, int *rid,
4181 u_long start, u_long end, u_long count, u_int flags)
4182{
4183 struct pci_devinfo *dinfo = device_get_ivars(child);
4184 struct resource_list *rl = &dinfo->resources;
4185 struct resource *res;
4186 struct pci_map *pm;
4187 pci_addr_t map, testval;
4188 int mapsize;
4189
4190 res = NULL;
4191 pm = pci_find_bar(child, *rid);
4192 if (pm != NULL) {
4193 /* This is a BAR that we failed to allocate earlier. */
4194 mapsize = pm->pm_size;
4195 map = pm->pm_value;
4196 } else {
4197 /*
4198 * Weed out the bogons, and figure out how large the
4199 * BAR/map is. BARs that read back 0 here are bogus
4200 * and unimplemented. Note: atapci in legacy mode are
4201 * special and handled elsewhere in the code. If you
4202 * have a atapci device in legacy mode and it fails
4203 * here, that other code is broken.
4204 */
4205 pci_read_bar(child, *rid, &map, &testval);
4206
4207 /*
4208 * Determine the size of the BAR and ignore BARs with a size
4209 * of 0. Device ROM BARs use a different mask value.
4210 */
4211 if (PCIR_IS_BIOS(&dinfo->cfg, *rid))
4212 mapsize = pci_romsize(testval);
4213 else
4214 mapsize = pci_mapsize(testval);
4215 if (mapsize == 0)
4216 goto out;
4217 pm = pci_add_bar(child, *rid, map, mapsize);
4218 }
4219
4220 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) {
4221 if (type != SYS_RES_MEMORY) {
4222 if (bootverbose)
4223 device_printf(dev,
4224 "child %s requested type %d for rid %#x,"
4225 " but the BAR says it is an memio\n",
4226 device_get_nameunit(child), type, *rid);
4227 goto out;
4228 }
4229 } else {
4230 if (type != SYS_RES_IOPORT) {
4231 if (bootverbose)
4232 device_printf(dev,
4233 "child %s requested type %d for rid %#x,"
4234 " but the BAR says it is an ioport\n",
4235 device_get_nameunit(child), type, *rid);
4236 goto out;
4237 }
4238 }
4239
4240 /*
4241 * For real BARs, we need to override the size that
4242 * the driver requests, because that's what the BAR
4243 * actually uses and we would otherwise have a
4244 * situation where we might allocate the excess to
4245 * another driver, which won't work.
4246 */
4247 count = (pci_addr_t)1 << mapsize;
4248 if (RF_ALIGNMENT(flags) < mapsize)
4249 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
4250 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH))
4251 flags |= RF_PREFETCHABLE;
4252
4253 /*
4254 * Allocate enough resource, and then write back the
4255 * appropriate BAR for that resource.
4256 */
4257 resource_list_add(rl, type, *rid, start, end, count);
4258 res = resource_list_reserve(rl, dev, child, type, rid, start, end,
4259 count, flags & ~RF_ACTIVE);
4260 if (res == NULL) {
4261 resource_list_delete(rl, type, *rid);
4262 device_printf(child,
4263 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
4264 count, *rid, type, start, end);
4265 goto out;
4266 }
4267 if (bootverbose)
4268 device_printf(child,
4269 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
4270 count, *rid, type, rman_get_start(res));
4271 map = rman_get_start(res);
4272 pci_write_bar(child, pm, map);
4273out:
4274 return (res);
4275}
4276
4277struct resource *
4278pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
4279 u_long start, u_long end, u_long count, u_int flags)
4280{
4281 struct pci_devinfo *dinfo;
4282 struct resource_list *rl;
4283 struct resource_list_entry *rle;
4284 struct resource *res;
4285 pcicfgregs *cfg;
4286
4287 if (device_get_parent(child) != dev)
4288 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
4289 type, rid, start, end, count, flags));
4290
4291 /*
4292 * Perform lazy resource allocation
4293 */
4294 dinfo = device_get_ivars(child);
4295 rl = &dinfo->resources;
4296 cfg = &dinfo->cfg;
4297 switch (type) {
| 4093
4094 pci_cfg_save(child, dinfo, 1);
4095}
4096
4097/*
4098 * Parse the PCI device database, if loaded, and return a pointer to a
4099 * description of the device.
4100 *
4101 * The database is flat text formatted as follows:
4102 *
4103 * Any line not in a valid format is ignored.
4104 * Lines are terminated with newline '\n' characters.
4105 *
4106 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
4107 * the vendor name.
4108 *
4109 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
4110 * - devices cannot be listed without a corresponding VENDOR line.
4111 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
4112 * another TAB, then the device name.
4113 */
4114
4115/*
4116 * Assuming (ptr) points to the beginning of a line in the database,
4117 * return the vendor or device and description of the next entry.
4118 * The value of (vendor) or (device) inappropriate for the entry type
4119 * is set to -1. Returns nonzero at the end of the database.
4120 *
4121 * Note that this is slightly unrobust in the face of corrupt data;
4122 * we attempt to safeguard against this by spamming the end of the
4123 * database with a newline when we initialise.
4124 */
4125static int
4126pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
4127{
4128 char *cp = *ptr;
4129 int left;
4130
4131 *device = -1;
4132 *vendor = -1;
4133 **desc = '\0';
4134 for (;;) {
4135 left = pci_vendordata_size - (cp - pci_vendordata);
4136 if (left <= 0) {
4137 *ptr = cp;
4138 return(1);
4139 }
4140
4141 /* vendor entry? */
4142 if (*cp != '\t' &&
4143 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
4144 break;
4145 /* device entry? */
4146 if (*cp == '\t' &&
4147 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
4148 break;
4149
4150 /* skip to next line */
4151 while (*cp != '\n' && left > 0) {
4152 cp++;
4153 left--;
4154 }
4155 if (*cp == '\n') {
4156 cp++;
4157 left--;
4158 }
4159 }
4160 /* skip to next line */
4161 while (*cp != '\n' && left > 0) {
4162 cp++;
4163 left--;
4164 }
4165 if (*cp == '\n' && left > 0)
4166 cp++;
4167 *ptr = cp;
4168 return(0);
4169}
4170
4171static char *
4172pci_describe_device(device_t dev)
4173{
4174 int vendor, device;
4175 char *desc, *vp, *dp, *line;
4176
4177 desc = vp = dp = NULL;
4178
4179 /*
4180 * If we have no vendor data, we can't do anything.
4181 */
4182 if (pci_vendordata == NULL)
4183 goto out;
4184
4185 /*
4186 * Scan the vendor data looking for this device
4187 */
4188 line = pci_vendordata;
4189 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
4190 goto out;
4191 for (;;) {
4192 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
4193 goto out;
4194 if (vendor == pci_get_vendor(dev))
4195 break;
4196 }
4197 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
4198 goto out;
4199 for (;;) {
4200 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
4201 *dp = 0;
4202 break;
4203 }
4204 if (vendor != -1) {
4205 *dp = 0;
4206 break;
4207 }
4208 if (device == pci_get_device(dev))
4209 break;
4210 }
4211 if (dp[0] == '\0')
4212 snprintf(dp, 80, "0x%x", pci_get_device(dev));
4213 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
4214 NULL)
4215 sprintf(desc, "%s, %s", vp, dp);
4216out:
4217 if (vp != NULL)
4218 free(vp, M_DEVBUF);
4219 if (dp != NULL)
4220 free(dp, M_DEVBUF);
4221 return(desc);
4222}
4223
4224int
4225pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
4226{
4227 struct pci_devinfo *dinfo;
4228 pcicfgregs *cfg;
4229
4230 dinfo = device_get_ivars(child);
4231 cfg = &dinfo->cfg;
4232
4233 switch (which) {
4234 case PCI_IVAR_ETHADDR:
4235 /*
4236 * The generic accessor doesn't deal with failure, so
4237 * we set the return value, then return an error.
4238 */
4239 *((uint8_t **) result) = NULL;
4240 return (EINVAL);
4241 case PCI_IVAR_SUBVENDOR:
4242 *result = cfg->subvendor;
4243 break;
4244 case PCI_IVAR_SUBDEVICE:
4245 *result = cfg->subdevice;
4246 break;
4247 case PCI_IVAR_VENDOR:
4248 *result = cfg->vendor;
4249 break;
4250 case PCI_IVAR_DEVICE:
4251 *result = cfg->device;
4252 break;
4253 case PCI_IVAR_DEVID:
4254 *result = (cfg->device << 16) | cfg->vendor;
4255 break;
4256 case PCI_IVAR_CLASS:
4257 *result = cfg->baseclass;
4258 break;
4259 case PCI_IVAR_SUBCLASS:
4260 *result = cfg->subclass;
4261 break;
4262 case PCI_IVAR_PROGIF:
4263 *result = cfg->progif;
4264 break;
4265 case PCI_IVAR_REVID:
4266 *result = cfg->revid;
4267 break;
4268 case PCI_IVAR_INTPIN:
4269 *result = cfg->intpin;
4270 break;
4271 case PCI_IVAR_IRQ:
4272 *result = cfg->intline;
4273 break;
4274 case PCI_IVAR_DOMAIN:
4275 *result = cfg->domain;
4276 break;
4277 case PCI_IVAR_BUS:
4278 *result = cfg->bus;
4279 break;
4280 case PCI_IVAR_SLOT:
4281 *result = cfg->slot;
4282 break;
4283 case PCI_IVAR_FUNCTION:
4284 *result = cfg->func;
4285 break;
4286 case PCI_IVAR_CMDREG:
4287 *result = cfg->cmdreg;
4288 break;
4289 case PCI_IVAR_CACHELNSZ:
4290 *result = cfg->cachelnsz;
4291 break;
4292 case PCI_IVAR_MINGNT:
4293 *result = cfg->mingnt;
4294 break;
4295 case PCI_IVAR_MAXLAT:
4296 *result = cfg->maxlat;
4297 break;
4298 case PCI_IVAR_LATTIMER:
4299 *result = cfg->lattimer;
4300 break;
4301 default:
4302 return (ENOENT);
4303 }
4304 return (0);
4305}
4306
4307int
4308pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
4309{
4310 struct pci_devinfo *dinfo;
4311
4312 dinfo = device_get_ivars(child);
4313
4314 switch (which) {
4315 case PCI_IVAR_INTPIN:
4316 dinfo->cfg.intpin = value;
4317 return (0);
4318 case PCI_IVAR_ETHADDR:
4319 case PCI_IVAR_SUBVENDOR:
4320 case PCI_IVAR_SUBDEVICE:
4321 case PCI_IVAR_VENDOR:
4322 case PCI_IVAR_DEVICE:
4323 case PCI_IVAR_DEVID:
4324 case PCI_IVAR_CLASS:
4325 case PCI_IVAR_SUBCLASS:
4326 case PCI_IVAR_PROGIF:
4327 case PCI_IVAR_REVID:
4328 case PCI_IVAR_IRQ:
4329 case PCI_IVAR_DOMAIN:
4330 case PCI_IVAR_BUS:
4331 case PCI_IVAR_SLOT:
4332 case PCI_IVAR_FUNCTION:
4333 return (EINVAL); /* disallow for now */
4334
4335 default:
4336 return (ENOENT);
4337 }
4338}
4339
4340#include "opt_ddb.h"
4341#ifdef DDB
4342#include <ddb/ddb.h>
4343#include <sys/cons.h>
4344
4345/*
4346 * List resources based on pci map registers, used for within ddb
4347 */
4348
4349DB_SHOW_COMMAND(pciregs, db_pci_dump)
4350{
4351 struct pci_devinfo *dinfo;
4352 struct devlist *devlist_head;
4353 struct pci_conf *p;
4354 const char *name;
4355 int i, error, none_count;
4356
4357 none_count = 0;
4358 /* get the head of the device queue */
4359 devlist_head = &pci_devq;
4360
4361 /*
4362 * Go through the list of devices and print out devices
4363 */
4364 for (error = 0, i = 0,
4365 dinfo = STAILQ_FIRST(devlist_head);
4366 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
4367 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4368
4369 /* Populate pd_name and pd_unit */
4370 name = NULL;
4371 if (dinfo->cfg.dev)
4372 name = device_get_name(dinfo->cfg.dev);
4373
4374 p = &dinfo->conf;
4375 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
4376 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
4377 (name && *name) ? name : "none",
4378 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
4379 none_count++,
4380 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
4381 p->pc_sel.pc_func, (p->pc_class << 16) |
4382 (p->pc_subclass << 8) | p->pc_progif,
4383 (p->pc_subdevice << 16) | p->pc_subvendor,
4384 (p->pc_device << 16) | p->pc_vendor,
4385 p->pc_revid, p->pc_hdr);
4386 }
4387}
4388#endif /* DDB */
4389
4390static struct resource *
4391pci_reserve_map(device_t dev, device_t child, int type, int *rid,
4392 u_long start, u_long end, u_long count, u_int flags)
4393{
4394 struct pci_devinfo *dinfo = device_get_ivars(child);
4395 struct resource_list *rl = &dinfo->resources;
4396 struct resource *res;
4397 struct pci_map *pm;
4398 pci_addr_t map, testval;
4399 int mapsize;
4400
4401 res = NULL;
4402 pm = pci_find_bar(child, *rid);
4403 if (pm != NULL) {
4404 /* This is a BAR that we failed to allocate earlier. */
4405 mapsize = pm->pm_size;
4406 map = pm->pm_value;
4407 } else {
4408 /*
4409 * Weed out the bogons, and figure out how large the
4410 * BAR/map is. BARs that read back 0 here are bogus
4411 * and unimplemented. Note: atapci in legacy mode are
4412 * special and handled elsewhere in the code. If you
4413 * have a atapci device in legacy mode and it fails
4414 * here, that other code is broken.
4415 */
4416 pci_read_bar(child, *rid, &map, &testval);
4417
4418 /*
4419 * Determine the size of the BAR and ignore BARs with a size
4420 * of 0. Device ROM BARs use a different mask value.
4421 */
4422 if (PCIR_IS_BIOS(&dinfo->cfg, *rid))
4423 mapsize = pci_romsize(testval);
4424 else
4425 mapsize = pci_mapsize(testval);
4426 if (mapsize == 0)
4427 goto out;
4428 pm = pci_add_bar(child, *rid, map, mapsize);
4429 }
4430
4431 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) {
4432 if (type != SYS_RES_MEMORY) {
4433 if (bootverbose)
4434 device_printf(dev,
4435 "child %s requested type %d for rid %#x,"
4436 " but the BAR says it is an memio\n",
4437 device_get_nameunit(child), type, *rid);
4438 goto out;
4439 }
4440 } else {
4441 if (type != SYS_RES_IOPORT) {
4442 if (bootverbose)
4443 device_printf(dev,
4444 "child %s requested type %d for rid %#x,"
4445 " but the BAR says it is an ioport\n",
4446 device_get_nameunit(child), type, *rid);
4447 goto out;
4448 }
4449 }
4450
4451 /*
4452 * For real BARs, we need to override the size that
4453 * the driver requests, because that's what the BAR
4454 * actually uses and we would otherwise have a
4455 * situation where we might allocate the excess to
4456 * another driver, which won't work.
4457 */
4458 count = (pci_addr_t)1 << mapsize;
4459 if (RF_ALIGNMENT(flags) < mapsize)
4460 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
4461 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH))
4462 flags |= RF_PREFETCHABLE;
4463
4464 /*
4465 * Allocate enough resource, and then write back the
4466 * appropriate BAR for that resource.
4467 */
4468 resource_list_add(rl, type, *rid, start, end, count);
4469 res = resource_list_reserve(rl, dev, child, type, rid, start, end,
4470 count, flags & ~RF_ACTIVE);
4471 if (res == NULL) {
4472 resource_list_delete(rl, type, *rid);
4473 device_printf(child,
4474 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
4475 count, *rid, type, start, end);
4476 goto out;
4477 }
4478 if (bootverbose)
4479 device_printf(child,
4480 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
4481 count, *rid, type, rman_get_start(res));
4482 map = rman_get_start(res);
4483 pci_write_bar(child, pm, map);
4484out:
4485 return (res);
4486}
4487
4488struct resource *
4489pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
4490 u_long start, u_long end, u_long count, u_int flags)
4491{
4492 struct pci_devinfo *dinfo;
4493 struct resource_list *rl;
4494 struct resource_list_entry *rle;
4495 struct resource *res;
4496 pcicfgregs *cfg;
4497
4498 if (device_get_parent(child) != dev)
4499 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
4500 type, rid, start, end, count, flags));
4501
4502 /*
4503 * Perform lazy resource allocation
4504 */
4505 dinfo = device_get_ivars(child);
4506 rl = &dinfo->resources;
4507 cfg = &dinfo->cfg;
4508 switch (type) {
|
| 4509#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
4510 case PCI_RES_BUS:
4511 return (pci_alloc_secbus(dev, child, rid, start, end, count,
4512 flags));
4513#endif
|
4298 case SYS_RES_IRQ:
4299 /*
4300 * Can't alloc legacy interrupt once MSI messages have
4301 * been allocated.
4302 */
4303 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
4304 cfg->msix.msix_alloc > 0))
4305 return (NULL);
4306
4307 /*
4308 * If the child device doesn't have an interrupt
4309 * routed and is deserving of an interrupt, try to
4310 * assign it one.
4311 */
4312 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
4313 (cfg->intpin != 0))
4314 pci_assign_interrupt(dev, child, 0);
4315 break;
4316 case SYS_RES_IOPORT:
4317 case SYS_RES_MEMORY:
4318#ifdef NEW_PCIB
4319 /*
4320 * PCI-PCI bridge I/O window resources are not BARs.
4321 * For those allocations just pass the request up the
4322 * tree.
4323 */
4324 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) {
4325 switch (*rid) {
4326 case PCIR_IOBASEL_1:
4327 case PCIR_MEMBASE_1:
4328 case PCIR_PMBASEL_1:
4329 /*
4330 * XXX: Should we bother creating a resource
4331 * list entry?
4332 */
4333 return (bus_generic_alloc_resource(dev, child,
4334 type, rid, start, end, count, flags));
4335 }
4336 }
4337#endif
4338 /* Reserve resources for this BAR if needed. */
4339 rle = resource_list_find(rl, type, *rid);
4340 if (rle == NULL) {
4341 res = pci_reserve_map(dev, child, type, rid, start, end,
4342 count, flags);
4343 if (res == NULL)
4344 return (NULL);
4345 }
4346 }
4347 return (resource_list_alloc(rl, dev, child, type, rid,
4348 start, end, count, flags));
4349}
4350
4351int
4352pci_release_resource(device_t dev, device_t child, int type, int rid,
4353 struct resource *r)
4354{
4355 struct pci_devinfo *dinfo;
4356 struct resource_list *rl;
4357 pcicfgregs *cfg;
4358
4359 if (device_get_parent(child) != dev)
4360 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
4361 type, rid, r));
4362
4363 dinfo = device_get_ivars(child);
4364 cfg = &dinfo->cfg;
4365#ifdef NEW_PCIB
4366 /*
4367 * PCI-PCI bridge I/O window resources are not BARs. For
4368 * those allocations just pass the request up the tree.
4369 */
4370 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE &&
4371 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) {
4372 switch (rid) {
4373 case PCIR_IOBASEL_1:
4374 case PCIR_MEMBASE_1:
4375 case PCIR_PMBASEL_1:
4376 return (bus_generic_release_resource(dev, child, type,
4377 rid, r));
4378 }
4379 }
4380#endif
4381
4382 rl = &dinfo->resources;
4383 return (resource_list_release(rl, dev, child, type, rid, r));
4384}
4385
4386int
4387pci_activate_resource(device_t dev, device_t child, int type, int rid,
4388 struct resource *r)
4389{
4390 struct pci_devinfo *dinfo;
4391 int error;
4392
4393 error = bus_generic_activate_resource(dev, child, type, rid, r);
4394 if (error)
4395 return (error);
4396
4397 /* Enable decoding in the command register when activating BARs. */
4398 if (device_get_parent(child) == dev) {
4399 /* Device ROMs need their decoding explicitly enabled. */
4400 dinfo = device_get_ivars(child);
4401 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
4402 pci_write_bar(child, pci_find_bar(child, rid),
4403 rman_get_start(r) | PCIM_BIOS_ENABLE);
4404 switch (type) {
4405 case SYS_RES_IOPORT:
4406 case SYS_RES_MEMORY:
4407 error = PCI_ENABLE_IO(dev, child, type);
4408 break;
4409 }
4410 }
4411 return (error);
4412}
4413
4414int
4415pci_deactivate_resource(device_t dev, device_t child, int type,
4416 int rid, struct resource *r)
4417{
4418 struct pci_devinfo *dinfo;
4419 int error;
4420
4421 error = bus_generic_deactivate_resource(dev, child, type, rid, r);
4422 if (error)
4423 return (error);
4424
4425 /* Disable decoding for device ROMs. */
4426 if (device_get_parent(child) == dev) {
4427 dinfo = device_get_ivars(child);
4428 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
4429 pci_write_bar(child, pci_find_bar(child, rid),
4430 rman_get_start(r));
4431 }
4432 return (0);
4433}
4434
4435void
4436pci_delete_child(device_t dev, device_t child)
4437{
4438 struct resource_list_entry *rle;
4439 struct resource_list *rl;
4440 struct pci_devinfo *dinfo;
4441
4442 dinfo = device_get_ivars(child);
4443 rl = &dinfo->resources;
4444
4445 if (device_is_attached(child))
4446 device_detach(child);
4447
4448 /* Turn off access to resources we're about to free */
4449 pci_write_config(child, PCIR_COMMAND, pci_read_config(child,
4450 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2);
4451
4452 /* Free all allocated resources */
4453 STAILQ_FOREACH(rle, rl, link) {
4454 if (rle->res) {
4455 if (rman_get_flags(rle->res) & RF_ACTIVE ||
4456 resource_list_busy(rl, rle->type, rle->rid)) {
4457 pci_printf(&dinfo->cfg,
4458 "Resource still owned, oops. "
4459 "(type=%d, rid=%d, addr=%lx)\n",
4460 rle->type, rle->rid,
4461 rman_get_start(rle->res));
4462 bus_release_resource(child, rle->type, rle->rid,
4463 rle->res);
4464 }
4465 resource_list_unreserve(rl, dev, child, rle->type,
4466 rle->rid);
4467 }
4468 }
4469 resource_list_free(rl);
4470
4471 device_delete_child(dev, child);
4472 pci_freecfg(dinfo);
4473}
4474
4475void
4476pci_delete_resource(device_t dev, device_t child, int type, int rid)
4477{
4478 struct pci_devinfo *dinfo;
4479 struct resource_list *rl;
4480 struct resource_list_entry *rle;
4481
4482 if (device_get_parent(child) != dev)
4483 return;
4484
4485 dinfo = device_get_ivars(child);
4486 rl = &dinfo->resources;
4487 rle = resource_list_find(rl, type, rid);
4488 if (rle == NULL)
4489 return;
4490
4491 if (rle->res) {
4492 if (rman_get_flags(rle->res) & RF_ACTIVE ||
4493 resource_list_busy(rl, type, rid)) {
4494 device_printf(dev, "delete_resource: "
4495 "Resource still owned by child, oops. "
4496 "(type=%d, rid=%d, addr=%lx)\n",
4497 type, rid, rman_get_start(rle->res));
4498 return;
4499 }
4500 resource_list_unreserve(rl, dev, child, type, rid);
4501 }
4502 resource_list_delete(rl, type, rid);
4503}
4504
4505struct resource_list *
4506pci_get_resource_list (device_t dev, device_t child)
4507{
4508 struct pci_devinfo *dinfo = device_get_ivars(child);
4509
4510 return (&dinfo->resources);
4511}
4512
4513bus_dma_tag_t
4514pci_get_dma_tag(device_t bus, device_t dev)
4515{
4516 struct pci_softc *sc = device_get_softc(bus);
4517
4518 return (sc->sc_dma_tag);
4519}
4520
4521uint32_t
4522pci_read_config_method(device_t dev, device_t child, int reg, int width)
4523{
4524 struct pci_devinfo *dinfo = device_get_ivars(child);
4525 pcicfgregs *cfg = &dinfo->cfg;
4526
4527 return (PCIB_READ_CONFIG(device_get_parent(dev),
4528 cfg->bus, cfg->slot, cfg->func, reg, width));
4529}
4530
4531void
4532pci_write_config_method(device_t dev, device_t child, int reg,
4533 uint32_t val, int width)
4534{
4535 struct pci_devinfo *dinfo = device_get_ivars(child);
4536 pcicfgregs *cfg = &dinfo->cfg;
4537
4538 PCIB_WRITE_CONFIG(device_get_parent(dev),
4539 cfg->bus, cfg->slot, cfg->func, reg, val, width);
4540}
4541
4542int
4543pci_child_location_str_method(device_t dev, device_t child, char *buf,
4544 size_t buflen)
4545{
4546
4547 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
4548 pci_get_function(child));
4549 return (0);
4550}
4551
4552int
4553pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
4554 size_t buflen)
4555{
4556 struct pci_devinfo *dinfo;
4557 pcicfgregs *cfg;
4558
4559 dinfo = device_get_ivars(child);
4560 cfg = &dinfo->cfg;
4561 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
4562 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
4563 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
4564 cfg->progif);
4565 return (0);
4566}
4567
4568int
4569pci_assign_interrupt_method(device_t dev, device_t child)
4570{
4571 struct pci_devinfo *dinfo = device_get_ivars(child);
4572 pcicfgregs *cfg = &dinfo->cfg;
4573
4574 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
4575 cfg->intpin));
4576}
4577
4578static int
4579pci_modevent(module_t mod, int what, void *arg)
4580{
4581 static struct cdev *pci_cdev;
4582
4583 switch (what) {
4584 case MOD_LOAD:
4585 STAILQ_INIT(&pci_devq);
4586 pci_generation = 0;
4587 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
4588 "pci");
4589 pci_load_vendor_data();
4590 break;
4591
4592 case MOD_UNLOAD:
4593 destroy_dev(pci_cdev);
4594 break;
4595 }
4596
4597 return (0);
4598}
4599
4600static void
4601pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo)
4602{
4603#define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2)
4604 struct pcicfg_pcie *cfg;
4605 int version, pos;
4606
4607 cfg = &dinfo->cfg.pcie;
4608 pos = cfg->pcie_location;
4609
4610 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
4611
4612 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl);
4613
4614 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4615 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
4616 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
4617 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl);
4618
4619 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4620 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
4621 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
4622 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl);
4623
4624 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4625 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
4626 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl);
4627
4628 if (version > 1) {
4629 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2);
4630 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2);
4631 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2);
4632 }
4633#undef WREG
4634}
4635
4636static void
4637pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo)
4638{
4639 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND,
4640 dinfo->cfg.pcix.pcix_command, 2);
4641}
4642
4643void
4644pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
4645{
4646
4647 /*
4648 * Only do header type 0 devices. Type 1 devices are bridges,
4649 * which we know need special treatment. Type 2 devices are
4650 * cardbus bridges which also require special treatment.
4651 * Other types are unknown, and we err on the side of safety
4652 * by ignoring them.
4653 */
4654 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
4655 return;
4656
4657 /*
4658 * Restore the device to full power mode. We must do this
4659 * before we restore the registers because moving from D3 to
4660 * D0 will cause the chip's BARs and some other registers to
4661 * be reset to some unknown power on reset values. Cut down
4662 * the noise on boot by doing nothing if we are already in
4663 * state D0.
4664 */
4665 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0)
4666 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4667 pci_restore_bars(dev);
4668 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4669 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4670 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4671 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4672 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4673 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4674 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4675 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4676 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4677
4678 /*
4679 * Restore extended capabilities for PCI-Express and PCI-X
4680 */
4681 if (dinfo->cfg.pcie.pcie_location != 0)
4682 pci_cfg_restore_pcie(dev, dinfo);
4683 if (dinfo->cfg.pcix.pcix_location != 0)
4684 pci_cfg_restore_pcix(dev, dinfo);
4685
4686 /* Restore MSI and MSI-X configurations if they are present. */
4687 if (dinfo->cfg.msi.msi_location != 0)
4688 pci_resume_msi(dev);
4689 if (dinfo->cfg.msix.msix_location != 0)
4690 pci_resume_msix(dev);
4691}
4692
4693static void
4694pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo)
4695{
4696#define RREG(n) pci_read_config(dev, pos + (n), 2)
4697 struct pcicfg_pcie *cfg;
4698 int version, pos;
4699
4700 cfg = &dinfo->cfg.pcie;
4701 pos = cfg->pcie_location;
4702
4703 cfg->pcie_flags = RREG(PCIER_FLAGS);
4704
4705 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
4706
4707 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL);
4708
4709 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4710 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
4711 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
4712 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL);
4713
4714 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4715 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
4716 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
4717 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL);
4718
4719 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4720 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
4721 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL);
4722
4723 if (version > 1) {
4724 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2);
4725 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2);
4726 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2);
4727 }
4728#undef RREG
4729}
4730
4731static void
4732pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo)
4733{
4734 dinfo->cfg.pcix.pcix_command = pci_read_config(dev,
4735 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2);
4736}
4737
4738void
4739pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4740{
4741 uint32_t cls;
4742 int ps;
4743
4744 /*
4745 * Only do header type 0 devices. Type 1 devices are bridges, which
4746 * we know need special treatment. Type 2 devices are cardbus bridges
4747 * which also require special treatment. Other types are unknown, and
4748 * we err on the side of safety by ignoring them. Powering down
4749 * bridges should not be undertaken lightly.
4750 */
4751 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
4752 return;
4753
4754 /*
4755 * Some drivers apparently write to these registers w/o updating our
4756 * cached copy. No harm happens if we update the copy, so do so here
4757 * so we can restore them. The COMMAND register is modified by the
4758 * bus w/o updating the cache. This should represent the normally
4759 * writable portion of the 'defined' part of type 0 headers. In
4760 * theory we also need to save/restore the PCI capability structures
4761 * we know about, but apart from power we don't know any that are
4762 * writable.
4763 */
4764 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4765 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4766 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4767 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4768 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4769 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4770 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4771 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4772 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4773 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4774 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4775 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4776 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4777 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4778 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4779
4780 if (dinfo->cfg.pcie.pcie_location != 0)
4781 pci_cfg_save_pcie(dev, dinfo);
4782
4783 if (dinfo->cfg.pcix.pcix_location != 0)
4784 pci_cfg_save_pcix(dev, dinfo);
4785
4786 /*
4787 * don't set the state for display devices, base peripherals and
4788 * memory devices since bad things happen when they are powered down.
4789 * We should (a) have drivers that can easily detach and (b) use
4790 * generic drivers for these devices so that some device actually
4791 * attaches. We need to make sure that when we implement (a) we don't
4792 * power the device down on a reattach.
4793 */
4794 cls = pci_get_class(dev);
4795 if (!setstate)
4796 return;
4797 switch (pci_do_power_nodriver)
4798 {
4799 case 0: /* NO powerdown at all */
4800 return;
4801 case 1: /* Conservative about what to power down */
4802 if (cls == PCIC_STORAGE)
4803 return;
4804 /*FALLTHROUGH*/
4805 case 2: /* Agressive about what to power down */
4806 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4807 cls == PCIC_BASEPERIPH)
4808 return;
4809 /*FALLTHROUGH*/
4810 case 3: /* Power down everything */
4811 break;
4812 }
4813 /*
4814 * PCI spec says we can only go into D3 state from D0 state.
4815 * Transition from D[12] into D0 before going to D3 state.
4816 */
4817 ps = pci_get_powerstate(dev);
4818 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4819 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4820 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4821 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
4822}
4823
4824/* Wrapper APIs suitable for device driver use. */
4825void
4826pci_save_state(device_t dev)
4827{
4828 struct pci_devinfo *dinfo;
4829
4830 dinfo = device_get_ivars(dev);
4831 pci_cfg_save(dev, dinfo, 0);
4832}
4833
4834void
4835pci_restore_state(device_t dev)
4836{
4837 struct pci_devinfo *dinfo;
4838
4839 dinfo = device_get_ivars(dev);
4840 pci_cfg_restore(dev, dinfo);
4841}
| 4514 case SYS_RES_IRQ:
4515 /*
4516 * Can't alloc legacy interrupt once MSI messages have
4517 * been allocated.
4518 */
4519 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
4520 cfg->msix.msix_alloc > 0))
4521 return (NULL);
4522
4523 /*
4524 * If the child device doesn't have an interrupt
4525 * routed and is deserving of an interrupt, try to
4526 * assign it one.
4527 */
4528 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
4529 (cfg->intpin != 0))
4530 pci_assign_interrupt(dev, child, 0);
4531 break;
4532 case SYS_RES_IOPORT:
4533 case SYS_RES_MEMORY:
4534#ifdef NEW_PCIB
4535 /*
4536 * PCI-PCI bridge I/O window resources are not BARs.
4537 * For those allocations just pass the request up the
4538 * tree.
4539 */
4540 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) {
4541 switch (*rid) {
4542 case PCIR_IOBASEL_1:
4543 case PCIR_MEMBASE_1:
4544 case PCIR_PMBASEL_1:
4545 /*
4546 * XXX: Should we bother creating a resource
4547 * list entry?
4548 */
4549 return (bus_generic_alloc_resource(dev, child,
4550 type, rid, start, end, count, flags));
4551 }
4552 }
4553#endif
4554 /* Reserve resources for this BAR if needed. */
4555 rle = resource_list_find(rl, type, *rid);
4556 if (rle == NULL) {
4557 res = pci_reserve_map(dev, child, type, rid, start, end,
4558 count, flags);
4559 if (res == NULL)
4560 return (NULL);
4561 }
4562 }
4563 return (resource_list_alloc(rl, dev, child, type, rid,
4564 start, end, count, flags));
4565}
4566
4567int
4568pci_release_resource(device_t dev, device_t child, int type, int rid,
4569 struct resource *r)
4570{
4571 struct pci_devinfo *dinfo;
4572 struct resource_list *rl;
4573 pcicfgregs *cfg;
4574
4575 if (device_get_parent(child) != dev)
4576 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
4577 type, rid, r));
4578
4579 dinfo = device_get_ivars(child);
4580 cfg = &dinfo->cfg;
4581#ifdef NEW_PCIB
4582 /*
4583 * PCI-PCI bridge I/O window resources are not BARs. For
4584 * those allocations just pass the request up the tree.
4585 */
4586 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE &&
4587 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) {
4588 switch (rid) {
4589 case PCIR_IOBASEL_1:
4590 case PCIR_MEMBASE_1:
4591 case PCIR_PMBASEL_1:
4592 return (bus_generic_release_resource(dev, child, type,
4593 rid, r));
4594 }
4595 }
4596#endif
4597
4598 rl = &dinfo->resources;
4599 return (resource_list_release(rl, dev, child, type, rid, r));
4600}
4601
4602int
4603pci_activate_resource(device_t dev, device_t child, int type, int rid,
4604 struct resource *r)
4605{
4606 struct pci_devinfo *dinfo;
4607 int error;
4608
4609 error = bus_generic_activate_resource(dev, child, type, rid, r);
4610 if (error)
4611 return (error);
4612
4613 /* Enable decoding in the command register when activating BARs. */
4614 if (device_get_parent(child) == dev) {
4615 /* Device ROMs need their decoding explicitly enabled. */
4616 dinfo = device_get_ivars(child);
4617 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
4618 pci_write_bar(child, pci_find_bar(child, rid),
4619 rman_get_start(r) | PCIM_BIOS_ENABLE);
4620 switch (type) {
4621 case SYS_RES_IOPORT:
4622 case SYS_RES_MEMORY:
4623 error = PCI_ENABLE_IO(dev, child, type);
4624 break;
4625 }
4626 }
4627 return (error);
4628}
4629
4630int
4631pci_deactivate_resource(device_t dev, device_t child, int type,
4632 int rid, struct resource *r)
4633{
4634 struct pci_devinfo *dinfo;
4635 int error;
4636
4637 error = bus_generic_deactivate_resource(dev, child, type, rid, r);
4638 if (error)
4639 return (error);
4640
4641 /* Disable decoding for device ROMs. */
4642 if (device_get_parent(child) == dev) {
4643 dinfo = device_get_ivars(child);
4644 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
4645 pci_write_bar(child, pci_find_bar(child, rid),
4646 rman_get_start(r));
4647 }
4648 return (0);
4649}
4650
4651void
4652pci_delete_child(device_t dev, device_t child)
4653{
4654 struct resource_list_entry *rle;
4655 struct resource_list *rl;
4656 struct pci_devinfo *dinfo;
4657
4658 dinfo = device_get_ivars(child);
4659 rl = &dinfo->resources;
4660
4661 if (device_is_attached(child))
4662 device_detach(child);
4663
4664 /* Turn off access to resources we're about to free */
4665 pci_write_config(child, PCIR_COMMAND, pci_read_config(child,
4666 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2);
4667
4668 /* Free all allocated resources */
4669 STAILQ_FOREACH(rle, rl, link) {
4670 if (rle->res) {
4671 if (rman_get_flags(rle->res) & RF_ACTIVE ||
4672 resource_list_busy(rl, rle->type, rle->rid)) {
4673 pci_printf(&dinfo->cfg,
4674 "Resource still owned, oops. "
4675 "(type=%d, rid=%d, addr=%lx)\n",
4676 rle->type, rle->rid,
4677 rman_get_start(rle->res));
4678 bus_release_resource(child, rle->type, rle->rid,
4679 rle->res);
4680 }
4681 resource_list_unreserve(rl, dev, child, rle->type,
4682 rle->rid);
4683 }
4684 }
4685 resource_list_free(rl);
4686
4687 device_delete_child(dev, child);
4688 pci_freecfg(dinfo);
4689}
4690
4691void
4692pci_delete_resource(device_t dev, device_t child, int type, int rid)
4693{
4694 struct pci_devinfo *dinfo;
4695 struct resource_list *rl;
4696 struct resource_list_entry *rle;
4697
4698 if (device_get_parent(child) != dev)
4699 return;
4700
4701 dinfo = device_get_ivars(child);
4702 rl = &dinfo->resources;
4703 rle = resource_list_find(rl, type, rid);
4704 if (rle == NULL)
4705 return;
4706
4707 if (rle->res) {
4708 if (rman_get_flags(rle->res) & RF_ACTIVE ||
4709 resource_list_busy(rl, type, rid)) {
4710 device_printf(dev, "delete_resource: "
4711 "Resource still owned by child, oops. "
4712 "(type=%d, rid=%d, addr=%lx)\n",
4713 type, rid, rman_get_start(rle->res));
4714 return;
4715 }
4716 resource_list_unreserve(rl, dev, child, type, rid);
4717 }
4718 resource_list_delete(rl, type, rid);
4719}
4720
4721struct resource_list *
4722pci_get_resource_list (device_t dev, device_t child)
4723{
4724 struct pci_devinfo *dinfo = device_get_ivars(child);
4725
4726 return (&dinfo->resources);
4727}
4728
4729bus_dma_tag_t
4730pci_get_dma_tag(device_t bus, device_t dev)
4731{
4732 struct pci_softc *sc = device_get_softc(bus);
4733
4734 return (sc->sc_dma_tag);
4735}
4736
4737uint32_t
4738pci_read_config_method(device_t dev, device_t child, int reg, int width)
4739{
4740 struct pci_devinfo *dinfo = device_get_ivars(child);
4741 pcicfgregs *cfg = &dinfo->cfg;
4742
4743 return (PCIB_READ_CONFIG(device_get_parent(dev),
4744 cfg->bus, cfg->slot, cfg->func, reg, width));
4745}
4746
4747void
4748pci_write_config_method(device_t dev, device_t child, int reg,
4749 uint32_t val, int width)
4750{
4751 struct pci_devinfo *dinfo = device_get_ivars(child);
4752 pcicfgregs *cfg = &dinfo->cfg;
4753
4754 PCIB_WRITE_CONFIG(device_get_parent(dev),
4755 cfg->bus, cfg->slot, cfg->func, reg, val, width);
4756}
4757
4758int
4759pci_child_location_str_method(device_t dev, device_t child, char *buf,
4760 size_t buflen)
4761{
4762
4763 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
4764 pci_get_function(child));
4765 return (0);
4766}
4767
4768int
4769pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
4770 size_t buflen)
4771{
4772 struct pci_devinfo *dinfo;
4773 pcicfgregs *cfg;
4774
4775 dinfo = device_get_ivars(child);
4776 cfg = &dinfo->cfg;
4777 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
4778 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
4779 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
4780 cfg->progif);
4781 return (0);
4782}
4783
4784int
4785pci_assign_interrupt_method(device_t dev, device_t child)
4786{
4787 struct pci_devinfo *dinfo = device_get_ivars(child);
4788 pcicfgregs *cfg = &dinfo->cfg;
4789
4790 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
4791 cfg->intpin));
4792}
4793
4794static int
4795pci_modevent(module_t mod, int what, void *arg)
4796{
4797 static struct cdev *pci_cdev;
4798
4799 switch (what) {
4800 case MOD_LOAD:
4801 STAILQ_INIT(&pci_devq);
4802 pci_generation = 0;
4803 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
4804 "pci");
4805 pci_load_vendor_data();
4806 break;
4807
4808 case MOD_UNLOAD:
4809 destroy_dev(pci_cdev);
4810 break;
4811 }
4812
4813 return (0);
4814}
4815
4816static void
4817pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo)
4818{
4819#define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2)
4820 struct pcicfg_pcie *cfg;
4821 int version, pos;
4822
4823 cfg = &dinfo->cfg.pcie;
4824 pos = cfg->pcie_location;
4825
4826 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
4827
4828 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl);
4829
4830 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4831 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
4832 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
4833 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl);
4834
4835 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4836 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
4837 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
4838 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl);
4839
4840 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4841 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
4842 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl);
4843
4844 if (version > 1) {
4845 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2);
4846 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2);
4847 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2);
4848 }
4849#undef WREG
4850}
4851
4852static void
4853pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo)
4854{
4855 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND,
4856 dinfo->cfg.pcix.pcix_command, 2);
4857}
4858
4859void
4860pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
4861{
4862
4863 /*
4864 * Only do header type 0 devices. Type 1 devices are bridges,
4865 * which we know need special treatment. Type 2 devices are
4866 * cardbus bridges which also require special treatment.
4867 * Other types are unknown, and we err on the side of safety
4868 * by ignoring them.
4869 */
4870 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
4871 return;
4872
4873 /*
4874 * Restore the device to full power mode. We must do this
4875 * before we restore the registers because moving from D3 to
4876 * D0 will cause the chip's BARs and some other registers to
4877 * be reset to some unknown power on reset values. Cut down
4878 * the noise on boot by doing nothing if we are already in
4879 * state D0.
4880 */
4881 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0)
4882 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4883 pci_restore_bars(dev);
4884 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4885 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4886 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4887 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4888 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4889 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4890 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4891 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4892 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4893
4894 /*
4895 * Restore extended capabilities for PCI-Express and PCI-X
4896 */
4897 if (dinfo->cfg.pcie.pcie_location != 0)
4898 pci_cfg_restore_pcie(dev, dinfo);
4899 if (dinfo->cfg.pcix.pcix_location != 0)
4900 pci_cfg_restore_pcix(dev, dinfo);
4901
4902 /* Restore MSI and MSI-X configurations if they are present. */
4903 if (dinfo->cfg.msi.msi_location != 0)
4904 pci_resume_msi(dev);
4905 if (dinfo->cfg.msix.msix_location != 0)
4906 pci_resume_msix(dev);
4907}
4908
4909static void
4910pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo)
4911{
4912#define RREG(n) pci_read_config(dev, pos + (n), 2)
4913 struct pcicfg_pcie *cfg;
4914 int version, pos;
4915
4916 cfg = &dinfo->cfg.pcie;
4917 pos = cfg->pcie_location;
4918
4919 cfg->pcie_flags = RREG(PCIER_FLAGS);
4920
4921 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
4922
4923 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL);
4924
4925 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4926 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
4927 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
4928 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL);
4929
4930 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4931 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
4932 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
4933 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL);
4934
4935 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4936 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
4937 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL);
4938
4939 if (version > 1) {
4940 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2);
4941 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2);
4942 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2);
4943 }
4944#undef RREG
4945}
4946
4947static void
4948pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo)
4949{
4950 dinfo->cfg.pcix.pcix_command = pci_read_config(dev,
4951 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2);
4952}
4953
4954void
4955pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4956{
4957 uint32_t cls;
4958 int ps;
4959
4960 /*
4961 * Only do header type 0 devices. Type 1 devices are bridges, which
4962 * we know need special treatment. Type 2 devices are cardbus bridges
4963 * which also require special treatment. Other types are unknown, and
4964 * we err on the side of safety by ignoring them. Powering down
4965 * bridges should not be undertaken lightly.
4966 */
4967 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
4968 return;
4969
4970 /*
4971 * Some drivers apparently write to these registers w/o updating our
4972 * cached copy. No harm happens if we update the copy, so do so here
4973 * so we can restore them. The COMMAND register is modified by the
4974 * bus w/o updating the cache. This should represent the normally
4975 * writable portion of the 'defined' part of type 0 headers. In
4976 * theory we also need to save/restore the PCI capability structures
4977 * we know about, but apart from power we don't know any that are
4978 * writable.
4979 */
4980 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4981 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4982 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4983 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4984 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4985 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4986 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4987 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4988 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4989 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4990 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4991 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4992 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4993 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4994 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4995
4996 if (dinfo->cfg.pcie.pcie_location != 0)
4997 pci_cfg_save_pcie(dev, dinfo);
4998
4999 if (dinfo->cfg.pcix.pcix_location != 0)
5000 pci_cfg_save_pcix(dev, dinfo);
5001
5002 /*
5003 * don't set the state for display devices, base peripherals and
5004 * memory devices since bad things happen when they are powered down.
5005 * We should (a) have drivers that can easily detach and (b) use
5006 * generic drivers for these devices so that some device actually
5007 * attaches. We need to make sure that when we implement (a) we don't
5008 * power the device down on a reattach.
5009 */
5010 cls = pci_get_class(dev);
5011 if (!setstate)
5012 return;
5013 switch (pci_do_power_nodriver)
5014 {
5015 case 0: /* NO powerdown at all */
5016 return;
5017 case 1: /* Conservative about what to power down */
5018 if (cls == PCIC_STORAGE)
5019 return;
5020 /*FALLTHROUGH*/
5021 case 2: /* Agressive about what to power down */
5022 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
5023 cls == PCIC_BASEPERIPH)
5024 return;
5025 /*FALLTHROUGH*/
5026 case 3: /* Power down everything */
5027 break;
5028 }
5029 /*
5030 * PCI spec says we can only go into D3 state from D0 state.
5031 * Transition from D[12] into D0 before going to D3 state.
5032 */
5033 ps = pci_get_powerstate(dev);
5034 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
5035 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
5036 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
5037 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
5038}
5039
5040/* Wrapper APIs suitable for device driver use. */
5041void
5042pci_save_state(device_t dev)
5043{
5044 struct pci_devinfo *dinfo;
5045
5046 dinfo = device_get_ivars(dev);
5047 pci_cfg_save(dev, dinfo, 0);
5048}
5049
5050void
5051pci_restore_state(device_t dev)
5052{
5053 struct pci_devinfo *dinfo;
5054
5055 dinfo = device_get_ivars(dev);
5056 pci_cfg_restore(dev, dinfo);
5057}
|