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oce_mbox.c (331722) oce_mbox.c (338938)
1/*-
2 * Copyright (C) 2013 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,

--- 22 unchanged lines hidden (view full) ---

31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
1/*-
2 * Copyright (C) 2013 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,

--- 22 unchanged lines hidden (view full) ---

31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
39/* $FreeBSD: stable/11/sys/dev/oce/oce_mbox.c 331722 2018-03-29 02:50:57Z eadler $ */
39/* $FreeBSD: stable/11/sys/dev/oce/oce_mbox.c 338938 2018-09-25 23:48:43Z jpaetzel $ */
40
41#include "oce_if.h"
42extern uint32_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_NUM_ELE];
43
44/**
45 * @brief Reset (firmware) common function
46 * @param sc software handle to the device
47 * @returns 0 on success, ETIMEDOUT on failure

--- 442 unchanged lines hidden (view full) ---

490 }
491
492 DW_SWAP(u32ptr(fwcmd), sizeof(struct mbx_common_query_fw_config));
493
494 sc->config_number = HOST_32(fwcmd->params.rsp.config_number);
495 sc->asic_revision = HOST_32(fwcmd->params.rsp.asic_revision);
496 sc->port_id = HOST_32(fwcmd->params.rsp.port_id);
497 sc->function_mode = HOST_32(fwcmd->params.rsp.function_mode);
40
41#include "oce_if.h"
42extern uint32_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_NUM_ELE];
43
44/**
45 * @brief Reset (firmware) common function
46 * @param sc software handle to the device
47 * @returns 0 on success, ETIMEDOUT on failure

--- 442 unchanged lines hidden (view full) ---

490 }
491
492 DW_SWAP(u32ptr(fwcmd), sizeof(struct mbx_common_query_fw_config));
493
494 sc->config_number = HOST_32(fwcmd->params.rsp.config_number);
495 sc->asic_revision = HOST_32(fwcmd->params.rsp.asic_revision);
496 sc->port_id = HOST_32(fwcmd->params.rsp.port_id);
497 sc->function_mode = HOST_32(fwcmd->params.rsp.function_mode);
498 if ((sc->function_mode & (ULP_NIC_MODE | ULP_RDMA_MODE)) ==
499 (ULP_NIC_MODE | ULP_RDMA_MODE)) {
500 sc->rdma_flags = OCE_RDMA_FLAG_SUPPORTED;
501 }
498 sc->function_caps = HOST_32(fwcmd->params.rsp.function_caps);
499
500 if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) {
501 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[0].nic_wq_tot);
502 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[0].lro_rqid_tot);
503 } else {
504 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[1].nic_wq_tot);
505 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[1].lro_rqid_tot);

--- 256 unchanged lines hidden (view full) ---

762 if (i == 0) {
763 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n");
764 rc = ENXIO;
765
766 }
767
768 /* fill log2 value indicating the size of the CPU table */
769 if (rc == 0)
502 sc->function_caps = HOST_32(fwcmd->params.rsp.function_caps);
503
504 if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) {
505 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[0].nic_wq_tot);
506 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[0].lro_rqid_tot);
507 } else {
508 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[1].nic_wq_tot);
509 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[1].lro_rqid_tot);

--- 256 unchanged lines hidden (view full) ---

766 if (i == 0) {
767 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n");
768 rc = ENXIO;
769
770 }
771
772 /* fill log2 value indicating the size of the CPU table */
773 if (rc == 0)
770 fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(i));
774 fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(INDIRECTION_TABLE_ENTRIES));
771
772 return rc;
773}
774
775/**
776 * @brief Function to set flow control capability in the hardware
777 * @param sc software handle to the device
778 * @param if_id interface id to read the address from

--- 24 unchanged lines hidden (view full) ---

803 MBX_TIMEOUT_SEC,
804 sizeof(struct mbx_config_nic_rss),
805 version);
806 if (enable_rss)
807 fwcmd->params.req.enable_rss |= (RSS_ENABLE_IPV4 |
808 RSS_ENABLE_TCP_IPV4 |
809 RSS_ENABLE_IPV6 |
810 RSS_ENABLE_TCP_IPV6);
775
776 return rc;
777}
778
779/**
780 * @brief Function to set flow control capability in the hardware
781 * @param sc software handle to the device
782 * @param if_id interface id to read the address from

--- 24 unchanged lines hidden (view full) ---

807 MBX_TIMEOUT_SEC,
808 sizeof(struct mbx_config_nic_rss),
809 version);
810 if (enable_rss)
811 fwcmd->params.req.enable_rss |= (RSS_ENABLE_IPV4 |
812 RSS_ENABLE_TCP_IPV4 |
813 RSS_ENABLE_IPV6 |
814 RSS_ENABLE_TCP_IPV6);
811 fwcmd->params.req.flush = OCE_FLUSH;
815
816 if(!sc->enable_hwlro)
817 fwcmd->params.req.flush = OCE_FLUSH;
818 else
819 fwcmd->params.req.flush = 0;
820
812 fwcmd->params.req.if_id = LE_32(if_id);
813
821 fwcmd->params.req.if_id = LE_32(if_id);
822
823 srandom(arc4random()); /* random entropy seed */
814 read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash));
815
816 rc = oce_rss_itbl_init(sc, fwcmd);
817 if (rc == 0) {
818 mbx.u0.s.embedded = 1;
819 mbx.payload_length = sizeof(struct mbx_config_nic_rss);
820 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
821

--- 37 unchanged lines hidden (view full) ---

859 req = &fwcmd->params.req;
860 req->iface_flags_mask = MBX_RX_IFACE_FLAGS_PROMISCUOUS |
861 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
862 /* Bit 0 Mac promisc, Bit 1 Vlan promisc */
863 if (enable & 0x01)
864 req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS;
865
866 if (enable & 0x02)
824 read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash));
825
826 rc = oce_rss_itbl_init(sc, fwcmd);
827 if (rc == 0) {
828 mbx.u0.s.embedded = 1;
829 mbx.payload_length = sizeof(struct mbx_config_nic_rss);
830 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
831

--- 37 unchanged lines hidden (view full) ---

869 req = &fwcmd->params.req;
870 req->iface_flags_mask = MBX_RX_IFACE_FLAGS_PROMISCUOUS |
871 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
872 /* Bit 0 Mac promisc, Bit 1 Vlan promisc */
873 if (enable & 0x01)
874 req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS;
875
876 if (enable & 0x02)
867 req->iface_flags = MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
877 req->iface_flags |= MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
868
869 req->if_id = sc->if_id;
870
871 rc = oce_set_common_iface_rx_filter(sc, &sgl);
872 oce_dma_free(sc, &sgl);
873
874 return rc;
875}

--- 87 unchanged lines hidden (view full) ---

963 link->qos_link_speed = HOST_16(fwcmd->params.rsp.qos_link_speed);
964 link->phys_port_speed = fwcmd->params.rsp.physical_port_speed;
965 link->logical_link_status = fwcmd->params.rsp.logical_link_status;
966error:
967 return rc;
968}
969
970
878
879 req->if_id = sc->if_id;
880
881 rc = oce_set_common_iface_rx_filter(sc, &sgl);
882 oce_dma_free(sc, &sgl);
883
884 return rc;
885}

--- 87 unchanged lines hidden (view full) ---

973 link->qos_link_speed = HOST_16(fwcmd->params.rsp.qos_link_speed);
974 link->phys_port_speed = fwcmd->params.rsp.physical_port_speed;
975 link->logical_link_status = fwcmd->params.rsp.logical_link_status;
976error:
977 return rc;
978}
979
980
971
972int
973oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem)
974{
975 struct oce_mbx mbx;
976 struct mbx_get_nic_stats_v0 *fwcmd;
977 int rc = 0;
978
979 bzero(&mbx, sizeof(struct oce_mbx));
980
981 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v0);
982 bzero(fwcmd, sizeof(struct mbx_get_nic_stats_v0));
983
984 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
985 MBX_SUBSYSTEM_NIC,
986 NIC_GET_STATS,
987 MBX_TIMEOUT_SEC,
988 sizeof(struct mbx_get_nic_stats_v0),
989 OCE_MBX_VER_V0);
990
991 mbx.u0.s.embedded = 0;
992 mbx.u0.s.sge_count = 1;
993
994 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
995
996 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
997 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
998 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_nic_stats_v0);
999
1000 mbx.payload_length = sizeof(struct mbx_get_nic_stats_v0);
1001
1002 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1003
1004 rc = oce_mbox_post(sc, &mbx, NULL);
1005
1006 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1007
1008 if (!rc)
1009 rc = fwcmd->hdr.u0.rsp.status;
1010 if (rc)
1011 device_printf(sc->dev,
1012 "%s failed - cmd status: %d addi status: %d\n",
1013 __FUNCTION__, rc,
1014 fwcmd->hdr.u0.rsp.additional_status);
1015 return rc;
1016}
1017
1018
1019
1020/**
1021 * @brief Function to get NIC statistics
981/**
982 * @brief Function to get NIC statistics
1022 * @param sc software handle to the device
1023 * @param *stats pointer to where to store statistics
1024 * @param reset_stats resets statistics of set
1025 * @returns 0 on success, EIO on failure
1026 * @note command depricated in Lancer
983 * @param sc software handle to the device
984 * @param *stats pointer to where to store statistics
985 * @param reset_stats resets statistics of set
986 * @returns 0 on success, EIO on failure
987 * @note command depricated in Lancer
1027 */
988 */
1028int
1029oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem)
1030{
1031 struct oce_mbx mbx;
1032 struct mbx_get_nic_stats *fwcmd;
1033 int rc = 0;
1034
1035 bzero(&mbx, sizeof(struct oce_mbx));
1036 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats);
1037 bzero(fwcmd, sizeof(struct mbx_get_nic_stats));
1038
1039 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1040 MBX_SUBSYSTEM_NIC,
1041 NIC_GET_STATS,
1042 MBX_TIMEOUT_SEC,
1043 sizeof(struct mbx_get_nic_stats),
1044 OCE_MBX_VER_V1);
1045
1046
1047 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1048 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1049
1050 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1051 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1052 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1053 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_nic_stats);
1054
1055 mbx.payload_length = sizeof(struct mbx_get_nic_stats);
1056 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1057
1058 rc = oce_mbox_post(sc, &mbx, NULL);
1059 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1060 if (!rc)
1061 rc = fwcmd->hdr.u0.rsp.status;
1062 if (rc)
1063 device_printf(sc->dev,
1064 "%s failed - cmd status: %d addi status: %d\n",
1065 __FUNCTION__, rc,
1066 fwcmd->hdr.u0.rsp.additional_status);
1067 return rc;
989#define OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, version) \
990int \
991oce_mbox_get_nic_stats_v##version(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem) \
992{ \
993 struct oce_mbx mbx; \
994 struct mbx_get_nic_stats_v##version *fwcmd; \
995 int rc = 0; \
996 \
997 bzero(&mbx, sizeof(struct oce_mbx)); \
998 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v##version); \
999 bzero(fwcmd, sizeof(*fwcmd)); \
1000 \
1001 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, \
1002 MBX_SUBSYSTEM_NIC, \
1003 NIC_GET_STATS, \
1004 MBX_TIMEOUT_SEC, \
1005 sizeof(*fwcmd), \
1006 OCE_MBX_VER_V##version); \
1007 \
1008 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ \
1009 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ \
1010 \
1011 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); \
1012 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); \
1013 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); \
1014 mbx.payload.u0.u1.sgl[0].length = sizeof(*fwcmd); \
1015 mbx.payload_length = sizeof(*fwcmd); \
1016 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); \
1017 \
1018 rc = oce_mbox_post(sc, &mbx, NULL); \
1019 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); \
1020 if (!rc) \
1021 rc = fwcmd->hdr.u0.rsp.status; \
1022 if (rc) \
1023 device_printf(sc->dev, \
1024 "%s failed - cmd status: %d addi status: %d\n", \
1025 __FUNCTION__, rc, \
1026 fwcmd->hdr.u0.rsp.additional_status); \
1027 return rc; \
1068}
1069
1028}
1029
1030OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 0);
1031OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 1);
1032OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 2);
1070
1033
1034
1071/**
1072 * @brief Function to get pport (physical port) statistics
1073 * @param sc software handle to the device
1074 * @param *stats pointer to where to store statistics
1075 * @param reset_stats resets statistics of set
1076 * @returns 0 on success, EIO on failure
1077 */
1078int

--- 1136 unchanged lines hidden (view full) ---

2215 sc->nrssqs = max_rss;
2216 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */
2217 }
2218error:
2219 oce_dma_free(sc, &dma);
2220 return rc;
2221
2222}
1035/**
1036 * @brief Function to get pport (physical port) statistics
1037 * @param sc software handle to the device
1038 * @param *stats pointer to where to store statistics
1039 * @param reset_stats resets statistics of set
1040 * @returns 0 on success, EIO on failure
1041 */
1042int

--- 1136 unchanged lines hidden (view full) ---

2179 sc->nrssqs = max_rss;
2180 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */
2181 }
2182error:
2183 oce_dma_free(sc, &dma);
2184 return rc;
2185
2186}
2187
2188/* hw lro functions */
2189
2190int
2191oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags)
2192{
2193 struct oce_mbx mbx;
2194 struct mbx_nic_query_lro_capabilities *fwcmd;
2195 int rc = 0;
2196
2197 bzero(&mbx, sizeof(struct oce_mbx));
2198
2199 fwcmd = (struct mbx_nic_query_lro_capabilities *)&mbx.payload;
2200 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2201 MBX_SUBSYSTEM_NIC,
2202 0x20,MBX_TIMEOUT_SEC,
2203 sizeof(struct mbx_nic_query_lro_capabilities),
2204 OCE_MBX_VER_V0);
2205
2206 mbx.u0.s.embedded = 1;
2207 mbx.payload_length = sizeof(struct mbx_nic_query_lro_capabilities);
2208
2209 rc = oce_mbox_post(sc, &mbx, NULL);
2210 if (!rc)
2211 rc = fwcmd->hdr.u0.rsp.status;
2212 if (rc) {
2213 device_printf(sc->dev,
2214 "%s failed - cmd status: %d addi status: %d\n",
2215 __FUNCTION__, rc,
2216 fwcmd->hdr.u0.rsp.additional_status);
2217
2218 return rc;
2219 }
2220 if(lro_flags)
2221 *lro_flags = HOST_32(fwcmd->params.rsp.lro_flags);
2222
2223 if(lro_rq_cnt)
2224 *lro_rq_cnt = HOST_16(fwcmd->params.rsp.lro_rq_cnt);
2225
2226 return rc;
2227}
2228
2229int
2230oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable)
2231{
2232 struct oce_mbx mbx;
2233 struct mbx_nic_set_iface_lro_config *fwcmd;
2234 int rc = 0;
2235
2236 bzero(&mbx, sizeof(struct oce_mbx));
2237
2238 fwcmd = (struct mbx_nic_set_iface_lro_config *)&mbx.payload;
2239 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2240 MBX_SUBSYSTEM_NIC,
2241 0x26,MBX_TIMEOUT_SEC,
2242 sizeof(struct mbx_nic_set_iface_lro_config),
2243 OCE_MBX_VER_V0);
2244
2245 mbx.u0.s.embedded = 1;
2246 mbx.payload_length = sizeof(struct mbx_nic_set_iface_lro_config);
2247
2248 fwcmd->params.req.iface_id = sc->if_id;
2249 fwcmd->params.req.lro_flags = 0;
2250
2251 if(enable) {
2252 fwcmd->params.req.lro_flags = LRO_FLAGS_HASH_MODE | LRO_FLAGS_RSS_MODE;
2253 fwcmd->params.req.lro_flags |= LRO_FLAGS_CLSC_IPV4 | LRO_FLAGS_CLSC_IPV6;
2254
2255 fwcmd->params.req.max_clsc_byte_cnt = 64*1024; /* min = 2974, max = 0xfa59 */
2256 fwcmd->params.req.max_clsc_seg_cnt = 43; /* min = 2, max = 64 */
2257 fwcmd->params.req.max_clsc_usec_delay = 18; /* min = 1, max = 256 */
2258 fwcmd->params.req.min_clsc_frame_byte_cnt = 0; /* min = 1, max = 9014 */
2259 }
2260
2261 rc = oce_mbox_post(sc, &mbx, NULL);
2262 if (!rc)
2263 rc = fwcmd->hdr.u0.rsp.status;
2264 if (rc) {
2265 device_printf(sc->dev,
2266 "%s failed - cmd status: %d addi status: %d\n",
2267 __FUNCTION__, rc,
2268 fwcmd->hdr.u0.rsp.additional_status);
2269
2270 return rc;
2271 }
2272 return rc;
2273}
2274
2275int
2276oce_mbox_create_rq_v2(struct oce_rq *rq)
2277{
2278 struct oce_mbx mbx;
2279 struct mbx_create_nic_rq_v2 *fwcmd;
2280 POCE_SOFTC sc = rq->parent;
2281 int rc = 0, num_pages = 0;
2282
2283 if (rq->qstate == QCREATED)
2284 return 0;
2285
2286 bzero(&mbx, sizeof(struct oce_mbx));
2287
2288 fwcmd = (struct mbx_create_nic_rq_v2 *)&mbx.payload;
2289 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2290 MBX_SUBSYSTEM_NIC,
2291 0x08, MBX_TIMEOUT_SEC,
2292 sizeof(struct mbx_create_nic_rq_v2),
2293 OCE_MBX_VER_V2);
2294
2295 /* oce_page_list will also prepare pages */
2296 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
2297
2298 fwcmd->params.req.cq_id = rq->cq->cq_id;
2299 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
2300 fwcmd->params.req.num_pages = num_pages;
2301
2302 fwcmd->params.req.if_id = sc->if_id;
2303
2304 fwcmd->params.req.max_frame_size = rq->cfg.mtu;
2305 fwcmd->params.req.page_size = 1;
2306 if(rq->cfg.is_rss_queue) {
2307 fwcmd->params.req.rq_flags = (NIC_RQ_FLAGS_RSS | NIC_RQ_FLAGS_LRO);
2308 }else {
2309 device_printf(sc->dev,
2310 "non rss lro queue should not be created \n");
2311 goto error;
2312 }
2313 mbx.u0.s.embedded = 1;
2314 mbx.payload_length = sizeof(struct mbx_create_nic_rq_v2);
2315
2316 rc = oce_mbox_post(sc, &mbx, NULL);
2317 if (!rc)
2318 rc = fwcmd->hdr.u0.rsp.status;
2319 if (rc) {
2320 device_printf(sc->dev,
2321 "%s failed - cmd status: %d addi status: %d\n",
2322 __FUNCTION__, rc,
2323 fwcmd->hdr.u0.rsp.additional_status);
2324 goto error;
2325 }
2326 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id);
2327 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;
2328
2329error:
2330 return rc;
2331}
2332