1/* $OpenBSD: if_nfereg.h,v 1.16 2006/02/22 19:23:44 damien Exp $ */
2
3/*-
4 * Copyright (c) 2005 Jonathan Gray <jsg@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
| 1/* $OpenBSD: if_nfereg.h,v 1.16 2006/02/22 19:23:44 damien Exp $ */
2
3/*-
4 * Copyright (c) 2005 Jonathan Gray <jsg@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
|
18 * $FreeBSD: head/sys/dev/nfe/if_nfereg.h 170604 2007-06-12 10:51:47Z yongari $
| 18 * $FreeBSD: head/sys/dev/nfe/if_nfereg.h 176859 2008-03-06 01:47:53Z yongari $
|
19 */
20
21#define NFE_RX_RING_COUNT 256
22#define NFE_JUMBO_RX_RING_COUNT NFE_RX_RING_COUNT
23#define NFE_TX_RING_COUNT 256
24
25#define NFE_PROC_DEFAULT ((NFE_RX_RING_COUNT * 3) / 4)
26#define NFE_PROC_MIN 50
27#define NFE_PROC_MAX (NFE_RX_RING_COUNT - 1)
28
29#define NFE_INC(x, y) (x) = ((x) + 1) % y
30
31/* RX/TX MAC addr + type + VLAN + align + slack */
32#define NFE_RX_HEADERS 64
33
34/* Maximum MTU size. */
35#define NV_PKTLIMIT_1 ETH_DATA_LEN /* Hard limit not known. */
36#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia:9202 */
37
38#define NFE_JUMBO_FRAMELEN NV_PKTLIMIT_2
39#define NFE_JUMBO_MTU \
40 (NFE_JUMBO_FRAMELEN - NFE_RX_HEADERS)
41#define NFE_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
| 19 */
20
21#define NFE_RX_RING_COUNT 256
22#define NFE_JUMBO_RX_RING_COUNT NFE_RX_RING_COUNT
23#define NFE_TX_RING_COUNT 256
24
25#define NFE_PROC_DEFAULT ((NFE_RX_RING_COUNT * 3) / 4)
26#define NFE_PROC_MIN 50
27#define NFE_PROC_MAX (NFE_RX_RING_COUNT - 1)
28
29#define NFE_INC(x, y) (x) = ((x) + 1) % y
30
31/* RX/TX MAC addr + type + VLAN + align + slack */
32#define NFE_RX_HEADERS 64
33
34/* Maximum MTU size. */
35#define NV_PKTLIMIT_1 ETH_DATA_LEN /* Hard limit not known. */
36#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia:9202 */
37
38#define NFE_JUMBO_FRAMELEN NV_PKTLIMIT_2
39#define NFE_JUMBO_MTU \
40 (NFE_JUMBO_FRAMELEN - NFE_RX_HEADERS)
41#define NFE_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
|
42#define NFE_JSLOTS ((NFE_JUMBO_RX_RING_COUNT * 3) / 2)
| |
43
| 42
|
44#define NFE_JRAWLEN (NFE_JUMBO_FRAMELEN + ETHER_ALIGN)
45#define NFE_JLEN \
46 (NFE_JRAWLEN + (sizeof(uint64_t) - (NFE_JRAWLEN % sizeof(uint64_t))))
47#define NFE_JPAGESZ PAGE_SIZE
48#define NFE_RESID \
49 (NFE_JPAGESZ - (NFE_JLEN * NFE_JSLOTS) % NFE_JPAGESZ)
50#define NFE_JMEM ((NFE_JLEN * NFE_JSLOTS) + NFE_RESID)
51
| |
52#define NFE_MAX_SCATTER 32
53#define NFE_TSO_MAXSGSIZE 4096
54#define NFE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header))
55
56#define NFE_IRQ_STATUS 0x000
57#define NFE_IRQ_MASK 0x004
58#define NFE_SETUP_R6 0x008
59#define NFE_IMTIMER 0x00c
60#define NFE_MSI_MAP0 0x020
61#define NFE_MSI_MAP1 0x024
62#define NFE_MSI_IRQ_MASK 0x030
63#define NFE_MAC_RESET 0x03c
64#define NFE_MISC1 0x080
65#define NFE_TX_CTL 0x084
66#define NFE_TX_STATUS 0x088
67#define NFE_RXFILTER 0x08c
68#define NFE_RXBUFSZ 0x090
69#define NFE_RX_CTL 0x094
70#define NFE_RX_STATUS 0x098
71#define NFE_RNDSEED 0x09c
72#define NFE_SETUP_R1 0x0a0
73#define NFE_SETUP_R2 0x0a4
74#define NFE_MACADDR_HI 0x0a8
75#define NFE_MACADDR_LO 0x0ac
76#define NFE_MULTIADDR_HI 0x0b0
77#define NFE_MULTIADDR_LO 0x0b4
78#define NFE_MULTIMASK_HI 0x0b8
79#define NFE_MULTIMASK_LO 0x0bc
80#define NFE_PHY_IFACE 0x0c0
81#define NFE_TX_RING_ADDR_LO 0x100
82#define NFE_RX_RING_ADDR_LO 0x104
83#define NFE_RING_SIZE 0x108
84#define NFE_TX_UNK 0x10c
85#define NFE_LINKSPEED 0x110
86#define NFE_SETUP_R5 0x130
87#define NFE_SETUP_R3 0x13C
88#define NFE_SETUP_R7 0x140
89#define NFE_RXTX_CTL 0x144
90#define NFE_TX_RING_ADDR_HI 0x148
91#define NFE_RX_RING_ADDR_HI 0x14c
92#define NFE_TX_PAUSE_FRAME 0x170
93#define NFE_PHY_STATUS 0x180
94#define NFE_SETUP_R4 0x184
95#define NFE_STATUS 0x188
96#define NFE_PHY_SPEED 0x18c
97#define NFE_PHY_CTL 0x190
98#define NFE_PHY_DATA 0x194
99#define NFE_WOL_CTL 0x200
100#define NFE_PATTERN_CRC 0x204
101#define NFE_PATTERN_MASK 0x208
102#define NFE_PWR_CAP 0x268
103#define NFE_PWR_STATE 0x26c
104#define NFE_VTAG_CTL 0x300
105#define NFE_MSIX_MAP0 0x3e0
106#define NFE_MSIX_MAP1 0x3e4
107#define NFE_MSIX_IRQ_STATUS 0x3f0
108#define NFE_PWR2_CTL 0x600
109
110#define NFE_MAC_RESET_MAGIC 0x00f3
111
112#define NFE_MAC_ADDR_INORDER 0x8000
113
114#define NFE_PHY_ERROR 0x00001
115#define NFE_PHY_WRITE 0x00400
116#define NFE_PHY_BUSY 0x08000
117#define NFE_PHYADD_SHIFT 5
118
119#define NFE_STATUS_MAGIC 0x140000
120
121#define NFE_R1_MAGIC_1000 0x14050f
122#define NFE_R1_MAGIC_10_100 0x16070f
123#define NFE_R1_MAGIC_DEFAULT 0x15050f
124#define NFE_R2_MAGIC 0x16
125#define NFE_R4_MAGIC 0x08
126#define NFE_R6_MAGIC 0x03
127#define NFE_WOL_MAGIC 0x1111
128#define NFE_RX_START 0x01
129#define NFE_TX_START 0x01
130
131#define NFE_IRQ_RXERR 0x0001
132#define NFE_IRQ_RX 0x0002
133#define NFE_IRQ_RX_NOBUF 0x0004
134#define NFE_IRQ_TXERR 0x0008
135#define NFE_IRQ_TX_DONE 0x0010
136#define NFE_IRQ_TIMER 0x0020
137#define NFE_IRQ_LINK 0x0040
138#define NFE_IRQ_TXERR2 0x0080
139#define NFE_IRQ_TX1 0x0100
140
141#define NFE_IRQ_WANTED \
142 (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX | \
143 NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE | \
144 NFE_IRQ_LINK)
145
146#define NFE_RXTX_KICKTX 0x0001
147#define NFE_RXTX_BIT1 0x0002
148#define NFE_RXTX_BIT2 0x0004
149#define NFE_RXTX_RESET 0x0010
150#define NFE_RXTX_VTAG_STRIP 0x0040
151#define NFE_RXTX_VTAG_INSERT 0x0080
152#define NFE_RXTX_RXCSUM 0x0400
153#define NFE_RXTX_V2MAGIC 0x2100
154#define NFE_RXTX_V3MAGIC 0x2200
155#define NFE_RXFILTER_MAGIC 0x007f0000
156#define NFE_PFF_RX_PAUSE (1 << 3)
157#define NFE_PFF_LOOPBACK (1 << 4)
158#define NFE_PFF_U2M (1 << 5)
159#define NFE_PFF_PROMISC (1 << 7)
160#define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
161
162/* default interrupt moderation timer of 128us */
163#define NFE_IM_DEFAULT ((128 * 100) / 1024)
164
165#define NFE_VTAG_ENABLE (1 << 13)
166
167#define NFE_PWR_VALID (1 << 8)
168#define NFE_PWR_WAKEUP (1 << 15)
169
170#define NFE_PWR2_WAKEUP_MASK 0x0f11
171#define NFE_PWR2_REVA3 (1 << 0)
172
173#define NFE_MEDIA_SET 0x10000
174#define NFE_MEDIA_1000T 0x00032
175#define NFE_MEDIA_100TX 0x00064
176#define NFE_MEDIA_10T 0x003e8
177
178#define NFE_PHY_100TX (1 << 0)
179#define NFE_PHY_1000T (1 << 1)
180#define NFE_PHY_HDX (1 << 8)
181
182#define NFE_MISC1_MAGIC 0x003b0f3c
183#define NFE_MISC1_TX_PAUSE (1 << 0)
184#define NFE_MISC1_HDX (1 << 1)
185
186#define NFE_TX_PAUSE_FRAME_DISABLE 0x1ff0080
187#define NFE_TX_PAUSE_FRAME_ENABLE 0x0c00030
188
189#define NFE_SEED_MASK 0x0003ff00
190#define NFE_SEED_10T 0x00007f00
191#define NFE_SEED_100TX 0x00002d00
192#define NFE_SEED_1000T 0x00007400
193
194#define NFE_MSI_MESSAGES 8
195#define NFE_MSI_VECTOR_0_ENABLED 0x01
196
197/*
198 * It seems that nForce supports only the lower 40 bits of a DMA address.
199 */
200#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
201#define NFE_DMA_MAXADDR BUS_SPACE_MAXADDR
202#else
203#define NFE_DMA_MAXADDR 0xFFFFFFFFFF
204#endif
205
206#define NFE_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff)
207#define NFE_ADDR_HI(x) ((u_int64_t) (x) >> 32)
208
209/* Rx/Tx descriptor */
210struct nfe_desc32 {
211 uint32_t physaddr;
212 uint16_t length;
213 uint16_t flags;
214#define NFE_RX_FIXME_V1 0x6004
215#define NFE_RX_VALID_V1 (1 << 0)
216#define NFE_TX_ERROR_V1 0x7808
217#define NFE_TX_LASTFRAG_V1 (1 << 0)
218#define NFE_RX_ERROR1_V1 (1<<7)
219#define NFE_RX_ERROR2_V1 (1<<8)
220#define NFE_RX_ERROR3_V1 (1<<9)
221#define NFE_RX_ERROR4_V1 (1<<10)
222} __packed;
223
224#define NFE_V1_TXERR "\020" \
225 "\14TXERROR\13UNDERFLOW\12LATECOLLISION\11LOSTCARRIER\10DEFERRED" \
226 "\08FORCEDINT\03RETRY\00LASTPACKET"
227
228/* V2 Rx/Tx descriptor */
229struct nfe_desc64 {
230 uint32_t physaddr[2];
231 uint32_t vtag;
232#define NFE_RX_VTAG (1 << 16)
233#define NFE_TX_VTAG (1 << 18)
234 uint16_t length;
235 uint16_t flags;
236#define NFE_RX_FIXME_V2 0x4300
237#define NFE_RX_VALID_V2 (1 << 13)
238#define NFE_TX_ERROR_V2 0x5c04
239#define NFE_TX_LASTFRAG_V2 (1 << 13)
240#define NFE_RX_ERROR1_V2 (1<<2)
241#define NFE_RX_ERROR2_V2 (1<<3)
242#define NFE_RX_ERROR3_V2 (1<<4)
243#define NFE_RX_ERROR4_V2 (1<<5)
244} __packed;
245
246#define NFE_V2_TXERR "\020" \
247 "\14FORCEDINT\13LASTPACKET\12UNDERFLOW\10LOSTCARRIER\09DEFERRED\02RETRY"
248
249#define NFE_RING_ALIGN (sizeof(struct nfe_desc64))
250
251/* flags common to V1/V2 descriptors */
252#define NFE_RX_UDP_CSUMOK (1 << 10)
253#define NFE_RX_TCP_CSUMOK (1 << 11)
254#define NFE_RX_IP_CSUMOK (1 << 12)
255#define NFE_RX_ERROR (1 << 14)
256#define NFE_RX_READY (1 << 15)
257#define NFE_RX_LEN_MASK 0x3fff
258#define NFE_TX_TCP_UDP_CSUM (1 << 10)
259#define NFE_TX_IP_CSUM (1 << 11)
260#define NFE_TX_TSO (1 << 12)
261#define NFE_TX_TSO_SHIFT 14
262#define NFE_TX_VALID (1 << 15)
263
264#define NFE_READ(sc, reg) \
265 bus_read_4((sc)->nfe_res[0], (reg))
266
267#define NFE_WRITE(sc, reg, val) \
268 bus_write_4((sc)->nfe_res[0], (reg), (val))
269
270#define NFE_TIMEOUT 1000
271
272#ifndef PCI_VENDOR_NVIDIA
273#define PCI_VENDOR_NVIDIA 0x10DE
274#endif
275
276#define PCI_PRODUCT_NVIDIA_NFORCE_LAN 0x01C3
277#define PCI_PRODUCT_NVIDIA_NFORCE2_LAN 0x0066
278#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 0x00D6
279#define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 0x0086
280#define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 0x008C
281#define PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 0x00E6
282#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 0x00DF
283#define PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 0x0056
284#define PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 0x0057
285#define PCI_PRODUCT_NVIDIA_MCP04_LAN1 0x0037
286#define PCI_PRODUCT_NVIDIA_MCP04_LAN2 0x0038
287#define PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 0x0268
288#define PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 0x0269
289#define PCI_PRODUCT_NVIDIA_MCP55_LAN1 0x0372
290#define PCI_PRODUCT_NVIDIA_MCP55_LAN2 0x0373
291#define PCI_PRODUCT_NVIDIA_MCP61_LAN1 0x03e5
292#define PCI_PRODUCT_NVIDIA_MCP61_LAN2 0x03e6
293#define PCI_PRODUCT_NVIDIA_MCP61_LAN3 0x03ee
294#define PCI_PRODUCT_NVIDIA_MCP61_LAN4 0x03ef
295#define PCI_PRODUCT_NVIDIA_MCP65_LAN1 0x0450
296#define PCI_PRODUCT_NVIDIA_MCP65_LAN2 0x0451
297#define PCI_PRODUCT_NVIDIA_MCP65_LAN3 0x0452
298#define PCI_PRODUCT_NVIDIA_MCP65_LAN4 0x0453
299#define PCI_PRODUCT_NVIDIA_MCP67_LAN1 0x054c
300#define PCI_PRODUCT_NVIDIA_MCP67_LAN2 0x054d
301#define PCI_PRODUCT_NVIDIA_MCP67_LAN3 0x054e
302#define PCI_PRODUCT_NVIDIA_MCP67_LAN4 0x054f
303
304#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1
305#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2
306#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN
307#define PCI_PRODUCT_NVIDIA_CK804_LAN1 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1
308#define PCI_PRODUCT_NVIDIA_CK804_LAN2 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2
309#define PCI_PRODUCT_NVIDIA_MCP51_LAN1 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1
310#define PCI_PRODUCT_NVIDIA_MCP51_LAN2 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2
311
312#define NFE_DEBUG 0x0000
313#define NFE_DEBUG_INIT 0x0001
314#define NFE_DEBUG_RUNNING 0x0002
315#define NFE_DEBUG_DEINIT 0x0004
316#define NFE_DEBUG_IOCTL 0x0008
317#define NFE_DEBUG_INTERRUPT 0x0010
318#define NFE_DEBUG_API 0x0020
319#define NFE_DEBUG_LOCK 0x0040
320#define NFE_DEBUG_BROKEN 0x0080
321#define NFE_DEBUG_MII 0x0100
322#define NFE_DEBUG_ALL 0xFFFF
| 43#define NFE_MAX_SCATTER 32
44#define NFE_TSO_MAXSGSIZE 4096
45#define NFE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header))
46
47#define NFE_IRQ_STATUS 0x000
48#define NFE_IRQ_MASK 0x004
49#define NFE_SETUP_R6 0x008
50#define NFE_IMTIMER 0x00c
51#define NFE_MSI_MAP0 0x020
52#define NFE_MSI_MAP1 0x024
53#define NFE_MSI_IRQ_MASK 0x030
54#define NFE_MAC_RESET 0x03c
55#define NFE_MISC1 0x080
56#define NFE_TX_CTL 0x084
57#define NFE_TX_STATUS 0x088
58#define NFE_RXFILTER 0x08c
59#define NFE_RXBUFSZ 0x090
60#define NFE_RX_CTL 0x094
61#define NFE_RX_STATUS 0x098
62#define NFE_RNDSEED 0x09c
63#define NFE_SETUP_R1 0x0a0
64#define NFE_SETUP_R2 0x0a4
65#define NFE_MACADDR_HI 0x0a8
66#define NFE_MACADDR_LO 0x0ac
67#define NFE_MULTIADDR_HI 0x0b0
68#define NFE_MULTIADDR_LO 0x0b4
69#define NFE_MULTIMASK_HI 0x0b8
70#define NFE_MULTIMASK_LO 0x0bc
71#define NFE_PHY_IFACE 0x0c0
72#define NFE_TX_RING_ADDR_LO 0x100
73#define NFE_RX_RING_ADDR_LO 0x104
74#define NFE_RING_SIZE 0x108
75#define NFE_TX_UNK 0x10c
76#define NFE_LINKSPEED 0x110
77#define NFE_SETUP_R5 0x130
78#define NFE_SETUP_R3 0x13C
79#define NFE_SETUP_R7 0x140
80#define NFE_RXTX_CTL 0x144
81#define NFE_TX_RING_ADDR_HI 0x148
82#define NFE_RX_RING_ADDR_HI 0x14c
83#define NFE_TX_PAUSE_FRAME 0x170
84#define NFE_PHY_STATUS 0x180
85#define NFE_SETUP_R4 0x184
86#define NFE_STATUS 0x188
87#define NFE_PHY_SPEED 0x18c
88#define NFE_PHY_CTL 0x190
89#define NFE_PHY_DATA 0x194
90#define NFE_WOL_CTL 0x200
91#define NFE_PATTERN_CRC 0x204
92#define NFE_PATTERN_MASK 0x208
93#define NFE_PWR_CAP 0x268
94#define NFE_PWR_STATE 0x26c
95#define NFE_VTAG_CTL 0x300
96#define NFE_MSIX_MAP0 0x3e0
97#define NFE_MSIX_MAP1 0x3e4
98#define NFE_MSIX_IRQ_STATUS 0x3f0
99#define NFE_PWR2_CTL 0x600
100
101#define NFE_MAC_RESET_MAGIC 0x00f3
102
103#define NFE_MAC_ADDR_INORDER 0x8000
104
105#define NFE_PHY_ERROR 0x00001
106#define NFE_PHY_WRITE 0x00400
107#define NFE_PHY_BUSY 0x08000
108#define NFE_PHYADD_SHIFT 5
109
110#define NFE_STATUS_MAGIC 0x140000
111
112#define NFE_R1_MAGIC_1000 0x14050f
113#define NFE_R1_MAGIC_10_100 0x16070f
114#define NFE_R1_MAGIC_DEFAULT 0x15050f
115#define NFE_R2_MAGIC 0x16
116#define NFE_R4_MAGIC 0x08
117#define NFE_R6_MAGIC 0x03
118#define NFE_WOL_MAGIC 0x1111
119#define NFE_RX_START 0x01
120#define NFE_TX_START 0x01
121
122#define NFE_IRQ_RXERR 0x0001
123#define NFE_IRQ_RX 0x0002
124#define NFE_IRQ_RX_NOBUF 0x0004
125#define NFE_IRQ_TXERR 0x0008
126#define NFE_IRQ_TX_DONE 0x0010
127#define NFE_IRQ_TIMER 0x0020
128#define NFE_IRQ_LINK 0x0040
129#define NFE_IRQ_TXERR2 0x0080
130#define NFE_IRQ_TX1 0x0100
131
132#define NFE_IRQ_WANTED \
133 (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX | \
134 NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE | \
135 NFE_IRQ_LINK)
136
137#define NFE_RXTX_KICKTX 0x0001
138#define NFE_RXTX_BIT1 0x0002
139#define NFE_RXTX_BIT2 0x0004
140#define NFE_RXTX_RESET 0x0010
141#define NFE_RXTX_VTAG_STRIP 0x0040
142#define NFE_RXTX_VTAG_INSERT 0x0080
143#define NFE_RXTX_RXCSUM 0x0400
144#define NFE_RXTX_V2MAGIC 0x2100
145#define NFE_RXTX_V3MAGIC 0x2200
146#define NFE_RXFILTER_MAGIC 0x007f0000
147#define NFE_PFF_RX_PAUSE (1 << 3)
148#define NFE_PFF_LOOPBACK (1 << 4)
149#define NFE_PFF_U2M (1 << 5)
150#define NFE_PFF_PROMISC (1 << 7)
151#define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
152
153/* default interrupt moderation timer of 128us */
154#define NFE_IM_DEFAULT ((128 * 100) / 1024)
155
156#define NFE_VTAG_ENABLE (1 << 13)
157
158#define NFE_PWR_VALID (1 << 8)
159#define NFE_PWR_WAKEUP (1 << 15)
160
161#define NFE_PWR2_WAKEUP_MASK 0x0f11
162#define NFE_PWR2_REVA3 (1 << 0)
163
164#define NFE_MEDIA_SET 0x10000
165#define NFE_MEDIA_1000T 0x00032
166#define NFE_MEDIA_100TX 0x00064
167#define NFE_MEDIA_10T 0x003e8
168
169#define NFE_PHY_100TX (1 << 0)
170#define NFE_PHY_1000T (1 << 1)
171#define NFE_PHY_HDX (1 << 8)
172
173#define NFE_MISC1_MAGIC 0x003b0f3c
174#define NFE_MISC1_TX_PAUSE (1 << 0)
175#define NFE_MISC1_HDX (1 << 1)
176
177#define NFE_TX_PAUSE_FRAME_DISABLE 0x1ff0080
178#define NFE_TX_PAUSE_FRAME_ENABLE 0x0c00030
179
180#define NFE_SEED_MASK 0x0003ff00
181#define NFE_SEED_10T 0x00007f00
182#define NFE_SEED_100TX 0x00002d00
183#define NFE_SEED_1000T 0x00007400
184
185#define NFE_MSI_MESSAGES 8
186#define NFE_MSI_VECTOR_0_ENABLED 0x01
187
188/*
189 * It seems that nForce supports only the lower 40 bits of a DMA address.
190 */
191#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
192#define NFE_DMA_MAXADDR BUS_SPACE_MAXADDR
193#else
194#define NFE_DMA_MAXADDR 0xFFFFFFFFFF
195#endif
196
197#define NFE_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff)
198#define NFE_ADDR_HI(x) ((u_int64_t) (x) >> 32)
199
200/* Rx/Tx descriptor */
201struct nfe_desc32 {
202 uint32_t physaddr;
203 uint16_t length;
204 uint16_t flags;
205#define NFE_RX_FIXME_V1 0x6004
206#define NFE_RX_VALID_V1 (1 << 0)
207#define NFE_TX_ERROR_V1 0x7808
208#define NFE_TX_LASTFRAG_V1 (1 << 0)
209#define NFE_RX_ERROR1_V1 (1<<7)
210#define NFE_RX_ERROR2_V1 (1<<8)
211#define NFE_RX_ERROR3_V1 (1<<9)
212#define NFE_RX_ERROR4_V1 (1<<10)
213} __packed;
214
215#define NFE_V1_TXERR "\020" \
216 "\14TXERROR\13UNDERFLOW\12LATECOLLISION\11LOSTCARRIER\10DEFERRED" \
217 "\08FORCEDINT\03RETRY\00LASTPACKET"
218
219/* V2 Rx/Tx descriptor */
220struct nfe_desc64 {
221 uint32_t physaddr[2];
222 uint32_t vtag;
223#define NFE_RX_VTAG (1 << 16)
224#define NFE_TX_VTAG (1 << 18)
225 uint16_t length;
226 uint16_t flags;
227#define NFE_RX_FIXME_V2 0x4300
228#define NFE_RX_VALID_V2 (1 << 13)
229#define NFE_TX_ERROR_V2 0x5c04
230#define NFE_TX_LASTFRAG_V2 (1 << 13)
231#define NFE_RX_ERROR1_V2 (1<<2)
232#define NFE_RX_ERROR2_V2 (1<<3)
233#define NFE_RX_ERROR3_V2 (1<<4)
234#define NFE_RX_ERROR4_V2 (1<<5)
235} __packed;
236
237#define NFE_V2_TXERR "\020" \
238 "\14FORCEDINT\13LASTPACKET\12UNDERFLOW\10LOSTCARRIER\09DEFERRED\02RETRY"
239
240#define NFE_RING_ALIGN (sizeof(struct nfe_desc64))
241
242/* flags common to V1/V2 descriptors */
243#define NFE_RX_UDP_CSUMOK (1 << 10)
244#define NFE_RX_TCP_CSUMOK (1 << 11)
245#define NFE_RX_IP_CSUMOK (1 << 12)
246#define NFE_RX_ERROR (1 << 14)
247#define NFE_RX_READY (1 << 15)
248#define NFE_RX_LEN_MASK 0x3fff
249#define NFE_TX_TCP_UDP_CSUM (1 << 10)
250#define NFE_TX_IP_CSUM (1 << 11)
251#define NFE_TX_TSO (1 << 12)
252#define NFE_TX_TSO_SHIFT 14
253#define NFE_TX_VALID (1 << 15)
254
255#define NFE_READ(sc, reg) \
256 bus_read_4((sc)->nfe_res[0], (reg))
257
258#define NFE_WRITE(sc, reg, val) \
259 bus_write_4((sc)->nfe_res[0], (reg), (val))
260
261#define NFE_TIMEOUT 1000
262
263#ifndef PCI_VENDOR_NVIDIA
264#define PCI_VENDOR_NVIDIA 0x10DE
265#endif
266
267#define PCI_PRODUCT_NVIDIA_NFORCE_LAN 0x01C3
268#define PCI_PRODUCT_NVIDIA_NFORCE2_LAN 0x0066
269#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 0x00D6
270#define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 0x0086
271#define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 0x008C
272#define PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 0x00E6
273#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 0x00DF
274#define PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 0x0056
275#define PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 0x0057
276#define PCI_PRODUCT_NVIDIA_MCP04_LAN1 0x0037
277#define PCI_PRODUCT_NVIDIA_MCP04_LAN2 0x0038
278#define PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 0x0268
279#define PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 0x0269
280#define PCI_PRODUCT_NVIDIA_MCP55_LAN1 0x0372
281#define PCI_PRODUCT_NVIDIA_MCP55_LAN2 0x0373
282#define PCI_PRODUCT_NVIDIA_MCP61_LAN1 0x03e5
283#define PCI_PRODUCT_NVIDIA_MCP61_LAN2 0x03e6
284#define PCI_PRODUCT_NVIDIA_MCP61_LAN3 0x03ee
285#define PCI_PRODUCT_NVIDIA_MCP61_LAN4 0x03ef
286#define PCI_PRODUCT_NVIDIA_MCP65_LAN1 0x0450
287#define PCI_PRODUCT_NVIDIA_MCP65_LAN2 0x0451
288#define PCI_PRODUCT_NVIDIA_MCP65_LAN3 0x0452
289#define PCI_PRODUCT_NVIDIA_MCP65_LAN4 0x0453
290#define PCI_PRODUCT_NVIDIA_MCP67_LAN1 0x054c
291#define PCI_PRODUCT_NVIDIA_MCP67_LAN2 0x054d
292#define PCI_PRODUCT_NVIDIA_MCP67_LAN3 0x054e
293#define PCI_PRODUCT_NVIDIA_MCP67_LAN4 0x054f
294
295#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1
296#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2
297#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN
298#define PCI_PRODUCT_NVIDIA_CK804_LAN1 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1
299#define PCI_PRODUCT_NVIDIA_CK804_LAN2 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2
300#define PCI_PRODUCT_NVIDIA_MCP51_LAN1 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1
301#define PCI_PRODUCT_NVIDIA_MCP51_LAN2 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2
302
303#define NFE_DEBUG 0x0000
304#define NFE_DEBUG_INIT 0x0001
305#define NFE_DEBUG_RUNNING 0x0002
306#define NFE_DEBUG_DEINIT 0x0004
307#define NFE_DEBUG_IOCTL 0x0008
308#define NFE_DEBUG_INTERRUPT 0x0010
309#define NFE_DEBUG_API 0x0020
310#define NFE_DEBUG_LOCK 0x0040
311#define NFE_DEBUG_BROKEN 0x0080
312#define NFE_DEBUG_MII 0x0100
313#define NFE_DEBUG_ALL 0xFFFF
|