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mrsas.h (273377) mrsas.h (282525)
1/*
2 * Copyright (c) 2014, LSI Corp. All rights reserved. Authors: Marian Choy
3 * Support: freebsdraid@lsi.com
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met:
8 *

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32 * official policies,either expressed or implied, of the FreeBSD Project.
33 *
34 * Send feedback to: <megaraidfbsd@lsi.com> Mail to: LSI Corporation, 1621
35 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD
36 *
37 */
38
39#include <sys/cdefs.h>
1/*
2 * Copyright (c) 2014, LSI Corp. All rights reserved. Authors: Marian Choy
3 * Support: freebsdraid@lsi.com
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met:
8 *

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32 * official policies,either expressed or implied, of the FreeBSD Project.
33 *
34 * Send feedback to: <megaraidfbsd@lsi.com> Mail to: LSI Corporation, 1621
35 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD
36 *
37 */
38
39#include <sys/cdefs.h>
40__FBSDID("$FreeBSD: head/sys/dev/mrsas/mrsas.h 273377 2014-10-21 07:31:21Z hselasky $");
40__FBSDID("$FreeBSD: head/sys/dev/mrsas/mrsas.h 282525 2015-05-06 10:32:27Z kadesai $");
41
42#ifndef MRSAS_H
43#define MRSAS_H
44
45#include <sys/param.h> /* defines used in kernel.h */
46#include <sys/module.h>
47#include <sys/systm.h>
48#include <sys/proc.h>

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2408#define MAX_MGMT_ADAPTERS 1024
2409
2410struct mrsas_mgmt_info {
2411 u_int16_t count;
2412 struct mrsas_softc *sc_ptr[MAX_MGMT_ADAPTERS];
2413 int max_index;
2414};
2415
41
42#ifndef MRSAS_H
43#define MRSAS_H
44
45#include <sys/param.h> /* defines used in kernel.h */
46#include <sys/module.h>
47#include <sys/systm.h>
48#include <sys/proc.h>

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2408#define MAX_MGMT_ADAPTERS 1024
2409
2410struct mrsas_mgmt_info {
2411 u_int16_t count;
2412 struct mrsas_softc *sc_ptr[MAX_MGMT_ADAPTERS];
2413 int max_index;
2414};
2415
2416#define PCI_TYPE0_ADDRESSES 6
2417#define PCI_TYPE1_ADDRESSES 2
2418#define PCI_TYPE2_ADDRESSES 5
2419
2420typedef struct _MRSAS_DRV_PCI_COMMON_HEADER
2421{
2422 u_int16_t vendorID; // (ro)
2423 u_int16_t deviceID; // (ro)
2424 u_int16_t command; // Device control
2425 u_int16_t status;
2426 u_int8_t revisionID; // (ro)
2427 u_int8_t progIf; // (ro)
2428 u_int8_t subClass; // (ro)
2429 u_int8_t baseClass; // (ro)
2430 u_int8_t cacheLineSize; // (ro+)
2431 u_int8_t latencyTimer; // (ro+)
2432 u_int8_t headerType; // (ro)
2433 u_int8_t bist; // Built in self test
2434
2435 union
2436 {
2437 struct _MRSAS_DRV_PCI_HEADER_TYPE_0
2438 {
2439 u_int32_t baseAddresses[PCI_TYPE0_ADDRESSES];
2440 u_int32_t cis;
2441 u_int16_t subVendorID;
2442 u_int16_t subSystemID;
2443 u_int32_t romBaseAddress;
2444 u_int8_t capabilitiesPtr;
2445 u_int8_t reserved1[3];
2446 u_int32_t reserved2;
2447 u_int8_t interruptLine;
2448 u_int8_t interruptPin; // (ro)
2449 u_int8_t minimumGrant; // (ro)
2450 u_int8_t maximumLatency; // (ro)
2451 } type0;
2452
2453 /*
2454 * PCI to PCI Bridge
2455 */
2456
2457 struct _MRSAS_DRV_PCI_HEADER_TYPE_1
2458 {
2459 u_int32_t baseAddresses[PCI_TYPE1_ADDRESSES];
2460 u_int8_t primaryBus;
2461 u_int8_t secondaryBus;
2462 u_int8_t subordinateBus;
2463 u_int8_t secondaryLatency;
2464 u_int8_t ioBase;
2465 u_int8_t ioLimit;
2466 u_int16_t secondaryStatus;
2467 u_int16_t memoryBase;
2468 u_int16_t memoryLimit;
2469 u_int16_t prefetchBase;
2470 u_int16_t prefetchLimit;
2471 u_int32_t prefetchBaseUpper32;
2472 u_int32_t prefetchLimitUpper32;
2473 u_int16_t ioBaseUpper16;
2474 u_int16_t ioLimitUpper16;
2475 u_int8_t capabilitiesPtr;
2476 u_int8_t reserved1[3];
2477 u_int32_t romBaseAddress;
2478 u_int8_t interruptLine;
2479 u_int8_t interruptPin;
2480 u_int16_t bridgeControl;
2481 } type1;
2482
2483 /*
2484 * PCI to CARDBUS Bridge
2485 */
2486
2487 struct _MRSAS_DRV_PCI_HEADER_TYPE_2
2488 {
2489 u_int32_t socketRegistersBaseAddress;
2490 u_int8_t capabilitiesPtr;
2491 u_int8_t reserved;
2492 u_int16_t secondaryStatus;
2493 u_int8_t primaryBus;
2494 u_int8_t secondaryBus;
2495 u_int8_t subordinateBus;
2496 u_int8_t secondaryLatency;
2497 struct
2498 {
2499 u_int32_t base;
2500 u_int32_t limit;
2501 } range[PCI_TYPE2_ADDRESSES-1];
2502 u_int8_t interruptLine;
2503 u_int8_t interruptPin;
2504 u_int16_t bridgeControl;
2505 } type2;
2506 } u;
2507
2508} MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER;
2509
2510#define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER) //64 bytes
2511
2512typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY
2513{
2514 union
2515 {
2516 struct
2517 {
2518 u_int32_t linkSpeed :4;
2519 u_int32_t linkWidth :6;
2520 u_int32_t aspmSupport :2;
2521 u_int32_t losExitLatency :3;
2522 u_int32_t l1ExitLatency :3;
2523 u_int32_t rsvdp :6;
2524 u_int32_t portNumber :8;
2525 }bits;
2526
2527 u_int32_t asUlong;
2528 }u;
2529}MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY;
2530
2531#define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY)
2532
2533typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY
2534{
2535 union
2536 {
2537 struct
2538 {
2539 u_int16_t linkSpeed :4;
2540 u_int16_t negotiatedLinkWidth :6;
2541 u_int16_t linkTrainingError :1;
2542 u_int16_t linkTraning :1;
2543 u_int16_t slotClockConfig :1;
2544 u_int16_t rsvdZ :3;
2545 }bits;
2546
2547 u_int16_t asUshort;
2548 }u;
2549 u_int16_t reserved;
2550} MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY;
2551
2552#define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY)
2553
2554
2555typedef struct _MRSAS_DRV_PCI_CAPABILITIES
2556{
2557 MRSAS_DRV_PCI_LINK_CAPABILITY linkCapability;
2558 MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY linkStatusCapability;
2559}MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES;
2560
2561#define MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES)
2562
2563/* PCI information */
2564typedef struct _MRSAS_DRV_PCI_INFORMATION
2565{
2566 u_int32_t busNumber;
2567 u_int8_t deviceNumber;
2568 u_int8_t functionNumber;
2569 u_int8_t interruptVector;
2570 u_int8_t reserved1;
2571 MRSAS_DRV_PCI_COMMON_HEADER pciHeaderInfo;
2572 MRSAS_DRV_PCI_CAPABILITIES capability;
2573 u_int32_t domainID;
2574 u_int8_t reserved2[28];
2575}MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION;
2576
2416/*******************************************************************
2417 * per-instance data
2418 ********************************************************************/
2419struct mrsas_softc {
2420 device_t mrsas_dev;
2421 struct cdev *mrsas_cdev;
2422 uint16_t device_id;
2423 struct resource *reg_res;

--- 175 unchanged lines hidden --- 		2577/*******************************************************************
2578 * per-instance data
2579 ********************************************************************/
2580struct mrsas_softc {
2581 device_t mrsas_dev;
2582 struct cdev *mrsas_cdev;
2583 uint16_t device_id;
2584 struct resource *reg_res;

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