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mrsas.c (323819) mrsas.c (342716)
1/*
2 * Copyright (c) 2015, AVAGO Tech. All rights reserved. Author: Marian Choy
3 * Copyright (c) 2014, LSI Corp. All rights reserved. Author: Marian Choy
4 * Support: freebsdraid@avagotech.com
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:

--- 24 unchanged lines hidden (view full) ---

33 * official policies,either expressed or implied, of the FreeBSD Project.
34 *
35 * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES 1621
36 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD
37 *
38 */
39
40#include <sys/cdefs.h>
1/*
2 * Copyright (c) 2015, AVAGO Tech. All rights reserved. Author: Marian Choy
3 * Copyright (c) 2014, LSI Corp. All rights reserved. Author: Marian Choy
4 * Support: freebsdraid@avagotech.com
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:

--- 24 unchanged lines hidden (view full) ---

33 * official policies,either expressed or implied, of the FreeBSD Project.
34 *
35 * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES 1621
36 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD
37 *
38 */
39
40#include <sys/cdefs.h>
41__FBSDID("$FreeBSD: stable/11/sys/dev/mrsas/mrsas.c 323819 2017-09-20 17:49:57Z jkim $");
41__FBSDID("$FreeBSD: stable/11/sys/dev/mrsas/mrsas.c 342716 2019-01-03 07:45:52Z kadesai $");
42
43#include <dev/mrsas/mrsas.h>
44#include <dev/mrsas/mrsas_ioctl.h>
45
46#include <cam/cam.h>
47#include <cam/cam_ccb.h>
48
49#include <sys/sysctl.h>

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85static void megasas_setup_jbod_map(struct mrsas_softc *sc);
86static int megasas_sync_pd_seq_num(struct mrsas_softc *sc, boolean_t pend);
87static int mrsas_clear_intr(struct mrsas_softc *sc);
88static int mrsas_get_ctrl_info(struct mrsas_softc *sc);
89static void mrsas_update_ext_vd_details(struct mrsas_softc *sc);
90static int
91mrsas_issue_blocked_abort_cmd(struct mrsas_softc *sc,
92 struct mrsas_mfi_cmd *cmd_to_abort);
42
43#include <dev/mrsas/mrsas.h>
44#include <dev/mrsas/mrsas_ioctl.h>
45
46#include <cam/cam.h>
47#include <cam/cam_ccb.h>
48
49#include <sys/sysctl.h>

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85static void megasas_setup_jbod_map(struct mrsas_softc *sc);
86static int megasas_sync_pd_seq_num(struct mrsas_softc *sc, boolean_t pend);
87static int mrsas_clear_intr(struct mrsas_softc *sc);
88static int mrsas_get_ctrl_info(struct mrsas_softc *sc);
89static void mrsas_update_ext_vd_details(struct mrsas_softc *sc);
90static int
91mrsas_issue_blocked_abort_cmd(struct mrsas_softc *sc,
92 struct mrsas_mfi_cmd *cmd_to_abort);
93static void
94mrsas_get_pd_info(struct mrsas_softc *sc, u_int16_t device_id);
93static struct mrsas_softc *
94mrsas_get_softc_instance(struct cdev *dev,
95 u_long cmd, caddr_t arg);
96u_int32_t mrsas_read_reg(struct mrsas_softc *sc, int offset);
97u_int8_t
98mrsas_build_mptmfi_passthru(struct mrsas_softc *sc,
99 struct mrsas_mfi_cmd *mfi_cmd);
100void mrsas_complete_outstanding_ioctls(struct mrsas_softc *sc);

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136 u_int32_t value);
137void
138mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo,
139 u_int32_t req_desc_hi);
140void mrsas_free_ctlr_info_cmd(struct mrsas_softc *sc);
141void
142mrsas_complete_mptmfi_passthru(struct mrsas_softc *sc,
143 struct mrsas_mfi_cmd *cmd, u_int8_t status);
95static struct mrsas_softc *
96mrsas_get_softc_instance(struct cdev *dev,
97 u_long cmd, caddr_t arg);
98u_int32_t mrsas_read_reg(struct mrsas_softc *sc, int offset);
99u_int8_t
100mrsas_build_mptmfi_passthru(struct mrsas_softc *sc,
101 struct mrsas_mfi_cmd *mfi_cmd);
102void mrsas_complete_outstanding_ioctls(struct mrsas_softc *sc);

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138 u_int32_t value);
139void
140mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo,
141 u_int32_t req_desc_hi);
142void mrsas_free_ctlr_info_cmd(struct mrsas_softc *sc);
143void
144mrsas_complete_mptmfi_passthru(struct mrsas_softc *sc,
145 struct mrsas_mfi_cmd *cmd, u_int8_t status);
144void
145mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd, u_int8_t status,
146 u_int8_t extStatus);
147struct mrsas_mfi_cmd *mrsas_get_mfi_cmd(struct mrsas_softc *sc);
148
149MRSAS_REQUEST_DESCRIPTOR_UNION *mrsas_build_mpt_cmd
150 (struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
151
152extern int mrsas_cam_attach(struct mrsas_softc *sc);
153extern void mrsas_cam_detach(struct mrsas_softc *sc);
154extern void mrsas_cmd_done(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd);

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162extern void mrsas_xpt_freeze(struct mrsas_softc *sc);
163extern void mrsas_xpt_release(struct mrsas_softc *sc);
164extern MRSAS_REQUEST_DESCRIPTOR_UNION *
165mrsas_get_request_desc(struct mrsas_softc *sc,
166 u_int16_t index);
167extern int mrsas_bus_scan_sim(struct mrsas_softc *sc, struct cam_sim *sim);
168static int mrsas_alloc_evt_log_info_cmd(struct mrsas_softc *sc);
169static void mrsas_free_evt_log_info_cmd(struct mrsas_softc *sc);
146struct mrsas_mfi_cmd *mrsas_get_mfi_cmd(struct mrsas_softc *sc);
147
148MRSAS_REQUEST_DESCRIPTOR_UNION *mrsas_build_mpt_cmd
149 (struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
150
151extern int mrsas_cam_attach(struct mrsas_softc *sc);
152extern void mrsas_cam_detach(struct mrsas_softc *sc);
153extern void mrsas_cmd_done(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd);

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161extern void mrsas_xpt_freeze(struct mrsas_softc *sc);
162extern void mrsas_xpt_release(struct mrsas_softc *sc);
163extern MRSAS_REQUEST_DESCRIPTOR_UNION *
164mrsas_get_request_desc(struct mrsas_softc *sc,
165 u_int16_t index);
166extern int mrsas_bus_scan_sim(struct mrsas_softc *sc, struct cam_sim *sim);
167static int mrsas_alloc_evt_log_info_cmd(struct mrsas_softc *sc);
168static void mrsas_free_evt_log_info_cmd(struct mrsas_softc *sc);
169void mrsas_release_mpt_cmd(struct mrsas_mpt_cmd *cmd);
170
170
171void mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd,
172 union ccb *ccb_ptr, u_int8_t status, u_int8_t extStatus,
173 u_int32_t data_length, u_int8_t *sense);
174
175
171SYSCTL_NODE(_hw, OID_AUTO, mrsas, CTLFLAG_RD, 0, "MRSAS Driver Parameters");
172
173/*
174 * PCI device struct and table
175 *
176 */
177typedef struct mrsas_ident {
178 uint16_t vendor;

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185MRSAS_CTLR_ID device_table[] = {
186 {0x1000, MRSAS_TBOLT, 0xffff, 0xffff, "AVAGO Thunderbolt SAS Controller"},
187 {0x1000, MRSAS_INVADER, 0xffff, 0xffff, "AVAGO Invader SAS Controller"},
188 {0x1000, MRSAS_FURY, 0xffff, 0xffff, "AVAGO Fury SAS Controller"},
189 {0x1000, MRSAS_INTRUDER, 0xffff, 0xffff, "AVAGO Intruder SAS Controller"},
190 {0x1000, MRSAS_INTRUDER_24, 0xffff, 0xffff, "AVAGO Intruder_24 SAS Controller"},
191 {0x1000, MRSAS_CUTLASS_52, 0xffff, 0xffff, "AVAGO Cutlass_52 SAS Controller"},
192 {0x1000, MRSAS_CUTLASS_53, 0xffff, 0xffff, "AVAGO Cutlass_53 SAS Controller"},
176SYSCTL_NODE(_hw, OID_AUTO, mrsas, CTLFLAG_RD, 0, "MRSAS Driver Parameters");
177
178/*
179 * PCI device struct and table
180 *
181 */
182typedef struct mrsas_ident {
183 uint16_t vendor;

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190MRSAS_CTLR_ID device_table[] = {
191 {0x1000, MRSAS_TBOLT, 0xffff, 0xffff, "AVAGO Thunderbolt SAS Controller"},
192 {0x1000, MRSAS_INVADER, 0xffff, 0xffff, "AVAGO Invader SAS Controller"},
193 {0x1000, MRSAS_FURY, 0xffff, 0xffff, "AVAGO Fury SAS Controller"},
194 {0x1000, MRSAS_INTRUDER, 0xffff, 0xffff, "AVAGO Intruder SAS Controller"},
195 {0x1000, MRSAS_INTRUDER_24, 0xffff, 0xffff, "AVAGO Intruder_24 SAS Controller"},
196 {0x1000, MRSAS_CUTLASS_52, 0xffff, 0xffff, "AVAGO Cutlass_52 SAS Controller"},
197 {0x1000, MRSAS_CUTLASS_53, 0xffff, 0xffff, "AVAGO Cutlass_53 SAS Controller"},
198 {0x1000, MRSAS_VENTURA, 0xffff, 0xffff, "AVAGO Ventura SAS Controller"},
199 {0x1000, MRSAS_CRUSADER, 0xffff, 0xffff, "AVAGO Crusader SAS Controller"},
200 {0x1000, MRSAS_HARPOON, 0xffff, 0xffff, "AVAGO Harpoon SAS Controller"},
201 {0x1000, MRSAS_TOMCAT, 0xffff, 0xffff, "AVAGO Tomcat SAS Controller"},
202 {0x1000, MRSAS_VENTURA_4PORT, 0xffff, 0xffff, "AVAGO Ventura_4Port SAS Controller"},
203 {0x1000, MRSAS_CRUSADER_4PORT, 0xffff, 0xffff, "AVAGO Crusader_4Port SAS Controller"},
193 {0, 0, 0, 0, NULL}
194};
195
196/*
197 * Character device entry points
198 *
199 */
200static struct cdevsw mrsas_cdevsw = {

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431 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
432 OID_AUTO, "reset_in_progress", CTLFLAG_RD,
433 &sc->reset_in_progress, 0, "ocr in progress status");
434
435 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
436 OID_AUTO, "block_sync_cache", CTLFLAG_RW,
437 &sc->block_sync_cache, 0,
438 "Block SYNC CACHE at driver. <default: 0, send it to FW>");
204 {0, 0, 0, 0, NULL}
205};
206
207/*
208 * Character device entry points
209 *
210 */
211static struct cdevsw mrsas_cdevsw = {

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442 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
443 OID_AUTO, "reset_in_progress", CTLFLAG_RD,
444 &sc->reset_in_progress, 0, "ocr in progress status");
445
446 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
447 OID_AUTO, "block_sync_cache", CTLFLAG_RW,
448 &sc->block_sync_cache, 0,
449 "Block SYNC CACHE at driver. <default: 0, send it to FW>");
439
450 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
451 OID_AUTO, "stream detection", CTLFLAG_RW,
452 &sc->drv_stream_detection, 0,
453 "Disable/Enable Stream detection. <default: 1, Enable Stream Detection>");
454 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
455 OID_AUTO, "prp_count", CTLFLAG_RD,
456 &sc->prp_count.val_rdonly, 0, "Number of IOs for which PRPs are built");
457 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
458 OID_AUTO, "SGE holes", CTLFLAG_RD,
459 &sc->sge_holes.val_rdonly, 0, "Number of IOs with holes in SGEs");
440}
441
442/*
443 * mrsas_get_tunables: get tunable parameters.
444 * input: Adapter instance soft state
445 *
446 * Get tunable parameters. This will help to debug driver at boot time.
447 */
448static void
449mrsas_get_tunables(struct mrsas_softc *sc)
450{
451 char tmpstr[80];
452
453 /* XXX default to some debugging for now */
460}
461
462/*
463 * mrsas_get_tunables: get tunable parameters.
464 * input: Adapter instance soft state
465 *
466 * Get tunable parameters. This will help to debug driver at boot time.
467 */
468static void
469mrsas_get_tunables(struct mrsas_softc *sc)
470{
471 char tmpstr[80];
472
473 /* XXX default to some debugging for now */
454 sc->mrsas_debug = MRSAS_FAULT;
474 sc->mrsas_debug =
475 (MRSAS_FAULT | MRSAS_OCR | MRSAS_INFO | MRSAS_TRACE | MRSAS_AEN);
455 sc->mrsas_io_timeout = MRSAS_IO_TIMEOUT;
456 sc->mrsas_fw_fault_check_delay = 1;
457 sc->reset_count = 0;
458 sc->reset_in_progress = 0;
459 sc->block_sync_cache = 0;
476 sc->mrsas_io_timeout = MRSAS_IO_TIMEOUT;
477 sc->mrsas_fw_fault_check_delay = 1;
478 sc->reset_count = 0;
479 sc->reset_in_progress = 0;
480 sc->block_sync_cache = 0;
481 sc->drv_stream_detection = 1;
460
461 /*
462 * Grab the global variables.
463 */
464 TUNABLE_INT_FETCH("hw.mrsas.debug_level", &sc->mrsas_debug);
465
466 /*
467 * Grab the global variables.

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810 * Performs setup of PCI and registers, initializes mutexes and linked lists,
811 * registers interrupts and CAM, and initializes the adapter/controller to
812 * its proper state.
813 */
814static int
815mrsas_attach(device_t dev)
816{
817 struct mrsas_softc *sc = device_get_softc(dev);
482
483 /*
484 * Grab the global variables.
485 */
486 TUNABLE_INT_FETCH("hw.mrsas.debug_level", &sc->mrsas_debug);
487
488 /*
489 * Grab the global variables.

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832 * Performs setup of PCI and registers, initializes mutexes and linked lists,
833 * registers interrupts and CAM, and initializes the adapter/controller to
834 * its proper state.
835 */
836static int
837mrsas_attach(device_t dev)
838{
839 struct mrsas_softc *sc = device_get_softc(dev);
818 uint32_t cmd, bar, error;
840 uint32_t cmd, error;
819
820 memset(sc, 0, sizeof(struct mrsas_softc));
821
822 /* Look up our softc and initialize its fields. */
823 sc->mrsas_dev = dev;
824 sc->device_id = pci_get_device(dev);
825
826 if ((sc->device_id == MRSAS_INVADER) ||
827 (sc->device_id == MRSAS_FURY) ||
828 (sc->device_id == MRSAS_INTRUDER) ||
829 (sc->device_id == MRSAS_INTRUDER_24) ||
830 (sc->device_id == MRSAS_CUTLASS_52) ||
831 (sc->device_id == MRSAS_CUTLASS_53)) {
832 sc->mrsas_gen3_ctrl = 1;
841
842 memset(sc, 0, sizeof(struct mrsas_softc));
843
844 /* Look up our softc and initialize its fields. */
845 sc->mrsas_dev = dev;
846 sc->device_id = pci_get_device(dev);
847
848 if ((sc->device_id == MRSAS_INVADER) ||
849 (sc->device_id == MRSAS_FURY) ||
850 (sc->device_id == MRSAS_INTRUDER) ||
851 (sc->device_id == MRSAS_INTRUDER_24) ||
852 (sc->device_id == MRSAS_CUTLASS_52) ||
853 (sc->device_id == MRSAS_CUTLASS_53)) {
854 sc->mrsas_gen3_ctrl = 1;
833 }
855 } else if ((sc->device_id == MRSAS_VENTURA) ||
856 (sc->device_id == MRSAS_CRUSADER) ||
857 (sc->device_id == MRSAS_HARPOON) ||
858 (sc->device_id == MRSAS_TOMCAT) ||
859 (sc->device_id == MRSAS_VENTURA_4PORT) ||
860 (sc->device_id == MRSAS_CRUSADER_4PORT)) {
861 sc->is_ventura = true;
862 }
834
835 mrsas_get_tunables(sc);
836
837 /*
838 * Set up PCI and registers
839 */
840 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
841 if ((cmd & PCIM_CMD_PORTEN) == 0) {
842 return (ENXIO);
843 }
844 /* Force the busmaster enable bit on. */
845 cmd |= PCIM_CMD_BUSMASTEREN;
846 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
847
863
864 mrsas_get_tunables(sc);
865
866 /*
867 * Set up PCI and registers
868 */
869 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
870 if ((cmd & PCIM_CMD_PORTEN) == 0) {
871 return (ENXIO);
872 }
873 /* Force the busmaster enable bit on. */
874 cmd |= PCIM_CMD_BUSMASTEREN;
875 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
876
848 bar = pci_read_config(dev, MRSAS_PCI_BAR1, 4);
877 /* For Ventura system registers are mapped to BAR0 */
878 if (sc->is_ventura)
879 sc->reg_res_id = PCIR_BAR(0); /* BAR0 offset */
880 else
881 sc->reg_res_id = PCIR_BAR(1); /* BAR1 offset */
849
882
850 sc->reg_res_id = MRSAS_PCI_BAR1;/* BAR1 offset */
851 if ((sc->reg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
852 &(sc->reg_res_id), RF_ACTIVE))
853 == NULL) {
854 device_printf(dev, "Cannot allocate PCI registers\n");
855 goto attach_fail;
856 }
857 sc->bus_tag = rman_get_bustag(sc->reg_res);
858 sc->bus_handle = rman_get_bushandle(sc->reg_res);
859
860 /* Intialize mutexes */
861 mtx_init(&sc->sim_lock, "mrsas_sim_lock", NULL, MTX_DEF);
862 mtx_init(&sc->pci_lock, "mrsas_pci_lock", NULL, MTX_DEF);
863 mtx_init(&sc->io_lock, "mrsas_io_lock", NULL, MTX_DEF);
864 mtx_init(&sc->aen_lock, "mrsas_aen_lock", NULL, MTX_DEF);
865 mtx_init(&sc->ioctl_lock, "mrsas_ioctl_lock", NULL, MTX_SPIN);
866 mtx_init(&sc->mpt_cmd_pool_lock, "mrsas_mpt_cmd_pool_lock", NULL, MTX_DEF);
867 mtx_init(&sc->mfi_cmd_pool_lock, "mrsas_mfi_cmd_pool_lock", NULL, MTX_DEF);
868 mtx_init(&sc->raidmap_lock, "mrsas_raidmap_lock", NULL, MTX_DEF);
883 if ((sc->reg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
884 &(sc->reg_res_id), RF_ACTIVE))
885 == NULL) {
886 device_printf(dev, "Cannot allocate PCI registers\n");
887 goto attach_fail;
888 }
889 sc->bus_tag = rman_get_bustag(sc->reg_res);
890 sc->bus_handle = rman_get_bushandle(sc->reg_res);
891
892 /* Intialize mutexes */
893 mtx_init(&sc->sim_lock, "mrsas_sim_lock", NULL, MTX_DEF);
894 mtx_init(&sc->pci_lock, "mrsas_pci_lock", NULL, MTX_DEF);
895 mtx_init(&sc->io_lock, "mrsas_io_lock", NULL, MTX_DEF);
896 mtx_init(&sc->aen_lock, "mrsas_aen_lock", NULL, MTX_DEF);
897 mtx_init(&sc->ioctl_lock, "mrsas_ioctl_lock", NULL, MTX_SPIN);
898 mtx_init(&sc->mpt_cmd_pool_lock, "mrsas_mpt_cmd_pool_lock", NULL, MTX_DEF);
899 mtx_init(&sc->mfi_cmd_pool_lock, "mrsas_mfi_cmd_pool_lock", NULL, MTX_DEF);
900 mtx_init(&sc->raidmap_lock, "mrsas_raidmap_lock", NULL, MTX_DEF);
901 mtx_init(&sc->stream_lock, "mrsas_stream_lock", NULL, MTX_DEF);
869
870 /* Intialize linked list */
871 TAILQ_INIT(&sc->mrsas_mpt_cmd_list_head);
872 TAILQ_INIT(&sc->mrsas_mfi_cmd_list_head);
873
874 mrsas_atomic_set(&sc->fw_outstanding, 0);
875 mrsas_atomic_set(&sc->target_reset_outstanding, 0);
902
903 /* Intialize linked list */
904 TAILQ_INIT(&sc->mrsas_mpt_cmd_list_head);
905 TAILQ_INIT(&sc->mrsas_mfi_cmd_list_head);
906
907 mrsas_atomic_set(&sc->fw_outstanding, 0);
908 mrsas_atomic_set(&sc->target_reset_outstanding, 0);
909 mrsas_atomic_set(&sc->prp_count, 0);
910 mrsas_atomic_set(&sc->sge_holes, 0);
876
877 sc->io_cmds_highwater = 0;
878
879 sc->adprecovery = MRSAS_HBA_OPERATIONAL;
880 sc->UnevenSpanSupport = 0;
881
882 sc->msix_enable = 0;
883

--- 43 unchanged lines hidden (view full) ---

927 mtx_destroy(&sc->sim_lock);
928 mtx_destroy(&sc->aen_lock);
929 mtx_destroy(&sc->pci_lock);
930 mtx_destroy(&sc->io_lock);
931 mtx_destroy(&sc->ioctl_lock);
932 mtx_destroy(&sc->mpt_cmd_pool_lock);
933 mtx_destroy(&sc->mfi_cmd_pool_lock);
934 mtx_destroy(&sc->raidmap_lock);
911
912 sc->io_cmds_highwater = 0;
913
914 sc->adprecovery = MRSAS_HBA_OPERATIONAL;
915 sc->UnevenSpanSupport = 0;
916
917 sc->msix_enable = 0;
918

--- 43 unchanged lines hidden (view full) ---

962 mtx_destroy(&sc->sim_lock);
963 mtx_destroy(&sc->aen_lock);
964 mtx_destroy(&sc->pci_lock);
965 mtx_destroy(&sc->io_lock);
966 mtx_destroy(&sc->ioctl_lock);
967 mtx_destroy(&sc->mpt_cmd_pool_lock);
968 mtx_destroy(&sc->mfi_cmd_pool_lock);
969 mtx_destroy(&sc->raidmap_lock);
970 mtx_destroy(&sc->stream_lock);
935attach_fail:
936 if (sc->reg_res) {
937 bus_release_resource(sc->mrsas_dev, SYS_RES_MEMORY,
938 sc->reg_res_id, sc->reg_res);
939 }
940 return (ENXIO);
941}
942
943/*
944 * Interrupt config hook
945 */
946static void
947mrsas_ich_startup(void *arg)
948{
971attach_fail:
972 if (sc->reg_res) {
973 bus_release_resource(sc->mrsas_dev, SYS_RES_MEMORY,
974 sc->reg_res_id, sc->reg_res);
975 }
976 return (ENXIO);
977}
978
979/*
980 * Interrupt config hook
981 */
982static void
983mrsas_ich_startup(void *arg)
984{
985 int i = 0;
949 struct mrsas_softc *sc = (struct mrsas_softc *)arg;
950
951 /*
952 * Intialize a counting Semaphore to take care no. of concurrent IOCTLs
953 */
954 sema_init(&sc->ioctl_count_sema, MRSAS_MAX_IOCTL_CMDS,
955 IOCTL_SEMA_DESCRIPTION);
956

--- 19 unchanged lines hidden (view full) ---

976
977 mrsas_mgmt_info.count++;
978 mrsas_mgmt_info.sc_ptr[mrsas_mgmt_info.max_index] = sc;
979 mrsas_mgmt_info.max_index++;
980
981 /* Enable Interrupts */
982 mrsas_enable_intr(sc);
983
986 struct mrsas_softc *sc = (struct mrsas_softc *)arg;
987
988 /*
989 * Intialize a counting Semaphore to take care no. of concurrent IOCTLs
990 */
991 sema_init(&sc->ioctl_count_sema, MRSAS_MAX_IOCTL_CMDS,
992 IOCTL_SEMA_DESCRIPTION);
993

--- 19 unchanged lines hidden (view full) ---

1013
1014 mrsas_mgmt_info.count++;
1015 mrsas_mgmt_info.sc_ptr[mrsas_mgmt_info.max_index] = sc;
1016 mrsas_mgmt_info.max_index++;
1017
1018 /* Enable Interrupts */
1019 mrsas_enable_intr(sc);
1020
1021 /* Call DCMD get_pd_info for all system PDs */
1022 for (i = 0; i < MRSAS_MAX_PD; i++) {
1023 if ((sc->target_list[i].target_id != 0xffff) &&
1024 sc->pd_info_mem)
1025 mrsas_get_pd_info(sc, sc->target_list[i].target_id);
1026 }
1027
984 /* Initiate AEN (Asynchronous Event Notification) */
985 if (mrsas_start_aen(sc)) {
986 device_printf(sc->mrsas_dev, "Error: AEN registration FAILED !!! "
987 "Further events from the controller will not be communicated.\n"
988 "Either there is some problem in the controller"
989 "or the controller does not support AEN.\n"
990 "Please contact to the SUPPORT TEAM if the problem persists\n");
991 }

--- 57 unchanged lines hidden (view full) ---

1049 "mrsas_ocr thread to quit ocr %d\n", i,
1050 sc->ocr_thread_active);
1051 }
1052 pause("mr_shutdown", hz);
1053 }
1054 mrsas_flush_cache(sc);
1055 mrsas_shutdown_ctlr(sc, MR_DCMD_CTRL_SHUTDOWN);
1056 mrsas_disable_intr(sc);
1028 /* Initiate AEN (Asynchronous Event Notification) */
1029 if (mrsas_start_aen(sc)) {
1030 device_printf(sc->mrsas_dev, "Error: AEN registration FAILED !!! "
1031 "Further events from the controller will not be communicated.\n"
1032 "Either there is some problem in the controller"
1033 "or the controller does not support AEN.\n"
1034 "Please contact to the SUPPORT TEAM if the problem persists\n");
1035 }

--- 57 unchanged lines hidden (view full) ---

1093 "mrsas_ocr thread to quit ocr %d\n", i,
1094 sc->ocr_thread_active);
1095 }
1096 pause("mr_shutdown", hz);
1097 }
1098 mrsas_flush_cache(sc);
1099 mrsas_shutdown_ctlr(sc, MR_DCMD_CTRL_SHUTDOWN);
1100 mrsas_disable_intr(sc);
1101
1102 if (sc->is_ventura && sc->streamDetectByLD) {
1103 for (i = 0; i < MAX_LOGICAL_DRIVES_EXT; ++i)
1104 free(sc->streamDetectByLD[i], M_MRSAS);
1105 free(sc->streamDetectByLD, M_MRSAS);
1106 sc->streamDetectByLD = NULL;
1107 }
1108
1057 mrsas_cam_detach(sc);
1058 mrsas_teardown_intr(sc);
1059 mrsas_free_mem(sc);
1060 mtx_destroy(&sc->sim_lock);
1061 mtx_destroy(&sc->aen_lock);
1062 mtx_destroy(&sc->pci_lock);
1063 mtx_destroy(&sc->io_lock);
1064 mtx_destroy(&sc->ioctl_lock);
1065 mtx_destroy(&sc->mpt_cmd_pool_lock);
1066 mtx_destroy(&sc->mfi_cmd_pool_lock);
1067 mtx_destroy(&sc->raidmap_lock);
1109 mrsas_cam_detach(sc);
1110 mrsas_teardown_intr(sc);
1111 mrsas_free_mem(sc);
1112 mtx_destroy(&sc->sim_lock);
1113 mtx_destroy(&sc->aen_lock);
1114 mtx_destroy(&sc->pci_lock);
1115 mtx_destroy(&sc->io_lock);
1116 mtx_destroy(&sc->ioctl_lock);
1117 mtx_destroy(&sc->mpt_cmd_pool_lock);
1118 mtx_destroy(&sc->mfi_cmd_pool_lock);
1119 mtx_destroy(&sc->raidmap_lock);
1120 mtx_destroy(&sc->stream_lock);
1068
1069 /* Wait for all the semaphores to be released */
1070 while (sema_value(&sc->ioctl_count_sema) != MRSAS_MAX_IOCTL_CMDS)
1071 pause("mr_shutdown", hz);
1072
1073 /* Destroy the counting semaphore created for Ioctl */
1074 sema_destroy(&sc->ioctl_count_sema);
1075

--- 13 unchanged lines hidden (view full) ---

1089 *
1090 * This function is called from mrsas_detach() to free previously allocated
1091 * memory.
1092 */
1093void
1094mrsas_free_mem(struct mrsas_softc *sc)
1095{
1096 int i;
1121
1122 /* Wait for all the semaphores to be released */
1123 while (sema_value(&sc->ioctl_count_sema) != MRSAS_MAX_IOCTL_CMDS)
1124 pause("mr_shutdown", hz);
1125
1126 /* Destroy the counting semaphore created for Ioctl */
1127 sema_destroy(&sc->ioctl_count_sema);
1128

--- 13 unchanged lines hidden (view full) ---

1142 *
1143 * This function is called from mrsas_detach() to free previously allocated
1144 * memory.
1145 */
1146void
1147mrsas_free_mem(struct mrsas_softc *sc)
1148{
1149 int i;
1097 u_int32_t max_cmd;
1150 u_int32_t max_fw_cmds;
1098 struct mrsas_mfi_cmd *mfi_cmd;
1099 struct mrsas_mpt_cmd *mpt_cmd;
1100
1101 /*
1102 * Free RAID map memory
1103 */
1104 for (i = 0; i < 2; i++) {
1105 if (sc->raidmap_phys_addr[i])

--- 71 unchanged lines hidden (view full) ---

1177 if (sc->evt_detail_phys_addr)
1178 bus_dmamap_unload(sc->evt_detail_tag, sc->evt_detail_dmamap);
1179 if (sc->evt_detail_mem != NULL)
1180 bus_dmamem_free(sc->evt_detail_tag, sc->evt_detail_mem, sc->evt_detail_dmamap);
1181 if (sc->evt_detail_tag != NULL)
1182 bus_dma_tag_destroy(sc->evt_detail_tag);
1183
1184 /*
1151 struct mrsas_mfi_cmd *mfi_cmd;
1152 struct mrsas_mpt_cmd *mpt_cmd;
1153
1154 /*
1155 * Free RAID map memory
1156 */
1157 for (i = 0; i < 2; i++) {
1158 if (sc->raidmap_phys_addr[i])

--- 71 unchanged lines hidden (view full) ---

1230 if (sc->evt_detail_phys_addr)
1231 bus_dmamap_unload(sc->evt_detail_tag, sc->evt_detail_dmamap);
1232 if (sc->evt_detail_mem != NULL)
1233 bus_dmamem_free(sc->evt_detail_tag, sc->evt_detail_mem, sc->evt_detail_dmamap);
1234 if (sc->evt_detail_tag != NULL)
1235 bus_dma_tag_destroy(sc->evt_detail_tag);
1236
1237 /*
1238 * Free PD info memory
1239 */
1240 if (sc->pd_info_phys_addr)
1241 bus_dmamap_unload(sc->pd_info_tag, sc->pd_info_dmamap);
1242 if (sc->pd_info_mem != NULL)
1243 bus_dmamem_free(sc->pd_info_tag, sc->pd_info_mem, sc->pd_info_dmamap);
1244 if (sc->pd_info_tag != NULL)
1245 bus_dma_tag_destroy(sc->pd_info_tag);
1246
1247 /*
1185 * Free MFI frames
1186 */
1187 if (sc->mfi_cmd_list) {
1188 for (i = 0; i < MRSAS_MAX_MFI_CMDS; i++) {
1189 mfi_cmd = sc->mfi_cmd_list[i];
1190 mrsas_free_frame(sc, mfi_cmd);
1191 }
1192 }
1193 if (sc->mficmd_frame_tag != NULL)
1194 bus_dma_tag_destroy(sc->mficmd_frame_tag);
1195
1196 /*
1197 * Free MPT internal command list
1198 */
1248 * Free MFI frames
1249 */
1250 if (sc->mfi_cmd_list) {
1251 for (i = 0; i < MRSAS_MAX_MFI_CMDS; i++) {
1252 mfi_cmd = sc->mfi_cmd_list[i];
1253 mrsas_free_frame(sc, mfi_cmd);
1254 }
1255 }
1256 if (sc->mficmd_frame_tag != NULL)
1257 bus_dma_tag_destroy(sc->mficmd_frame_tag);
1258
1259 /*
1260 * Free MPT internal command list
1261 */
1199 max_cmd = sc->max_fw_cmds;
1262 max_fw_cmds = sc->max_fw_cmds;
1200 if (sc->mpt_cmd_list) {
1263 if (sc->mpt_cmd_list) {
1201 for (i = 0; i < max_cmd; i++) {
1264 for (i = 0; i < max_fw_cmds; i++) {
1202 mpt_cmd = sc->mpt_cmd_list[i];
1203 bus_dmamap_destroy(sc->data_tag, mpt_cmd->data_dmamap);
1204 free(sc->mpt_cmd_list[i], M_MRSAS);
1205 }
1206 free(sc->mpt_cmd_list, M_MRSAS);
1207 sc->mpt_cmd_list = NULL;
1208 }
1209 /*

--- 323 unchanged lines hidden (view full) ---

1533 * interrupt.
1534 */
1535int
1536mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t MSIxIndex)
1537{
1538 Mpi2ReplyDescriptorsUnion_t *desc;
1539 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *reply_desc;
1540 MRSAS_RAID_SCSI_IO_REQUEST *scsi_io_req;
1265 mpt_cmd = sc->mpt_cmd_list[i];
1266 bus_dmamap_destroy(sc->data_tag, mpt_cmd->data_dmamap);
1267 free(sc->mpt_cmd_list[i], M_MRSAS);
1268 }
1269 free(sc->mpt_cmd_list, M_MRSAS);
1270 sc->mpt_cmd_list = NULL;
1271 }
1272 /*

--- 323 unchanged lines hidden (view full) ---

1596 * interrupt.
1597 */
1598int
1599mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t MSIxIndex)
1600{
1601 Mpi2ReplyDescriptorsUnion_t *desc;
1602 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *reply_desc;
1603 MRSAS_RAID_SCSI_IO_REQUEST *scsi_io_req;
1541 struct mrsas_mpt_cmd *cmd_mpt;
1604 struct mrsas_mpt_cmd *cmd_mpt, *r1_cmd = NULL;
1542 struct mrsas_mfi_cmd *cmd_mfi;
1605 struct mrsas_mfi_cmd *cmd_mfi;
1543 u_int8_t reply_descript_type;
1606 u_int8_t reply_descript_type, *sense;
1544 u_int16_t smid, num_completed;
1545 u_int8_t status, extStatus;
1546 union desc_value desc_val;
1547 PLD_LOAD_BALANCE_INFO lbinfo;
1607 u_int16_t smid, num_completed;
1608 u_int8_t status, extStatus;
1609 union desc_value desc_val;
1610 PLD_LOAD_BALANCE_INFO lbinfo;
1548 u_int32_t device_id;
1611 u_int32_t device_id, data_length;
1549 int threshold_reply_count = 0;
1550#if TM_DEBUG
1551 MR_TASK_MANAGE_REQUEST *mr_tm_req;
1552 MPI2_SCSI_TASK_MANAGE_REQUEST *mpi_tm_req;
1553#endif
1554
1555 /* If we have a hardware error, not need to continue */
1556 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR)

--- 11 unchanged lines hidden (view full) ---

1568 reply_descript_type = reply_desc->ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1569
1570 /* Find our reply descriptor for the command and process */
1571 while ((desc_val.u.low != 0xFFFFFFFF) && (desc_val.u.high != 0xFFFFFFFF)) {
1572 smid = reply_desc->SMID;
1573 cmd_mpt = sc->mpt_cmd_list[smid - 1];
1574 scsi_io_req = (MRSAS_RAID_SCSI_IO_REQUEST *) cmd_mpt->io_request;
1575
1612 int threshold_reply_count = 0;
1613#if TM_DEBUG
1614 MR_TASK_MANAGE_REQUEST *mr_tm_req;
1615 MPI2_SCSI_TASK_MANAGE_REQUEST *mpi_tm_req;
1616#endif
1617
1618 /* If we have a hardware error, not need to continue */
1619 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR)

--- 11 unchanged lines hidden (view full) ---

1631 reply_descript_type = reply_desc->ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1632
1633 /* Find our reply descriptor for the command and process */
1634 while ((desc_val.u.low != 0xFFFFFFFF) && (desc_val.u.high != 0xFFFFFFFF)) {
1635 smid = reply_desc->SMID;
1636 cmd_mpt = sc->mpt_cmd_list[smid - 1];
1637 scsi_io_req = (MRSAS_RAID_SCSI_IO_REQUEST *) cmd_mpt->io_request;
1638
1576 status = scsi_io_req->RaidContext.status;
1577 extStatus = scsi_io_req->RaidContext.exStatus;
1639 status = scsi_io_req->RaidContext.raid_context.status;
1640 extStatus = scsi_io_req->RaidContext.raid_context.exStatus;
1641 sense = cmd_mpt->sense;
1642 data_length = scsi_io_req->DataLength;
1578
1579 switch (scsi_io_req->Function) {
1580 case MPI2_FUNCTION_SCSI_TASK_MGMT:
1581#if TM_DEBUG
1582 mr_tm_req = (MR_TASK_MANAGE_REQUEST *) cmd_mpt->io_request;
1583 mpi_tm_req = (MPI2_SCSI_TASK_MANAGE_REQUEST *)
1584 &mr_tm_req->TmRequest;
1585 device_printf(sc->mrsas_dev, "TM completion type 0x%X, "
1586 "TaskMID: 0x%X", mpi_tm_req->TaskType, mpi_tm_req->TaskMID);
1587#endif
1588 wakeup_one((void *)&sc->ocr_chan);
1589 break;
1590 case MPI2_FUNCTION_SCSI_IO_REQUEST: /* Fast Path IO. */
1591 device_id = cmd_mpt->ccb_ptr->ccb_h.target_id;
1592 lbinfo = &sc->load_balance_info[device_id];
1643
1644 switch (scsi_io_req->Function) {
1645 case MPI2_FUNCTION_SCSI_TASK_MGMT:
1646#if TM_DEBUG
1647 mr_tm_req = (MR_TASK_MANAGE_REQUEST *) cmd_mpt->io_request;
1648 mpi_tm_req = (MPI2_SCSI_TASK_MANAGE_REQUEST *)
1649 &mr_tm_req->TmRequest;
1650 device_printf(sc->mrsas_dev, "TM completion type 0x%X, "
1651 "TaskMID: 0x%X", mpi_tm_req->TaskType, mpi_tm_req->TaskMID);
1652#endif
1653 wakeup_one((void *)&sc->ocr_chan);
1654 break;
1655 case MPI2_FUNCTION_SCSI_IO_REQUEST: /* Fast Path IO. */
1656 device_id = cmd_mpt->ccb_ptr->ccb_h.target_id;
1657 lbinfo = &sc->load_balance_info[device_id];
1658 /* R1 load balancing for READ */
1593 if (cmd_mpt->load_balance == MRSAS_LOAD_BALANCE_FLAG) {
1594 mrsas_atomic_dec(&lbinfo->scsi_pending_cmds[cmd_mpt->pd_r1_lb]);
1595 cmd_mpt->load_balance &= ~MRSAS_LOAD_BALANCE_FLAG;
1596 }
1597 /* Fall thru and complete IO */
1598 case MRSAS_MPI2_FUNCTION_LD_IO_REQUEST:
1659 if (cmd_mpt->load_balance == MRSAS_LOAD_BALANCE_FLAG) {
1660 mrsas_atomic_dec(&lbinfo->scsi_pending_cmds[cmd_mpt->pd_r1_lb]);
1661 cmd_mpt->load_balance &= ~MRSAS_LOAD_BALANCE_FLAG;
1662 }
1663 /* Fall thru and complete IO */
1664 case MRSAS_MPI2_FUNCTION_LD_IO_REQUEST:
1599 mrsas_map_mpt_cmd_status(cmd_mpt, status, extStatus);
1600 mrsas_cmd_done(sc, cmd_mpt);
1601 scsi_io_req->RaidContext.status = 0;
1602 scsi_io_req->RaidContext.exStatus = 0;
1665 if (cmd_mpt->r1_alt_dev_handle == MR_DEVHANDLE_INVALID) {
1666 mrsas_map_mpt_cmd_status(cmd_mpt, cmd_mpt->ccb_ptr, status,
1667 extStatus, data_length, sense);
1668 mrsas_cmd_done(sc, cmd_mpt);
1669 } else {
1670 /*
1671 * If the peer Raid 1/10 fast path failed,
1672 * mark IO as failed to the scsi layer.
1673 * Overwrite the current status by the failed status
1674 * and make sure that if any command fails,
1675 * driver returns fail status to CAM.
1676 */
1677 cmd_mpt->cmd_completed = 1;
1678 r1_cmd = cmd_mpt->peer_cmd;
1679 if (r1_cmd->cmd_completed) {
1680 if (r1_cmd->io_request->RaidContext.raid_context.status != MFI_STAT_OK) {
1681 status = r1_cmd->io_request->RaidContext.raid_context.status;
1682 extStatus = r1_cmd->io_request->RaidContext.raid_context.exStatus;
1683 data_length = r1_cmd->io_request->DataLength;
1684 sense = r1_cmd->sense;
1685 }
1686 r1_cmd->ccb_ptr = NULL;
1687 if (r1_cmd->callout_owner) {
1688 callout_stop(&r1_cmd->cm_callout);
1689 r1_cmd->callout_owner = false;
1690 }
1691 mrsas_release_mpt_cmd(r1_cmd);
1692 mrsas_map_mpt_cmd_status(cmd_mpt, cmd_mpt->ccb_ptr, status,
1693 extStatus, data_length, sense);
1694 mrsas_cmd_done(sc, cmd_mpt);
1695 }
1696 }
1603 mrsas_atomic_dec(&sc->fw_outstanding);
1604 break;
1605 case MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST: /* MFI command */
1606 cmd_mfi = sc->mfi_cmd_list[cmd_mpt->sync_cmd_idx];
1607 /*
1608 * Make sure NOT TO release the mfi command from the called
1609 * function's context if it is fired with issue_polled call.
1610 * And also make sure that the issue_polled call should only be

--- 32 unchanged lines hidden (view full) ---

1643
1644 /*
1645 * Write to reply post index after completing threshold reply
1646 * count and still there are more replies in reply queue
1647 * pending to be completed.
1648 */
1649 if (threshold_reply_count >= THRESHOLD_REPLY_COUNT) {
1650 if (sc->msix_enable) {
1697 mrsas_atomic_dec(&sc->fw_outstanding);
1698 break;
1699 case MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST: /* MFI command */
1700 cmd_mfi = sc->mfi_cmd_list[cmd_mpt->sync_cmd_idx];
1701 /*
1702 * Make sure NOT TO release the mfi command from the called
1703 * function's context if it is fired with issue_polled call.
1704 * And also make sure that the issue_polled call should only be

--- 32 unchanged lines hidden (view full) ---

1737
1738 /*
1739 * Write to reply post index after completing threshold reply
1740 * count and still there are more replies in reply queue
1741 * pending to be completed.
1742 */
1743 if (threshold_reply_count >= THRESHOLD_REPLY_COUNT) {
1744 if (sc->msix_enable) {
1651 if (sc->mrsas_gen3_ctrl)
1745 if (sc->msix_combined)
1652 mrsas_write_reg(sc, sc->msix_reg_offset[MSIxIndex / 8],
1653 ((MSIxIndex & 0x7) << 24) |
1654 sc->last_reply_idx[MSIxIndex]);
1655 else
1656 mrsas_write_reg(sc, sc->msix_reg_offset[0], (MSIxIndex << 24) |
1657 sc->last_reply_idx[MSIxIndex]);
1658 } else
1659 mrsas_write_reg(sc, offsetof(mrsas_reg_set,

--- 4 unchanged lines hidden (view full) ---

1664 }
1665
1666 /* No match, just return */
1667 if (num_completed == 0)
1668 return (DONE);
1669
1670 /* Clear response interrupt */
1671 if (sc->msix_enable) {
1746 mrsas_write_reg(sc, sc->msix_reg_offset[MSIxIndex / 8],
1747 ((MSIxIndex & 0x7) << 24) |
1748 sc->last_reply_idx[MSIxIndex]);
1749 else
1750 mrsas_write_reg(sc, sc->msix_reg_offset[0], (MSIxIndex << 24) |
1751 sc->last_reply_idx[MSIxIndex]);
1752 } else
1753 mrsas_write_reg(sc, offsetof(mrsas_reg_set,

--- 4 unchanged lines hidden (view full) ---

1758 }
1759
1760 /* No match, just return */
1761 if (num_completed == 0)
1762 return (DONE);
1763
1764 /* Clear response interrupt */
1765 if (sc->msix_enable) {
1672 if (sc->mrsas_gen3_ctrl) {
1766 if (sc->msix_combined) {
1673 mrsas_write_reg(sc, sc->msix_reg_offset[MSIxIndex / 8],
1674 ((MSIxIndex & 0x7) << 24) |
1675 sc->last_reply_idx[MSIxIndex]);
1676 } else
1677 mrsas_write_reg(sc, sc->msix_reg_offset[0], (MSIxIndex << 24) |
1678 sc->last_reply_idx[MSIxIndex]);
1679 } else
1680 mrsas_write_reg(sc, offsetof(mrsas_reg_set,

--- 6 unchanged lines hidden (view full) ---

1687 * mrsas_map_mpt_cmd_status: Allocate DMAable memory.
1688 * input: Adapter instance soft state
1689 *
1690 * This function is called from mrsas_complete_cmd(), for LD IO and FastPath IO.
1691 * It checks the command status and maps the appropriate CAM status for the
1692 * CCB.
1693 */
1694void
1767 mrsas_write_reg(sc, sc->msix_reg_offset[MSIxIndex / 8],
1768 ((MSIxIndex & 0x7) << 24) |
1769 sc->last_reply_idx[MSIxIndex]);
1770 } else
1771 mrsas_write_reg(sc, sc->msix_reg_offset[0], (MSIxIndex << 24) |
1772 sc->last_reply_idx[MSIxIndex]);
1773 } else
1774 mrsas_write_reg(sc, offsetof(mrsas_reg_set,

--- 6 unchanged lines hidden (view full) ---

1781 * mrsas_map_mpt_cmd_status: Allocate DMAable memory.
1782 * input: Adapter instance soft state
1783 *
1784 * This function is called from mrsas_complete_cmd(), for LD IO and FastPath IO.
1785 * It checks the command status and maps the appropriate CAM status for the
1786 * CCB.
1787 */
1788void
1695mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd, u_int8_t status, u_int8_t extStatus)
1789mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd, union ccb *ccb_ptr, u_int8_t status,
1790 u_int8_t extStatus, u_int32_t data_length, u_int8_t *sense)
1696{
1697 struct mrsas_softc *sc = cmd->sc;
1698 u_int8_t *sense_data;
1699
1700 switch (status) {
1701 case MFI_STAT_OK:
1791{
1792 struct mrsas_softc *sc = cmd->sc;
1793 u_int8_t *sense_data;
1794
1795 switch (status) {
1796 case MFI_STAT_OK:
1702 cmd->ccb_ptr->ccb_h.status = CAM_REQ_CMP;
1797 ccb_ptr->ccb_h.status = CAM_REQ_CMP;
1703 break;
1704 case MFI_STAT_SCSI_IO_FAILED:
1705 case MFI_STAT_SCSI_DONE_WITH_ERROR:
1798 break;
1799 case MFI_STAT_SCSI_IO_FAILED:
1800 case MFI_STAT_SCSI_DONE_WITH_ERROR:
1706 cmd->ccb_ptr->ccb_h.status = CAM_SCSI_STATUS_ERROR;
1707 sense_data = (u_int8_t *)&cmd->ccb_ptr->csio.sense_data;
1801 ccb_ptr->ccb_h.status = CAM_SCSI_STATUS_ERROR;
1802 sense_data = (u_int8_t *)&ccb_ptr->csio.sense_data;
1708 if (sense_data) {
1709 /* For now just copy 18 bytes back */
1803 if (sense_data) {
1804 /* For now just copy 18 bytes back */
1710 memcpy(sense_data, cmd->sense, 18);
1711 cmd->ccb_ptr->csio.sense_len = 18;
1712 cmd->ccb_ptr->ccb_h.status |= CAM_AUTOSNS_VALID;
1805 memcpy(sense_data, sense, 18);
1806 ccb_ptr->csio.sense_len = 18;
1807 ccb_ptr->ccb_h.status |= CAM_AUTOSNS_VALID;
1713 }
1714 break;
1715 case MFI_STAT_LD_OFFLINE:
1716 case MFI_STAT_DEVICE_NOT_FOUND:
1808 }
1809 break;
1810 case MFI_STAT_LD_OFFLINE:
1811 case MFI_STAT_DEVICE_NOT_FOUND:
1717 if (cmd->ccb_ptr->ccb_h.target_lun)
1718 cmd->ccb_ptr->ccb_h.status |= CAM_LUN_INVALID;
1812 if (ccb_ptr->ccb_h.target_lun)
1813 ccb_ptr->ccb_h.status |= CAM_LUN_INVALID;
1719 else
1814 else
1720 cmd->ccb_ptr->ccb_h.status |= CAM_DEV_NOT_THERE;
1815 ccb_ptr->ccb_h.status |= CAM_DEV_NOT_THERE;
1721 break;
1722 case MFI_STAT_CONFIG_SEQ_MISMATCH:
1816 break;
1817 case MFI_STAT_CONFIG_SEQ_MISMATCH:
1723 cmd->ccb_ptr->ccb_h.status |= CAM_REQUEUE_REQ;
1818 ccb_ptr->ccb_h.status |= CAM_REQUEUE_REQ;
1724 break;
1725 default:
1726 device_printf(sc->mrsas_dev, "FW cmd complete status %x\n", status);
1819 break;
1820 default:
1821 device_printf(sc->mrsas_dev, "FW cmd complete status %x\n", status);
1727 cmd->ccb_ptr->ccb_h.status = CAM_REQ_CMP_ERR;
1728 cmd->ccb_ptr->csio.scsi_status = status;
1822 ccb_ptr->ccb_h.status = CAM_REQ_CMP_ERR;
1823 ccb_ptr->csio.scsi_status = status;
1729 }
1730 return;
1731}
1732
1733/*
1734 * mrsas_alloc_mem: Allocate DMAable memory
1735 * input: Adapter instance soft state
1736 *
1737 * This function creates the parent DMA tag and allocates DMAable memory. DMA
1738 * tag describes constraints of DMA mapping. Memory allocated is mapped into
1739 * Kernel virtual address. Callback argument is physical memory address.
1740 */
1741static int
1742mrsas_alloc_mem(struct mrsas_softc *sc)
1743{
1824 }
1825 return;
1826}
1827
1828/*
1829 * mrsas_alloc_mem: Allocate DMAable memory
1830 * input: Adapter instance soft state
1831 *
1832 * This function creates the parent DMA tag and allocates DMAable memory. DMA
1833 * tag describes constraints of DMA mapping. Memory allocated is mapped into
1834 * Kernel virtual address. Callback argument is physical memory address.
1835 */
1836static int
1837mrsas_alloc_mem(struct mrsas_softc *sc)
1838{
1744 u_int32_t verbuf_size, io_req_size, reply_desc_size, sense_size,
1745 chain_frame_size, evt_detail_size, count;
1839 u_int32_t verbuf_size, io_req_size, reply_desc_size, sense_size, chain_frame_size,
1840 evt_detail_size, count, pd_info_size;
1746
1747 /*
1748 * Allocate parent DMA tag
1749 */
1750 if (bus_dma_tag_create(NULL, /* parent */
1751 1, /* alignment */
1752 0, /* boundary */
1753 BUS_SPACE_MAXADDR, /* lowaddr */

--- 153 unchanged lines hidden (view full) ---

1907 return (ENOMEM);
1908 }
1909 if (bus_dmamap_load(sc->sense_tag, sc->sense_dmamap,
1910 sc->sense_mem, sense_size, mrsas_addr_cb, &sc->sense_phys_addr,
1911 BUS_DMA_NOWAIT)) {
1912 device_printf(sc->mrsas_dev, "Cannot load sense buf memory\n");
1913 return (ENOMEM);
1914 }
1841
1842 /*
1843 * Allocate parent DMA tag
1844 */
1845 if (bus_dma_tag_create(NULL, /* parent */
1846 1, /* alignment */
1847 0, /* boundary */
1848 BUS_SPACE_MAXADDR, /* lowaddr */

--- 153 unchanged lines hidden (view full) ---

2002 return (ENOMEM);
2003 }
2004 if (bus_dmamap_load(sc->sense_tag, sc->sense_dmamap,
2005 sc->sense_mem, sense_size, mrsas_addr_cb, &sc->sense_phys_addr,
2006 BUS_DMA_NOWAIT)) {
2007 device_printf(sc->mrsas_dev, "Cannot load sense buf memory\n");
2008 return (ENOMEM);
2009 }
2010
1915 /*
1916 * Allocate for Event detail structure
1917 */
1918 evt_detail_size = sizeof(struct mrsas_evt_detail);
1919 if (bus_dma_tag_create(sc->mrsas_parent_tag,
1920 1, 0,
1921 BUS_SPACE_MAXADDR_32BIT,
1922 BUS_SPACE_MAXADDR,

--- 14 unchanged lines hidden (view full) ---

1937 }
1938 bzero(sc->evt_detail_mem, evt_detail_size);
1939 if (bus_dmamap_load(sc->evt_detail_tag, sc->evt_detail_dmamap,
1940 sc->evt_detail_mem, evt_detail_size, mrsas_addr_cb,
1941 &sc->evt_detail_phys_addr, BUS_DMA_NOWAIT)) {
1942 device_printf(sc->mrsas_dev, "Cannot load Event detail buffer memory\n");
1943 return (ENOMEM);
1944 }
2011 /*
2012 * Allocate for Event detail structure
2013 */
2014 evt_detail_size = sizeof(struct mrsas_evt_detail);
2015 if (bus_dma_tag_create(sc->mrsas_parent_tag,
2016 1, 0,
2017 BUS_SPACE_MAXADDR_32BIT,
2018 BUS_SPACE_MAXADDR,

--- 14 unchanged lines hidden (view full) ---

2033 }
2034 bzero(sc->evt_detail_mem, evt_detail_size);
2035 if (bus_dmamap_load(sc->evt_detail_tag, sc->evt_detail_dmamap,
2036 sc->evt_detail_mem, evt_detail_size, mrsas_addr_cb,
2037 &sc->evt_detail_phys_addr, BUS_DMA_NOWAIT)) {
2038 device_printf(sc->mrsas_dev, "Cannot load Event detail buffer memory\n");
2039 return (ENOMEM);
2040 }
2041
1945 /*
2042 /*
2043 * Allocate for PD INFO structure
2044 */
2045 pd_info_size = sizeof(struct mrsas_pd_info);
2046 if (bus_dma_tag_create(sc->mrsas_parent_tag,
2047 1, 0,
2048 BUS_SPACE_MAXADDR_32BIT,
2049 BUS_SPACE_MAXADDR,
2050 NULL, NULL,
2051 pd_info_size,
2052 1,
2053 pd_info_size,
2054 BUS_DMA_ALLOCNOW,
2055 NULL, NULL,
2056 &sc->pd_info_tag)) {
2057 device_printf(sc->mrsas_dev, "Cannot create PD INFO tag\n");
2058 return (ENOMEM);
2059 }
2060 if (bus_dmamem_alloc(sc->pd_info_tag, (void **)&sc->pd_info_mem,
2061 BUS_DMA_NOWAIT, &sc->pd_info_dmamap)) {
2062 device_printf(sc->mrsas_dev, "Cannot alloc PD INFO buffer memory\n");
2063 return (ENOMEM);
2064 }
2065 bzero(sc->pd_info_mem, pd_info_size);
2066 if (bus_dmamap_load(sc->pd_info_tag, sc->pd_info_dmamap,
2067 sc->pd_info_mem, pd_info_size, mrsas_addr_cb,
2068 &sc->pd_info_phys_addr, BUS_DMA_NOWAIT)) {
2069 device_printf(sc->mrsas_dev, "Cannot load PD INFO buffer memory\n");
2070 return (ENOMEM);
2071 }
2072
2073 /*
1946 * Create a dma tag for data buffers; size will be the maximum
1947 * possible I/O size (280kB).
1948 */
1949 if (bus_dma_tag_create(sc->mrsas_parent_tag,
1950 1,
1951 0,
1952 BUS_SPACE_MAXADDR,
1953 BUS_SPACE_MAXADDR,

--- 188 unchanged lines hidden (view full) ---

2142static int
2143mrsas_init_fw(struct mrsas_softc *sc)
2144{
2145
2146 int ret, loop, ocr = 0;
2147 u_int32_t max_sectors_1;
2148 u_int32_t max_sectors_2;
2149 u_int32_t tmp_sectors;
2074 * Create a dma tag for data buffers; size will be the maximum
2075 * possible I/O size (280kB).
2076 */
2077 if (bus_dma_tag_create(sc->mrsas_parent_tag,
2078 1,
2079 0,
2080 BUS_SPACE_MAXADDR,
2081 BUS_SPACE_MAXADDR,

--- 188 unchanged lines hidden (view full) ---

2270static int
2271mrsas_init_fw(struct mrsas_softc *sc)
2272{
2273
2274 int ret, loop, ocr = 0;
2275 u_int32_t max_sectors_1;
2276 u_int32_t max_sectors_2;
2277 u_int32_t tmp_sectors;
2150 u_int32_t scratch_pad_2;
2278 u_int32_t scratch_pad_2, scratch_pad_3, scratch_pad_4;
2151 int msix_enable = 0;
2152 int fw_msix_count = 0;
2279 int msix_enable = 0;
2280 int fw_msix_count = 0;
2281 int i, j;
2153
2154 /* Make sure Firmware is ready */
2155 ret = mrsas_transition_to_ready(sc, ocr);
2156 if (ret != SUCCESS) {
2157 return (ret);
2158 }
2282
2283 /* Make sure Firmware is ready */
2284 ret = mrsas_transition_to_ready(sc, ocr);
2285 if (ret != SUCCESS) {
2286 return (ret);
2287 }
2288 if (sc->is_ventura) {
2289 scratch_pad_3 = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_scratch_pad_3));
2290#if VD_EXT_DEBUG
2291 device_printf(sc->mrsas_dev, "scratch_pad_3 0x%x\n", scratch_pad_3);
2292#endif
2293 sc->maxRaidMapSize = ((scratch_pad_3 >>
2294 MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT) &
2295 MR_MAX_RAID_MAP_SIZE_MASK);
2296 }
2159 /* MSI-x index 0- reply post host index register */
2160 sc->msix_reg_offset[0] = MPI2_REPLY_POST_HOST_INDEX_OFFSET;
2161 /* Check if MSI-X is supported while in ready state */
2162 msix_enable = (mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_scratch_pad)) & 0x4000000) >> 0x1a;
2163
2164 if (msix_enable) {
2165 scratch_pad_2 = mrsas_read_reg(sc, offsetof(mrsas_reg_set,
2166 outbound_scratch_pad_2));

--- 5 unchanged lines hidden (view full) ---

2172 fw_msix_count = sc->msix_vectors;
2173 } else {
2174 /* Invader/Fury supports 96 MSI-X vectors */
2175 sc->msix_vectors = ((scratch_pad_2
2176 & MR_MAX_REPLY_QUEUES_EXT_OFFSET)
2177 >> MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT) + 1;
2178 fw_msix_count = sc->msix_vectors;
2179
2297 /* MSI-x index 0- reply post host index register */
2298 sc->msix_reg_offset[0] = MPI2_REPLY_POST_HOST_INDEX_OFFSET;
2299 /* Check if MSI-X is supported while in ready state */
2300 msix_enable = (mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_scratch_pad)) & 0x4000000) >> 0x1a;
2301
2302 if (msix_enable) {
2303 scratch_pad_2 = mrsas_read_reg(sc, offsetof(mrsas_reg_set,
2304 outbound_scratch_pad_2));

--- 5 unchanged lines hidden (view full) ---

2310 fw_msix_count = sc->msix_vectors;
2311 } else {
2312 /* Invader/Fury supports 96 MSI-X vectors */
2313 sc->msix_vectors = ((scratch_pad_2
2314 & MR_MAX_REPLY_QUEUES_EXT_OFFSET)
2315 >> MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT) + 1;
2316 fw_msix_count = sc->msix_vectors;
2317
2318 if ((sc->mrsas_gen3_ctrl && (sc->msix_vectors > 8)) ||
2319 (sc->is_ventura && (sc->msix_vectors > 16)))
2320 sc->msix_combined = true;
2321 /*
2322 * Save 1-15 reply post index
2323 * address to local memory Index 0
2324 * is already saved from reg offset
2325 * MPI2_REPLY_POST_HOST_INDEX_OFFSET
2326 */
2180 for (loop = 1; loop < MR_MAX_MSIX_REG_ARRAY;
2181 loop++) {
2182 sc->msix_reg_offset[loop] =
2183 MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET +
2184 (loop * 0x10);
2185 }
2186 }
2187

--- 6 unchanged lines hidden (view full) ---

2194 sc->msix_enable = 1;
2195 else
2196 sc->msix_enable = 0;
2197
2198 device_printf(sc->mrsas_dev, "FW supports <%d> MSIX vector,"
2199 "Online CPU %d Current MSIX <%d>\n",
2200 fw_msix_count, mp_ncpus, sc->msix_vectors);
2201 }
2327 for (loop = 1; loop < MR_MAX_MSIX_REG_ARRAY;
2328 loop++) {
2329 sc->msix_reg_offset[loop] =
2330 MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET +
2331 (loop * 0x10);
2332 }
2333 }
2334

--- 6 unchanged lines hidden (view full) ---

2341 sc->msix_enable = 1;
2342 else
2343 sc->msix_enable = 0;
2344
2345 device_printf(sc->mrsas_dev, "FW supports <%d> MSIX vector,"
2346 "Online CPU %d Current MSIX <%d>\n",
2347 fw_msix_count, mp_ncpus, sc->msix_vectors);
2348 }
2349 /*
2350 * MSI-X host index 0 is common for all adapter.
2351 * It is used for all MPT based Adapters.
2352 */
2353 if (sc->msix_combined) {
2354 sc->msix_reg_offset[0] =
2355 MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET;
2356 }
2202 if (mrsas_init_adapter(sc) != SUCCESS) {
2203 device_printf(sc->mrsas_dev, "Adapter initialize Fail.\n");
2204 return (1);
2205 }
2357 if (mrsas_init_adapter(sc) != SUCCESS) {
2358 device_printf(sc->mrsas_dev, "Adapter initialize Fail.\n");
2359 return (1);
2360 }
2361
2362 if (sc->is_ventura) {
2363 scratch_pad_4 = mrsas_read_reg(sc, offsetof(mrsas_reg_set,
2364 outbound_scratch_pad_4));
2365 if ((scratch_pad_4 & MR_NVME_PAGE_SIZE_MASK) >= MR_DEFAULT_NVME_PAGE_SHIFT)
2366 sc->nvme_page_size = 1 << (scratch_pad_4 & MR_NVME_PAGE_SIZE_MASK);
2367
2368 device_printf(sc->mrsas_dev, "NVME page size\t: (%d)\n", sc->nvme_page_size);
2369 }
2370
2206 /* Allocate internal commands for pass-thru */
2207 if (mrsas_alloc_mfi_cmds(sc) != SUCCESS) {
2208 device_printf(sc->mrsas_dev, "Allocate MFI cmd failed.\n");
2209 return (1);
2210 }
2211 sc->ctrl_info = malloc(sizeof(struct mrsas_ctrl_info), M_MRSAS, M_NOWAIT);
2212 if (!sc->ctrl_info) {
2213 device_printf(sc->mrsas_dev, "Malloc for ctrl_info failed.\n");

--- 11 unchanged lines hidden (view full) ---

2225 (u_int8_t)sc->ctrl_info->adapterOperations3.supportSecurityonJBOD;
2226
2227 if (sc->secure_jbod_support)
2228 device_printf(sc->mrsas_dev, "FW supports SED \n");
2229
2230 if (sc->use_seqnum_jbod_fp)
2231 device_printf(sc->mrsas_dev, "FW supports JBOD Map \n");
2232
2371 /* Allocate internal commands for pass-thru */
2372 if (mrsas_alloc_mfi_cmds(sc) != SUCCESS) {
2373 device_printf(sc->mrsas_dev, "Allocate MFI cmd failed.\n");
2374 return (1);
2375 }
2376 sc->ctrl_info = malloc(sizeof(struct mrsas_ctrl_info), M_MRSAS, M_NOWAIT);
2377 if (!sc->ctrl_info) {
2378 device_printf(sc->mrsas_dev, "Malloc for ctrl_info failed.\n");

--- 11 unchanged lines hidden (view full) ---

2390 (u_int8_t)sc->ctrl_info->adapterOperations3.supportSecurityonJBOD;
2391
2392 if (sc->secure_jbod_support)
2393 device_printf(sc->mrsas_dev, "FW supports SED \n");
2394
2395 if (sc->use_seqnum_jbod_fp)
2396 device_printf(sc->mrsas_dev, "FW supports JBOD Map \n");
2397
2398 if (sc->support_morethan256jbod)
2399 device_printf(sc->mrsas_dev, "FW supports JBOD Map Ext \n");
2400
2233 if (mrsas_setup_raidmap(sc) != SUCCESS) {
2234 device_printf(sc->mrsas_dev, "Error: RAID map setup FAILED !!! "
2235 "There seems to be some problem in the controller\n"
2236 "Please contact to the SUPPORT TEAM if the problem persists\n");
2237 }
2238 megasas_setup_jbod_map(sc);
2239
2401 if (mrsas_setup_raidmap(sc) != SUCCESS) {
2402 device_printf(sc->mrsas_dev, "Error: RAID map setup FAILED !!! "
2403 "There seems to be some problem in the controller\n"
2404 "Please contact to the SUPPORT TEAM if the problem persists\n");
2405 }
2406 megasas_setup_jbod_map(sc);
2407
2408
2409 memset(sc->target_list, 0,
2410 MRSAS_MAX_TM_TARGETS * sizeof(struct mrsas_target));
2411 for (i = 0; i < MRSAS_MAX_TM_TARGETS; i++)
2412 sc->target_list[i].target_id = 0xffff;
2413
2240 /* For pass-thru, get PD/LD list and controller info */
2241 memset(sc->pd_list, 0,
2242 MRSAS_MAX_PD * sizeof(struct mrsas_pd_list));
2243 if (mrsas_get_pd_list(sc) != SUCCESS) {
2244 device_printf(sc->mrsas_dev, "Get PD list failed.\n");
2245 return (1);
2246 }
2247 memset(sc->ld_ids, 0xff, MRSAS_MAX_LD_IDS);
2248 if (mrsas_get_ld_list(sc) != SUCCESS) {
2249 device_printf(sc->mrsas_dev, "Get LD lsit failed.\n");
2250 return (1);
2251 }
2414 /* For pass-thru, get PD/LD list and controller info */
2415 memset(sc->pd_list, 0,
2416 MRSAS_MAX_PD * sizeof(struct mrsas_pd_list));
2417 if (mrsas_get_pd_list(sc) != SUCCESS) {
2418 device_printf(sc->mrsas_dev, "Get PD list failed.\n");
2419 return (1);
2420 }
2421 memset(sc->ld_ids, 0xff, MRSAS_MAX_LD_IDS);
2422 if (mrsas_get_ld_list(sc) != SUCCESS) {
2423 device_printf(sc->mrsas_dev, "Get LD lsit failed.\n");
2424 return (1);
2425 }
2426
2427 if (sc->is_ventura && sc->drv_stream_detection) {
2428 sc->streamDetectByLD = malloc(sizeof(PTR_LD_STREAM_DETECT) *
2429 MAX_LOGICAL_DRIVES_EXT, M_MRSAS, M_NOWAIT);
2430 if (!sc->streamDetectByLD) {
2431 device_printf(sc->mrsas_dev,
2432 "unable to allocate stream detection for pool of LDs\n");
2433 return (1);
2434 }
2435 for (i = 0; i < MAX_LOGICAL_DRIVES_EXT; ++i) {
2436 sc->streamDetectByLD[i] = malloc(sizeof(LD_STREAM_DETECT), M_MRSAS, M_NOWAIT);
2437 if (!sc->streamDetectByLD[i]) {
2438 device_printf(sc->mrsas_dev, "unable to allocate stream detect by LD\n");
2439 for (j = 0; j < i; ++j)
2440 free(sc->streamDetectByLD[j], M_MRSAS);
2441 free(sc->streamDetectByLD, M_MRSAS);
2442 sc->streamDetectByLD = NULL;
2443 return (1);
2444 }
2445 memset(sc->streamDetectByLD[i], 0, sizeof(LD_STREAM_DETECT));
2446 sc->streamDetectByLD[i]->mruBitMap = MR_STREAM_BITMAP;
2447 }
2448 }
2449
2252 /*
2253 * Compute the max allowed sectors per IO: The controller info has
2254 * two limits on max sectors. Driver should use the minimum of these
2255 * two.
2256 *
2257 * 1 << stripe_sz_ops.min = max sectors per strip
2258 *
2259 * Note that older firmwares ( < FW ver 30) didn't report information to

--- 33 unchanged lines hidden (view full) ---

2293 * ROC/controller. The FW register is read to determined the number of
2294 * commands that is supported. All memory allocations for IO is based on
2295 * max_cmd. Appropriate calculations are performed in this function.
2296 */
2297int
2298mrsas_init_adapter(struct mrsas_softc *sc)
2299{
2300 uint32_t status;
2450 /*
2451 * Compute the max allowed sectors per IO: The controller info has
2452 * two limits on max sectors. Driver should use the minimum of these
2453 * two.
2454 *
2455 * 1 << stripe_sz_ops.min = max sectors per strip
2456 *
2457 * Note that older firmwares ( < FW ver 30) didn't report information to

--- 33 unchanged lines hidden (view full) ---

2491 * ROC/controller. The FW register is read to determined the number of
2492 * commands that is supported. All memory allocations for IO is based on
2493 * max_cmd. Appropriate calculations are performed in this function.
2494 */
2495int
2496mrsas_init_adapter(struct mrsas_softc *sc)
2497{
2498 uint32_t status;
2301 u_int32_t max_cmd, scratch_pad_2;
2499 u_int32_t scratch_pad_2;
2302 int ret;
2303 int i = 0;
2304
2305 /* Read FW status register */
2306 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_scratch_pad));
2307
2500 int ret;
2501 int i = 0;
2502
2503 /* Read FW status register */
2504 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_scratch_pad));
2505
2308 /* Get operational params from status register */
2309 sc->max_fw_cmds = status & MRSAS_FWSTATE_MAXCMD_MASK;
2310
2311 /* Decrement the max supported by 1, to correlate with FW */
2312 sc->max_fw_cmds = sc->max_fw_cmds - 1;
2506 sc->max_fw_cmds = status & MRSAS_FWSTATE_MAXCMD_MASK;
2507
2508 /* Decrement the max supported by 1, to correlate with FW */
2509 sc->max_fw_cmds = sc->max_fw_cmds - 1;
2313 max_cmd = sc->max_fw_cmds;
2510 sc->max_scsi_cmds = sc->max_fw_cmds -
2511 (MRSAS_FUSION_INT_CMDS + MRSAS_MAX_IOCTL_CMDS);
2314
2315 /* Determine allocation size of command frames */
2512
2513 /* Determine allocation size of command frames */
2316 sc->reply_q_depth = ((max_cmd + 1 + 15) / 16 * 16) * 2;
2317 sc->request_alloc_sz = sizeof(MRSAS_REQUEST_DESCRIPTOR_UNION) * max_cmd;
2514 sc->reply_q_depth = ((sc->max_fw_cmds + 1 + 15) / 16 * 16) * 2;
2515 sc->request_alloc_sz = sizeof(MRSAS_REQUEST_DESCRIPTOR_UNION) * sc->max_fw_cmds;
2318 sc->reply_alloc_sz = sizeof(MPI2_REPLY_DESCRIPTORS_UNION) * (sc->reply_q_depth);
2516 sc->reply_alloc_sz = sizeof(MPI2_REPLY_DESCRIPTORS_UNION) * (sc->reply_q_depth);
2319 sc->io_frames_alloc_sz = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE + (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * (max_cmd + 1));
2517 sc->io_frames_alloc_sz = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE +
2518 (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * (sc->max_fw_cmds + 1));
2320 scratch_pad_2 = mrsas_read_reg(sc, offsetof(mrsas_reg_set,
2321 outbound_scratch_pad_2));
2322 /*
2323 * If scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK is set,
2324 * Firmware support extended IO chain frame which is 4 time more
2325 * than legacy Firmware. Legacy Firmware - Frame size is (8 * 128) =
2326 * 1K 1M IO Firmware - Frame size is (8 * 128 * 4) = 4K
2327 */
2328 if (scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK)
2329 sc->max_chain_frame_sz =
2330 ((scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK) >> 5)
2331 * MEGASAS_1MB_IO;
2332 else
2333 sc->max_chain_frame_sz =
2334 ((scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK) >> 5)
2335 * MEGASAS_256K_IO;
2336
2519 scratch_pad_2 = mrsas_read_reg(sc, offsetof(mrsas_reg_set,
2520 outbound_scratch_pad_2));
2521 /*
2522 * If scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK is set,
2523 * Firmware support extended IO chain frame which is 4 time more
2524 * than legacy Firmware. Legacy Firmware - Frame size is (8 * 128) =
2525 * 1K 1M IO Firmware - Frame size is (8 * 128 * 4) = 4K
2526 */
2527 if (scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK)
2528 sc->max_chain_frame_sz =
2529 ((scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK) >> 5)
2530 * MEGASAS_1MB_IO;
2531 else
2532 sc->max_chain_frame_sz =
2533 ((scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK) >> 5)
2534 * MEGASAS_256K_IO;
2535
2337 sc->chain_frames_alloc_sz = sc->max_chain_frame_sz * max_cmd;
2536 sc->chain_frames_alloc_sz = sc->max_chain_frame_sz * sc->max_fw_cmds;
2338 sc->max_sge_in_main_msg = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE -
2339 offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL)) / 16;
2340
2341 sc->max_sge_in_chain = sc->max_chain_frame_sz / sizeof(MPI2_SGE_IO_UNION);
2342 sc->max_num_sge = sc->max_sge_in_main_msg + sc->max_sge_in_chain - 2;
2343
2537 sc->max_sge_in_main_msg = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE -
2538 offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL)) / 16;
2539
2540 sc->max_sge_in_chain = sc->max_chain_frame_sz / sizeof(MPI2_SGE_IO_UNION);
2541 sc->max_num_sge = sc->max_sge_in_main_msg + sc->max_sge_in_chain - 2;
2542
2344 mrsas_dprint(sc, MRSAS_INFO, "Avago Debug: MAX sge 0x%X MAX chain frame size 0x%X \n",
2345 sc->max_num_sge, sc->max_chain_frame_sz);
2543 mrsas_dprint(sc, MRSAS_INFO,
2544 "max sge: 0x%x, max chain frame size: 0x%x, "
2545 "max fw cmd: 0x%x\n", sc->max_num_sge,
2546 sc->max_chain_frame_sz, sc->max_fw_cmds);
2346
2347 /* Used for pass thru MFI frame (DCMD) */
2348 sc->chain_offset_mfi_pthru = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL) / 16;
2349
2350 sc->chain_offset_io_request = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE -
2351 sizeof(MPI2_SGE_IO_UNION)) / 16;
2352
2353 int count = sc->msix_vectors > 0 ? sc->msix_vectors : 1;

--- 82 unchanged lines hidden (view full) ---

2436 * Issues the IOC Init cmd to FW to initialize the ROC/controller.
2437 */
2438int
2439mrsas_ioc_init(struct mrsas_softc *sc)
2440{
2441 struct mrsas_init_frame *init_frame;
2442 pMpi2IOCInitRequest_t IOCInitMsg;
2443 MRSAS_REQUEST_DESCRIPTOR_UNION req_desc;
2547
2548 /* Used for pass thru MFI frame (DCMD) */
2549 sc->chain_offset_mfi_pthru = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL) / 16;
2550
2551 sc->chain_offset_io_request = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE -
2552 sizeof(MPI2_SGE_IO_UNION)) / 16;
2553
2554 int count = sc->msix_vectors > 0 ? sc->msix_vectors : 1;

--- 82 unchanged lines hidden (view full) ---

2637 * Issues the IOC Init cmd to FW to initialize the ROC/controller.
2638 */
2639int
2640mrsas_ioc_init(struct mrsas_softc *sc)
2641{
2642 struct mrsas_init_frame *init_frame;
2643 pMpi2IOCInitRequest_t IOCInitMsg;
2644 MRSAS_REQUEST_DESCRIPTOR_UNION req_desc;
2444 u_int8_t max_wait = MRSAS_IOC_INIT_WAIT_TIME;
2645 u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME;
2445 bus_addr_t phys_addr;
2446 int i, retcode = 0;
2447 u_int32_t scratch_pad_2;
2448
2449 /* Allocate memory for the IOC INIT command */
2450 if (mrsas_alloc_ioc_cmd(sc)) {
2451 device_printf(sc->mrsas_dev, "Cannot allocate IOC command.\n");
2452 return (1);

--- 11 unchanged lines hidden (view full) ---

2464 IOCInitMsg->WhoInit = MPI2_WHOINIT_HOST_DRIVER;
2465 IOCInitMsg->MsgVersion = MPI2_VERSION;
2466 IOCInitMsg->HeaderVersion = MPI2_HEADER_VERSION;
2467 IOCInitMsg->SystemRequestFrameSize = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE / 4;
2468 IOCInitMsg->ReplyDescriptorPostQueueDepth = sc->reply_q_depth;
2469 IOCInitMsg->ReplyDescriptorPostQueueAddress = sc->reply_desc_phys_addr;
2470 IOCInitMsg->SystemRequestFrameBaseAddress = sc->io_request_phys_addr;
2471 IOCInitMsg->HostMSIxVectors = (sc->msix_vectors > 0 ? sc->msix_vectors : 0);
2646 bus_addr_t phys_addr;
2647 int i, retcode = 0;
2648 u_int32_t scratch_pad_2;
2649
2650 /* Allocate memory for the IOC INIT command */
2651 if (mrsas_alloc_ioc_cmd(sc)) {
2652 device_printf(sc->mrsas_dev, "Cannot allocate IOC command.\n");
2653 return (1);

--- 11 unchanged lines hidden (view full) ---

2665 IOCInitMsg->WhoInit = MPI2_WHOINIT_HOST_DRIVER;
2666 IOCInitMsg->MsgVersion = MPI2_VERSION;
2667 IOCInitMsg->HeaderVersion = MPI2_HEADER_VERSION;
2668 IOCInitMsg->SystemRequestFrameSize = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE / 4;
2669 IOCInitMsg->ReplyDescriptorPostQueueDepth = sc->reply_q_depth;
2670 IOCInitMsg->ReplyDescriptorPostQueueAddress = sc->reply_desc_phys_addr;
2671 IOCInitMsg->SystemRequestFrameBaseAddress = sc->io_request_phys_addr;
2672 IOCInitMsg->HostMSIxVectors = (sc->msix_vectors > 0 ? sc->msix_vectors : 0);
2673 IOCInitMsg->HostPageSize = MR_DEFAULT_NVME_PAGE_SHIFT;
2472
2473 init_frame = (struct mrsas_init_frame *)sc->ioc_init_mem;
2474 init_frame->cmd = MFI_CMD_INIT;
2475 init_frame->cmd_status = 0xFF;
2476 init_frame->flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE;
2477
2478 /* driver support Extended MSIX */
2674
2675 init_frame = (struct mrsas_init_frame *)sc->ioc_init_mem;
2676 init_frame->cmd = MFI_CMD_INIT;
2677 init_frame->cmd_status = 0xFF;
2678 init_frame->flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE;
2679
2680 /* driver support Extended MSIX */
2479 if (sc->mrsas_gen3_ctrl) {
2681 if (sc->mrsas_gen3_ctrl || sc->is_ventura) {
2480 init_frame->driver_operations.
2481 mfi_capabilities.support_additional_msix = 1;
2482 }
2483 if (sc->verbuf_mem) {
2484 snprintf((char *)sc->verbuf_mem, strlen(MRSAS_VERSION) + 2, "%s\n",
2485 MRSAS_VERSION);
2486 init_frame->driver_ver_lo = (bus_addr_t)sc->verbuf_phys_addr;
2487 init_frame->driver_ver_hi = 0;

--- 52 unchanged lines hidden (view full) ---

2540 * array is allocated with mrsas_mpt_cmd context. The free commands are
2541 * maintained in a linked list (cmd pool). SMID value range is from 1 to
2542 * max_fw_cmds.
2543 */
2544int
2545mrsas_alloc_mpt_cmds(struct mrsas_softc *sc)
2546{
2547 int i, j;
2682 init_frame->driver_operations.
2683 mfi_capabilities.support_additional_msix = 1;
2684 }
2685 if (sc->verbuf_mem) {
2686 snprintf((char *)sc->verbuf_mem, strlen(MRSAS_VERSION) + 2, "%s\n",
2687 MRSAS_VERSION);
2688 init_frame->driver_ver_lo = (bus_addr_t)sc->verbuf_phys_addr;
2689 init_frame->driver_ver_hi = 0;

--- 52 unchanged lines hidden (view full) ---

2742 * array is allocated with mrsas_mpt_cmd context. The free commands are
2743 * maintained in a linked list (cmd pool). SMID value range is from 1 to
2744 * max_fw_cmds.
2745 */
2746int
2747mrsas_alloc_mpt_cmds(struct mrsas_softc *sc)
2748{
2749 int i, j;
2548 u_int32_t max_cmd, count;
2750 u_int32_t max_fw_cmds, count;
2549 struct mrsas_mpt_cmd *cmd;
2550 pMpi2ReplyDescriptorsUnion_t reply_desc;
2551 u_int32_t offset, chain_offset, sense_offset;
2552 bus_addr_t io_req_base_phys, chain_frame_base_phys, sense_base_phys;
2553 u_int8_t *io_req_base, *chain_frame_base, *sense_base;
2554
2751 struct mrsas_mpt_cmd *cmd;
2752 pMpi2ReplyDescriptorsUnion_t reply_desc;
2753 u_int32_t offset, chain_offset, sense_offset;
2754 bus_addr_t io_req_base_phys, chain_frame_base_phys, sense_base_phys;
2755 u_int8_t *io_req_base, *chain_frame_base, *sense_base;
2756
2555 max_cmd = sc->max_fw_cmds;
2757 max_fw_cmds = sc->max_fw_cmds;
2556
2557 sc->req_desc = malloc(sc->request_alloc_sz, M_MRSAS, M_NOWAIT);
2558 if (!sc->req_desc) {
2559 device_printf(sc->mrsas_dev, "Out of memory, cannot alloc req desc\n");
2560 return (ENOMEM);
2561 }
2562 memset(sc->req_desc, 0, sc->request_alloc_sz);
2563
2564 /*
2565 * sc->mpt_cmd_list is an array of struct mrsas_mpt_cmd pointers.
2566 * Allocate the dynamic array first and then allocate individual
2567 * commands.
2568 */
2758
2759 sc->req_desc = malloc(sc->request_alloc_sz, M_MRSAS, M_NOWAIT);
2760 if (!sc->req_desc) {
2761 device_printf(sc->mrsas_dev, "Out of memory, cannot alloc req desc\n");
2762 return (ENOMEM);
2763 }
2764 memset(sc->req_desc, 0, sc->request_alloc_sz);
2765
2766 /*
2767 * sc->mpt_cmd_list is an array of struct mrsas_mpt_cmd pointers.
2768 * Allocate the dynamic array first and then allocate individual
2769 * commands.
2770 */
2569 sc->mpt_cmd_list = malloc(sizeof(struct mrsas_mpt_cmd *) * max_cmd, M_MRSAS, M_NOWAIT);
2771 sc->mpt_cmd_list = malloc(sizeof(struct mrsas_mpt_cmd *) * max_fw_cmds,
2772 M_MRSAS, M_NOWAIT);
2570 if (!sc->mpt_cmd_list) {
2571 device_printf(sc->mrsas_dev, "Cannot alloc memory for mpt_cmd_list.\n");
2572 return (ENOMEM);
2573 }
2773 if (!sc->mpt_cmd_list) {
2774 device_printf(sc->mrsas_dev, "Cannot alloc memory for mpt_cmd_list.\n");
2775 return (ENOMEM);
2776 }
2574 memset(sc->mpt_cmd_list, 0, sizeof(struct mrsas_mpt_cmd *) * max_cmd);
2575 for (i = 0; i < max_cmd; i++) {
2777 memset(sc->mpt_cmd_list, 0, sizeof(struct mrsas_mpt_cmd *) * max_fw_cmds);
2778 for (i = 0; i < max_fw_cmds; i++) {
2576 sc->mpt_cmd_list[i] = malloc(sizeof(struct mrsas_mpt_cmd),
2577 M_MRSAS, M_NOWAIT);
2578 if (!sc->mpt_cmd_list[i]) {
2579 for (j = 0; j < i; j++)
2580 free(sc->mpt_cmd_list[j], M_MRSAS);
2581 free(sc->mpt_cmd_list, M_MRSAS);
2582 sc->mpt_cmd_list = NULL;
2583 return (ENOMEM);
2584 }
2585 }
2586
2587 io_req_base = (u_int8_t *)sc->io_request_mem + MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE;
2588 io_req_base_phys = (bus_addr_t)sc->io_request_phys_addr + MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE;
2589 chain_frame_base = (u_int8_t *)sc->chain_frame_mem;
2590 chain_frame_base_phys = (bus_addr_t)sc->chain_frame_phys_addr;
2591 sense_base = (u_int8_t *)sc->sense_mem;
2592 sense_base_phys = (bus_addr_t)sc->sense_phys_addr;
2779 sc->mpt_cmd_list[i] = malloc(sizeof(struct mrsas_mpt_cmd),
2780 M_MRSAS, M_NOWAIT);
2781 if (!sc->mpt_cmd_list[i]) {
2782 for (j = 0; j < i; j++)
2783 free(sc->mpt_cmd_list[j], M_MRSAS);
2784 free(sc->mpt_cmd_list, M_MRSAS);
2785 sc->mpt_cmd_list = NULL;
2786 return (ENOMEM);
2787 }
2788 }
2789
2790 io_req_base = (u_int8_t *)sc->io_request_mem + MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE;
2791 io_req_base_phys = (bus_addr_t)sc->io_request_phys_addr + MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE;
2792 chain_frame_base = (u_int8_t *)sc->chain_frame_mem;
2793 chain_frame_base_phys = (bus_addr_t)sc->chain_frame_phys_addr;
2794 sense_base = (u_int8_t *)sc->sense_mem;
2795 sense_base_phys = (bus_addr_t)sc->sense_phys_addr;
2593 for (i = 0; i < max_cmd; i++) {
2796 for (i = 0; i < max_fw_cmds; i++) {
2594 cmd = sc->mpt_cmd_list[i];
2595 offset = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * i;
2596 chain_offset = sc->max_chain_frame_sz * i;
2597 sense_offset = MRSAS_SENSE_LEN * i;
2598 memset(cmd, 0, sizeof(struct mrsas_mpt_cmd));
2599 cmd->index = i + 1;
2600 cmd->ccb_ptr = NULL;
2797 cmd = sc->mpt_cmd_list[i];
2798 offset = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * i;
2799 chain_offset = sc->max_chain_frame_sz * i;
2800 sense_offset = MRSAS_SENSE_LEN * i;
2801 memset(cmd, 0, sizeof(struct mrsas_mpt_cmd));
2802 cmd->index = i + 1;
2803 cmd->ccb_ptr = NULL;
2804 cmd->r1_alt_dev_handle = MR_DEVHANDLE_INVALID;
2601 callout_init_mtx(&cmd->cm_callout, &sc->sim_lock, 0);
2602 cmd->sync_cmd_idx = (u_int32_t)MRSAS_ULONG_MAX;
2603 cmd->sc = sc;
2604 cmd->io_request = (MRSAS_RAID_SCSI_IO_REQUEST *) (io_req_base + offset);
2605 memset(cmd->io_request, 0, sizeof(MRSAS_RAID_SCSI_IO_REQUEST));
2606 cmd->io_request_phys_addr = io_req_base_phys + offset;
2607 cmd->chain_frame = (MPI2_SGE_IO_UNION *) (chain_frame_base + chain_offset);
2608 cmd->chain_frame_phys_addr = chain_frame_base_phys + chain_offset;

--- 335 unchanged lines hidden (view full) ---

2944 if (mrsas_wait_for_outstanding(sc, reset_reason)) {
2945 mrsas_dprint(sc, MRSAS_OCR,
2946 "resetting adapter from %s.\n",
2947 __func__);
2948 /* Now return commands back to the CAM layer */
2949 mtx_unlock(&sc->sim_lock);
2950 for (i = 0; i < sc->max_fw_cmds; i++) {
2951 mpt_cmd = sc->mpt_cmd_list[i];
2805 callout_init_mtx(&cmd->cm_callout, &sc->sim_lock, 0);
2806 cmd->sync_cmd_idx = (u_int32_t)MRSAS_ULONG_MAX;
2807 cmd->sc = sc;
2808 cmd->io_request = (MRSAS_RAID_SCSI_IO_REQUEST *) (io_req_base + offset);
2809 memset(cmd->io_request, 0, sizeof(MRSAS_RAID_SCSI_IO_REQUEST));
2810 cmd->io_request_phys_addr = io_req_base_phys + offset;
2811 cmd->chain_frame = (MPI2_SGE_IO_UNION *) (chain_frame_base + chain_offset);
2812 cmd->chain_frame_phys_addr = chain_frame_base_phys + chain_offset;

--- 335 unchanged lines hidden (view full) ---

3148 if (mrsas_wait_for_outstanding(sc, reset_reason)) {
3149 mrsas_dprint(sc, MRSAS_OCR,
3150 "resetting adapter from %s.\n",
3151 __func__);
3152 /* Now return commands back to the CAM layer */
3153 mtx_unlock(&sc->sim_lock);
3154 for (i = 0; i < sc->max_fw_cmds; i++) {
3155 mpt_cmd = sc->mpt_cmd_list[i];
3156
3157 if (mpt_cmd->peer_cmd) {
3158 mrsas_dprint(sc, MRSAS_OCR,
3159 "R1 FP command [%d] - (mpt_cmd) %p, (peer_cmd) %p\n",
3160 i, mpt_cmd, mpt_cmd->peer_cmd);
3161 }
3162
2952 if (mpt_cmd->ccb_ptr) {
3163 if (mpt_cmd->ccb_ptr) {
2953 ccb = (union ccb *)(mpt_cmd->ccb_ptr);
2954 ccb->ccb_h.status = CAM_SCSI_BUS_RESET;
2955 mrsas_cmd_done(sc, mpt_cmd);
2956 mrsas_atomic_dec(&sc->fw_outstanding);
3164 if (mpt_cmd->callout_owner) {
3165 ccb = (union ccb *)(mpt_cmd->ccb_ptr);
3166 ccb->ccb_h.status = CAM_SCSI_BUS_RESET;
3167 mrsas_cmd_done(sc, mpt_cmd);
3168 } else {
3169 mpt_cmd->ccb_ptr = NULL;
3170 mrsas_release_mpt_cmd(mpt_cmd);
3171 }
2957 }
2958 }
3172 }
3173 }
3174
3175 mrsas_atomic_set(&sc->fw_outstanding, 0);
3176
2959 mtx_lock(&sc->sim_lock);
2960
2961 status_reg = mrsas_read_reg(sc, offsetof(mrsas_reg_set,
2962 outbound_scratch_pad));
2963 abs_state = status_reg & MFI_STATE_MASK;
2964 reset_adapter = status_reg & MFI_RESET_ADAPTER;
2965 if (sc->disableOnlineCtrlReset ||
2966 (abs_state == MFI_STATE_FAULT && !reset_adapter)) {

--- 116 unchanged lines hidden (view full) ---

3083 retval = FAIL;
3084 goto out;
3085 }
3086 if (!mrsas_get_map_info(sc))
3087 mrsas_sync_map_info(sc);
3088
3089 megasas_setup_jbod_map(sc);
3090
3177 mtx_lock(&sc->sim_lock);
3178
3179 status_reg = mrsas_read_reg(sc, offsetof(mrsas_reg_set,
3180 outbound_scratch_pad));
3181 abs_state = status_reg & MFI_STATE_MASK;
3182 reset_adapter = status_reg & MFI_RESET_ADAPTER;
3183 if (sc->disableOnlineCtrlReset ||
3184 (abs_state == MFI_STATE_FAULT && !reset_adapter)) {

--- 116 unchanged lines hidden (view full) ---

3301 retval = FAIL;
3302 goto out;
3303 }
3304 if (!mrsas_get_map_info(sc))
3305 mrsas_sync_map_info(sc);
3306
3307 megasas_setup_jbod_map(sc);
3308
3309 if (sc->is_ventura && sc->streamDetectByLD) {
3310 for (j = 0; j < MAX_LOGICAL_DRIVES_EXT; ++j) {
3311 memset(sc->streamDetectByLD[i], 0, sizeof(LD_STREAM_DETECT));
3312 sc->streamDetectByLD[i]->mruBitMap = MR_STREAM_BITMAP;
3313 }
3314 }
3315
3091 mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags);
3092 mrsas_enable_intr(sc);
3093 sc->adprecovery = MRSAS_HBA_OPERATIONAL;
3094
3095 /* Register AEN with FW for last sequence number */
3096 class_locale.members.reserved = 0;
3097 class_locale.members.locale = MR_EVT_LOCALE_ALL;
3098 class_locale.members.class = MR_EVT_CLASS_DEBUG;

--- 68 unchanged lines hidden (view full) ---

3167 for (i = 0; i < sc->max_fw_cmds; i++) {
3168 cmd_mpt = sc->mpt_cmd_list[i];
3169
3170 if (cmd_mpt->sync_cmd_idx != (u_int32_t)MRSAS_ULONG_MAX) {
3171 cmd_mfi = sc->mfi_cmd_list[cmd_mpt->sync_cmd_idx];
3172 if (cmd_mfi->sync_cmd && cmd_mfi->frame->hdr.cmd != MFI_CMD_ABORT) {
3173 for (MSIxIndex = 0; MSIxIndex < count; MSIxIndex++)
3174 mrsas_complete_mptmfi_passthru(sc, cmd_mfi,
3316 mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags);
3317 mrsas_enable_intr(sc);
3318 sc->adprecovery = MRSAS_HBA_OPERATIONAL;
3319
3320 /* Register AEN with FW for last sequence number */
3321 class_locale.members.reserved = 0;
3322 class_locale.members.locale = MR_EVT_LOCALE_ALL;
3323 class_locale.members.class = MR_EVT_CLASS_DEBUG;

--- 68 unchanged lines hidden (view full) ---

3392 for (i = 0; i < sc->max_fw_cmds; i++) {
3393 cmd_mpt = sc->mpt_cmd_list[i];
3394
3395 if (cmd_mpt->sync_cmd_idx != (u_int32_t)MRSAS_ULONG_MAX) {
3396 cmd_mfi = sc->mfi_cmd_list[cmd_mpt->sync_cmd_idx];
3397 if (cmd_mfi->sync_cmd && cmd_mfi->frame->hdr.cmd != MFI_CMD_ABORT) {
3398 for (MSIxIndex = 0; MSIxIndex < count; MSIxIndex++)
3399 mrsas_complete_mptmfi_passthru(sc, cmd_mfi,
3175 cmd_mpt->io_request->RaidContext.status);
3400 cmd_mpt->io_request->RaidContext.raid_context.status);
3176 }
3177 }
3178 }
3179}
3180
3181/*
3182 * mrsas_wait_for_outstanding: Wait for outstanding commands
3183 * input: Adapter Context.

--- 150 unchanged lines hidden (view full) ---

3334 else
3335 memcpy(sc->ctrl_info, sc->ctlr_info_mem, sizeof(struct mrsas_ctrl_info));
3336
3337 do_ocr = 0;
3338 mrsas_update_ext_vd_details(sc);
3339
3340 sc->use_seqnum_jbod_fp =
3341 sc->ctrl_info->adapterOperations3.useSeqNumJbodFP;
3401 }
3402 }
3403 }
3404}
3405
3406/*
3407 * mrsas_wait_for_outstanding: Wait for outstanding commands
3408 * input: Adapter Context.

--- 150 unchanged lines hidden (view full) ---

3559 else
3560 memcpy(sc->ctrl_info, sc->ctlr_info_mem, sizeof(struct mrsas_ctrl_info));
3561
3562 do_ocr = 0;
3563 mrsas_update_ext_vd_details(sc);
3564
3565 sc->use_seqnum_jbod_fp =
3566 sc->ctrl_info->adapterOperations3.useSeqNumJbodFP;
3567 sc->support_morethan256jbod =
3568 sc->ctrl_info->adapterOperations4.supportPdMapTargetId;
3569
3342 sc->disableOnlineCtrlReset =
3343 sc->ctrl_info->properties.OnOffProperties.disableOnlineCtrlReset;
3344
3345dcmd_timeout:
3346 mrsas_free_ctlr_info_cmd(sc);
3347
3348 if (do_ocr)
3349 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR;

--- 7 unchanged lines hidden (view full) ---

3357/*
3358 * mrsas_update_ext_vd_details : Update details w.r.t Extended VD
3359 * input:
3360 * sc - Controller's softc
3361*/
3362static void
3363mrsas_update_ext_vd_details(struct mrsas_softc *sc)
3364{
3570 sc->disableOnlineCtrlReset =
3571 sc->ctrl_info->properties.OnOffProperties.disableOnlineCtrlReset;
3572
3573dcmd_timeout:
3574 mrsas_free_ctlr_info_cmd(sc);
3575
3576 if (do_ocr)
3577 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR;

--- 7 unchanged lines hidden (view full) ---

3585/*
3586 * mrsas_update_ext_vd_details : Update details w.r.t Extended VD
3587 * input:
3588 * sc - Controller's softc
3589*/
3590static void
3591mrsas_update_ext_vd_details(struct mrsas_softc *sc)
3592{
3593 u_int32_t ventura_map_sz = 0;
3365 sc->max256vdSupport =
3594 sc->max256vdSupport =
3366 sc->ctrl_info->adapterOperations3.supportMaxExtLDs;
3595 sc->ctrl_info->adapterOperations3.supportMaxExtLDs;
3596
3367 /* Below is additional check to address future FW enhancement */
3368 if (sc->ctrl_info->max_lds > 64)
3369 sc->max256vdSupport = 1;
3370
3371 sc->drv_supported_vd_count = MRSAS_MAX_LD_CHANNELS
3372 * MRSAS_MAX_DEV_PER_CHANNEL;
3373 sc->drv_supported_pd_count = MRSAS_MAX_PD_CHANNELS
3374 * MRSAS_MAX_DEV_PER_CHANNEL;
3375 if (sc->max256vdSupport) {
3376 sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES_EXT;
3377 sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES;
3378 } else {
3379 sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES;
3380 sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES;
3381 }
3382
3597 /* Below is additional check to address future FW enhancement */
3598 if (sc->ctrl_info->max_lds > 64)
3599 sc->max256vdSupport = 1;
3600
3601 sc->drv_supported_vd_count = MRSAS_MAX_LD_CHANNELS
3602 * MRSAS_MAX_DEV_PER_CHANNEL;
3603 sc->drv_supported_pd_count = MRSAS_MAX_PD_CHANNELS
3604 * MRSAS_MAX_DEV_PER_CHANNEL;
3605 if (sc->max256vdSupport) {
3606 sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES_EXT;
3607 sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES;
3608 } else {
3609 sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES;
3610 sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES;
3611 }
3612
3383 sc->old_map_sz = sizeof(MR_FW_RAID_MAP) +
3384 (sizeof(MR_LD_SPAN_MAP) *
3385 (sc->fw_supported_vd_count - 1));
3386 sc->new_map_sz = sizeof(MR_FW_RAID_MAP_EXT);
3387 sc->drv_map_sz = sizeof(MR_DRV_RAID_MAP) +
3388 (sizeof(MR_LD_SPAN_MAP) *
3389 (sc->drv_supported_vd_count - 1));
3613 if (sc->maxRaidMapSize) {
3614 ventura_map_sz = sc->maxRaidMapSize *
3615 MR_MIN_MAP_SIZE;
3616 sc->current_map_sz = ventura_map_sz;
3617 sc->max_map_sz = ventura_map_sz;
3618 } else {
3619 sc->old_map_sz = sizeof(MR_FW_RAID_MAP) +
3620 (sizeof(MR_LD_SPAN_MAP) * (sc->fw_supported_vd_count - 1));
3621 sc->new_map_sz = sizeof(MR_FW_RAID_MAP_EXT);
3622 sc->max_map_sz = max(sc->old_map_sz, sc->new_map_sz);
3623 if (sc->max256vdSupport)
3624 sc->current_map_sz = sc->new_map_sz;
3625 else
3626 sc->current_map_sz = sc->old_map_sz;
3627 }
3390
3628
3391 sc->max_map_sz = max(sc->old_map_sz, sc->new_map_sz);
3392
3393 if (sc->max256vdSupport)
3394 sc->current_map_sz = sc->new_map_sz;
3395 else
3396 sc->current_map_sz = sc->old_map_sz;
3629 sc->drv_map_sz = sizeof(MR_DRV_RAID_MAP_ALL);
3630#if VD_EXT_DEBUG
3631 device_printf(sc->mrsas_dev, "sc->maxRaidMapSize 0x%x \n",
3632 sc->maxRaidMapSize);
3633 device_printf(sc->mrsas_dev,
3634 "new_map_sz = 0x%x, old_map_sz = 0x%x, "
3635 "ventura_map_sz = 0x%x, current_map_sz = 0x%x "
3636 "fusion->drv_map_sz =0x%x, size of driver raid map 0x%lx \n",
3637 sc->new_map_sz, sc->old_map_sz, ventura_map_sz,
3638 sc->current_map_sz, sc->drv_map_sz, sizeof(MR_DRV_RAID_MAP_ALL));
3639#endif
3397}
3398
3399/*
3400 * mrsas_alloc_ctlr_info_cmd: Allocates memory for controller info command
3401 * input: Adapter soft state
3402 *
3403 * Allocates DMAable memory for the controller info internal command.
3404 */

--- 181 unchanged lines hidden (view full) ---

3586 * mrsas_complete_cmd.
3587 */
3588
3589 if (frame_hdr->flags & MFI_FRAME_DONT_POST_IN_REPLY_QUEUE)
3590 mpt_cmd->flags = MFI_FRAME_DONT_POST_IN_REPLY_QUEUE;
3591
3592 io_req = mpt_cmd->io_request;
3593
3640}
3641
3642/*
3643 * mrsas_alloc_ctlr_info_cmd: Allocates memory for controller info command
3644 * input: Adapter soft state
3645 *
3646 * Allocates DMAable memory for the controller info internal command.
3647 */

--- 181 unchanged lines hidden (view full) ---

3829 * mrsas_complete_cmd.
3830 */
3831
3832 if (frame_hdr->flags & MFI_FRAME_DONT_POST_IN_REPLY_QUEUE)
3833 mpt_cmd->flags = MFI_FRAME_DONT_POST_IN_REPLY_QUEUE;
3834
3835 io_req = mpt_cmd->io_request;
3836
3594 if (sc->mrsas_gen3_ctrl) {
3837 if (sc->mrsas_gen3_ctrl || sc->is_ventura) {
3595 pMpi25IeeeSgeChain64_t sgl_ptr_end = (pMpi25IeeeSgeChain64_t)&io_req->SGL;
3596
3597 sgl_ptr_end += sc->max_sge_in_main_msg - 1;
3598 sgl_ptr_end->Flags = 0;
3599 }
3600 mpi25_ieee_chain = (MPI25_IEEE_SGE_CHAIN64 *) & io_req->SGL.IeeeChain;
3601
3602 io_req->Function = MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST;

--- 498 unchanged lines hidden (view full) ---

4101 if (mrsas_issue_dcmd(sc, cmd)) {
4102 device_printf(sc->mrsas_dev,
4103 "Fail to send sync map info command.\n");
4104 return (1);
4105 }
4106 return (retcode);
4107}
4108
3838 pMpi25IeeeSgeChain64_t sgl_ptr_end = (pMpi25IeeeSgeChain64_t)&io_req->SGL;
3839
3840 sgl_ptr_end += sc->max_sge_in_main_msg - 1;
3841 sgl_ptr_end->Flags = 0;
3842 }
3843 mpi25_ieee_chain = (MPI25_IEEE_SGE_CHAIN64 *) & io_req->SGL.IeeeChain;
3844
3845 io_req->Function = MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST;

--- 498 unchanged lines hidden (view full) ---

4344 if (mrsas_issue_dcmd(sc, cmd)) {
4345 device_printf(sc->mrsas_dev,
4346 "Fail to send sync map info command.\n");
4347 return (1);
4348 }
4349 return (retcode);
4350}
4351
4352/* Input: dcmd.opcode - MR_DCMD_PD_GET_INFO
4353 * dcmd.mbox.s[0] - deviceId for this physical drive
4354 * dcmd.sge IN - ptr to returned MR_PD_INFO structure
4355 * Desc: Firmware return the physical drive info structure
4356 *
4357 */
4358static void
4359mrsas_get_pd_info(struct mrsas_softc *sc, u_int16_t device_id)
4360{
4361 int retcode;
4362 u_int8_t do_ocr = 1;
4363 struct mrsas_mfi_cmd *cmd;
4364 struct mrsas_dcmd_frame *dcmd;
4365
4366 cmd = mrsas_get_mfi_cmd(sc);
4367
4368 if (!cmd) {
4369 device_printf(sc->mrsas_dev,
4370 "Cannot alloc for get PD info cmd\n");
4371 return;
4372 }
4373 dcmd = &cmd->frame->dcmd;
4374
4375 memset(sc->pd_info_mem, 0, sizeof(struct mrsas_pd_info));
4376 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE);
4377
4378 dcmd->mbox.s[0] = device_id;
4379 dcmd->cmd = MFI_CMD_DCMD;
4380 dcmd->cmd_status = 0xFF;
4381 dcmd->sge_count = 1;
4382 dcmd->flags = MFI_FRAME_DIR_READ;
4383 dcmd->timeout = 0;
4384 dcmd->pad_0 = 0;
4385 dcmd->data_xfer_len = sizeof(struct mrsas_pd_info);
4386 dcmd->opcode = MR_DCMD_PD_GET_INFO;
4387 dcmd->sgl.sge32[0].phys_addr = (u_int32_t)sc->pd_info_phys_addr;
4388 dcmd->sgl.sge32[0].length = sizeof(struct mrsas_pd_info);
4389
4390 if (!sc->mask_interrupts)
4391 retcode = mrsas_issue_blocked_cmd(sc, cmd);
4392 else
4393 retcode = mrsas_issue_polled(sc, cmd);
4394
4395 if (retcode == ETIMEDOUT)
4396 goto dcmd_timeout;
4397
4398 sc->target_list[device_id].interface_type =
4399 sc->pd_info_mem->state.ddf.pdType.intf;
4400
4401 do_ocr = 0;
4402
4403dcmd_timeout:
4404
4405 if (do_ocr)
4406 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR;
4407
4408 if (!sc->mask_interrupts)
4409 mrsas_release_mfi_cmd(cmd);
4410}
4411
4109/*
4412/*
4413 * mrsas_add_target: Add target ID of system PD/VD to driver's data structure.
4414 * sc: Adapter's soft state
4415 * target_id: Unique target id per controller(managed by driver)
4416 * for system PDs- target ID ranges from 0 to (MRSAS_MAX_PD - 1)
4417 * for VDs- target ID ranges from MRSAS_MAX_PD to MRSAS_MAX_TM_TARGETS
4418 * return: void
4419 * Descripton: This function will be called whenever system PD or VD is created.
4420 */
4421static void mrsas_add_target(struct mrsas_softc *sc,
4422 u_int16_t target_id)
4423{
4424 sc->target_list[target_id].target_id = target_id;
4425
4426 device_printf(sc->mrsas_dev,
4427 "%s created target ID: 0x%x\n",
4428 (target_id < MRSAS_MAX_PD ? "System PD" : "VD"),
4429 (target_id < MRSAS_MAX_PD ? target_id : (target_id - MRSAS_MAX_PD)));
4430 /*
4431 * If interrupts are enabled, then only fire DCMD to get pd_info
4432 * for system PDs
4433 */
4434 if (!sc->mask_interrupts && sc->pd_info_mem &&
4435 (target_id < MRSAS_MAX_PD))
4436 mrsas_get_pd_info(sc, target_id);
4437
4438}
4439
4440/*
4441 * mrsas_remove_target: Remove target ID of system PD/VD from driver's data structure.
4442 * sc: Adapter's soft state
4443 * target_id: Unique target id per controller(managed by driver)
4444 * for system PDs- target ID ranges from 0 to (MRSAS_MAX_PD - 1)
4445 * for VDs- target ID ranges from MRSAS_MAX_PD to MRSAS_MAX_TM_TARGETS
4446 * return: void
4447 * Descripton: This function will be called whenever system PD or VD is deleted
4448 */
4449static void mrsas_remove_target(struct mrsas_softc *sc,
4450 u_int16_t target_id)
4451{
4452 sc->target_list[target_id].target_id = 0xffff;
4453 device_printf(sc->mrsas_dev,
4454 "%s deleted target ID: 0x%x\n",
4455 (target_id < MRSAS_MAX_PD ? "System PD" : "VD"),
4456 (target_id < MRSAS_MAX_PD ? target_id : (target_id - MRSAS_MAX_PD)));
4457}
4458
4459/*
4110 * mrsas_get_pd_list: Returns FW's PD list structure input:
4111 * Adapter soft state
4112 *
4113 * Issues an internal command (DCMD) to get the FW's controller PD list
4114 * structure. This information is mainly used to find out about system
4115 * supported by Firmware.
4116 */
4117static int

--- 59 unchanged lines hidden (view full) ---

4177 memset(sc->local_pd_list, 0,
4178 MRSAS_MAX_PD * sizeof(struct mrsas_pd_list));
4179 for (pd_index = 0; pd_index < pd_list_mem->count; pd_index++) {
4180 sc->local_pd_list[pd_addr->deviceId].tid = pd_addr->deviceId;
4181 sc->local_pd_list[pd_addr->deviceId].driveType =
4182 pd_addr->scsiDevType;
4183 sc->local_pd_list[pd_addr->deviceId].driveState =
4184 MR_PD_STATE_SYSTEM;
4460 * mrsas_get_pd_list: Returns FW's PD list structure input:
4461 * Adapter soft state
4462 *
4463 * Issues an internal command (DCMD) to get the FW's controller PD list
4464 * structure. This information is mainly used to find out about system
4465 * supported by Firmware.
4466 */
4467static int

--- 59 unchanged lines hidden (view full) ---

4527 memset(sc->local_pd_list, 0,
4528 MRSAS_MAX_PD * sizeof(struct mrsas_pd_list));
4529 for (pd_index = 0; pd_index < pd_list_mem->count; pd_index++) {
4530 sc->local_pd_list[pd_addr->deviceId].tid = pd_addr->deviceId;
4531 sc->local_pd_list[pd_addr->deviceId].driveType =
4532 pd_addr->scsiDevType;
4533 sc->local_pd_list[pd_addr->deviceId].driveState =
4534 MR_PD_STATE_SYSTEM;
4535 if (sc->target_list[pd_addr->deviceId].target_id == 0xffff)
4536 mrsas_add_target(sc, pd_addr->deviceId);
4185 pd_addr++;
4186 }
4537 pd_addr++;
4538 }
4539 for (pd_index = 0; pd_index < MRSAS_MAX_PD; pd_index++) {
4540 if ((sc->local_pd_list[pd_index].driveState !=
4541 MR_PD_STATE_SYSTEM) &&
4542 (sc->target_list[pd_index].target_id !=
4543 0xffff)) {
4544 mrsas_remove_target(sc, pd_index);
4545 }
4546 }
4187 /*
4188 * Use mutext/spinlock if pd_list component size increase more than
4189 * 32 bit.
4190 */
4191 memcpy(sc->pd_list, sc->local_pd_list, sizeof(sc->local_pd_list));
4192 do_ocr = 0;
4193 }
4194dcmd_timeout:

--- 15 unchanged lines hidden (view full) ---

4210 *
4211 * Issues an internal command (DCMD) to get the FW's controller PD list
4212 * structure. This information is mainly used to find out about supported by
4213 * the FW.
4214 */
4215static int
4216mrsas_get_ld_list(struct mrsas_softc *sc)
4217{
4547 /*
4548 * Use mutext/spinlock if pd_list component size increase more than
4549 * 32 bit.
4550 */
4551 memcpy(sc->pd_list, sc->local_pd_list, sizeof(sc->local_pd_list));
4552 do_ocr = 0;
4553 }
4554dcmd_timeout:

--- 15 unchanged lines hidden (view full) ---

4570 *
4571 * Issues an internal command (DCMD) to get the FW's controller PD list
4572 * structure. This information is mainly used to find out about supported by
4573 * the FW.
4574 */
4575static int
4576mrsas_get_ld_list(struct mrsas_softc *sc)
4577{
4218 int ld_list_size, retcode = 0, ld_index = 0, ids = 0;
4578 int ld_list_size, retcode = 0, ld_index = 0, ids = 0, drv_tgt_id;
4219 u_int8_t do_ocr = 1;
4220 struct mrsas_mfi_cmd *cmd;
4221 struct mrsas_dcmd_frame *dcmd;
4222 struct MR_LD_LIST *ld_list_mem;
4223 bus_addr_t ld_list_phys_addr = 0;
4224 struct mrsas_tmp_dcmd *tcmd;
4225
4226 cmd = mrsas_get_mfi_cmd(sc);

--- 45 unchanged lines hidden (view full) ---

4272 printf("Number of LDs %d\n", ld_list_mem->ldCount);
4273#endif
4274
4275 /* Get the instance LD list */
4276 if (ld_list_mem->ldCount <= sc->fw_supported_vd_count) {
4277 sc->CurLdCount = ld_list_mem->ldCount;
4278 memset(sc->ld_ids, 0xff, MAX_LOGICAL_DRIVES_EXT);
4279 for (ld_index = 0; ld_index < ld_list_mem->ldCount; ld_index++) {
4579 u_int8_t do_ocr = 1;
4580 struct mrsas_mfi_cmd *cmd;
4581 struct mrsas_dcmd_frame *dcmd;
4582 struct MR_LD_LIST *ld_list_mem;
4583 bus_addr_t ld_list_phys_addr = 0;
4584 struct mrsas_tmp_dcmd *tcmd;
4585
4586 cmd = mrsas_get_mfi_cmd(sc);

--- 45 unchanged lines hidden (view full) ---

4632 printf("Number of LDs %d\n", ld_list_mem->ldCount);
4633#endif
4634
4635 /* Get the instance LD list */
4636 if (ld_list_mem->ldCount <= sc->fw_supported_vd_count) {
4637 sc->CurLdCount = ld_list_mem->ldCount;
4638 memset(sc->ld_ids, 0xff, MAX_LOGICAL_DRIVES_EXT);
4639 for (ld_index = 0; ld_index < ld_list_mem->ldCount; ld_index++) {
4640 ids = ld_list_mem->ldList[ld_index].ref.ld_context.targetId;
4641 drv_tgt_id = ids + MRSAS_MAX_PD;
4280 if (ld_list_mem->ldList[ld_index].state != 0) {
4642 if (ld_list_mem->ldList[ld_index].state != 0) {
4281 ids = ld_list_mem->ldList[ld_index].ref.ld_context.targetId;
4282 sc->ld_ids[ids] = ld_list_mem->ldList[ld_index].ref.ld_context.targetId;
4643 sc->ld_ids[ids] = ld_list_mem->ldList[ld_index].ref.ld_context.targetId;
4644 if (sc->target_list[drv_tgt_id].target_id ==
4645 0xffff)
4646 mrsas_add_target(sc, drv_tgt_id);
4647 } else {
4648 if (sc->target_list[drv_tgt_id].target_id !=
4649 0xffff)
4650 mrsas_remove_target(sc,
4651 drv_tgt_id);
4283 }
4284 }
4652 }
4653 }
4654
4285 do_ocr = 0;
4286 }
4287dcmd_timeout:
4288 mrsas_free_tmp_dcmd(tcmd);
4289 free(tcmd, M_MRSAS);
4290
4291 if (do_ocr)
4292 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR;

--- 309 unchanged lines hidden --- 		4655 do_ocr = 0;
4656 }
4657dcmd_timeout:
4658 mrsas_free_tmp_dcmd(tcmd);
4659 free(tcmd, M_MRSAS);
4660
4661 if (do_ocr)
4662 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR;

--- 309 unchanged lines hidden ---