1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: head/sys/dev/lge/if_lge.c 104094 2002-09-28 17:15:38Z phk $
34 */
35
36/*
37 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
38 * documentation not available, but ask me nicely.
39 *
40 * Written by Bill Paul <william.paul@windriver.com>
41 * Wind River Systems
42 */
43
44/*
45 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
46 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
47 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
48 * are three supported methods for data transfer between host and
49 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
50 * Propulsion Technology (tm) DMA. The latter mechanism is a form
51 * of double buffer DMA where the packet data is copied to a
52 * pre-allocated DMA buffer who's physical address has been loaded
53 * into a table at device initialization time. The rationale is that
54 * the virtual to physical address translation needed for normal
55 * scatter/gather DMA is more expensive than the data copy needed
56 * for double buffering. This may be true in Windows NT and the like,
57 * but it isn't true for us, at least on the x86 arch. This driver
58 * uses the scatter/gather I/O method for both TX and RX.
59 *
60 * The LXT1001 only supports TCP/IP checksum offload on receive.
61 * Also, the VLAN tagging is done using a 16-entry table which allows
62 * the chip to perform hardware filtering based on VLAN tags. Sadly,
63 * our vlan support doesn't currently play well with this kind of
64 * hardware support.
65 *
66 * Special thanks to:
67 * - Jeff James at Intel, for arranging to have the LXT1001 manual
68 * released (at long last)
69 * - Beny Chen at D-Link, for actually sending it to me
70 * - Brad Short and Keith Alexis at SMC, for sending me sample
71 * SMC9462SX and SMC9462TX adapters for testing
72 * - Paul Saab at Y!, for not killing me (though it remains to be seen
73 * if in fact he did me much of a favor)
74 */
75
76#include <sys/param.h>
77#include <sys/systm.h>
78#include <sys/sockio.h>
79#include <sys/mbuf.h>
80#include <sys/malloc.h>
81#include <sys/kernel.h>
82#include <sys/socket.h>
83
84#include <net/if.h>
85#include <net/if_arp.h>
86#include <net/ethernet.h>
87#include <net/if_dl.h>
88#include <net/if_media.h>
89
90#include <net/bpf.h>
91
92#include <vm/vm.h> /* for vtophys */
93#include <vm/pmap.h> /* for vtophys */
94#include <machine/clock.h> /* for DELAY */
95#include <machine/bus_pio.h>
96#include <machine/bus_memio.h>
97#include <machine/bus.h>
98#include <machine/resource.h>
99#include <sys/bus.h>
100#include <sys/rman.h>
101
102#include <dev/mii/mii.h>
103#include <dev/mii/miivar.h>
104
105#include <pci/pcireg.h>
106#include <pci/pcivar.h>
107
108#define LGE_USEIOSPACE
109
110#include <dev/lge/if_lgereg.h>
111
112/* "controller miibus0" required. See GENERIC if you get errors here. */
113#include "miibus_if.h"
114
115#ifndef lint
116static const char rcsid[] =
117 "$FreeBSD: head/sys/dev/lge/if_lge.c 104094 2002-09-28 17:15:38Z phk $";
118#endif
119
120/*
121 * Various supported device vendors/types and their names.
122 */
123static struct lge_type lge_devs[] = {
124 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
125 { 0, 0, NULL }
126};
127
128static int lge_probe(device_t);
129static int lge_attach(device_t);
130static int lge_detach(device_t);
131
132static int lge_alloc_jumbo_mem(struct lge_softc *);
133static void lge_free_jumbo_mem(struct lge_softc *);
134static void *lge_jalloc(struct lge_softc *);
135static void lge_jfree(void *, void *);
136
137static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *);
138static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *);
139static void lge_rxeof(struct lge_softc *, int);
140static void lge_rxeoc(struct lge_softc *);
141static void lge_txeof(struct lge_softc *);
142static void lge_intr(void *);
143static void lge_tick(void *);
144static void lge_start(struct ifnet *);
145static int lge_ioctl(struct ifnet *, u_long, caddr_t);
146static void lge_init(void *);
147static void lge_stop(struct lge_softc *);
148static void lge_watchdog(struct ifnet *);
149static void lge_shutdown(device_t);
150static int lge_ifmedia_upd(struct ifnet *);
151static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
152
153static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *);
154static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int);
155
156static int lge_miibus_readreg(device_t, int, int);
157static int lge_miibus_writereg(device_t, int, int, int);
158static void lge_miibus_statchg(device_t);
159
160static void lge_setmulti(struct lge_softc *);
161static u_int32_t lge_crc(struct lge_softc *, caddr_t);
162static void lge_reset(struct lge_softc *);
163static int lge_list_rx_init(struct lge_softc *);
164static int lge_list_tx_init(struct lge_softc *);
165
166#ifdef LGE_USEIOSPACE
167#define LGE_RES SYS_RES_IOPORT
168#define LGE_RID LGE_PCI_LOIO
169#else
170#define LGE_RES SYS_RES_MEMORY
171#define LGE_RID LGE_PCI_LOMEM
172#endif
173
174static device_method_t lge_methods[] = {
175 /* Device interface */
176 DEVMETHOD(device_probe, lge_probe),
177 DEVMETHOD(device_attach, lge_attach),
178 DEVMETHOD(device_detach, lge_detach),
179 DEVMETHOD(device_shutdown, lge_shutdown),
180
181 /* bus interface */
182 DEVMETHOD(bus_print_child, bus_generic_print_child),
183 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
184
185 /* MII interface */
186 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
187 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
188 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
189
190 { 0, 0 }
191};
192
193static driver_t lge_driver = {
194 "lge",
195 lge_methods,
196 sizeof(struct lge_softc)
197};
198
199static devclass_t lge_devclass;
200
201DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0);
202DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
203
204#define LGE_SETBIT(sc, reg, x) \
205 CSR_WRITE_4(sc, reg, \
206 CSR_READ_4(sc, reg) | (x))
207
208#define LGE_CLRBIT(sc, reg, x) \
209 CSR_WRITE_4(sc, reg, \
210 CSR_READ_4(sc, reg) & ~(x))
211
212#define SIO_SET(x) \
213 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
214
215#define SIO_CLR(x) \
216 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
217
218/*
219 * Read a word of data stored in the EEPROM at address 'addr.'
220 */
221static void
222lge_eeprom_getword(sc, addr, dest)
223 struct lge_softc *sc;
224 int addr;
225 u_int16_t *dest;
226{
227 register int i;
228 u_int32_t val;
229
230 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
231 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
232
233 for (i = 0; i < LGE_TIMEOUT; i++)
234 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
235 break;
236
237 if (i == LGE_TIMEOUT) {
238 printf("lge%d: EEPROM read timed out\n", sc->lge_unit);
239 return;
240 }
241
242 val = CSR_READ_4(sc, LGE_EEDATA);
243
244 if (addr & 1)
245 *dest = (val >> 16) & 0xFFFF;
246 else
247 *dest = val & 0xFFFF;
248
249 return;
250}
251
252/*
253 * Read a sequence of words from the EEPROM.
254 */
255static void
256lge_read_eeprom(sc, dest, off, cnt, swap)
257 struct lge_softc *sc;
258 caddr_t dest;
259 int off;
260 int cnt;
261 int swap;
262{
263 int i;
264 u_int16_t word = 0, *ptr;
265
266 for (i = 0; i < cnt; i++) {
267 lge_eeprom_getword(sc, off + i, &word);
268 ptr = (u_int16_t *)(dest + (i * 2));
269 if (swap)
270 *ptr = ntohs(word);
271 else
272 *ptr = word;
273 }
274
275 return;
276}
277
278static int
279lge_miibus_readreg(dev, phy, reg)
280 device_t dev;
281 int phy, reg;
282{
283 struct lge_softc *sc;
284 int i;
285
286 sc = device_get_softc(dev);
287
288 /*
289 * If we have a non-PCS PHY, pretend that the internal
290 * autoneg stuff at PHY address 0 isn't there so that
291 * the miibus code will find only the GMII PHY.
292 */
293 if (sc->lge_pcs == 0 && phy == 0)
294 return(0);
295
296 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
297
298 for (i = 0; i < LGE_TIMEOUT; i++)
299 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
300 break;
301
302 if (i == LGE_TIMEOUT) {
303 printf("lge%d: PHY read timed out\n", sc->lge_unit);
304 return(0);
305 }
306
307 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
308}
309
310static int
311lge_miibus_writereg(dev, phy, reg, data)
312 device_t dev;
313 int phy, reg, data;
314{
315 struct lge_softc *sc;
316 int i;
317
318 sc = device_get_softc(dev);
319
320 CSR_WRITE_4(sc, LGE_GMIICTL,
321 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
322
323 for (i = 0; i < LGE_TIMEOUT; i++)
324 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
325 break;
326
327 if (i == LGE_TIMEOUT) {
328 printf("lge%d: PHY write timed out\n", sc->lge_unit);
329 return(0);
330 }
331
332 return(0);
333}
334
335static void
336lge_miibus_statchg(dev)
337 device_t dev;
338{
339 struct lge_softc *sc;
340 struct mii_data *mii;
341
342 sc = device_get_softc(dev);
343 mii = device_get_softc(sc->lge_miibus);
344
345 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
346 switch (IFM_SUBTYPE(mii->mii_media_active)) {
347 case IFM_1000_T:
348 case IFM_1000_SX:
349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
350 break;
351 case IFM_100_TX:
352 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
353 break;
354 case IFM_10_T:
355 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
356 break;
357 default:
358 /*
359 * Choose something, even if it's wrong. Clearing
360 * all the bits will hose autoneg on the internal
361 * PHY.
362 */
363 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
364 break;
365 }
366
367 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
368 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
369 } else {
370 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
371 }
372
373 return;
374}
375
376static u_int32_t
377lge_crc(sc, addr)
378 struct lge_softc *sc;
379 caddr_t addr;
380{
381 u_int32_t crc, carry;
382 int i, j;
383 u_int8_t c;
384
385 /* Compute CRC for the address value. */
386 crc = 0xFFFFFFFF; /* initial value */
387
388 for (i = 0; i < 6; i++) {
389 c = *(addr + i);
390 for (j = 0; j < 8; j++) {
391 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
392 crc <<= 1;
393 c >>= 1;
394 if (carry)
395 crc = (crc ^ 0x04c11db6) | carry;
396 }
397 }
398
399 /*
400 * return the filter bit position
401 */
402 return((crc >> 26) & 0x0000003F);
403}
404
405static void
406lge_setmulti(sc)
407 struct lge_softc *sc;
408{
409 struct ifnet *ifp;
410 struct ifmultiaddr *ifma;
411 u_int32_t h = 0, hashes[2] = { 0, 0 };
412
413 ifp = &sc->arpcom.ac_if;
414
415 /* Make sure multicast hash table is enabled. */
416 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
417
418 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
419 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
420 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
421 return;
422 }
423
424 /* first, zot all the existing hash bits */
425 CSR_WRITE_4(sc, LGE_MAR0, 0);
426 CSR_WRITE_4(sc, LGE_MAR1, 0);
427
428 /* now program new ones */
429 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
430 if (ifma->ifma_addr->sa_family != AF_LINK)
431 continue;
432 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
433 if (h < 32)
434 hashes[0] |= (1 << h);
435 else
436 hashes[1] |= (1 << (h - 32));
437 }
438
439 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
440 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
441
442 return;
443}
444
445static void
446lge_reset(sc)
447 struct lge_softc *sc;
448{
449 register int i;
450
451 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
452
453 for (i = 0; i < LGE_TIMEOUT; i++) {
454 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
455 break;
456 }
457
458 if (i == LGE_TIMEOUT)
459 printf("lge%d: reset never completed\n", sc->lge_unit);
460
461 /* Wait a little while for the chip to get its brains in order. */
462 DELAY(1000);
463
464 return;
465}
466
467/*
468 * Probe for a Level 1 chip. Check the PCI vendor and device
469 * IDs against our list and return a device name if we find a match.
470 */
471static int
472lge_probe(dev)
473 device_t dev;
474{
475 struct lge_type *t;
476
477 t = lge_devs;
478
479 while(t->lge_name != NULL) {
480 if ((pci_get_vendor(dev) == t->lge_vid) &&
481 (pci_get_device(dev) == t->lge_did)) {
482 device_set_desc(dev, t->lge_name);
483 return(0);
484 }
485 t++;
486 }
487
488 return(ENXIO);
489}
490
491/*
492 * Attach the interface. Allocate softc structures, do ifmedia
493 * setup and ethernet/BPF attach.
494 */
495static int
496lge_attach(dev)
497 device_t dev;
498{
499 int s;
500 u_char eaddr[ETHER_ADDR_LEN];
501 u_int32_t command;
502 struct lge_softc *sc;
503 struct ifnet *ifp;
504 int unit, error = 0, rid;
505
506 s = splimp();
507
508 sc = device_get_softc(dev);
509 unit = device_get_unit(dev);
510 bzero(sc, sizeof(struct lge_softc));
511
512 /*
513 * Handle power management nonsense.
514 */
515 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
516 u_int32_t iobase, membase, irq;
517
518 /* Save important PCI config data. */
519 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4);
520 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4);
521 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4);
522
523 /* Reset the power state. */
524 printf("lge%d: chip is in D%d power mode "
525 "-- setting to D0\n", unit,
526 pci_get_powerstate(dev));
527 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
528
529 /* Restore PCI config data. */
530 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4);
531 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4);
532 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4);
533 }
534
535 /*
536 * Map control/status registers.
537 */
538 pci_enable_busmaster(dev);
539 pci_enable_io(dev, SYS_RES_IOPORT);
540 pci_enable_io(dev, SYS_RES_MEMORY);
541 command = pci_read_config(dev, PCIR_COMMAND, 4);
542
543#ifdef LGE_USEIOSPACE
544 if (!(command & PCIM_CMD_PORTEN)) {
545 printf("lge%d: failed to enable I/O ports!\n", unit);
546 error = ENXIO;;
547 goto fail;
548 }
549#else
550 if (!(command & PCIM_CMD_MEMEN)) {
551 printf("lge%d: failed to enable memory mapping!\n", unit);
552 error = ENXIO;;
553 goto fail;
554 }
555#endif
556
557 rid = LGE_RID;
558 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid,
559 0, ~0, 1, RF_ACTIVE);
560
561 if (sc->lge_res == NULL) {
562 printf("lge%d: couldn't map ports/memory\n", unit);
563 error = ENXIO;
564 goto fail;
565 }
566
567 sc->lge_btag = rman_get_bustag(sc->lge_res);
568 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
569
570 /* Allocate interrupt */
571 rid = 0;
572 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
573 RF_SHAREABLE | RF_ACTIVE);
574
575 if (sc->lge_irq == NULL) {
576 printf("lge%d: couldn't map interrupt\n", unit);
577 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
578 error = ENXIO;
579 goto fail;
580 }
581
582 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET,
583 lge_intr, sc, &sc->lge_intrhand);
584
585 if (error) {
586 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
587 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
588 printf("lge%d: couldn't set up irq\n", unit);
589 goto fail;
590 }
591
592 /* Reset the adapter. */
593 lge_reset(sc);
594
595 /*
596 * Get station address from the EEPROM.
597 */
598 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
599 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
600 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
601
602 /*
603 * A Level 1 chip was detected. Inform the world.
604 */
605 printf("lge%d: Ethernet address: %6D\n", unit, eaddr, ":");
606
607 sc->lge_unit = unit;
608 callout_handle_init(&sc->lge_stat_ch);
609 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
610
611 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
612 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
613
614 if (sc->lge_ldata == NULL) {
615 printf("lge%d: no memory for list buffers!\n", unit);
616 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
617 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
618 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
619 error = ENXIO;
620 goto fail;
621 }
622 bzero(sc->lge_ldata, sizeof(struct lge_list_data));
623
624 /* Try to allocate memory for jumbo buffers. */
625 if (lge_alloc_jumbo_mem(sc)) {
626 printf("lge%d: jumbo buffer allocation failed\n",
627 sc->lge_unit);
628 contigfree(sc->lge_ldata,
629 sizeof(struct lge_list_data), M_DEVBUF);
630 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
631 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
632 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
633 error = ENXIO;
634 goto fail;
635 }
636
637 ifp = &sc->arpcom.ac_if;
638 ifp->if_softc = sc;
639 ifp->if_unit = unit;
640 ifp->if_name = "lge";
641 ifp->if_mtu = ETHERMTU;
642 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
643 ifp->if_ioctl = lge_ioctl;
644 ifp->if_output = ether_output;
645 ifp->if_start = lge_start;
646 ifp->if_watchdog = lge_watchdog;
647 ifp->if_init = lge_init;
648 ifp->if_baudrate = 1000000000;
649 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1;
650 ifp->if_capabilities = IFCAP_RXCSUM;
651 ifp->if_capenable = ifp->if_capabilities;
652
653 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
654 sc->lge_pcs = 1;
655 else
656 sc->lge_pcs = 0;
657
658 /*
659 * Do MII setup.
660 */
661 if (mii_phy_probe(dev, &sc->lge_miibus,
662 lge_ifmedia_upd, lge_ifmedia_sts)) {
663 printf("lge%d: MII without any PHY!\n", sc->lge_unit);
664 contigfree(sc->lge_ldata,
665 sizeof(struct lge_list_data), M_DEVBUF);
666 lge_free_jumbo_mem(sc);
667 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
668 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
669 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
670 error = ENXIO;
671 goto fail;
672 }
673
674 /*
675 * Call MI attach routine.
676 */
677 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
678 callout_handle_init(&sc->lge_stat_ch);
679
680fail:
681 splx(s);
682 return(error);
683}
684
685static int
686lge_detach(dev)
687 device_t dev;
688{
689 struct lge_softc *sc;
690 struct ifnet *ifp;
691 int s;
692
693 s = splimp();
694
695 sc = device_get_softc(dev);
696 ifp = &sc->arpcom.ac_if;
697
698 lge_reset(sc);
699 lge_stop(sc);
700 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
701
702 bus_generic_detach(dev);
703 device_delete_child(dev, sc->lge_miibus);
704
705 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
706 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
707 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
708
709 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
710 lge_free_jumbo_mem(sc);
711
712 splx(s);
713
714 return(0);
715}
716
717/*
718 * Initialize the transmit descriptors.
719 */
720static int
721lge_list_tx_init(sc)
722 struct lge_softc *sc;
723{
724 struct lge_list_data *ld;
725 struct lge_ring_data *cd;
726 int i;
727
728 cd = &sc->lge_cdata;
729 ld = sc->lge_ldata;
730 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
731 ld->lge_tx_list[i].lge_mbuf = NULL;
732 ld->lge_tx_list[i].lge_ctl = 0;
733 }
734
735 cd->lge_tx_prod = cd->lge_tx_cons = 0;
736
737 return(0);
738}
739
740
741/*
742 * Initialize the RX descriptors and allocate mbufs for them. Note that
743 * we arralge the descriptors in a closed ring, so that the last descriptor
744 * points back to the first.
745 */
746static int
747lge_list_rx_init(sc)
748 struct lge_softc *sc;
749{
750 struct lge_list_data *ld;
751 struct lge_ring_data *cd;
752 int i;
753
754 ld = sc->lge_ldata;
755 cd = &sc->lge_cdata;
756
757 cd->lge_rx_prod = cd->lge_rx_cons = 0;
758
759 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
760
761 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
762 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
763 break;
764 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
765 return(ENOBUFS);
766 }
767
768 /* Clear possible 'rx command queue empty' interrupt. */
769 CSR_READ_4(sc, LGE_ISR);
770
771 return(0);
772}
773
774/*
775 * Initialize an RX descriptor and attach an MBUF cluster.
776 */
777static int
778lge_newbuf(sc, c, m)
779 struct lge_softc *sc;
780 struct lge_rx_desc *c;
781 struct mbuf *m;
782{
783 struct mbuf *m_new = NULL;
784 caddr_t *buf = NULL;
785
786 if (m == NULL) {
787 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
788 if (m_new == NULL) {
789 printf("lge%d: no memory for rx list "
790 "-- packet dropped!\n", sc->lge_unit);
791 return(ENOBUFS);
792 }
793
794 /* Allocate the jumbo buffer */
795 buf = lge_jalloc(sc);
796 if (buf == NULL) {
797#ifdef LGE_VERBOSE
798 printf("lge%d: jumbo allocation failed "
799 "-- packet dropped!\n", sc->lge_unit);
800#endif
801 m_freem(m_new);
802 return(ENOBUFS);
803 }
804 /* Attach the buffer to the mbuf */
805 m_new->m_data = (void *)buf;
806 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
807 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree,
808 (struct lge_softc *)sc, 0, EXT_NET_DRV);
809 } else {
810 m_new = m;
811 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
812 m_new->m_data = m_new->m_ext.ext_buf;
813 }
814
815 /*
816 * Adjust alignment so packet payload begins on a
817 * longword boundary. Mandatory for Alpha, useful on
818 * x86 too.
819 */
820 m_adj(m_new, ETHER_ALIGN);
821
822 c->lge_mbuf = m_new;
823 c->lge_fragptr_hi = 0;
824 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
825 c->lge_fraglen = m_new->m_len;
826 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
827 c->lge_sts = 0;
828
829 /*
830 * Put this buffer in the RX command FIFO. To do this,
831 * we just write the physical address of the descriptor
832 * into the RX descriptor address registers. Note that
833 * there are two registers, one high DWORD and one low
834 * DWORD, which lets us specify a 64-bit address if
835 * desired. We only use a 32-bit address for now.
836 * Writing to the low DWORD register is what actually
837 * causes the command to be issued, so we do that
838 * last.
839 */
840 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
841 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
842
843 return(0);
844}
845
846static int
847lge_alloc_jumbo_mem(sc)
848 struct lge_softc *sc;
849{
850 caddr_t ptr;
851 register int i;
852 struct lge_jpool_entry *entry;
853
854 /* Grab a big chunk o' storage. */
855 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
856 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
857
858 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
859 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit);
860 return(ENOBUFS);
861 }
862
863 SLIST_INIT(&sc->lge_jfree_listhead);
864 SLIST_INIT(&sc->lge_jinuse_listhead);
865
866 /*
867 * Now divide it up into 9K pieces and save the addresses
868 * in an array.
869 */
870 ptr = sc->lge_cdata.lge_jumbo_buf;
871 for (i = 0; i < LGE_JSLOTS; i++) {
872 sc->lge_cdata.lge_jslots[i] = ptr;
873 ptr += LGE_JLEN;
874 entry = malloc(sizeof(struct lge_jpool_entry),
875 M_DEVBUF, M_NOWAIT);
876 if (entry == NULL) {
877 printf("lge%d: no memory for jumbo "
878 "buffer queue!\n", sc->lge_unit);
879 return(ENOBUFS);
880 }
881 entry->slot = i;
882 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
883 entry, jpool_entries);
884 }
885
886 return(0);
887}
888
889static void
890lge_free_jumbo_mem(sc)
891 struct lge_softc *sc;
892{
893 int i;
894 struct lge_jpool_entry *entry;
895
896 for (i = 0; i < LGE_JSLOTS; i++) {
897 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
898 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
899 free(entry, M_DEVBUF);
900 }
901
902 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
903
904 return;
905}
906
907/*
908 * Allocate a jumbo buffer.
909 */
910static void *
911lge_jalloc(sc)
912 struct lge_softc *sc;
913{
914 struct lge_jpool_entry *entry;
915
916 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
917
918 if (entry == NULL) {
919#ifdef LGE_VERBOSE
920 printf("lge%d: no free jumbo buffers\n", sc->lge_unit);
921#endif
922 return(NULL);
923 }
924
925 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
926 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
927 return(sc->lge_cdata.lge_jslots[entry->slot]);
928}
929
930/*
931 * Release a jumbo buffer.
932 */
933static void
934lge_jfree(buf, args)
935 void *buf;
936 void *args;
937{
938 struct lge_softc *sc;
939 int i;
940 struct lge_jpool_entry *entry;
941
942 /* Extract the softc struct pointer. */
943 sc = args;
944
945 if (sc == NULL)
946 panic("lge_jfree: can't find softc pointer!");
947
948 /* calculate the slot this buffer belongs to */
949 i = ((vm_offset_t)buf
950 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
951
952 if ((i < 0) || (i >= LGE_JSLOTS))
953 panic("lge_jfree: asked to free buffer that we don't manage!");
954
955 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
956 if (entry == NULL)
957 panic("lge_jfree: buffer not in use!");
958 entry->slot = i;
959 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
960 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries);
961
962 return;
963}
964
965/*
966 * A frame has been uploaded: pass the resulting mbuf chain up to
967 * the higher level protocols.
968 */
969static void
970lge_rxeof(sc, cnt)
971 struct lge_softc *sc;
972 int cnt;
973{
974 struct ether_header *eh;
975 struct mbuf *m;
976 struct ifnet *ifp;
977 struct lge_rx_desc *cur_rx;
978 int c, i, total_len = 0;
979 u_int32_t rxsts, rxctl;
980
981 ifp = &sc->arpcom.ac_if;
982
983 /* Find out how many frames were processed. */
984 c = cnt;
985 i = sc->lge_cdata.lge_rx_cons;
986
987 /* Suck them in. */
988 while(c) {
989 struct mbuf *m0 = NULL;
990
991 cur_rx = &sc->lge_ldata->lge_rx_list[i];
992 rxctl = cur_rx->lge_ctl;
993 rxsts = cur_rx->lge_sts;
994 m = cur_rx->lge_mbuf;
995 cur_rx->lge_mbuf = NULL;
996 total_len = LGE_RXBYTES(cur_rx);
997 LGE_INC(i, LGE_RX_LIST_CNT);
998 c--;
999
1000 /*
1001 * If an error occurs, update stats, clear the
1002 * status word and leave the mbuf cluster in place:
1003 * it should simply get re-used next time this descriptor
1004 * comes up in the ring.
1005 */
1006 if (rxctl & LGE_RXCTL_ERRMASK) {
1007 ifp->if_ierrors++;
1008 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
1009 continue;
1010 }
1011
1012 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
1013 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN,
1014 ifp, NULL);
1015 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
1016 if (m0 == NULL) {
1017 printf("lge%d: no receive buffers "
1018 "available -- packet dropped!\n",
1019 sc->lge_unit);
1020 ifp->if_ierrors++;
1021 continue;
1022 }
1023 m = m0;
1024 } else {
1025 m->m_pkthdr.rcvif = ifp;
1026 m->m_pkthdr.len = m->m_len = total_len;
1027 }
1028
1029 ifp->if_ipackets++;
1030 eh = mtod(m, struct ether_header *);
1031
1032 /* Remove header from mbuf and pass it on. */
1033 m_adj(m, sizeof(struct ether_header));
1034
1035 /* Do IP checksum checking. */
1036 if (rxsts & LGE_RXSTS_ISIP)
1037 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1038 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
1039 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1040 if ((rxsts & LGE_RXSTS_ISTCP &&
1041 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
1042 (rxsts & LGE_RXSTS_ISUDP &&
1043 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
1044 m->m_pkthdr.csum_flags |=
1045 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1046 m->m_pkthdr.csum_data = 0xffff;
1047 }
1048
1049 ether_input(ifp, eh, m);
1050 }
1051
1052 sc->lge_cdata.lge_rx_cons = i;
1053
1054 return;
1055}
1056
1057static void
1058lge_rxeoc(sc)
1059 struct lge_softc *sc;
1060{
1061 struct ifnet *ifp;
1062
1063 ifp = &sc->arpcom.ac_if;
1064 ifp->if_flags &= ~IFF_RUNNING;
1065 lge_init(sc);
1066 return;
1067}
1068
1069/*
1070 * A frame was downloaded to the chip. It's safe for us to clean up
1071 * the list buffers.
1072 */
1073
1074static void
1075lge_txeof(sc)
1076 struct lge_softc *sc;
1077{
1078 struct lge_tx_desc *cur_tx = NULL;
1079 struct ifnet *ifp;
1080 u_int32_t idx, txdone;
1081
1082 ifp = &sc->arpcom.ac_if;
1083
1084 /* Clear the timeout timer. */
1085 ifp->if_timer = 0;
1086
1087 /*
1088 * Go through our tx list and free mbufs for those
1089 * frames that have been transmitted.
1090 */
1091 idx = sc->lge_cdata.lge_tx_cons;
1092 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1093
1094 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1095 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1096
1097 ifp->if_opackets++;
1098 if (cur_tx->lge_mbuf != NULL) {
1099 m_freem(cur_tx->lge_mbuf);
1100 cur_tx->lge_mbuf = NULL;
1101 }
1102 cur_tx->lge_ctl = 0;
1103
1104 txdone--;
1105 LGE_INC(idx, LGE_TX_LIST_CNT);
1106 ifp->if_timer = 0;
1107 }
1108
1109 sc->lge_cdata.lge_tx_cons = idx;
1110
1111 if (cur_tx != NULL)
1112 ifp->if_flags &= ~IFF_OACTIVE;
1113
1114 return;
1115}
1116
1117static void
1118lge_tick(xsc)
1119 void *xsc;
1120{
1121 struct lge_softc *sc;
1122 struct mii_data *mii;
1123 struct ifnet *ifp;
1124 int s;
1125
1126 s = splimp();
1127
1128 sc = xsc;
1129 ifp = &sc->arpcom.ac_if;
1130
1131 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1132 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1133 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1134 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1135
1136 if (!sc->lge_link) {
1137 mii = device_get_softc(sc->lge_miibus);
1138 mii_tick(mii);
1139 if (mii->mii_media_status & IFM_ACTIVE &&
1140 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1141 sc->lge_link++;
1142 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1143 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
1144 printf("lge%d: gigabit link up\n",
1145 sc->lge_unit);
1146 if (ifp->if_snd.ifq_head != NULL)
1147 lge_start(ifp);
1148 }
1149 }
1150
1151 sc->lge_stat_ch = timeout(lge_tick, sc, hz);
1152
1153 splx(s);
1154
1155 return;
1156}
1157
1158static void
1159lge_intr(arg)
1160 void *arg;
1161{
1162 struct lge_softc *sc;
1163 struct ifnet *ifp;
1164 u_int32_t status;
1165
1166 sc = arg;
1167 ifp = &sc->arpcom.ac_if;
1168
1169 /* Supress unwanted interrupts */
1170 if (!(ifp->if_flags & IFF_UP)) {
1171 lge_stop(sc);
1172 return;
1173 }
1174
1175 for (;;) {
1176 /*
1177 * Reading the ISR register clears all interrupts, and
1178 * clears the 'interrupts enabled' bit in the IMR
1179 * register.
1180 */
1181 status = CSR_READ_4(sc, LGE_ISR);
1182
1183 if ((status & LGE_INTRS) == 0)
1184 break;
1185
1186 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1187 lge_txeof(sc);
1188
1189 if (status & LGE_ISR_RXDMA_DONE)
1190 lge_rxeof(sc, LGE_RX_DMACNT(status));
1191
1192 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1193 lge_rxeoc(sc);
1194
1195 if (status & LGE_ISR_PHY_INTR) {
1196 sc->lge_link = 0;
1197 untimeout(lge_tick, sc, sc->lge_stat_ch);
1198 lge_tick(sc);
1199 }
1200 }
1201
1202 /* Re-enable interrupts. */
1203 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1204
1205 if (ifp->if_snd.ifq_head != NULL)
1206 lge_start(ifp);
1207
1208 return;
1209}
1210
1211/*
1212 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1213 * pointers to the fragment pointers.
1214 */
1215static int
1216lge_encap(sc, m_head, txidx)
1217 struct lge_softc *sc;
1218 struct mbuf *m_head;
1219 u_int32_t *txidx;
1220{
1221 struct lge_frag *f = NULL;
1222 struct lge_tx_desc *cur_tx;
1223 struct mbuf *m;
1224 int frag = 0, tot_len = 0;
1225
1226 /*
1227 * Start packing the mbufs in this chain into
1228 * the fragment pointers. Stop when we run out
1229 * of fragments or hit the end of the mbuf chain.
1230 */
1231 m = m_head;
1232 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1233 frag = 0;
1234
1235 for (m = m_head; m != NULL; m = m->m_next) {
1236 if (m->m_len != 0) {
1237 tot_len += m->m_len;
1238 f = &cur_tx->lge_frags[frag];
1239 f->lge_fraglen = m->m_len;
1240 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1241 f->lge_fragptr_hi = 0;
1242 frag++;
1243 }
1244 }
1245
1246 if (m != NULL)
1247 return(ENOBUFS);
1248
1249 cur_tx->lge_mbuf = m_head;
1250 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1251 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1252
1253 /* Queue for transmit */
1254 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1255
1256 return(0);
1257}
1258
1259/*
1260 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1261 * to the mbuf data regions directly in the transmit lists. We also save a
1262 * copy of the pointers since the transmit list fragment pointers are
1263 * physical addresses.
1264 */
1265
1266static void
1267lge_start(ifp)
1268 struct ifnet *ifp;
1269{
1270 struct lge_softc *sc;
1271 struct mbuf *m_head = NULL;
1272 u_int32_t idx;
1273
1274 sc = ifp->if_softc;
1275
1276 if (!sc->lge_link)
1277 return;
1278
1279 idx = sc->lge_cdata.lge_tx_prod;
1280
1281 if (ifp->if_flags & IFF_OACTIVE)
1282 return;
1283
1284 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1285 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1286 break;
1287
1288 IF_DEQUEUE(&ifp->if_snd, m_head);
1289 if (m_head == NULL)
1290 break;
1291
1292 if (lge_encap(sc, m_head, &idx)) {
1293 IF_PREPEND(&ifp->if_snd, m_head);
1294 ifp->if_flags |= IFF_OACTIVE;
1295 break;
1296 }
1297
1298 /*
1299 * If there's a BPF listener, bounce a copy of this frame
1300 * to him.
1301 */
1302 if (ifp->if_bpf)
1303 bpf_mtap(ifp, m_head);
1304 }
1305
1306 sc->lge_cdata.lge_tx_prod = idx;
1307
1308 /*
1309 * Set a timeout in case the chip goes out to lunch.
1310 */
1311 ifp->if_timer = 5;
1312
1313 return;
1314}
1315
1316static void
1317lge_init(xsc)
1318 void *xsc;
1319{
1320 struct lge_softc *sc = xsc;
1321 struct ifnet *ifp = &sc->arpcom.ac_if;
1322 struct mii_data *mii;
1323 int s;
1324
1325 if (ifp->if_flags & IFF_RUNNING)
1326 return;
1327
1328 s = splimp();
1329
1330 /*
1331 * Cancel pending I/O and free all RX/TX buffers.
1332 */
1333 lge_stop(sc);
1334 lge_reset(sc);
1335
1336 mii = device_get_softc(sc->lge_miibus);
1337
1338 /* Set MAC address */
1339 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1340 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1341
1342 /* Init circular RX list. */
1343 if (lge_list_rx_init(sc) == ENOBUFS) {
1344 printf("lge%d: initialization failed: no "
1345 "memory for rx buffers\n", sc->lge_unit);
1346 lge_stop(sc);
1347 (void)splx(s);
1348 return;
1349 }
1350
1351 /*
1352 * Init tx descriptors.
1353 */
1354 lge_list_tx_init(sc);
1355
1356 /* Set initial value for MODE1 register. */
1357 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1358 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1359 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1360 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1361
1362 /* If we want promiscuous mode, set the allframes bit. */
1363 if (ifp->if_flags & IFF_PROMISC) {
1364 CSR_WRITE_4(sc, LGE_MODE1,
1365 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1366 } else {
1367 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1368 }
1369
1370 /*
1371 * Set the capture broadcast bit to capture broadcast frames.
1372 */
1373 if (ifp->if_flags & IFF_BROADCAST) {
1374 CSR_WRITE_4(sc, LGE_MODE1,
1375 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1376 } else {
1377 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1378 }
1379
1380 /* Packet padding workaround? */
1381 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1382
1383 /* No error frames */
1384 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1385
1386 /* Receive large frames */
1387 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1388
1389 /* Workaround: disable RX/TX flow control */
1390 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1391 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1392
1393 /* Make sure to strip CRC from received frames */
1394 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1395
1396 /* Turn off magic packet mode */
1397 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1398
1399 /* Turn off all VLAN stuff */
1400 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1401 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1402
1403 /* Workarond: FIFO overflow */
1404 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1405 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1406
1407 /*
1408 * Load the multicast filter.
1409 */
1410 lge_setmulti(sc);
1411
1412 /*
1413 * Enable hardware checksum validation for all received IPv4
1414 * packets, do not reject packets with bad checksums.
1415 */
1416 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1417 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1418 LGE_MODE2_RX_ERRCSUM);
1419
1420 /*
1421 * Enable the delivery of PHY interrupts based on
1422 * link/speed/duplex status chalges.
1423 */
1424 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1425
1426 /* Enable receiver and transmitter. */
1427 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1428 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1429
1430 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1431 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1432
1433 /*
1434 * Enable interrupts.
1435 */
1436 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1437 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1438
1439 lge_ifmedia_upd(ifp);
1440
1441 ifp->if_flags |= IFF_RUNNING;
1442 ifp->if_flags &= ~IFF_OACTIVE;
1443
1444 (void)splx(s);
1445
1446 sc->lge_stat_ch = timeout(lge_tick, sc, hz);
1447
1448 return;
1449}
1450
1451/*
1452 * Set media options.
1453 */
1454static int
1455lge_ifmedia_upd(ifp)
1456 struct ifnet *ifp;
1457{
1458 struct lge_softc *sc;
1459 struct mii_data *mii;
1460
1461 sc = ifp->if_softc;
1462
1463 mii = device_get_softc(sc->lge_miibus);
1464 sc->lge_link = 0;
1465 if (mii->mii_instance) {
1466 struct mii_softc *miisc;
1467 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1468 miisc = LIST_NEXT(miisc, mii_list))
1469 mii_phy_reset(miisc);
1470 }
1471 mii_mediachg(mii);
1472
1473 return(0);
1474}
1475
1476/*
1477 * Report current media status.
1478 */
1479static void
1480lge_ifmedia_sts(ifp, ifmr)
1481 struct ifnet *ifp;
1482 struct ifmediareq *ifmr;
1483{
1484 struct lge_softc *sc;
1485 struct mii_data *mii;
1486
1487 sc = ifp->if_softc;
1488
1489 mii = device_get_softc(sc->lge_miibus);
1490 mii_pollstat(mii);
1491 ifmr->ifm_active = mii->mii_media_active;
1492 ifmr->ifm_status = mii->mii_media_status;
1493
1494 return;
1495}
1496
1497static int
1498lge_ioctl(ifp, command, data)
1499 struct ifnet *ifp;
1500 u_long command;
1501 caddr_t data;
1502{
1503 struct lge_softc *sc = ifp->if_softc;
1504 struct ifreq *ifr = (struct ifreq *) data;
1505 struct mii_data *mii;
1506 int s, error = 0;
1507
1508 s = splimp();
1509
1510 switch(command) {
1511 case SIOCSIFADDR:
1512 case SIOCGIFADDR:
1513 error = ether_ioctl(ifp, command, data);
1514 break;
1515 case SIOCSIFMTU:
1516 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1517 error = EINVAL;
1518 else
1519 ifp->if_mtu = ifr->ifr_mtu;
1520 break;
1521 case SIOCSIFFLAGS:
1522 if (ifp->if_flags & IFF_UP) {
1523 if (ifp->if_flags & IFF_RUNNING &&
1524 ifp->if_flags & IFF_PROMISC &&
1525 !(sc->lge_if_flags & IFF_PROMISC)) {
1526 CSR_WRITE_4(sc, LGE_MODE1,
1527 LGE_MODE1_SETRST_CTL1|
1528 LGE_MODE1_RX_PROMISC);
1529 } else if (ifp->if_flags & IFF_RUNNING &&
1530 !(ifp->if_flags & IFF_PROMISC) &&
1531 sc->lge_if_flags & IFF_PROMISC) {
1532 CSR_WRITE_4(sc, LGE_MODE1,
1533 LGE_MODE1_RX_PROMISC);
1534 } else {
1535 ifp->if_flags &= ~IFF_RUNNING;
1536 lge_init(sc);
1537 }
1538 } else {
1539 if (ifp->if_flags & IFF_RUNNING)
1540 lge_stop(sc);
1541 }
1542 sc->lge_if_flags = ifp->if_flags;
1543 error = 0;
1544 break;
1545 case SIOCADDMULTI:
1546 case SIOCDELMULTI:
1547 lge_setmulti(sc);
1548 error = 0;
1549 break;
1550 case SIOCGIFMEDIA:
1551 case SIOCSIFMEDIA:
1552 mii = device_get_softc(sc->lge_miibus);
1553 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1554 break;
1555 default:
1556 error = EINVAL;
1557 break;
1558 }
1559
1560 (void)splx(s);
1561
1562 return(error);
1563}
1564
1565static void
1566lge_watchdog(ifp)
1567 struct ifnet *ifp;
1568{
1569 struct lge_softc *sc;
1570
1571 sc = ifp->if_softc;
1572
1573 ifp->if_oerrors++;
1574 printf("lge%d: watchdog timeout\n", sc->lge_unit);
1575
1576 lge_stop(sc);
1577 lge_reset(sc);
1578 ifp->if_flags &= ~IFF_RUNNING;
1579 lge_init(sc);
1580
1581 if (ifp->if_snd.ifq_head != NULL)
1582 lge_start(ifp);
1583
1584 return;
1585}
1586
1587/*
1588 * Stop the adapter and free any mbufs allocated to the
1589 * RX and TX lists.
1590 */
1591static void
1592lge_stop(sc)
1593 struct lge_softc *sc;
1594{
1595 register int i;
1596 struct ifnet *ifp;
1597
1598 ifp = &sc->arpcom.ac_if;
1599 ifp->if_timer = 0;
1600 untimeout(lge_tick, sc, sc->lge_stat_ch);
1601 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1602
1603 /* Disable receiver and transmitter. */
1604 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1605 sc->lge_link = 0;
1606
1607 /*
1608 * Free data in the RX lists.
1609 */
1610 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1611 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1612 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1613 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1614 }
1615 }
1616 bzero((char *)&sc->lge_ldata->lge_rx_list,
1617 sizeof(sc->lge_ldata->lge_rx_list));
1618
1619 /*
1620 * Free the TX list buffers.
1621 */
1622 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1623 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1624 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1625 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1626 }
1627 }
1628
1629 bzero((char *)&sc->lge_ldata->lge_tx_list,
1630 sizeof(sc->lge_ldata->lge_tx_list));
1631
1632 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1633
1634 return;
1635}
1636
1637/*
1638 * Stop all chip I/O so that the kernel's probe routines don't
1639 * get confused by errant DMAs when rebooting.
1640 */
1641static void
1642lge_shutdown(dev)
1643 device_t dev;
1644{
1645 struct lge_softc *sc;
1646
1647 sc = device_get_softc(dev);
1648
1649 lge_reset(sc);
1650 lge_stop(sc);
1651
1652 return;
1653}
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: head/sys/dev/lge/if_lge.c 104094 2002-09-28 17:15:38Z phk $
34 */
35
36/*
37 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
38 * documentation not available, but ask me nicely.
39 *
40 * Written by Bill Paul <william.paul@windriver.com>
41 * Wind River Systems
42 */
43
44/*
45 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
46 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
47 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
48 * are three supported methods for data transfer between host and
49 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
50 * Propulsion Technology (tm) DMA. The latter mechanism is a form
51 * of double buffer DMA where the packet data is copied to a
52 * pre-allocated DMA buffer who's physical address has been loaded
53 * into a table at device initialization time. The rationale is that
54 * the virtual to physical address translation needed for normal
55 * scatter/gather DMA is more expensive than the data copy needed
56 * for double buffering. This may be true in Windows NT and the like,
57 * but it isn't true for us, at least on the x86 arch. This driver
58 * uses the scatter/gather I/O method for both TX and RX.
59 *
60 * The LXT1001 only supports TCP/IP checksum offload on receive.
61 * Also, the VLAN tagging is done using a 16-entry table which allows
62 * the chip to perform hardware filtering based on VLAN tags. Sadly,
63 * our vlan support doesn't currently play well with this kind of
64 * hardware support.
65 *
66 * Special thanks to:
67 * - Jeff James at Intel, for arranging to have the LXT1001 manual
68 * released (at long last)
69 * - Beny Chen at D-Link, for actually sending it to me
70 * - Brad Short and Keith Alexis at SMC, for sending me sample
71 * SMC9462SX and SMC9462TX adapters for testing
72 * - Paul Saab at Y!, for not killing me (though it remains to be seen
73 * if in fact he did me much of a favor)
74 */
75
76#include <sys/param.h>
77#include <sys/systm.h>
78#include <sys/sockio.h>
79#include <sys/mbuf.h>
80#include <sys/malloc.h>
81#include <sys/kernel.h>
82#include <sys/socket.h>
83
84#include <net/if.h>
85#include <net/if_arp.h>
86#include <net/ethernet.h>
87#include <net/if_dl.h>
88#include <net/if_media.h>
89
90#include <net/bpf.h>
91
92#include <vm/vm.h> /* for vtophys */
93#include <vm/pmap.h> /* for vtophys */
94#include <machine/clock.h> /* for DELAY */
95#include <machine/bus_pio.h>
96#include <machine/bus_memio.h>
97#include <machine/bus.h>
98#include <machine/resource.h>
99#include <sys/bus.h>
100#include <sys/rman.h>
101
102#include <dev/mii/mii.h>
103#include <dev/mii/miivar.h>
104
105#include <pci/pcireg.h>
106#include <pci/pcivar.h>
107
108#define LGE_USEIOSPACE
109
110#include <dev/lge/if_lgereg.h>
111
112/* "controller miibus0" required. See GENERIC if you get errors here. */
113#include "miibus_if.h"
114
115#ifndef lint
116static const char rcsid[] =
117 "$FreeBSD: head/sys/dev/lge/if_lge.c 104094 2002-09-28 17:15:38Z phk $";
118#endif
119
120/*
121 * Various supported device vendors/types and their names.
122 */
123static struct lge_type lge_devs[] = {
124 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
125 { 0, 0, NULL }
126};
127
128static int lge_probe(device_t);
129static int lge_attach(device_t);
130static int lge_detach(device_t);
131
132static int lge_alloc_jumbo_mem(struct lge_softc *);
133static void lge_free_jumbo_mem(struct lge_softc *);
134static void *lge_jalloc(struct lge_softc *);
135static void lge_jfree(void *, void *);
136
137static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *);
138static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *);
139static void lge_rxeof(struct lge_softc *, int);
140static void lge_rxeoc(struct lge_softc *);
141static void lge_txeof(struct lge_softc *);
142static void lge_intr(void *);
143static void lge_tick(void *);
144static void lge_start(struct ifnet *);
145static int lge_ioctl(struct ifnet *, u_long, caddr_t);
146static void lge_init(void *);
147static void lge_stop(struct lge_softc *);
148static void lge_watchdog(struct ifnet *);
149static void lge_shutdown(device_t);
150static int lge_ifmedia_upd(struct ifnet *);
151static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
152
153static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *);
154static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int);
155
156static int lge_miibus_readreg(device_t, int, int);
157static int lge_miibus_writereg(device_t, int, int, int);
158static void lge_miibus_statchg(device_t);
159
160static void lge_setmulti(struct lge_softc *);
161static u_int32_t lge_crc(struct lge_softc *, caddr_t);
162static void lge_reset(struct lge_softc *);
163static int lge_list_rx_init(struct lge_softc *);
164static int lge_list_tx_init(struct lge_softc *);
165
166#ifdef LGE_USEIOSPACE
167#define LGE_RES SYS_RES_IOPORT
168#define LGE_RID LGE_PCI_LOIO
169#else
170#define LGE_RES SYS_RES_MEMORY
171#define LGE_RID LGE_PCI_LOMEM
172#endif
173
174static device_method_t lge_methods[] = {
175 /* Device interface */
176 DEVMETHOD(device_probe, lge_probe),
177 DEVMETHOD(device_attach, lge_attach),
178 DEVMETHOD(device_detach, lge_detach),
179 DEVMETHOD(device_shutdown, lge_shutdown),
180
181 /* bus interface */
182 DEVMETHOD(bus_print_child, bus_generic_print_child),
183 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
184
185 /* MII interface */
186 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
187 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
188 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
189
190 { 0, 0 }
191};
192
193static driver_t lge_driver = {
194 "lge",
195 lge_methods,
196 sizeof(struct lge_softc)
197};
198
199static devclass_t lge_devclass;
200
201DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0);
202DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
203
204#define LGE_SETBIT(sc, reg, x) \
205 CSR_WRITE_4(sc, reg, \
206 CSR_READ_4(sc, reg) | (x))
207
208#define LGE_CLRBIT(sc, reg, x) \
209 CSR_WRITE_4(sc, reg, \
210 CSR_READ_4(sc, reg) & ~(x))
211
212#define SIO_SET(x) \
213 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
214
215#define SIO_CLR(x) \
216 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
217
218/*
219 * Read a word of data stored in the EEPROM at address 'addr.'
220 */
221static void
222lge_eeprom_getword(sc, addr, dest)
223 struct lge_softc *sc;
224 int addr;
225 u_int16_t *dest;
226{
227 register int i;
228 u_int32_t val;
229
230 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
231 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
232
233 for (i = 0; i < LGE_TIMEOUT; i++)
234 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
235 break;
236
237 if (i == LGE_TIMEOUT) {
238 printf("lge%d: EEPROM read timed out\n", sc->lge_unit);
239 return;
240 }
241
242 val = CSR_READ_4(sc, LGE_EEDATA);
243
244 if (addr & 1)
245 *dest = (val >> 16) & 0xFFFF;
246 else
247 *dest = val & 0xFFFF;
248
249 return;
250}
251
252/*
253 * Read a sequence of words from the EEPROM.
254 */
255static void
256lge_read_eeprom(sc, dest, off, cnt, swap)
257 struct lge_softc *sc;
258 caddr_t dest;
259 int off;
260 int cnt;
261 int swap;
262{
263 int i;
264 u_int16_t word = 0, *ptr;
265
266 for (i = 0; i < cnt; i++) {
267 lge_eeprom_getword(sc, off + i, &word);
268 ptr = (u_int16_t *)(dest + (i * 2));
269 if (swap)
270 *ptr = ntohs(word);
271 else
272 *ptr = word;
273 }
274
275 return;
276}
277
278static int
279lge_miibus_readreg(dev, phy, reg)
280 device_t dev;
281 int phy, reg;
282{
283 struct lge_softc *sc;
284 int i;
285
286 sc = device_get_softc(dev);
287
288 /*
289 * If we have a non-PCS PHY, pretend that the internal
290 * autoneg stuff at PHY address 0 isn't there so that
291 * the miibus code will find only the GMII PHY.
292 */
293 if (sc->lge_pcs == 0 && phy == 0)
294 return(0);
295
296 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
297
298 for (i = 0; i < LGE_TIMEOUT; i++)
299 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
300 break;
301
302 if (i == LGE_TIMEOUT) {
303 printf("lge%d: PHY read timed out\n", sc->lge_unit);
304 return(0);
305 }
306
307 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
308}
309
310static int
311lge_miibus_writereg(dev, phy, reg, data)
312 device_t dev;
313 int phy, reg, data;
314{
315 struct lge_softc *sc;
316 int i;
317
318 sc = device_get_softc(dev);
319
320 CSR_WRITE_4(sc, LGE_GMIICTL,
321 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
322
323 for (i = 0; i < LGE_TIMEOUT; i++)
324 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
325 break;
326
327 if (i == LGE_TIMEOUT) {
328 printf("lge%d: PHY write timed out\n", sc->lge_unit);
329 return(0);
330 }
331
332 return(0);
333}
334
335static void
336lge_miibus_statchg(dev)
337 device_t dev;
338{
339 struct lge_softc *sc;
340 struct mii_data *mii;
341
342 sc = device_get_softc(dev);
343 mii = device_get_softc(sc->lge_miibus);
344
345 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
346 switch (IFM_SUBTYPE(mii->mii_media_active)) {
347 case IFM_1000_T:
348 case IFM_1000_SX:
349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
350 break;
351 case IFM_100_TX:
352 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
353 break;
354 case IFM_10_T:
355 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
356 break;
357 default:
358 /*
359 * Choose something, even if it's wrong. Clearing
360 * all the bits will hose autoneg on the internal
361 * PHY.
362 */
363 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
364 break;
365 }
366
367 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
368 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
369 } else {
370 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
371 }
372
373 return;
374}
375
376static u_int32_t
377lge_crc(sc, addr)
378 struct lge_softc *sc;
379 caddr_t addr;
380{
381 u_int32_t crc, carry;
382 int i, j;
383 u_int8_t c;
384
385 /* Compute CRC for the address value. */
386 crc = 0xFFFFFFFF; /* initial value */
387
388 for (i = 0; i < 6; i++) {
389 c = *(addr + i);
390 for (j = 0; j < 8; j++) {
391 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
392 crc <<= 1;
393 c >>= 1;
394 if (carry)
395 crc = (crc ^ 0x04c11db6) | carry;
396 }
397 }
398
399 /*
400 * return the filter bit position
401 */
402 return((crc >> 26) & 0x0000003F);
403}
404
405static void
406lge_setmulti(sc)
407 struct lge_softc *sc;
408{
409 struct ifnet *ifp;
410 struct ifmultiaddr *ifma;
411 u_int32_t h = 0, hashes[2] = { 0, 0 };
412
413 ifp = &sc->arpcom.ac_if;
414
415 /* Make sure multicast hash table is enabled. */
416 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
417
418 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
419 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
420 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
421 return;
422 }
423
424 /* first, zot all the existing hash bits */
425 CSR_WRITE_4(sc, LGE_MAR0, 0);
426 CSR_WRITE_4(sc, LGE_MAR1, 0);
427
428 /* now program new ones */
429 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
430 if (ifma->ifma_addr->sa_family != AF_LINK)
431 continue;
432 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
433 if (h < 32)
434 hashes[0] |= (1 << h);
435 else
436 hashes[1] |= (1 << (h - 32));
437 }
438
439 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
440 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
441
442 return;
443}
444
445static void
446lge_reset(sc)
447 struct lge_softc *sc;
448{
449 register int i;
450
451 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
452
453 for (i = 0; i < LGE_TIMEOUT; i++) {
454 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
455 break;
456 }
457
458 if (i == LGE_TIMEOUT)
459 printf("lge%d: reset never completed\n", sc->lge_unit);
460
461 /* Wait a little while for the chip to get its brains in order. */
462 DELAY(1000);
463
464 return;
465}
466
467/*
468 * Probe for a Level 1 chip. Check the PCI vendor and device
469 * IDs against our list and return a device name if we find a match.
470 */
471static int
472lge_probe(dev)
473 device_t dev;
474{
475 struct lge_type *t;
476
477 t = lge_devs;
478
479 while(t->lge_name != NULL) {
480 if ((pci_get_vendor(dev) == t->lge_vid) &&
481 (pci_get_device(dev) == t->lge_did)) {
482 device_set_desc(dev, t->lge_name);
483 return(0);
484 }
485 t++;
486 }
487
488 return(ENXIO);
489}
490
491/*
492 * Attach the interface. Allocate softc structures, do ifmedia
493 * setup and ethernet/BPF attach.
494 */
495static int
496lge_attach(dev)
497 device_t dev;
498{
499 int s;
500 u_char eaddr[ETHER_ADDR_LEN];
501 u_int32_t command;
502 struct lge_softc *sc;
503 struct ifnet *ifp;
504 int unit, error = 0, rid;
505
506 s = splimp();
507
508 sc = device_get_softc(dev);
509 unit = device_get_unit(dev);
510 bzero(sc, sizeof(struct lge_softc));
511
512 /*
513 * Handle power management nonsense.
514 */
515 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
516 u_int32_t iobase, membase, irq;
517
518 /* Save important PCI config data. */
519 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4);
520 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4);
521 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4);
522
523 /* Reset the power state. */
524 printf("lge%d: chip is in D%d power mode "
525 "-- setting to D0\n", unit,
526 pci_get_powerstate(dev));
527 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
528
529 /* Restore PCI config data. */
530 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4);
531 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4);
532 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4);
533 }
534
535 /*
536 * Map control/status registers.
537 */
538 pci_enable_busmaster(dev);
539 pci_enable_io(dev, SYS_RES_IOPORT);
540 pci_enable_io(dev, SYS_RES_MEMORY);
541 command = pci_read_config(dev, PCIR_COMMAND, 4);
542
543#ifdef LGE_USEIOSPACE
544 if (!(command & PCIM_CMD_PORTEN)) {
545 printf("lge%d: failed to enable I/O ports!\n", unit);
546 error = ENXIO;;
547 goto fail;
548 }
549#else
550 if (!(command & PCIM_CMD_MEMEN)) {
551 printf("lge%d: failed to enable memory mapping!\n", unit);
552 error = ENXIO;;
553 goto fail;
554 }
555#endif
556
557 rid = LGE_RID;
558 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid,
559 0, ~0, 1, RF_ACTIVE);
560
561 if (sc->lge_res == NULL) {
562 printf("lge%d: couldn't map ports/memory\n", unit);
563 error = ENXIO;
564 goto fail;
565 }
566
567 sc->lge_btag = rman_get_bustag(sc->lge_res);
568 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
569
570 /* Allocate interrupt */
571 rid = 0;
572 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
573 RF_SHAREABLE | RF_ACTIVE);
574
575 if (sc->lge_irq == NULL) {
576 printf("lge%d: couldn't map interrupt\n", unit);
577 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
578 error = ENXIO;
579 goto fail;
580 }
581
582 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET,
583 lge_intr, sc, &sc->lge_intrhand);
584
585 if (error) {
586 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
587 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
588 printf("lge%d: couldn't set up irq\n", unit);
589 goto fail;
590 }
591
592 /* Reset the adapter. */
593 lge_reset(sc);
594
595 /*
596 * Get station address from the EEPROM.
597 */
598 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
599 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
600 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
601
602 /*
603 * A Level 1 chip was detected. Inform the world.
604 */
605 printf("lge%d: Ethernet address: %6D\n", unit, eaddr, ":");
606
607 sc->lge_unit = unit;
608 callout_handle_init(&sc->lge_stat_ch);
609 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
610
611 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
612 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
613
614 if (sc->lge_ldata == NULL) {
615 printf("lge%d: no memory for list buffers!\n", unit);
616 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
617 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
618 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
619 error = ENXIO;
620 goto fail;
621 }
622 bzero(sc->lge_ldata, sizeof(struct lge_list_data));
623
624 /* Try to allocate memory for jumbo buffers. */
625 if (lge_alloc_jumbo_mem(sc)) {
626 printf("lge%d: jumbo buffer allocation failed\n",
627 sc->lge_unit);
628 contigfree(sc->lge_ldata,
629 sizeof(struct lge_list_data), M_DEVBUF);
630 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
631 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
632 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
633 error = ENXIO;
634 goto fail;
635 }
636
637 ifp = &sc->arpcom.ac_if;
638 ifp->if_softc = sc;
639 ifp->if_unit = unit;
640 ifp->if_name = "lge";
641 ifp->if_mtu = ETHERMTU;
642 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
643 ifp->if_ioctl = lge_ioctl;
644 ifp->if_output = ether_output;
645 ifp->if_start = lge_start;
646 ifp->if_watchdog = lge_watchdog;
647 ifp->if_init = lge_init;
648 ifp->if_baudrate = 1000000000;
649 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1;
650 ifp->if_capabilities = IFCAP_RXCSUM;
651 ifp->if_capenable = ifp->if_capabilities;
652
653 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
654 sc->lge_pcs = 1;
655 else
656 sc->lge_pcs = 0;
657
658 /*
659 * Do MII setup.
660 */
661 if (mii_phy_probe(dev, &sc->lge_miibus,
662 lge_ifmedia_upd, lge_ifmedia_sts)) {
663 printf("lge%d: MII without any PHY!\n", sc->lge_unit);
664 contigfree(sc->lge_ldata,
665 sizeof(struct lge_list_data), M_DEVBUF);
666 lge_free_jumbo_mem(sc);
667 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
668 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
669 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
670 error = ENXIO;
671 goto fail;
672 }
673
674 /*
675 * Call MI attach routine.
676 */
677 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
678 callout_handle_init(&sc->lge_stat_ch);
679
680fail:
681 splx(s);
682 return(error);
683}
684
685static int
686lge_detach(dev)
687 device_t dev;
688{
689 struct lge_softc *sc;
690 struct ifnet *ifp;
691 int s;
692
693 s = splimp();
694
695 sc = device_get_softc(dev);
696 ifp = &sc->arpcom.ac_if;
697
698 lge_reset(sc);
699 lge_stop(sc);
700 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
701
702 bus_generic_detach(dev);
703 device_delete_child(dev, sc->lge_miibus);
704
705 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
706 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
707 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
708
709 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
710 lge_free_jumbo_mem(sc);
711
712 splx(s);
713
714 return(0);
715}
716
717/*
718 * Initialize the transmit descriptors.
719 */
720static int
721lge_list_tx_init(sc)
722 struct lge_softc *sc;
723{
724 struct lge_list_data *ld;
725 struct lge_ring_data *cd;
726 int i;
727
728 cd = &sc->lge_cdata;
729 ld = sc->lge_ldata;
730 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
731 ld->lge_tx_list[i].lge_mbuf = NULL;
732 ld->lge_tx_list[i].lge_ctl = 0;
733 }
734
735 cd->lge_tx_prod = cd->lge_tx_cons = 0;
736
737 return(0);
738}
739
740
741/*
742 * Initialize the RX descriptors and allocate mbufs for them. Note that
743 * we arralge the descriptors in a closed ring, so that the last descriptor
744 * points back to the first.
745 */
746static int
747lge_list_rx_init(sc)
748 struct lge_softc *sc;
749{
750 struct lge_list_data *ld;
751 struct lge_ring_data *cd;
752 int i;
753
754 ld = sc->lge_ldata;
755 cd = &sc->lge_cdata;
756
757 cd->lge_rx_prod = cd->lge_rx_cons = 0;
758
759 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
760
761 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
762 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
763 break;
764 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
765 return(ENOBUFS);
766 }
767
768 /* Clear possible 'rx command queue empty' interrupt. */
769 CSR_READ_4(sc, LGE_ISR);
770
771 return(0);
772}
773
774/*
775 * Initialize an RX descriptor and attach an MBUF cluster.
776 */
777static int
778lge_newbuf(sc, c, m)
779 struct lge_softc *sc;
780 struct lge_rx_desc *c;
781 struct mbuf *m;
782{
783 struct mbuf *m_new = NULL;
784 caddr_t *buf = NULL;
785
786 if (m == NULL) {
787 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
788 if (m_new == NULL) {
789 printf("lge%d: no memory for rx list "
790 "-- packet dropped!\n", sc->lge_unit);
791 return(ENOBUFS);
792 }
793
794 /* Allocate the jumbo buffer */
795 buf = lge_jalloc(sc);
796 if (buf == NULL) {
797#ifdef LGE_VERBOSE
798 printf("lge%d: jumbo allocation failed "
799 "-- packet dropped!\n", sc->lge_unit);
800#endif
801 m_freem(m_new);
802 return(ENOBUFS);
803 }
804 /* Attach the buffer to the mbuf */
805 m_new->m_data = (void *)buf;
806 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
807 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree,
808 (struct lge_softc *)sc, 0, EXT_NET_DRV);
809 } else {
810 m_new = m;
811 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
812 m_new->m_data = m_new->m_ext.ext_buf;
813 }
814
815 /*
816 * Adjust alignment so packet payload begins on a
817 * longword boundary. Mandatory for Alpha, useful on
818 * x86 too.
819 */
820 m_adj(m_new, ETHER_ALIGN);
821
822 c->lge_mbuf = m_new;
823 c->lge_fragptr_hi = 0;
824 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
825 c->lge_fraglen = m_new->m_len;
826 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
827 c->lge_sts = 0;
828
829 /*
830 * Put this buffer in the RX command FIFO. To do this,
831 * we just write the physical address of the descriptor
832 * into the RX descriptor address registers. Note that
833 * there are two registers, one high DWORD and one low
834 * DWORD, which lets us specify a 64-bit address if
835 * desired. We only use a 32-bit address for now.
836 * Writing to the low DWORD register is what actually
837 * causes the command to be issued, so we do that
838 * last.
839 */
840 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
841 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
842
843 return(0);
844}
845
846static int
847lge_alloc_jumbo_mem(sc)
848 struct lge_softc *sc;
849{
850 caddr_t ptr;
851 register int i;
852 struct lge_jpool_entry *entry;
853
854 /* Grab a big chunk o' storage. */
855 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
856 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
857
858 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
859 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit);
860 return(ENOBUFS);
861 }
862
863 SLIST_INIT(&sc->lge_jfree_listhead);
864 SLIST_INIT(&sc->lge_jinuse_listhead);
865
866 /*
867 * Now divide it up into 9K pieces and save the addresses
868 * in an array.
869 */
870 ptr = sc->lge_cdata.lge_jumbo_buf;
871 for (i = 0; i < LGE_JSLOTS; i++) {
872 sc->lge_cdata.lge_jslots[i] = ptr;
873 ptr += LGE_JLEN;
874 entry = malloc(sizeof(struct lge_jpool_entry),
875 M_DEVBUF, M_NOWAIT);
876 if (entry == NULL) {
877 printf("lge%d: no memory for jumbo "
878 "buffer queue!\n", sc->lge_unit);
879 return(ENOBUFS);
880 }
881 entry->slot = i;
882 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
883 entry, jpool_entries);
884 }
885
886 return(0);
887}
888
889static void
890lge_free_jumbo_mem(sc)
891 struct lge_softc *sc;
892{
893 int i;
894 struct lge_jpool_entry *entry;
895
896 for (i = 0; i < LGE_JSLOTS; i++) {
897 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
898 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
899 free(entry, M_DEVBUF);
900 }
901
902 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
903
904 return;
905}
906
907/*
908 * Allocate a jumbo buffer.
909 */
910static void *
911lge_jalloc(sc)
912 struct lge_softc *sc;
913{
914 struct lge_jpool_entry *entry;
915
916 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
917
918 if (entry == NULL) {
919#ifdef LGE_VERBOSE
920 printf("lge%d: no free jumbo buffers\n", sc->lge_unit);
921#endif
922 return(NULL);
923 }
924
925 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
926 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
927 return(sc->lge_cdata.lge_jslots[entry->slot]);
928}
929
930/*
931 * Release a jumbo buffer.
932 */
933static void
934lge_jfree(buf, args)
935 void *buf;
936 void *args;
937{
938 struct lge_softc *sc;
939 int i;
940 struct lge_jpool_entry *entry;
941
942 /* Extract the softc struct pointer. */
943 sc = args;
944
945 if (sc == NULL)
946 panic("lge_jfree: can't find softc pointer!");
947
948 /* calculate the slot this buffer belongs to */
949 i = ((vm_offset_t)buf
950 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
951
952 if ((i < 0) || (i >= LGE_JSLOTS))
953 panic("lge_jfree: asked to free buffer that we don't manage!");
954
955 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
956 if (entry == NULL)
957 panic("lge_jfree: buffer not in use!");
958 entry->slot = i;
959 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
960 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries);
961
962 return;
963}
964
965/*
966 * A frame has been uploaded: pass the resulting mbuf chain up to
967 * the higher level protocols.
968 */
969static void
970lge_rxeof(sc, cnt)
971 struct lge_softc *sc;
972 int cnt;
973{
974 struct ether_header *eh;
975 struct mbuf *m;
976 struct ifnet *ifp;
977 struct lge_rx_desc *cur_rx;
978 int c, i, total_len = 0;
979 u_int32_t rxsts, rxctl;
980
981 ifp = &sc->arpcom.ac_if;
982
983 /* Find out how many frames were processed. */
984 c = cnt;
985 i = sc->lge_cdata.lge_rx_cons;
986
987 /* Suck them in. */
988 while(c) {
989 struct mbuf *m0 = NULL;
990
991 cur_rx = &sc->lge_ldata->lge_rx_list[i];
992 rxctl = cur_rx->lge_ctl;
993 rxsts = cur_rx->lge_sts;
994 m = cur_rx->lge_mbuf;
995 cur_rx->lge_mbuf = NULL;
996 total_len = LGE_RXBYTES(cur_rx);
997 LGE_INC(i, LGE_RX_LIST_CNT);
998 c--;
999
1000 /*
1001 * If an error occurs, update stats, clear the
1002 * status word and leave the mbuf cluster in place:
1003 * it should simply get re-used next time this descriptor
1004 * comes up in the ring.
1005 */
1006 if (rxctl & LGE_RXCTL_ERRMASK) {
1007 ifp->if_ierrors++;
1008 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
1009 continue;
1010 }
1011
1012 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
1013 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN,
1014 ifp, NULL);
1015 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
1016 if (m0 == NULL) {
1017 printf("lge%d: no receive buffers "
1018 "available -- packet dropped!\n",
1019 sc->lge_unit);
1020 ifp->if_ierrors++;
1021 continue;
1022 }
1023 m = m0;
1024 } else {
1025 m->m_pkthdr.rcvif = ifp;
1026 m->m_pkthdr.len = m->m_len = total_len;
1027 }
1028
1029 ifp->if_ipackets++;
1030 eh = mtod(m, struct ether_header *);
1031
1032 /* Remove header from mbuf and pass it on. */
1033 m_adj(m, sizeof(struct ether_header));
1034
1035 /* Do IP checksum checking. */
1036 if (rxsts & LGE_RXSTS_ISIP)
1037 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1038 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
1039 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1040 if ((rxsts & LGE_RXSTS_ISTCP &&
1041 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
1042 (rxsts & LGE_RXSTS_ISUDP &&
1043 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
1044 m->m_pkthdr.csum_flags |=
1045 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1046 m->m_pkthdr.csum_data = 0xffff;
1047 }
1048
1049 ether_input(ifp, eh, m);
1050 }
1051
1052 sc->lge_cdata.lge_rx_cons = i;
1053
1054 return;
1055}
1056
1057static void
1058lge_rxeoc(sc)
1059 struct lge_softc *sc;
1060{
1061 struct ifnet *ifp;
1062
1063 ifp = &sc->arpcom.ac_if;
1064 ifp->if_flags &= ~IFF_RUNNING;
1065 lge_init(sc);
1066 return;
1067}
1068
1069/*
1070 * A frame was downloaded to the chip. It's safe for us to clean up
1071 * the list buffers.
1072 */
1073
1074static void
1075lge_txeof(sc)
1076 struct lge_softc *sc;
1077{
1078 struct lge_tx_desc *cur_tx = NULL;
1079 struct ifnet *ifp;
1080 u_int32_t idx, txdone;
1081
1082 ifp = &sc->arpcom.ac_if;
1083
1084 /* Clear the timeout timer. */
1085 ifp->if_timer = 0;
1086
1087 /*
1088 * Go through our tx list and free mbufs for those
1089 * frames that have been transmitted.
1090 */
1091 idx = sc->lge_cdata.lge_tx_cons;
1092 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1093
1094 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1095 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1096
1097 ifp->if_opackets++;
1098 if (cur_tx->lge_mbuf != NULL) {
1099 m_freem(cur_tx->lge_mbuf);
1100 cur_tx->lge_mbuf = NULL;
1101 }
1102 cur_tx->lge_ctl = 0;
1103
1104 txdone--;
1105 LGE_INC(idx, LGE_TX_LIST_CNT);
1106 ifp->if_timer = 0;
1107 }
1108
1109 sc->lge_cdata.lge_tx_cons = idx;
1110
1111 if (cur_tx != NULL)
1112 ifp->if_flags &= ~IFF_OACTIVE;
1113
1114 return;
1115}
1116
1117static void
1118lge_tick(xsc)
1119 void *xsc;
1120{
1121 struct lge_softc *sc;
1122 struct mii_data *mii;
1123 struct ifnet *ifp;
1124 int s;
1125
1126 s = splimp();
1127
1128 sc = xsc;
1129 ifp = &sc->arpcom.ac_if;
1130
1131 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1132 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1133 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1134 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1135
1136 if (!sc->lge_link) {
1137 mii = device_get_softc(sc->lge_miibus);
1138 mii_tick(mii);
1139 if (mii->mii_media_status & IFM_ACTIVE &&
1140 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1141 sc->lge_link++;
1142 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1143 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
1144 printf("lge%d: gigabit link up\n",
1145 sc->lge_unit);
1146 if (ifp->if_snd.ifq_head != NULL)
1147 lge_start(ifp);
1148 }
1149 }
1150
1151 sc->lge_stat_ch = timeout(lge_tick, sc, hz);
1152
1153 splx(s);
1154
1155 return;
1156}
1157
1158static void
1159lge_intr(arg)
1160 void *arg;
1161{
1162 struct lge_softc *sc;
1163 struct ifnet *ifp;
1164 u_int32_t status;
1165
1166 sc = arg;
1167 ifp = &sc->arpcom.ac_if;
1168
1169 /* Supress unwanted interrupts */
1170 if (!(ifp->if_flags & IFF_UP)) {
1171 lge_stop(sc);
1172 return;
1173 }
1174
1175 for (;;) {
1176 /*
1177 * Reading the ISR register clears all interrupts, and
1178 * clears the 'interrupts enabled' bit in the IMR
1179 * register.
1180 */
1181 status = CSR_READ_4(sc, LGE_ISR);
1182
1183 if ((status & LGE_INTRS) == 0)
1184 break;
1185
1186 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1187 lge_txeof(sc);
1188
1189 if (status & LGE_ISR_RXDMA_DONE)
1190 lge_rxeof(sc, LGE_RX_DMACNT(status));
1191
1192 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1193 lge_rxeoc(sc);
1194
1195 if (status & LGE_ISR_PHY_INTR) {
1196 sc->lge_link = 0;
1197 untimeout(lge_tick, sc, sc->lge_stat_ch);
1198 lge_tick(sc);
1199 }
1200 }
1201
1202 /* Re-enable interrupts. */
1203 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1204
1205 if (ifp->if_snd.ifq_head != NULL)
1206 lge_start(ifp);
1207
1208 return;
1209}
1210
1211/*
1212 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1213 * pointers to the fragment pointers.
1214 */
1215static int
1216lge_encap(sc, m_head, txidx)
1217 struct lge_softc *sc;
1218 struct mbuf *m_head;
1219 u_int32_t *txidx;
1220{
1221 struct lge_frag *f = NULL;
1222 struct lge_tx_desc *cur_tx;
1223 struct mbuf *m;
1224 int frag = 0, tot_len = 0;
1225
1226 /*
1227 * Start packing the mbufs in this chain into
1228 * the fragment pointers. Stop when we run out
1229 * of fragments or hit the end of the mbuf chain.
1230 */
1231 m = m_head;
1232 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1233 frag = 0;
1234
1235 for (m = m_head; m != NULL; m = m->m_next) {
1236 if (m->m_len != 0) {
1237 tot_len += m->m_len;
1238 f = &cur_tx->lge_frags[frag];
1239 f->lge_fraglen = m->m_len;
1240 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1241 f->lge_fragptr_hi = 0;
1242 frag++;
1243 }
1244 }
1245
1246 if (m != NULL)
1247 return(ENOBUFS);
1248
1249 cur_tx->lge_mbuf = m_head;
1250 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1251 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1252
1253 /* Queue for transmit */
1254 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1255
1256 return(0);
1257}
1258
1259/*
1260 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1261 * to the mbuf data regions directly in the transmit lists. We also save a
1262 * copy of the pointers since the transmit list fragment pointers are
1263 * physical addresses.
1264 */
1265
1266static void
1267lge_start(ifp)
1268 struct ifnet *ifp;
1269{
1270 struct lge_softc *sc;
1271 struct mbuf *m_head = NULL;
1272 u_int32_t idx;
1273
1274 sc = ifp->if_softc;
1275
1276 if (!sc->lge_link)
1277 return;
1278
1279 idx = sc->lge_cdata.lge_tx_prod;
1280
1281 if (ifp->if_flags & IFF_OACTIVE)
1282 return;
1283
1284 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1285 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1286 break;
1287
1288 IF_DEQUEUE(&ifp->if_snd, m_head);
1289 if (m_head == NULL)
1290 break;
1291
1292 if (lge_encap(sc, m_head, &idx)) {
1293 IF_PREPEND(&ifp->if_snd, m_head);
1294 ifp->if_flags |= IFF_OACTIVE;
1295 break;
1296 }
1297
1298 /*
1299 * If there's a BPF listener, bounce a copy of this frame
1300 * to him.
1301 */
1302 if (ifp->if_bpf)
1303 bpf_mtap(ifp, m_head);
1304 }
1305
1306 sc->lge_cdata.lge_tx_prod = idx;
1307
1308 /*
1309 * Set a timeout in case the chip goes out to lunch.
1310 */
1311 ifp->if_timer = 5;
1312
1313 return;
1314}
1315
1316static void
1317lge_init(xsc)
1318 void *xsc;
1319{
1320 struct lge_softc *sc = xsc;
1321 struct ifnet *ifp = &sc->arpcom.ac_if;
1322 struct mii_data *mii;
1323 int s;
1324
1325 if (ifp->if_flags & IFF_RUNNING)
1326 return;
1327
1328 s = splimp();
1329
1330 /*
1331 * Cancel pending I/O and free all RX/TX buffers.
1332 */
1333 lge_stop(sc);
1334 lge_reset(sc);
1335
1336 mii = device_get_softc(sc->lge_miibus);
1337
1338 /* Set MAC address */
1339 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1340 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1341
1342 /* Init circular RX list. */
1343 if (lge_list_rx_init(sc) == ENOBUFS) {
1344 printf("lge%d: initialization failed: no "
1345 "memory for rx buffers\n", sc->lge_unit);
1346 lge_stop(sc);
1347 (void)splx(s);
1348 return;
1349 }
1350
1351 /*
1352 * Init tx descriptors.
1353 */
1354 lge_list_tx_init(sc);
1355
1356 /* Set initial value for MODE1 register. */
1357 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1358 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1359 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1360 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1361
1362 /* If we want promiscuous mode, set the allframes bit. */
1363 if (ifp->if_flags & IFF_PROMISC) {
1364 CSR_WRITE_4(sc, LGE_MODE1,
1365 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1366 } else {
1367 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1368 }
1369
1370 /*
1371 * Set the capture broadcast bit to capture broadcast frames.
1372 */
1373 if (ifp->if_flags & IFF_BROADCAST) {
1374 CSR_WRITE_4(sc, LGE_MODE1,
1375 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1376 } else {
1377 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1378 }
1379
1380 /* Packet padding workaround? */
1381 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1382
1383 /* No error frames */
1384 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1385
1386 /* Receive large frames */
1387 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1388
1389 /* Workaround: disable RX/TX flow control */
1390 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1391 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1392
1393 /* Make sure to strip CRC from received frames */
1394 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1395
1396 /* Turn off magic packet mode */
1397 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1398
1399 /* Turn off all VLAN stuff */
1400 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1401 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1402
1403 /* Workarond: FIFO overflow */
1404 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1405 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1406
1407 /*
1408 * Load the multicast filter.
1409 */
1410 lge_setmulti(sc);
1411
1412 /*
1413 * Enable hardware checksum validation for all received IPv4
1414 * packets, do not reject packets with bad checksums.
1415 */
1416 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1417 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1418 LGE_MODE2_RX_ERRCSUM);
1419
1420 /*
1421 * Enable the delivery of PHY interrupts based on
1422 * link/speed/duplex status chalges.
1423 */
1424 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1425
1426 /* Enable receiver and transmitter. */
1427 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1428 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1429
1430 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1431 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1432
1433 /*
1434 * Enable interrupts.
1435 */
1436 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1437 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1438
1439 lge_ifmedia_upd(ifp);
1440
1441 ifp->if_flags |= IFF_RUNNING;
1442 ifp->if_flags &= ~IFF_OACTIVE;
1443
1444 (void)splx(s);
1445
1446 sc->lge_stat_ch = timeout(lge_tick, sc, hz);
1447
1448 return;
1449}
1450
1451/*
1452 * Set media options.
1453 */
1454static int
1455lge_ifmedia_upd(ifp)
1456 struct ifnet *ifp;
1457{
1458 struct lge_softc *sc;
1459 struct mii_data *mii;
1460
1461 sc = ifp->if_softc;
1462
1463 mii = device_get_softc(sc->lge_miibus);
1464 sc->lge_link = 0;
1465 if (mii->mii_instance) {
1466 struct mii_softc *miisc;
1467 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1468 miisc = LIST_NEXT(miisc, mii_list))
1469 mii_phy_reset(miisc);
1470 }
1471 mii_mediachg(mii);
1472
1473 return(0);
1474}
1475
1476/*
1477 * Report current media status.
1478 */
1479static void
1480lge_ifmedia_sts(ifp, ifmr)
1481 struct ifnet *ifp;
1482 struct ifmediareq *ifmr;
1483{
1484 struct lge_softc *sc;
1485 struct mii_data *mii;
1486
1487 sc = ifp->if_softc;
1488
1489 mii = device_get_softc(sc->lge_miibus);
1490 mii_pollstat(mii);
1491 ifmr->ifm_active = mii->mii_media_active;
1492 ifmr->ifm_status = mii->mii_media_status;
1493
1494 return;
1495}
1496
1497static int
1498lge_ioctl(ifp, command, data)
1499 struct ifnet *ifp;
1500 u_long command;
1501 caddr_t data;
1502{
1503 struct lge_softc *sc = ifp->if_softc;
1504 struct ifreq *ifr = (struct ifreq *) data;
1505 struct mii_data *mii;
1506 int s, error = 0;
1507
1508 s = splimp();
1509
1510 switch(command) {
1511 case SIOCSIFADDR:
1512 case SIOCGIFADDR:
1513 error = ether_ioctl(ifp, command, data);
1514 break;
1515 case SIOCSIFMTU:
1516 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1517 error = EINVAL;
1518 else
1519 ifp->if_mtu = ifr->ifr_mtu;
1520 break;
1521 case SIOCSIFFLAGS:
1522 if (ifp->if_flags & IFF_UP) {
1523 if (ifp->if_flags & IFF_RUNNING &&
1524 ifp->if_flags & IFF_PROMISC &&
1525 !(sc->lge_if_flags & IFF_PROMISC)) {
1526 CSR_WRITE_4(sc, LGE_MODE1,
1527 LGE_MODE1_SETRST_CTL1|
1528 LGE_MODE1_RX_PROMISC);
1529 } else if (ifp->if_flags & IFF_RUNNING &&
1530 !(ifp->if_flags & IFF_PROMISC) &&
1531 sc->lge_if_flags & IFF_PROMISC) {
1532 CSR_WRITE_4(sc, LGE_MODE1,
1533 LGE_MODE1_RX_PROMISC);
1534 } else {
1535 ifp->if_flags &= ~IFF_RUNNING;
1536 lge_init(sc);
1537 }
1538 } else {
1539 if (ifp->if_flags & IFF_RUNNING)
1540 lge_stop(sc);
1541 }
1542 sc->lge_if_flags = ifp->if_flags;
1543 error = 0;
1544 break;
1545 case SIOCADDMULTI:
1546 case SIOCDELMULTI:
1547 lge_setmulti(sc);
1548 error = 0;
1549 break;
1550 case SIOCGIFMEDIA:
1551 case SIOCSIFMEDIA:
1552 mii = device_get_softc(sc->lge_miibus);
1553 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1554 break;
1555 default:
1556 error = EINVAL;
1557 break;
1558 }
1559
1560 (void)splx(s);
1561
1562 return(error);
1563}
1564
1565static void
1566lge_watchdog(ifp)
1567 struct ifnet *ifp;
1568{
1569 struct lge_softc *sc;
1570
1571 sc = ifp->if_softc;
1572
1573 ifp->if_oerrors++;
1574 printf("lge%d: watchdog timeout\n", sc->lge_unit);
1575
1576 lge_stop(sc);
1577 lge_reset(sc);
1578 ifp->if_flags &= ~IFF_RUNNING;
1579 lge_init(sc);
1580
1581 if (ifp->if_snd.ifq_head != NULL)
1582 lge_start(ifp);
1583
1584 return;
1585}
1586
1587/*
1588 * Stop the adapter and free any mbufs allocated to the
1589 * RX and TX lists.
1590 */
1591static void
1592lge_stop(sc)
1593 struct lge_softc *sc;
1594{
1595 register int i;
1596 struct ifnet *ifp;
1597
1598 ifp = &sc->arpcom.ac_if;
1599 ifp->if_timer = 0;
1600 untimeout(lge_tick, sc, sc->lge_stat_ch);
1601 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1602
1603 /* Disable receiver and transmitter. */
1604 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1605 sc->lge_link = 0;
1606
1607 /*
1608 * Free data in the RX lists.
1609 */
1610 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1611 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1612 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1613 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1614 }
1615 }
1616 bzero((char *)&sc->lge_ldata->lge_rx_list,
1617 sizeof(sc->lge_ldata->lge_rx_list));
1618
1619 /*
1620 * Free the TX list buffers.
1621 */
1622 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1623 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1624 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1625 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1626 }
1627 }
1628
1629 bzero((char *)&sc->lge_ldata->lge_tx_list,
1630 sizeof(sc->lge_ldata->lge_tx_list));
1631
1632 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1633
1634 return;
1635}
1636
1637/*
1638 * Stop all chip I/O so that the kernel's probe routines don't
1639 * get confused by errant DMAs when rebooting.
1640 */
1641static void
1642lge_shutdown(dev)
1643 device_t dev;
1644{
1645 struct lge_softc *sc;
1646
1647 sc = device_get_softc(dev);
1648
1649 lge_reset(sc);
1650 lge_stop(sc);
1651
1652 return;
1653}