3c3
< Copyright (c) 2001-2015, Intel Corporation
---
> Copyright (c) 2001-2017, Intel Corporation
5,6c5,6
<
< Redistribution and use in source and binary forms, with or without
---
>
> Redistribution and use in source and binary forms, with or without
8,9c8,9
<
< 1. Redistributions of source code must retain the above copyright notice,
---
>
> 1. Redistributions of source code must retain the above copyright notice,
11,13c11,13
<
< 2. Redistributions in binary form must reproduce the above copyright
< notice, this list of conditions and the following disclaimer in the
---
>
> 2. Redistributions in binary form must reproduce the above copyright
> notice, this list of conditions and the following disclaimer in the
15,17c15,17
<
< 3. Neither the name of the Intel Corporation nor the names of its
< contributors may be used to endorse or promote products derived from
---
>
> 3. Neither the name of the Intel Corporation nor the names of its
> contributors may be used to endorse or promote products derived from
19c19
<
---
>
21,28c21,28
< AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
< IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
< ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
< LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
< CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
< SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
< INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
< CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
---
> AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
> LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
> CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
> SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
> INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
> CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33c33
< /*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_x550.c 295093 2016-01-31 15:14:23Z smh $*/
---
> /*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_x550.c 320897 2017-07-11 21:25:07Z erj $*/
42a43,45
> static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
> static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
> static s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
63c66
< mac->ops.setup_eee = ixgbe_setup_eee_X550;
---
> mac->ops.setup_eee = NULL;
84c87,95
< if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
---
> /* Manageability interface */
> mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
> switch (hw->device_id) {
> case IXGBE_DEV_ID_X550EM_X_1G_T:
> hw->mac.ops.led_on = NULL;
> hw->mac.ops.led_off = NULL;
> break;
> case IXGBE_DEV_ID_X550EM_X_10G_T:
> case IXGBE_DEV_ID_X550EM_A_10G_T:
86a98,100
> break;
> default:
> break;
101c115
< return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
---
> return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
114c128
< return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
---
> return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
325a340,431
> * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
> * @hw: pointer to hardware structure
> * @reg_addr: 32 bit address of PHY register to read
> * @dev_type: always unused
> * @phy_data: Pointer to read data from PHY register
> */
> static s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
> u32 dev_type, u16 *phy_data)
> {
> u32 i, data, command;
> UNREFERENCED_1PARAMETER(dev_type);
>
> /* Setup and write the read command */
> command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
> (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
> IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
> IXGBE_MSCA_MDI_COMMAND;
>
> IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
>
> /* Check every 10 usec to see if the access completed.
> * The MDI Command bit will clear when the operation is
> * complete
> */
> for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
> usec_delay(10);
>
> command = IXGBE_READ_REG(hw, IXGBE_MSCA);
> if (!(command & IXGBE_MSCA_MDI_COMMAND))
> break;
> }
>
> if (command & IXGBE_MSCA_MDI_COMMAND) {
> ERROR_REPORT1(IXGBE_ERROR_POLLING,
> "PHY read command did not complete.\n");
> return IXGBE_ERR_PHY;
> }
>
> /* Read operation is complete. Get the data from MSRWD */
> data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
> data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
> *phy_data = (u16)data;
>
> return IXGBE_SUCCESS;
> }
>
> /**
> * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
> * @hw: pointer to hardware structure
> * @reg_addr: 32 bit PHY register to write
> * @dev_type: always unused
> * @phy_data: Data to write to the PHY register
> */
> static s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
> u32 dev_type, u16 phy_data)
> {
> u32 i, command;
> UNREFERENCED_1PARAMETER(dev_type);
>
> /* Put the data in the MDI single read and write data register*/
> IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
>
> /* Setup and write the write command */
> command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
> (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
> IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
> IXGBE_MSCA_MDI_COMMAND;
>
> IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
>
> /* Check every 10 usec to see if the access completed.
> * The MDI Command bit will clear when the operation is
> * complete
> */
> for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
> usec_delay(10);
>
> command = IXGBE_READ_REG(hw, IXGBE_MSCA);
> if (!(command & IXGBE_MSCA_MDI_COMMAND))
> break;
> }
>
> if (command & IXGBE_MSCA_MDI_COMMAND) {
> ERROR_REPORT1(IXGBE_ERROR_POLLING,
> "PHY write cmd didn't complete\n");
> return IXGBE_ERR_PHY;
> }
>
> return IXGBE_SUCCESS;
> }
>
> /**
332a439,442
> hw->mac.ops.set_lan_id(hw);
>
> ixgbe_read_mng_if_sel_x550em(hw);
>
333a444,445
> case IXGBE_DEV_ID_X550EM_A_SFP:
> return ixgbe_identify_module_generic(hw);
336d447
< hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
338a450
> /* Fallthrough */
339a452
> case IXGBE_DEV_ID_X550EM_A_SFP_N:
344a458,460
> case IXGBE_DEV_ID_X550EM_X_XFI:
> hw->phy.type = ixgbe_phy_x550em_xfi;
> break;
345a462,463
> case IXGBE_DEV_ID_X550EM_A_KR:
> case IXGBE_DEV_ID_X550EM_A_KR_L:
348c466
< case IXGBE_DEV_ID_X550EM_X_1G_T:
---
> case IXGBE_DEV_ID_X550EM_A_10G_T:
350a469,483
> case IXGBE_DEV_ID_X550EM_X_1G_T:
> hw->phy.type = ixgbe_phy_ext_1g_t;
> hw->phy.ops.read_reg = NULL;
> hw->phy.ops.write_reg = NULL;
> break;
> case IXGBE_DEV_ID_X550EM_A_1G_T:
> case IXGBE_DEV_ID_X550EM_A_1G_T_L:
> hw->phy.type = ixgbe_phy_fw;
> hw->phy.ops.read_reg = NULL;
> hw->phy.ops.write_reg = NULL;
> if (hw->bus.lan_id)
> hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
> else
> hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
> break;
356a490,616
> /**
> * ixgbe_fw_phy_activity - Perform an activity on a PHY
> * @hw: pointer to hardware structure
> * @activity: activity to perform
> * @data: Pointer to 4 32-bit words of data
> */
> s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
> u32 (*data)[FW_PHY_ACT_DATA_COUNT])
> {
> union {
> struct ixgbe_hic_phy_activity_req cmd;
> struct ixgbe_hic_phy_activity_resp rsp;
> } hic;
> u16 retries = FW_PHY_ACT_RETRIES;
> s32 rc;
> u16 i;
>
> do {
> memset(&hic, 0, sizeof(hic));
> hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
> hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
> hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
> hic.cmd.port_number = hw->bus.lan_id;
> hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
> for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
> hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
>
> rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
> sizeof(hic.cmd),
> IXGBE_HI_COMMAND_TIMEOUT,
> TRUE);
> if (rc != IXGBE_SUCCESS)
> return rc;
> if (hic.rsp.hdr.cmd_or_resp.ret_status ==
> FW_CEM_RESP_STATUS_SUCCESS) {
> for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
> (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
> return IXGBE_SUCCESS;
> }
> usec_delay(20);
> --retries;
> } while (retries > 0);
>
> return IXGBE_ERR_HOST_INTERFACE_COMMAND;
> }
>
> static const struct {
> u16 fw_speed;
> ixgbe_link_speed phy_speed;
> } ixgbe_fw_map[] = {
> { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
> { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
> { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
> { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
> { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
> { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
> };
>
> /**
> * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
> * @hw: pointer to hardware structure
> *
> * Returns error code
> */
> static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
> {
> u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
> u16 phy_speeds;
> u16 phy_id_lo;
> s32 rc;
> u16 i;
>
> rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
> if (rc)
> return rc;
>
> hw->phy.speeds_supported = 0;
> phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
> for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
> if (phy_speeds & ixgbe_fw_map[i].fw_speed)
> hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
> }
> if (!hw->phy.autoneg_advertised)
> hw->phy.autoneg_advertised = hw->phy.speeds_supported;
>
> hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
> phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
> hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
> hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
> if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
> return IXGBE_ERR_PHY_ADDR_INVALID;
> return IXGBE_SUCCESS;
> }
>
> /**
> * ixgbe_identify_phy_fw - Get PHY type based on firmware command
> * @hw: pointer to hardware structure
> *
> * Returns error code
> */
> static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
> {
> if (hw->bus.lan_id)
> hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
> else
> hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
>
> hw->phy.type = ixgbe_phy_fw;
> hw->phy.ops.read_reg = NULL;
> hw->phy.ops.write_reg = NULL;
> return ixgbe_get_phy_id_fw(hw);
> }
>
> /**
> * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
> * @hw: pointer to hardware structure
> *
> * Returns error code
> */
> s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
> {
> u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
>
> setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
> return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
> }
>
371a632,693
> * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
> * @hw: pointer to the hardware structure
> * @addr: I2C bus address to read from
> * @reg: I2C device register to read from
> * @val: pointer to location to receive read value
> *
> * Returns an error code on error.
> **/
> static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
> u16 reg, u16 *val)
> {
> return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE);
> }
>
> /**
> * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
> * @hw: pointer to the hardware structure
> * @addr: I2C bus address to read from
> * @reg: I2C device register to read from
> * @val: pointer to location to receive read value
> *
> * Returns an error code on error.
> **/
> static s32
> ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
> u16 reg, u16 *val)
> {
> return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE);
> }
>
> /**
> * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
> * @hw: pointer to the hardware structure
> * @addr: I2C bus address to write to
> * @reg: I2C device register to write to
> * @val: value to write
> *
> * Returns an error code on error.
> **/
> static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
> u8 addr, u16 reg, u16 val)
> {
> return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE);
> }
>
> /**
> * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
> * @hw: pointer to the hardware structure
> * @addr: I2C bus address to write to
> * @reg: I2C device register to write to
> * @val: value to write
> *
> * Returns an error code on error.
> **/
> static s32
> ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
> u8 addr, u16 reg, u16 val)
> {
> return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE);
> }
>
> /**
395a718,723
> /* Bypass not supported in x550EM */
> mac->ops.bypass_rw = NULL;
> mac->ops.bypass_valid_rd = NULL;
> mac->ops.bypass_set = NULL;
> mac->ops.bypass_rd_eep = NULL;
>
414,417d741
< if (hw->mac.type == ixgbe_mac_X550EM_x) {
< mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
< mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
< }
431,436d754
< mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
< mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
<
< if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
< mac->ops.setup_eee = NULL;
<
439c757,773
< phy->ops.identify = ixgbe_identify_phy_x550em;
---
> switch (hw->device_id) {
> case IXGBE_DEV_ID_X550EM_A_1G_T:
> case IXGBE_DEV_ID_X550EM_A_1G_T_L:
> mac->ops.setup_fc = NULL;
> phy->ops.identify = ixgbe_identify_phy_fw;
> phy->ops.set_phy_power = NULL;
> phy->ops.get_firmware_version = NULL;
> break;
> case IXGBE_DEV_ID_X550EM_X_1G_T:
> mac->ops.setup_fc = NULL;
> phy->ops.identify = ixgbe_identify_phy_x550em;
> phy->ops.set_phy_power = NULL;
> break;
> default:
> phy->ops.identify = ixgbe_identify_phy_x550em;
> }
>
457a792,973
> * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
> * @hw: pointer to hardware structure
> */
> static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
> {
> u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
> s32 rc;
> u16 i;
>
> if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
> return 0;
>
> if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
> ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
> "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
> return IXGBE_ERR_INVALID_LINK_SETTINGS;
> }
>
> switch (hw->fc.requested_mode) {
> case ixgbe_fc_full:
> setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
> FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
> break;
> case ixgbe_fc_rx_pause:
> setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
> FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
> break;
> case ixgbe_fc_tx_pause:
> setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
> FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
> break;
> default:
> break;
> }
>
> for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
> if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
> setup[0] |= ixgbe_fw_map[i].fw_speed;
> }
> setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
>
> if (hw->phy.eee_speeds_advertised)
> setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
>
> rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
> if (rc)
> return rc;
> if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
> return IXGBE_ERR_OVERTEMP;
> return IXGBE_SUCCESS;
> }
>
> /**
> * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
> * @hw: pointer to hardware structure
> *
> * Called at init time to set up flow control.
> */
> static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
> {
> if (hw->fc.requested_mode == ixgbe_fc_default)
> hw->fc.requested_mode = ixgbe_fc_full;
>
> return ixgbe_setup_fw_link(hw);
> }
>
> /**
> * ixgbe_setup_eee_fw - Enable/disable EEE support
> * @hw: pointer to the HW structure
> * @enable_eee: boolean flag to enable EEE
> *
> * Enable/disable EEE based on enable_eee flag.
> * This function controls EEE for firmware-based PHY implementations.
> */
> static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
> {
> if (!!hw->phy.eee_speeds_advertised == enable_eee)
> return IXGBE_SUCCESS;
> if (enable_eee)
> hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
> else
> hw->phy.eee_speeds_advertised = 0;
> return hw->phy.ops.setup_link(hw);
> }
>
> /**
> * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
> * @hw: pointer to hardware structure
> *
> * Initialize the function pointers and for MAC type X550EM_a.
> * Does not touch the hardware.
> **/
> s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
> {
> struct ixgbe_mac_info *mac = &hw->mac;
> s32 ret_val;
>
> DEBUGFUNC("ixgbe_init_ops_X550EM_a");
>
> /* Start with generic X550EM init */
> ret_val = ixgbe_init_ops_X550EM(hw);
>
> if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
> hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
> mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
> mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
> } else {
> mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
> mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
> }
> mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
> mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
>
> switch (mac->ops.get_media_type(hw)) {
> case ixgbe_media_type_fiber:
> mac->ops.setup_fc = NULL;
> mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
> break;
> case ixgbe_media_type_backplane:
> mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
> mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
> break;
> default:
> break;
> }
>
> switch (hw->device_id) {
> case IXGBE_DEV_ID_X550EM_A_1G_T:
> case IXGBE_DEV_ID_X550EM_A_1G_T_L:
> mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
> mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
> mac->ops.setup_eee = ixgbe_setup_eee_fw;
> hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
> IXGBE_LINK_SPEED_1GB_FULL;
> hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
> break;
> default:
> break;
> }
>
> return ret_val;
> }
>
> /**
> * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
> * @hw: pointer to hardware structure
> *
> * Initialize the function pointers and for MAC type X550EM_x.
> * Does not touch the hardware.
> **/
> s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
> {
> struct ixgbe_mac_info *mac = &hw->mac;
> struct ixgbe_link_info *link = &hw->link;
> s32 ret_val;
>
> DEBUGFUNC("ixgbe_init_ops_X550EM_x");
>
> /* Start with generic X550EM init */
> ret_val = ixgbe_init_ops_X550EM(hw);
>
> mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
> mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
> mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
> mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
> link->ops.read_link = ixgbe_read_i2c_combined_generic;
> link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
> link->ops.write_link = ixgbe_write_i2c_combined_generic;
> link->ops.write_link_unlocked =
> ixgbe_write_i2c_combined_generic_unlocked;
> link->addr = IXGBE_CS4227;
>
> if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) {
> mac->ops.setup_fc = NULL;
> mac->ops.setup_eee = NULL;
> mac->ops.init_led_link_act = NULL;
> }
>
> return ret_val;
> }
>
> /**
519a1036
> case IXGBE_LINK_SPEED_10_FULL:
620,718d1136
< * ixgbe_setup_eee_X550 - Enable/disable EEE support
< * @hw: pointer to the HW structure
< * @enable_eee: boolean flag to enable EEE
< *
< * Enable/disable EEE based on enable_eee flag.
< * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
< * are modified.
< *
< **/
< s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
< {
< u32 eeer;
< u16 autoneg_eee_reg;
< u32 link_reg;
< s32 status;
< u32 fuse;
<
< DEBUGFUNC("ixgbe_setup_eee_X550");
<
< eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
< /* Enable or disable EEE per flag */
< if (enable_eee) {
< eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
<
< if (hw->mac.type == ixgbe_mac_X550) {
< /* Advertise EEE capability */
< hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
< IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
<
< autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
< IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
< IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
<
< hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
< IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
< } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
< /* Not supported on first revision. */
< fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
< if (!(fuse & IXGBE_FUSES0_REV1))
< return IXGBE_SUCCESS;
<
< status = ixgbe_read_iosf_sb_reg_x550(hw,
< IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
< if (status != IXGBE_SUCCESS)
< return status;
<
< link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
< IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
<
< /* Don't advertise FEC capability when EEE enabled. */
< link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
<
< status = ixgbe_write_iosf_sb_reg_x550(hw,
< IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
< if (status != IXGBE_SUCCESS)
< return status;
< }
< } else {
< eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
<
< if (hw->mac.type == ixgbe_mac_X550) {
< /* Disable advertised EEE capability */
< hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
< IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
<
< autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
< IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
< IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
<
< hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
< IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
< } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
< status = ixgbe_read_iosf_sb_reg_x550(hw,
< IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
< if (status != IXGBE_SUCCESS)
< return status;
<
< link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
< IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
<
< /* Advertise FEC capability when EEE is disabled. */
< link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
<
< status = ixgbe_write_iosf_sb_reg_x550(hw,
< IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
< if (status != IXGBE_SUCCESS)
< return status;
< }
< }
< IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
<
< return IXGBE_SUCCESS;
< }
<
< /**
804,805c1222,1223
< * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
< * device
---
> * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
> * of the IOSF device
851,852c1269
< * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
< * device
---
> * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
856c1273
< * @phy_data: Pointer to read data from the register
---
> * @data: Pointer to read data from the register
897a1315,1448
> * ixgbe_get_phy_token - Get the token for shared phy access
> * @hw: Pointer to hardware structure
> */
>
> s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
> {
> struct ixgbe_hic_phy_token_req token_cmd;
> s32 status;
>
> token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
> token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
> token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
> token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
> token_cmd.port_number = hw->bus.lan_id;
> token_cmd.command_type = FW_PHY_TOKEN_REQ;
> token_cmd.pad = 0;
> status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
> sizeof(token_cmd),
> IXGBE_HI_COMMAND_TIMEOUT,
> TRUE);
> if (status) {
> DEBUGOUT1("Issuing host interface command failed with Status = %d\n",
> status);
> return status;
> }
> if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
> return IXGBE_SUCCESS;
> if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) {
> DEBUGOUT1("Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n",
> token_cmd.hdr.cmd_or_resp.ret_status);
> return IXGBE_ERR_FW_RESP_INVALID;
> }
>
> DEBUGOUT("Returning IXGBE_ERR_TOKEN_RETRY\n");
> return IXGBE_ERR_TOKEN_RETRY;
> }
>
> /**
> * ixgbe_put_phy_token - Put the token for shared phy access
> * @hw: Pointer to hardware structure
> */
>
> s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
> {
> struct ixgbe_hic_phy_token_req token_cmd;
> s32 status;
>
> token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
> token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
> token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
> token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
> token_cmd.port_number = hw->bus.lan_id;
> token_cmd.command_type = FW_PHY_TOKEN_REL;
> token_cmd.pad = 0;
> status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
> sizeof(token_cmd),
> IXGBE_HI_COMMAND_TIMEOUT,
> TRUE);
> if (status)
> return status;
> if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
> return IXGBE_SUCCESS;
>
> DEBUGOUT("Put PHY Token host interface command failed");
> return IXGBE_ERR_FW_RESP_INVALID;
> }
>
> /**
> * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
> * of the IOSF device
> * @hw: pointer to hardware structure
> * @reg_addr: 32 bit PHY register to write
> * @device_type: 3 bit device type
> * @data: Data to write to the register
> **/
> s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
> u32 device_type, u32 data)
> {
> struct ixgbe_hic_internal_phy_req write_cmd;
> s32 status;
> UNREFERENCED_1PARAMETER(device_type);
>
> memset(&write_cmd, 0, sizeof(write_cmd));
> write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
> write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
> write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
> write_cmd.port_number = hw->bus.lan_id;
> write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
> write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
> write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
>
> status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
> sizeof(write_cmd),
> IXGBE_HI_COMMAND_TIMEOUT, FALSE);
>
> return status;
> }
>
> /**
> * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
> * @hw: pointer to hardware structure
> * @reg_addr: 32 bit PHY register to write
> * @device_type: 3 bit device type
> * @data: Pointer to read data from the register
> **/
> s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
> u32 device_type, u32 *data)
> {
> union {
> struct ixgbe_hic_internal_phy_req cmd;
> struct ixgbe_hic_internal_phy_resp rsp;
> } hic;
> s32 status;
> UNREFERENCED_1PARAMETER(device_type);
>
> memset(&hic, 0, sizeof(hic));
> hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
> hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
> hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
> hic.cmd.port_number = hw->bus.lan_id;
> hic.cmd.command_type = FW_INT_PHY_REQ_READ;
> hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
>
> status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
> sizeof(hic.cmd),
> IXGBE_HI_COMMAND_TIMEOUT, TRUE);
>
> /* Extract the register value from the response. */
> *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
>
> return status;
> }
>
> /**
968c1519
< default: /* 64 VFs / pools */
---
> default: /* 64 VFs / pools */
1055a1607,1609
> case IXGBE_DEV_ID_X550EM_X_XFI:
> case IXGBE_DEV_ID_X550EM_A_KR:
> case IXGBE_DEV_ID_X550EM_A_KR_L:
1058a1613,1616
> case IXGBE_DEV_ID_X550EM_A_SFP:
> case IXGBE_DEV_ID_X550EM_A_SFP_N:
> case IXGBE_DEV_ID_X550EM_A_QSFP:
> case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1062a1621
> case IXGBE_DEV_ID_X550EM_A_10G_T:
1064a1624,1632
> case IXGBE_DEV_ID_X550EM_A_SGMII:
> case IXGBE_DEV_ID_X550EM_A_SGMII_L:
> media_type = ixgbe_media_type_backplane;
> hw->phy.type = ixgbe_phy_sgmii;
> break;
> case IXGBE_DEV_ID_X550EM_A_1G_T:
> case IXGBE_DEV_ID_X550EM_A_1G_T_L:
> media_type = ixgbe_media_type_copper;
> break;
1155a1724,1908
> * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
> * internal PHY
> * @hw: pointer to hardware structure
> **/
> static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
> {
> s32 status;
> u32 link_ctrl;
>
> /* Restart auto-negotiation. */
> status = hw->mac.ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
>
> if (status) {
> DEBUGOUT("Auto-negotiation did not complete\n");
> return status;
> }
>
> link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
> status = hw->mac.ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
>
> if (hw->mac.type == ixgbe_mac_X550EM_a) {
> u32 flx_mask_st20;
>
> /* Indicate to FW that AN restart has been asserted */
> status = hw->mac.ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
>
> if (status) {
> DEBUGOUT("Auto-negotiation did not complete\n");
> return status;
> }
>
> flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
> status = hw->mac.ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
> }
>
> return status;
> }
>
> /**
> * ixgbe_setup_sgmii - Set up link for sgmii
> * @hw: pointer to hardware structure
> */
> static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
> bool autoneg_wait)
> {
> struct ixgbe_mac_info *mac = &hw->mac;
> u32 lval, sval, flx_val;
> s32 rc;
>
> rc = mac->ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
> if (rc)
> return rc;
>
> lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
> lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
> lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
> lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
> lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
> rc = mac->ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
> if (rc)
> return rc;
>
> rc = mac->ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
> if (rc)
> return rc;
>
> sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
> sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
> rc = mac->ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
> if (rc)
> return rc;
>
> rc = mac->ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
> if (rc)
> return rc;
>
> flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
> flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
> flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
> flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
> flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
>
> rc = mac->ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
> if (rc)
> return rc;
>
> rc = ixgbe_restart_an_internal_phy_x550em(hw);
> if (rc)
> return rc;
>
> return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
> }
>
> /**
> * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
> * @hw: pointer to hardware structure
> */
> static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
> bool autoneg_wait)
> {
> struct ixgbe_mac_info *mac = &hw->mac;
> u32 lval, sval, flx_val;
> s32 rc;
>
> rc = mac->ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
> if (rc)
> return rc;
>
> lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
> lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
> lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
> lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
> lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
> rc = mac->ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
> if (rc)
> return rc;
>
> rc = mac->ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
> if (rc)
> return rc;
>
> sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
> sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
> rc = mac->ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
> if (rc)
> return rc;
>
> rc = mac->ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
> if (rc)
> return rc;
>
> rc = mac->ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
> if (rc)
> return rc;
>
> flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
> flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
> flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
> flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
> flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
>
> rc = mac->ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
> if (rc)
> return rc;
>
> rc = ixgbe_restart_an_internal_phy_x550em(hw);
>
> return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
> }
>
> /**
1165,1166c1918,1919
< switch (hw->mac.ops.get_media_type(hw)) {
< case ixgbe_media_type_fiber:
---
> switch (hw->mac.ops.get_media_type(hw)) {
> case ixgbe_media_type_fiber:
1174d1926
< mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1176a1929,1936
>
> if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
> (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
> mac->ops.setup_mac_link =
> ixgbe_setup_mac_link_sfp_x550a;
> else
> mac->ops.setup_mac_link =
> ixgbe_setup_mac_link_sfp_x550em;
1179,1180c1939,1954
< mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
< mac->ops.check_link = ixgbe_check_link_t_X550em;
---
> if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
> break;
> if (hw->mac.type == ixgbe_mac_X550EM_a) {
> if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
> hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
> mac->ops.setup_link = ixgbe_setup_sgmii_fw;
> mac->ops.check_link =
> ixgbe_check_mac_link_generic;
> } else {
> mac->ops.setup_link =
> ixgbe_setup_mac_link_t_X550em;
> }
> } else {
> mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
> mac->ops.check_link = ixgbe_check_link_t_X550em;
> }
1181a1956,1960
> case ixgbe_media_type_backplane:
> if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
> hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
> mac->ops.setup_link = ixgbe_setup_sgmii;
> break;
1184c1963
< }
---
> }
1198a1978,1984
>
> if (hw->phy.type == ixgbe_phy_fw) {
> *autoneg = TRUE;
> *speed = hw->phy.speeds_supported;
> return 0;
> }
>
1221,1222c2007,2030
< *speed = IXGBE_LINK_SPEED_10GB_FULL |
< IXGBE_LINK_SPEED_1GB_FULL;
---
> switch (hw->phy.type) {
> case ixgbe_phy_ext_1g_t:
> case ixgbe_phy_sgmii:
> *speed = IXGBE_LINK_SPEED_1GB_FULL;
> break;
> case ixgbe_phy_x550em_kr:
> if (hw->mac.type == ixgbe_mac_X550EM_a) {
> /* check different backplane modes */
> if (hw->phy.nw_mng_if_sel &
> IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
> *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
> break;
> } else if (hw->device_id ==
> IXGBE_DEV_ID_X550EM_A_KR_L) {
> *speed = IXGBE_LINK_SPEED_1GB_FULL;
> break;
> }
> }
> /* fall through */
> default:
> *speed = IXGBE_LINK_SPEED_10GB_FULL |
> IXGBE_LINK_SPEED_1GB_FULL;
> break;
> }
1338,1339d2145
< status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
< IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1341,1342c2147,2158
< if (status != IXGBE_SUCCESS)
< return status;
---
> /* Enable the LASI interrupts on X552 devices to receive notifications
> * of the link configurations of the external PHY and correspondingly
> * support the configuration of the internal iXFI link, since iXFI does
> * not support auto-negotiation. This is not required for X553 devices
> * having KR support, which performs auto-negotiations and which is used
> * as the internal link to the external PHY. Hence adding a check here
> * to avoid enabling LASI interrupts for X553 devices.
> */
> if (hw->mac.type != ixgbe_mac_X550EM_a) {
> status = hw->phy.ops.read_reg(hw,
> IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
> IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1344c2160,2161
< reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
---
> if (status != IXGBE_SUCCESS)
> return status;
1346,1347c2163
< status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
< IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
---
> reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1349,1350c2165,2167
< if (status != IXGBE_SUCCESS)
< return status;
---
> status = hw->phy.ops.write_reg(hw,
> IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
> IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1352c2169,2173
< /* Enables high temperature failure alarm */
---
> if (status != IXGBE_SUCCESS)
> return status;
> }
>
> /* Enable high temperature failure and global fault alarms */
1360c2181,2182
< reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
---
> reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
> IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1417,1419c2239,2241
< status = ixgbe_read_iosf_sb_reg_x550(hw,
< IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
---
> status = hw->mac.ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1435,1439c2257,2259
< /* Restart auto-negotiation. */
< reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
< status = ixgbe_write_iosf_sb_reg_x550(hw,
< IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
---
> status = hw->mac.ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1441c2261,2281
< return status;
---
> if (hw->mac.type == ixgbe_mac_X550EM_a) {
> /* Set lane mode to KR auto negotiation */
> status = hw->mac.ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
>
> if (status)
> return status;
>
> reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
> reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
> reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
> reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
> reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
>
> status = hw->mac.ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
> }
>
> return ixgbe_restart_an_internal_phy_x550em(hw);
1444a2285,2355
> * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
> * @hw: pointer to hardware structure
> */
> static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
> {
> u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
> s32 rc;
>
> if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
> return IXGBE_SUCCESS;
>
> rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
> if (rc)
> return rc;
> memset(store, 0, sizeof(store));
>
> rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
> if (rc)
> return rc;
>
> return ixgbe_setup_fw_link(hw);
> }
>
> /**
> * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
> * @hw: pointer to hardware structure
> */
> static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
> {
> u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
> s32 rc;
>
> rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
> if (rc)
> return rc;
>
> if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
> ixgbe_shutdown_fw_phy(hw);
> return IXGBE_ERR_OVERTEMP;
> }
> return IXGBE_SUCCESS;
> }
>
> /**
> * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
> * @hw: pointer to hardware structure
> *
> * Read NW_MNG_IF_SEL register and save field values, and check for valid field
> * values.
> **/
> static s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
> {
> /* Save NW management interface connected on board. This is used
> * to determine internal PHY mode.
> */
> hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
>
> /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
> * PHY address. This register field was has only been used for X552.
> */
> if (hw->mac.type == ixgbe_mac_X550EM_a &&
> hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
> hw->phy.addr = (hw->phy.nw_mng_if_sel &
> IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
> IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
> }
>
> return IXGBE_SUCCESS;
> }
>
> /**
1455d2365
< ixgbe_link_speed speed;
1460a2371
> ixgbe_read_mng_if_sel_x550em(hw);
1465,1473d2375
<
< /* Save NW management interface connected on board. This is used
< * to determine internal PHY mode.
< */
< phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
< if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
< speed = IXGBE_LINK_SPEED_10GB_FULL |
< IXGBE_LINK_SPEED_1GB_FULL;
< }
1476a2379,2409
> switch (hw->device_id) {
> case IXGBE_DEV_ID_X550EM_A_1G_T:
> case IXGBE_DEV_ID_X550EM_A_1G_T_L:
> phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
> phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
> hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
> hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
> phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
> if (hw->bus.lan_id)
> hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
> else
> hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
>
> break;
> case IXGBE_DEV_ID_X550EM_A_10G_T:
> case IXGBE_DEV_ID_X550EM_A_SFP:
> hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
> hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
> if (hw->bus.lan_id)
> hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
> else
> hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
> break;
> case IXGBE_DEV_ID_X550EM_X_SFP:
> /* set up for CS4227 usage */
> hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
> break;
> default:
> break;
> }
>
1479c2412,2413
< if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
---
> if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
> ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
1498a2433,2443
> case ixgbe_phy_ext_1g_t:
> /* link is managed by FW */
> phy->ops.setup_link = NULL;
> phy->ops.reset = NULL;
> break;
> case ixgbe_phy_x550em_xfi:
> /* link is managed by HW */
> phy->ops.setup_link = NULL;
> phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
> phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
> break;
1500,1504d2444
< /* Save NW management interface connected on board. This is used
< * to determine internal PHY mode
< */
< phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
<
1508,1509c2448
< if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
< phy->ops.setup_internal_link =
---
> phy->ops.setup_internal_link =
1511,1515d2449
< } else {
< speed = IXGBE_LINK_SPEED_10GB_FULL |
< IXGBE_LINK_SPEED_1GB_FULL;
< ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
< }
1517,1519c2451,2454
< /* setup SW LPLU only for first revision */
< if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
< IXGBE_FUSES0_GROUP(0))))
---
> /* setup SW LPLU only for first revision of X550EM_x */
> if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
> !(IXGBE_FUSES0_REV_MASK &
> IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1524a2460,2466
> case ixgbe_phy_sgmii:
> phy->ops.setup_link = NULL;
> break;
> case ixgbe_phy_fw:
> phy->ops.setup_link = ixgbe_setup_fw_link;
> phy->ops.reset = ixgbe_reset_phy_fw;
> break;
1531a2474,2505
> * ixgbe_set_mdio_speed - Set MDIO clock speed
> * @hw: pointer to hardware structure
> */
> static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
> {
> u32 hlreg0;
>
> switch (hw->device_id) {
> case IXGBE_DEV_ID_X550EM_X_10G_T:
> case IXGBE_DEV_ID_X550EM_A_SGMII:
> case IXGBE_DEV_ID_X550EM_A_SGMII_L:
> case IXGBE_DEV_ID_X550EM_A_10G_T:
> case IXGBE_DEV_ID_X550EM_A_SFP:
> case IXGBE_DEV_ID_X550EM_A_QSFP:
> /* Config MDIO clock speed before the first MDIO PHY access */
> hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
> hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
> IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
> break;
> case IXGBE_DEV_ID_X550EM_A_1G_T:
> case IXGBE_DEV_ID_X550EM_A_1G_T_L:
> /* Select fast MDIO clock speed for these devices */
> hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
> hlreg0 |= IXGBE_HLREG0_MDCSPD;
> IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
> break;
> default:
> break;
> }
> }
>
> /**
1545d2518
< u32 hlreg0;
1546a2520
> u32 swfw_mask = hw->phy.phy_semaphore_mask;
1552c2526,2527
< if (status != IXGBE_SUCCESS)
---
> if (status != IXGBE_SUCCESS) {
> DEBUGOUT1("Failed to stop adapter, STATUS = %d\n", status);
1554c2529
<
---
> }
1558,1563c2533
< if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
< /* Config MDIO clock speed before the first MDIO PHY access */
< hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
< hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
< IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
< }
---
> ixgbe_set_mdio_speed(hw);
1568c2538,2543
< if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
---
> if (status)
> DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n",
> status);
>
> if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) {
> DEBUGOUT("Returning from reset HW due to PHY init failure\n");
1569a2545
> }
1574c2550,2552
< if (status)
---
> if (status) {
> DEBUGOUT1("Failed to start the external PHY, STATUS = %d\n",
> status);
1575a2554
> }
1588,1589c2567,2570
< if (!hw->phy.reset_disable && hw->phy.ops.reset)
< hw->phy.ops.reset(hw);
---
> if (!hw->phy.reset_disable && hw->phy.ops.reset) {
> if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
> return IXGBE_ERR_OVERTEMP;
> }
1603a2585,2590
> status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
> if (status != IXGBE_SUCCESS) {
> ERROR_REPORT2(IXGBE_ERROR_CAUTION,
> "semaphore failed with %d", status);
> return IXGBE_ERR_SWFW_SYNC;
> }
1606a2594
> hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1641a2630,2631
> ixgbe_set_mdio_speed(hw);
>
1644a2635,2637
> if (status != IXGBE_SUCCESS)
> DEBUGOUT1("Reset HW failed, STATUS = %d\n", status);
>
1694,1695d2686
< *
< * Configures the integrated KR PHY.
1698a2690,2696
> /* leave link alone for 2.5G */
> if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
> return IXGBE_SUCCESS;
>
> if (ixgbe_check_reset_blocked(hw))
> return 0;
>
1730,1736c2728,2729
< if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
< /* Configure CS4227 LINE side to 10G SR. */
< reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
< (hw->bus.lan_id << 12);
< reg_val = IXGBE_CS4227_SPEED_10G;
< ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
< reg_val);
---
> /* Configure internal PHY for KR/KX. */
> ixgbe_setup_kr_speed_x550em(hw, speed);
1738,1739c2731,2736
< reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
< (hw->bus.lan_id << 12);
---
> /* Configure CS4227 LINE side to proper mode. */
> reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
> (hw->bus.lan_id << 12);
> if (setup_linear)
> reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
> else
1741,1776c2738,2739
< ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
< reg_val);
<
< /* Configure CS4227 for HOST connection rate then type. */
< reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
< (hw->bus.lan_id << 12);
< reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
< IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
< ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
< reg_val);
<
< reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
< (hw->bus.lan_id << 12);
< if (setup_linear)
< reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
< else
< reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
< ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
< reg_val);
<
< /* Setup XFI internal link. */
< ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
< } else {
< /* Configure internal PHY for KR/KX. */
< ixgbe_setup_kr_speed_x550em(hw, speed);
<
< /* Configure CS4227 LINE side to proper mode. */
< reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
< (hw->bus.lan_id << 12);
< if (setup_linear)
< reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
< else
< reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
< ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
< reg_val);
< }
---
> ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
> reg_val);
1781c2744
< * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
---
> * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
1785,1786c2748,2749
< * Configures the integrated KR PHY to use iXFI mode. Used to connect an
< * internal and external PHY at a specific speed, without autonegotiation.
---
> * Configures the integrated PHY for native SFI mode. Used to connect the
> * internal PHY directly to an SFP cage, without autonegotiation.
1788c2751
< static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
---
> static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1789a2753
> struct ixgbe_mac_info *mac = &hw->mac;
1793,1796c2757,2760
< /* Disable AN and force speed to 10G Serial. */
< status = ixgbe_read_iosf_sb_reg_x550(hw,
< IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
---
> /* Disable all AN and force speed to 10G Serial. */
> status = mac->ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1800,1801c2764,2767
< reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
< reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
---
> reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
> reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
> reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
> reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1806c2772
< reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
---
> reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
1809c2775
< reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
---
> reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1812c2778
< /* Other link speeds are not supported by internal KR PHY. */
---
> /* Other link speeds are not supported by internal PHY. */
1816,1820c2782,2784
< status = ixgbe_write_iosf_sb_reg_x550(hw,
< IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
< if (status != IXGBE_SUCCESS)
< return status;
---
> status = mac->ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1821a2786,2906
> /* Toggle port SW reset by AN reset. */
> status = ixgbe_restart_an_internal_phy_x550em(hw);
>
> return status;
> }
>
> /**
> * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
> * @hw: pointer to hardware structure
> *
> * Configure the the integrated PHY for SFP support.
> **/
> s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
> ixgbe_link_speed speed,
> bool autoneg_wait_to_complete)
> {
> s32 ret_val;
> u16 reg_phy_ext;
> bool setup_linear = FALSE;
> u32 reg_slice, reg_phy_int, slice_offset;
>
> UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
>
> /* Check if SFP module is supported and linear */
> ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
>
> /* If no SFP module present, then return success. Return success since
> * SFP not present error is not excepted in the setup MAC link flow.
> */
> if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
> return IXGBE_SUCCESS;
>
> if (ret_val != IXGBE_SUCCESS)
> return ret_val;
>
> if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
> /* Configure internal PHY for native SFI based on module type */
> ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
>
> if (ret_val != IXGBE_SUCCESS)
> return ret_val;
>
> reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
> if (!setup_linear)
> reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
>
> ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
>
> if (ret_val != IXGBE_SUCCESS)
> return ret_val;
>
> /* Setup SFI internal link. */
> ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
> } else {
> /* Configure internal PHY for KR/KX. */
> ixgbe_setup_kr_speed_x550em(hw, speed);
>
> if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
> /* Find Address */
> DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
> return IXGBE_ERR_PHY_ADDR_INVALID;
> }
>
> /* Get external PHY SKU id */
> ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
> IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
>
> if (ret_val != IXGBE_SUCCESS)
> return ret_val;
>
> /* When configuring quad port CS4223, the MAC instance is part
> * of the slice offset.
> */
> if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
> slice_offset = (hw->bus.lan_id +
> (hw->bus.instance_id << 1)) << 12;
> else
> slice_offset = hw->bus.lan_id << 12;
>
> /* Configure CS4227/CS4223 LINE side to proper mode. */
> reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
>
> ret_val = hw->phy.ops.read_reg(hw, reg_slice,
> IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
>
> if (ret_val != IXGBE_SUCCESS)
> return ret_val;
>
> reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
> (IXGBE_CS4227_EDC_MODE_SR << 1));
>
> if (setup_linear)
> reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
> else
> reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
> ret_val = hw->phy.ops.write_reg(hw, reg_slice,
> IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
>
> /* Flush previous write with a read */
> ret_val = hw->phy.ops.read_reg(hw, reg_slice,
> IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
> }
> return ret_val;
> }
>
> /**
> * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
> * @hw: pointer to hardware structure
> *
> * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
> **/
> static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
> {
> struct ixgbe_mac_info *mac = &hw->mac;
> s32 status;
> u32 reg_val;
>
1823c2908
< status = ixgbe_read_iosf_sb_reg_x550(hw,
---
> status = mac->ops.read_iosf_sb_reg(hw,
1829c2914
< status = ixgbe_write_iosf_sb_reg_x550(hw,
---
> status = mac->ops.write_iosf_sb_reg(hw,
1836c2921
< status = ixgbe_read_iosf_sb_reg_x550(hw,
---
> status = mac->ops.read_iosf_sb_reg(hw,
1844c2929
< status = ixgbe_write_iosf_sb_reg_x550(hw,
---
> status = mac->ops.write_iosf_sb_reg(hw,
1849c2934
< status = ixgbe_read_iosf_sb_reg_x550(hw,
---
> status = mac->ops.read_iosf_sb_reg(hw,
1857c2942
< status = ixgbe_write_iosf_sb_reg_x550(hw,
---
> status = mac->ops.write_iosf_sb_reg(hw,
1864c2949
< status = ixgbe_read_iosf_sb_reg_x550(hw,
---
> status = mac->ops.read_iosf_sb_reg(hw,
1873c2958
< status = ixgbe_write_iosf_sb_reg_x550(hw,
---
> status = mac->ops.write_iosf_sb_reg(hw,
1876,1877c2961,2962
< if (status != IXGBE_SUCCESS)
< return status;
---
> return status;
> }
1879,1880c2964,2983
< /* Toggle port SW reset by AN reset. */
< status = ixgbe_read_iosf_sb_reg_x550(hw,
---
> /**
> * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
> * @hw: pointer to hardware structure
> * @speed: the link speed to force
> *
> * Configures the integrated KR PHY to use iXFI mode. Used to connect an
> * internal and external PHY at a specific speed, without autonegotiation.
> **/
> static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
> {
> struct ixgbe_mac_info *mac = &hw->mac;
> s32 status;
> u32 reg_val;
>
> /* iXFI is only supported with X552 */
> if (mac->type != ixgbe_mac_X550EM_x)
> return IXGBE_ERR_LINK_SETUP;
>
> /* Disable AN and force speed to 10G Serial. */
> status = mac->ops.read_iosf_sb_reg(hw,
1885,1886c2988,3005
< reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
< status = ixgbe_write_iosf_sb_reg_x550(hw,
---
>
> reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
> reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
>
> /* Select forced link speed for internal PHY. */
> switch (*speed) {
> case IXGBE_LINK_SPEED_10GB_FULL:
> reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
> break;
> case IXGBE_LINK_SPEED_1GB_FULL:
> reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
> break;
> default:
> /* Other link speeds are not supported by internal KR PHY. */
> return IXGBE_ERR_LINK_SETUP;
> }
>
> status = mac->ops.write_iosf_sb_reg(hw,
1888a3008,3009
> if (status != IXGBE_SUCCESS)
> return status;
1889a3011,3020
> /* Additional configuration needed for x550em_x */
> if (hw->mac.type == ixgbe_mac_X550EM_x) {
> status = ixgbe_setup_ixfi_x550em_x(hw);
> if (status != IXGBE_SUCCESS)
> return status;
> }
>
> /* Toggle port SW reset by AN reset. */
> status = ixgbe_restart_an_internal_phy_x550em(hw);
>
1947,1950c3078,3083
< /* If link is not up, then there is no setup necessary so return */
< status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
< if (status != IXGBE_SUCCESS)
< return status;
---
> if (hw->mac.type == ixgbe_mac_X550EM_x &&
> !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
> /* If link is down, there is no setup necessary so return */
> status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
> if (status != IXGBE_SUCCESS)
> return status;
1952,1953c3085,3086
< if (!link_up)
< return IXGBE_SUCCESS;
---
> if (!link_up)
> return IXGBE_SUCCESS;
1955,1959c3088,3093
< status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
< IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
< &speed);
< if (status != IXGBE_SUCCESS)
< return status;
---
> status = hw->phy.ops.read_reg(hw,
> IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
> IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
> &speed);
> if (status != IXGBE_SUCCESS)
> return status;
1961,1966c3095,3100
< /* If link is not still up, then no setup is necessary so return */
< status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
< if (status != IXGBE_SUCCESS)
< return status;
< if (!link_up)
< return IXGBE_SUCCESS;
---
> /* If link is still down - no setup is required so return */
> status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
> if (status != IXGBE_SUCCESS)
> return status;
> if (!link_up)
> return IXGBE_SUCCESS;
1968,1969c3102,3103
< /* clear everything but the speed and duplex bits */
< speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
---
> /* clear everything but the speed and duplex bits */
> speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1971,1981c3105,3115
< switch (speed) {
< case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
< force_speed = IXGBE_LINK_SPEED_10GB_FULL;
< break;
< case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
< force_speed = IXGBE_LINK_SPEED_1GB_FULL;
< break;
< default:
< /* Internal PHY does not support anything else */
< return IXGBE_ERR_INVALID_LINK_SETTINGS;
< }
---
> switch (speed) {
> case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
> force_speed = IXGBE_LINK_SPEED_10GB_FULL;
> break;
> case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
> force_speed = IXGBE_LINK_SPEED_1GB_FULL;
> break;
> default:
> /* Internal PHY does not support anything else */
> return IXGBE_ERR_INVALID_LINK_SETTINGS;
> }
1983c3117,3122
< return ixgbe_setup_ixfi_x550em(hw, &force_speed);
---
> return ixgbe_setup_ixfi_x550em(hw, &force_speed);
> } else {
> speed = IXGBE_LINK_SPEED_10GB_FULL |
> IXGBE_LINK_SPEED_1GB_FULL;
> return ixgbe_setup_kr_speed_x550em(hw, speed);
> }
1998,2000c3137,3139
< status = ixgbe_read_iosf_sb_reg_x550(hw,
< IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
---
> status = hw->mac.ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2006,2008c3145,3147
< status = ixgbe_write_iosf_sb_reg_x550(hw,
< IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
---
> status = hw->mac.ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2013,2015c3152,3154
< status = ixgbe_read_iosf_sb_reg_x550(hw,
< IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
---
> status = hw->mac.ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2020,2022c3159,3161
< status = ixgbe_write_iosf_sb_reg_x550(hw,
< IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
---
> status = hw->mac.ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2027,2029c3166,3168
< status = ixgbe_read_iosf_sb_reg_x550(hw,
< IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
---
> status = hw->mac.ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2033,2035c3172,3174
< status = ixgbe_write_iosf_sb_reg_x550(hw,
< IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
---
> status = hw->mac.ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2040,2042c3179,3181
< status = ixgbe_read_iosf_sb_reg_x550(hw,
< IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
---
> status = hw->mac.ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2046,2048c3185,3187
< status = ixgbe_write_iosf_sb_reg_x550(hw,
< IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
---
> status = hw->mac.ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2062,2063c3201
< s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
< u16 *data)
---
> s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
2065c3203
< s32 status;
---
> const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
2066a3205
> s32 status;
2068c3207
< DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
---
> DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2079,2082c3218
< status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
< sizeof(buffer),
< IXGBE_HI_COMMAND_TIMEOUT, FALSE);
<
---
> status = hw->mac.ops.acquire_swfw_sync(hw, mask);
2086,2112c3222,3226
< *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
< FW_NVM_DATA_OFFSET);
<
< return 0;
< }
<
< /**
< * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
< * @hw: pointer to hardware structure
< * @offset: offset of word in the EEPROM to read
< * @data: word read from the EEPROM
< *
< * Reads a 16 bit word from the EEPROM using the hostif.
< **/
< s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
< u16 *data)
< {
< s32 status = IXGBE_SUCCESS;
<
< DEBUGFUNC("ixgbe_read_ee_hostif_X550");
<
< if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
< IXGBE_SUCCESS) {
< status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
< hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
< } else {
< status = IXGBE_ERR_SWFW_SYNC;
---
> status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
> IXGBE_HI_COMMAND_TIMEOUT);
> if (!status) {
> *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
> FW_NVM_DATA_OFFSET);
2114a3229
> hw->mac.ops.release_swfw_sync(hw, mask);
2129a3245
> const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
2139c3255
< status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
---
> status = hw->mac.ops.acquire_swfw_sync(hw, mask);
2143a3260
>
2159,2162c3276,3277
< status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
< sizeof(buffer),
< IXGBE_HI_COMMAND_TIMEOUT,
< FALSE);
---
> status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
> IXGBE_HI_COMMAND_TIMEOUT);
2187c3302
< hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
---
> hw->mac.ops.release_swfw_sync(hw, mask);
2580c3695
< u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
---
> u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2582c3697
< u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
---
> u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2590a3706,3720
> if (hw->mac.type == ixgbe_mac_X550EM_a) {
> if (hw->phy.nw_mng_if_sel &
> IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
> physical_layer =
> IXGBE_PHYSICAL_LAYER_2500BASE_KX;
> break;
> } else if (hw->device_id ==
> IXGBE_DEV_ID_X550EM_A_KR_L) {
> physical_layer =
> IXGBE_PHYSICAL_LAYER_1000BASE_KX;
> break;
> }
> }
> /* fall through */
> case ixgbe_phy_x550em_xfi:
2606a3737,3750
> case ixgbe_phy_fw:
> if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)
> physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
> if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)
> physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
> if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)
> physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;
> break;
> case ixgbe_phy_sgmii:
> physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
> break;
> case ixgbe_phy_ext_1g_t:
> physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
> break;
2698c3842,3844
< if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
---
> if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
> (IXGBE_FUSES0_REV_MASK &
> IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2882,2885c4028,4034
< if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
< ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
< IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
---
> switch (hw->device_id) {
> case IXGBE_DEV_ID_X550EM_X_KR:
> case IXGBE_DEV_ID_X550EM_A_KR:
> case IXGBE_DEV_ID_X550EM_A_KR_L:
> ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2894,2896c4043,4045
< ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
< IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
< IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
---
> ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2899a4049,4054
> break;
> case IXGBE_DEV_ID_X550EM_X_XFI:
> hw->fc.disable_fc_autoneg = TRUE;
> break;
> default:
> break;
2906a4062,4293
> * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
> * @hw: pointer to hardware structure
> *
> * Enable flow control according to IEEE clause 37.
> **/
> void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
> {
> u32 link_s1, lp_an_page_low, an_cntl_1;
> s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
> ixgbe_link_speed speed;
> bool link_up;
>
> /* AN should have completed when the cable was plugged in.
> * Look for reasons to bail out. Bail out if:
> * - FC autoneg is disabled, or if
> * - link is not up.
> */
> if (hw->fc.disable_fc_autoneg) {
> ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
> "Flow control autoneg is disabled");
> goto out;
> }
>
> hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
> if (!link_up) {
> ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
> goto out;
> }
>
> /* Check at auto-negotiation has completed */
> status = hw->mac.ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_LINK_S1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
>
> if (status != IXGBE_SUCCESS ||
> (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
> DEBUGOUT("Auto-Negotiation did not complete\n");
> status = IXGBE_ERR_FC_NOT_NEGOTIATED;
> goto out;
> }
>
> /* Read the 10g AN autoc and LP ability registers and resolve
> * local flow control settings accordingly
> */
> status = hw->mac.ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
>
> if (status != IXGBE_SUCCESS) {
> DEBUGOUT("Auto-Negotiation did not complete\n");
> goto out;
> }
>
> status = hw->mac.ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
>
> if (status != IXGBE_SUCCESS) {
> DEBUGOUT("Auto-Negotiation did not complete\n");
> goto out;
> }
>
> status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
> IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
> IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
> IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
> IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
>
> out:
> if (status == IXGBE_SUCCESS) {
> hw->fc.fc_was_autonegged = TRUE;
> } else {
> hw->fc.fc_was_autonegged = FALSE;
> hw->fc.current_mode = hw->fc.requested_mode;
> }
> }
>
> /**
> * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
> * @hw: pointer to hardware structure
> *
> **/
> void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
> {
> hw->fc.fc_was_autonegged = FALSE;
> hw->fc.current_mode = hw->fc.requested_mode;
> }
>
> /**
> * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
> * @hw: pointer to hardware structure
> *
> * Enable flow control according to IEEE clause 37.
> **/
> void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
> {
> s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
> u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
> ixgbe_link_speed speed;
> bool link_up;
>
> /* AN should have completed when the cable was plugged in.
> * Look for reasons to bail out. Bail out if:
> * - FC autoneg is disabled, or if
> * - link is not up.
> */
> if (hw->fc.disable_fc_autoneg) {
> ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
> "Flow control autoneg is disabled");
> goto out;
> }
>
> hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
> if (!link_up) {
> ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
> goto out;
> }
>
> /* Check if auto-negotiation has completed */
> status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
> if (status != IXGBE_SUCCESS ||
> !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
> DEBUGOUT("Auto-Negotiation did not complete\n");
> status = IXGBE_ERR_FC_NOT_NEGOTIATED;
> goto out;
> }
>
> /* Negotiate the flow control */
> status = ixgbe_negotiate_fc(hw, info[0], info[0],
> FW_PHY_ACT_GET_LINK_INFO_FC_RX,
> FW_PHY_ACT_GET_LINK_INFO_FC_TX,
> FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
> FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
>
> out:
> if (status == IXGBE_SUCCESS) {
> hw->fc.fc_was_autonegged = TRUE;
> } else {
> hw->fc.fc_was_autonegged = FALSE;
> hw->fc.current_mode = hw->fc.requested_mode;
> }
> }
>
> /**
> * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
> * @hw: pointer to hardware structure
> *
> * Called at init time to set up flow control.
> **/
> s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
> {
> s32 status = IXGBE_SUCCESS;
> u32 an_cntl = 0;
>
> DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
>
> /* Validate the requested mode */
> if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
> ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
> "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
> return IXGBE_ERR_INVALID_LINK_SETTINGS;
> }
>
> if (hw->fc.requested_mode == ixgbe_fc_default)
> hw->fc.requested_mode = ixgbe_fc_full;
>
> /* Set up the 1G and 10G flow control advertisement registers so the
> * HW will be able to do FC autoneg once the cable is plugged in. If
> * we link at 10G, the 1G advertisement is harmless and vice versa.
> */
> status = hw->mac.ops.read_iosf_sb_reg(hw,
> IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
>
> if (status != IXGBE_SUCCESS) {
> DEBUGOUT("Auto-Negotiation did not complete\n");
> return status;
> }
>
> /* The possible values of fc.requested_mode are:
> * 0: Flow control is completely disabled
> * 1: Rx flow control is enabled (we can receive pause frames,
> * but not send pause frames).
> * 2: Tx flow control is enabled (we can send pause frames but
> * we do not support receiving pause frames).
> * 3: Both Rx and Tx flow control (symmetric) are enabled.
> * other: Invalid.
> */
> switch (hw->fc.requested_mode) {
> case ixgbe_fc_none:
> /* Flow control completely disabled by software override. */
> an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
> IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
> break;
> case ixgbe_fc_tx_pause:
> /* Tx Flow control is enabled, and Rx Flow control is
> * disabled by software override.
> */
> an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
> an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
> break;
> case ixgbe_fc_rx_pause:
> /* Rx Flow control is enabled and Tx Flow control is
> * disabled by software override. Since there really
> * isn't a way to advertise that we are capable of RX
> * Pause ONLY, we will advertise that we support both
> * symmetric and asymmetric Rx PAUSE, as such we fall
> * through to the fc_full statement. Later, we will
> * disable the adapter's ability to send PAUSE frames.
> */
> case ixgbe_fc_full:
> /* Flow control (both Rx and Tx) is enabled by SW override. */
> an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
> IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
> break;
> default:
> ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
> "Flow control param set incorrectly\n");
> return IXGBE_ERR_CONFIG;
> }
>
> status = hw->mac.ops.write_iosf_sb_reg(hw,
> IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
> IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
>
> /* Restart auto-negotiation. */
> status = ixgbe_restart_an_internal_phy_x550em(hw);
>
> return status;
> }
>
> /**
2966a4354,4480
> * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
> * @hw: pointer to hardware structure
> * @mask: Mask to specify which semaphore to acquire
> *
> * Acquires the SWFW semaphore and get the shared phy token as needed
> */
> static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
> {
> u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
> int retries = FW_PHY_TOKEN_RETRIES;
> s32 status = IXGBE_SUCCESS;
>
> DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
>
> while (--retries) {
> status = IXGBE_SUCCESS;
> if (hmask)
> status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
> if (status) {
> DEBUGOUT1("Could not acquire SWFW semaphore, Status = %d\n",
> status);
> return status;
> }
> if (!(mask & IXGBE_GSSR_TOKEN_SM))
> return IXGBE_SUCCESS;
>
> status = ixgbe_get_phy_token(hw);
> if (status == IXGBE_ERR_TOKEN_RETRY)
> DEBUGOUT1("Could not acquire PHY token, Status = %d\n",
> status);
>
> if (status == IXGBE_SUCCESS)
> return IXGBE_SUCCESS;
>
> if (hmask)
> ixgbe_release_swfw_sync_X540(hw, hmask);
>
> if (status != IXGBE_ERR_TOKEN_RETRY) {
> DEBUGOUT1("Unable to retry acquiring the PHY token, Status = %d\n",
> status);
> return status;
> }
> }
>
> DEBUGOUT1("Semaphore acquisition retries failed!: PHY ID = 0x%08X\n",
> hw->phy.id);
> return status;
> }
>
> /**
> * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
> * @hw: pointer to hardware structure
> * @mask: Mask to specify which semaphore to release
> *
> * Releases the SWFW semaphore and puts the shared phy token as needed
> */
> static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
> {
> u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
>
> DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
>
> if (mask & IXGBE_GSSR_TOKEN_SM)
> ixgbe_put_phy_token(hw);
>
> if (hmask)
> ixgbe_release_swfw_sync_X540(hw, hmask);
> }
>
> /**
> * ixgbe_read_phy_reg_x550a - Reads specified PHY register
> * @hw: pointer to hardware structure
> * @reg_addr: 32 bit address of PHY register to read
> * @phy_data: Pointer to read data from PHY register
> *
> * Reads a value from a specified PHY register using the SWFW lock and PHY
> * Token. The PHY Token is needed since the MDIO is shared between to MAC
> * instances.
> **/
> s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
> u32 device_type, u16 *phy_data)
> {
> s32 status;
> u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
>
> DEBUGFUNC("ixgbe_read_phy_reg_x550a");
>
> if (hw->mac.ops.acquire_swfw_sync(hw, mask))
> return IXGBE_ERR_SWFW_SYNC;
>
> status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
>
> hw->mac.ops.release_swfw_sync(hw, mask);
>
> return status;
> }
>
> /**
> * ixgbe_write_phy_reg_x550a - Writes specified PHY register
> * @hw: pointer to hardware structure
> * @reg_addr: 32 bit PHY register to write
> * @device_type: 5 bit device type
> * @phy_data: Data to write to the PHY register
> *
> * Writes a value to specified PHY register using the SWFW lock and PHY Token.
> * The PHY Token is needed since the MDIO is shared between to MAC instances.
> **/
> s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
> u32 device_type, u16 phy_data)
> {
> s32 status;
> u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
>
> DEBUGFUNC("ixgbe_write_phy_reg_x550a");
>
> if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
> status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
> phy_data);
> hw->mac.ops.release_swfw_sync(hw, mask);
> } else {
> status = IXGBE_ERR_SWFW_SYNC;
> }
>
> return status;
> }
>
> /**
3021,3022c4535,4538
< /* If internal link mode is XFI, then setup XFI internal link. */
< if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
---
> /* If X552 and internal link mode is XFI, then setup XFI internal link.
> */
> if (hw->mac.type == ixgbe_mac_X550EM_x &&
> !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3045c4561
< u16 autoneg_status;
---
> u16 i, autoneg_status = 0;
3058c4574,4576
< * Read this twice back to back to indicate current status.
---
> * X557 PHY. Link status is latching low, and can only be used to detect
> * link drop, and not the current status of the link without performing
> * back-to-back reads.
3060,3062c4578,4581
< status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
< IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
< &autoneg_status);
---
> for (i = 0; i < 2; i++) {
> status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
> IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
> &autoneg_status);
3064,3065c4583,4585
< if (status != IXGBE_SUCCESS)
< return status;
---
> if (status != IXGBE_SUCCESS)
> return status;
> }
3067,3073d4586
< status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
< IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
< &autoneg_status);
<
< if (status != IXGBE_SUCCESS)
< return status;
<
3119c4632,4633
< return IXGBE_SUCCESS;
---
> /* Some designs have the LEDs wired to the MAC */
> return ixgbe_led_on_generic(hw, led_idx);
3143c4657,4658
< return IXGBE_SUCCESS;
---
> /* Some designs have the LEDs wired to the MAC */
> return ixgbe_led_off_generic(hw, led_idx);
3145a4661,4720
> /**
> * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
> * @hw: pointer to the HW structure
> * @maj: driver version major number
> * @min: driver version minor number
> * @build: driver version build number
> * @sub: driver version sub build number
> * @len: length of driver_ver string
> * @driver_ver: driver string
> *
> * Sends driver version number to firmware through the manageability
> * block. On success return IXGBE_SUCCESS
> * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
> * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
> **/
> s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
> u8 build, u8 sub, u16 len, const char *driver_ver)
> {
> struct ixgbe_hic_drv_info2 fw_cmd;
> s32 ret_val = IXGBE_SUCCESS;
> int i;
>
> DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
>
> if ((len == 0) || (driver_ver == NULL) ||
> (len > sizeof(fw_cmd.driver_string)))
> return IXGBE_ERR_INVALID_ARGUMENT;
>
> fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
> fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
> fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
> fw_cmd.port_num = (u8)hw->bus.func;
> fw_cmd.ver_maj = maj;
> fw_cmd.ver_min = min;
> fw_cmd.ver_build = build;
> fw_cmd.ver_sub = sub;
> fw_cmd.hdr.checksum = 0;
> memcpy(fw_cmd.driver_string, driver_ver, len);
> fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
> (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
>
> for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
> ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
> sizeof(fw_cmd),
> IXGBE_HI_COMMAND_TIMEOUT,
> TRUE);
> if (ret_val != IXGBE_SUCCESS)
> continue;
>
> if (fw_cmd.hdr.cmd_or_resp.ret_status ==
> FW_CEM_RESP_STATUS_SUCCESS)
> ret_val = IXGBE_SUCCESS;
> else
> ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
>
> break;
> }
>
> return ret_val;
> }