1/******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_x550.c 295093 2016-01-31 15:14:23Z smh $*/
34
35#include "ixgbe_x550.h"
36#include "ixgbe_x540.h"
37#include "ixgbe_type.h"
38#include "ixgbe_api.h"
39#include "ixgbe_common.h"
40#include "ixgbe_phy.h"
41
42static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
43
44/**
45 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
46 * @hw: pointer to hardware structure
47 *
48 * Initialize the function pointers and assign the MAC type for X550.
49 * Does not touch the hardware.
50 **/
--- 4 unchanged lines hidden (view full) ---
55 s32 ret_val;
56
57 DEBUGFUNC("ixgbe_init_ops_X550");
58
59 ret_val = ixgbe_init_ops_X540(hw);
60 mac->ops.dmac_config = ixgbe_dmac_config_X550;
61 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
62 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
63 mac->ops.setup_eee = ixgbe_setup_eee_X550;
64 mac->ops.set_source_address_pruning =
65 ixgbe_set_source_address_pruning_X550;
66 mac->ops.set_ethertype_anti_spoofing =
67 ixgbe_set_ethertype_anti_spoofing_X550;
68
69 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
70 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
71 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
--- 4 unchanged lines hidden (view full) ---
76 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
77 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
78
79 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
80 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
81 mac->ops.mdd_event = ixgbe_mdd_event_X550;
82 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
83 mac->ops.disable_rx = ixgbe_disable_rx_x550;
84 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
85 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
86 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
87 }
88 return ret_val;
89}
90
91/**
92 * ixgbe_read_cs4227 - Read CS4227 register
93 * @hw: pointer to hardware structure
94 * @reg: register number to write
95 * @value: pointer to receive value read
96 *
97 * Returns status code
98 **/
99static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
100{
101 return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
102}
103
104/**
105 * ixgbe_write_cs4227 - Write CS4227 register
106 * @hw: pointer to hardware structure
107 * @reg: register number to write
108 * @value: value to write to register
109 *
110 * Returns status code
111 **/
112static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
113{
114 return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
115}
116
117/**
118 * ixgbe_read_pe - Read register from port expander
119 * @hw: pointer to hardware structure
120 * @reg: register number to read
121 * @value: pointer to receive read value
122 *
--- 195 unchanged lines hidden (view full) ---
318 esdp |= IXGBE_ESDP_SDP1_DIR;
319 }
320 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
321 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
322 IXGBE_WRITE_FLUSH(hw);
323}
324
325/**
326 * ixgbe_identify_phy_x550em - Get PHY type based on device id
327 * @hw: pointer to hardware structure
328 *
329 * Returns error code
330 */
331static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
332{
333 switch (hw->device_id) {
334 case IXGBE_DEV_ID_X550EM_X_SFP:
335 /* set up for CS4227 usage */
336 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
337 ixgbe_setup_mux_ctl(hw);
338 ixgbe_check_cs4227(hw);
339
340 return ixgbe_identify_module_generic(hw);
341 break;
342 case IXGBE_DEV_ID_X550EM_X_KX4:
343 hw->phy.type = ixgbe_phy_x550em_kx4;
344 break;
345 case IXGBE_DEV_ID_X550EM_X_KR:
346 hw->phy.type = ixgbe_phy_x550em_kr;
347 break;
348 case IXGBE_DEV_ID_X550EM_X_1G_T:
349 case IXGBE_DEV_ID_X550EM_X_10G_T:
350 return ixgbe_identify_phy_generic(hw);
351 default:
352 break;
353 }
354 return IXGBE_SUCCESS;
355}
356
357static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
358 u32 device_type, u16 *phy_data)
359{
360 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
361 return IXGBE_NOT_IMPLEMENTED;
362}
363
364static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
365 u32 device_type, u16 phy_data)
366{
367 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
368 return IXGBE_NOT_IMPLEMENTED;
369}
370
371/**
372* ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
373* @hw: pointer to hardware structure
374*
375* Initialize the function pointers and for MAC type X550EM.
376* Does not touch the hardware.
377**/
378s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
379{
--- 8 unchanged lines hidden (view full) ---
388 ret_val = ixgbe_init_ops_X550(hw);
389
390 /* Since this function eventually calls
391 * ixgbe_init_ops_540 by design, we are setting
392 * the pointers to NULL explicitly here to overwrite
393 * the values being set in the x540 function.
394 */
395
396 /* FCOE not supported in x550EM */
397 mac->ops.get_san_mac_addr = NULL;
398 mac->ops.set_san_mac_addr = NULL;
399 mac->ops.get_wwn_prefix = NULL;
400 mac->ops.get_fcoe_boot_status = NULL;
401
402 /* IPsec not supported in x550EM */
403 mac->ops.disable_sec_rx_path = NULL;
404 mac->ops.enable_sec_rx_path = NULL;
405
406 /* AUTOC register is not present in x550EM. */
407 mac->ops.prot_autoc_read = NULL;
408 mac->ops.prot_autoc_write = NULL;
409
410 /* X550EM bus type is internal*/
411 hw->bus.type = ixgbe_bus_type_internal;
412 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
413
414 if (hw->mac.type == ixgbe_mac_X550EM_x) {
415 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
416 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
417 }
418
419 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
420 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
421 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
422 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
423 mac->ops.get_supported_physical_layer =
424 ixgbe_get_supported_physical_layer_X550em;
425
426 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
427 mac->ops.setup_fc = ixgbe_setup_fc_generic;
428 else
429 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
430
431 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
432 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
433
434 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
435 mac->ops.setup_eee = NULL;
436
437 /* PHY */
438 phy->ops.init = ixgbe_init_phy_ops_X550em;
439 phy->ops.identify = ixgbe_identify_phy_x550em;
440 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
441 phy->ops.set_phy_power = NULL;
442
443
444 /* EEPROM */
445 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
446 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
447 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
448 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
449 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
450 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
451 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
452 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
453
454 return ret_val;
455}
456
457/**
458 * ixgbe_dmac_config_X550
459 * @hw: pointer to hardware structure
460 *
461 * Configure DMA coalescing. If enabling dmac, dmac is activated.
462 * When disabling dmac, dmac enable dmac bit is cleared.
463 **/
464s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
465{
--- 46 unchanged lines hidden (view full) ---
512s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
513{
514 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
515
516 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
517
518 /* Configure DMA coalescing enabled */
519 switch (hw->mac.dmac_config.link_speed) {
520 case IXGBE_LINK_SPEED_100_FULL:
521 pb_headroom = IXGBE_DMACRXT_100M;
522 break;
523 case IXGBE_LINK_SPEED_1GB_FULL:
524 pb_headroom = IXGBE_DMACRXT_1G;
525 break;
526 default:
527 pb_headroom = IXGBE_DMACRXT_10G;
--- 84 unchanged lines hidden (view full) ---
612 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
613 eeprom->type, eeprom->word_size);
614 }
615
616 return IXGBE_SUCCESS;
617}
618
619/**
620 * ixgbe_setup_eee_X550 - Enable/disable EEE support
621 * @hw: pointer to the HW structure
622 * @enable_eee: boolean flag to enable EEE
623 *
624 * Enable/disable EEE based on enable_eee flag.
625 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
626 * are modified.
627 *
628 **/
629s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
630{
631 u32 eeer;
632 u16 autoneg_eee_reg;
633 u32 link_reg;
634 s32 status;
635 u32 fuse;
636
637 DEBUGFUNC("ixgbe_setup_eee_X550");
638
639 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
640 /* Enable or disable EEE per flag */
641 if (enable_eee) {
642 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
643
644 if (hw->mac.type == ixgbe_mac_X550) {
645 /* Advertise EEE capability */
646 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
647 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
648
649 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
650 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
651 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
652
653 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
654 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
655 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
656 /* Not supported on first revision. */
657 fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
658 if (!(fuse & IXGBE_FUSES0_REV1))
659 return IXGBE_SUCCESS;
660
661 status = ixgbe_read_iosf_sb_reg_x550(hw,
662 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
663 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
664 if (status != IXGBE_SUCCESS)
665 return status;
666
667 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
668 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
669
670 /* Don't advertise FEC capability when EEE enabled. */
671 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
672
673 status = ixgbe_write_iosf_sb_reg_x550(hw,
674 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
675 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
676 if (status != IXGBE_SUCCESS)
677 return status;
678 }
679 } else {
680 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
681
682 if (hw->mac.type == ixgbe_mac_X550) {
683 /* Disable advertised EEE capability */
684 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
685 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
686
687 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
688 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
689 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
690
691 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
692 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
693 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
694 status = ixgbe_read_iosf_sb_reg_x550(hw,
695 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
696 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
697 if (status != IXGBE_SUCCESS)
698 return status;
699
700 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
701 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
702
703 /* Advertise FEC capability when EEE is disabled. */
704 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
705
706 status = ixgbe_write_iosf_sb_reg_x550(hw,
707 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
708 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
709 if (status != IXGBE_SUCCESS)
710 return status;
711 }
712 }
713 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
714
715 return IXGBE_SUCCESS;
716}
717
718/**
719 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
720 * @hw: pointer to hardware structure
721 * @enable: enable or disable source address pruning
722 * @pool: Rx pool to set source address pruning for
723 **/
724void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
725 unsigned int pool)
726{
--- 69 unchanged lines hidden (view full) ---
796 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
797 return IXGBE_ERR_PHY;
798 }
799
800 return IXGBE_SUCCESS;
801}
802
803/**
804 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
805 * device
806 * @hw: pointer to hardware structure
807 * @reg_addr: 32 bit PHY register to write
808 * @device_type: 3 bit device type
809 * @data: Data to write to the register
810 **/
811s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
812 u32 device_type, u32 data)
813{
--- 29 unchanged lines hidden (view full) ---
843 }
844
845out:
846 ixgbe_release_swfw_semaphore(hw, gssr);
847 return ret;
848}
849
850/**
851 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
852 * device
853 * @hw: pointer to hardware structure
854 * @reg_addr: 32 bit PHY register to write
855 * @device_type: 3 bit device type
856 * @phy_data: Pointer to read data from the register
857 **/
858s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
859 u32 device_type, u32 *data)
860{
861 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
862 u32 command, error;
863 s32 ret;
864
--- 25 unchanged lines hidden (view full) ---
890 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
891
892out:
893 ixgbe_release_swfw_semaphore(hw, gssr);
894 return ret;
895}
896
897/**
898 * ixgbe_disable_mdd_X550
899 * @hw: pointer to hardware structure
900 *
901 * Disable malicious driver detection
902 **/
903void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
904{
905 u32 reg;
--- 54 unchanged lines hidden (view full) ---
960 num_qs = 8; /* 16 VFs / pools */
961 bitmask = 0x000000FF;
962 break;
963 case IXGBE_MRQC_VMDQRSS32EN:
964 case IXGBE_MRQC_VMDQRT4TCEN:
965 num_qs = 4; /* 32 VFs / pools */
966 bitmask = 0x0000000F;
967 break;
968 default: /* 64 VFs / pools */
969 num_qs = 2;
970 bitmask = 0x00000003;
971 break;
972 }
973 start_q = vf * num_qs;
974
975 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
976 idx = start_q / 32;
--- 71 unchanged lines hidden (view full) ---
1048 enum ixgbe_media_type media_type;
1049
1050 DEBUGFUNC("ixgbe_get_media_type_X550em");
1051
1052 /* Detect if there is a copper PHY attached. */
1053 switch (hw->device_id) {
1054 case IXGBE_DEV_ID_X550EM_X_KR:
1055 case IXGBE_DEV_ID_X550EM_X_KX4:
1056 media_type = ixgbe_media_type_backplane;
1057 break;
1058 case IXGBE_DEV_ID_X550EM_X_SFP:
1059 media_type = ixgbe_media_type_fiber;
1060 break;
1061 case IXGBE_DEV_ID_X550EM_X_1G_T:
1062 case IXGBE_DEV_ID_X550EM_X_10G_T:
1063 media_type = ixgbe_media_type_copper;
1064 break;
1065 default:
1066 media_type = ixgbe_media_type_unknown;
1067 break;
1068 }
1069 return media_type;
1070}
1071
1072/**
--- 75 unchanged lines hidden (view full) ---
1148
1149 ixgbe_init_mac_link_ops_X550em(hw);
1150 hw->phy.ops.reset = NULL;
1151
1152 return IXGBE_SUCCESS;
1153}
1154
1155/**
1156 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1157 * @hw: pointer to hardware structure
1158 */
1159void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1160{
1161 struct ixgbe_mac_info *mac = &hw->mac;
1162
1163 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1164
1165 switch (hw->mac.ops.get_media_type(hw)) {
1166 case ixgbe_media_type_fiber:
1167 /* CS4227 does not support autoneg, so disable the laser control
1168 * functions for SFP+ fiber
1169 */
1170 mac->ops.disable_tx_laser = NULL;
1171 mac->ops.enable_tx_laser = NULL;
1172 mac->ops.flap_tx_laser = NULL;
1173 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1174 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1175 mac->ops.set_rate_select_speed =
1176 ixgbe_set_soft_rate_select_speed;
1177 break;
1178 case ixgbe_media_type_copper:
1179 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1180 mac->ops.check_link = ixgbe_check_link_t_X550em;
1181 break;
1182 default:
1183 break;
1184 }
1185}
1186
1187/**
1188 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1189 * @hw: pointer to hardware structure
1190 * @speed: pointer to link speed
1191 * @autoneg: TRUE when autoneg or autotry is enabled
1192 */
1193s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1194 ixgbe_link_speed *speed,
1195 bool *autoneg)
1196{
1197 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1198
1199 /* SFP */
1200 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1201
1202 /* CS4227 SFP must not enable auto-negotiation */
1203 *autoneg = FALSE;
1204
1205 /* Check if 1G SFP module. */
1206 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
--- 6 unchanged lines hidden (view full) ---
1213
1214 /* Link capabilities are based on SFP */
1215 if (hw->phy.multispeed_fiber)
1216 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1217 IXGBE_LINK_SPEED_1GB_FULL;
1218 else
1219 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1220 } else {
1221 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1222 IXGBE_LINK_SPEED_1GB_FULL;
1223 *autoneg = TRUE;
1224 }
1225
1226 return IXGBE_SUCCESS;
1227}
1228
1229/**
1230 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
--- 99 unchanged lines hidden (view full) ---
1330 u32 status;
1331 u16 reg;
1332 bool lsc;
1333
1334 /* Clear interrupt flags */
1335 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1336
1337 /* Enable link status change alarm */
1338 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1339 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1340
1341 if (status != IXGBE_SUCCESS)
1342 return status;
1343
1344 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1345
1346 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1347 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1348
1349 if (status != IXGBE_SUCCESS)
1350 return status;
1351
1352 /* Enables high temperature failure alarm */
1353 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1354 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1355 ®);
1356
1357 if (status != IXGBE_SUCCESS)
1358 return status;
1359
1360 reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1361
1362 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1363 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1364 reg);
1365
1366 if (status != IXGBE_SUCCESS)
1367 return status;
1368
--- 40 unchanged lines hidden (view full) ---
1409 * Configures the integrated KR PHY.
1410 **/
1411static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1412 ixgbe_link_speed speed)
1413{
1414 s32 status;
1415 u32 reg_val;
1416
1417 status = ixgbe_read_iosf_sb_reg_x550(hw,
1418 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1419 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1420 if (status)
1421 return status;
1422
1423 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1424 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1425 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1426
1427 /* Advertise 10G support. */
1428 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1429 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1430
1431 /* Advertise 1G support. */
1432 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1433 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1434
1435 /* Restart auto-negotiation. */
1436 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1437 status = ixgbe_write_iosf_sb_reg_x550(hw,
1438 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1439 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1440
1441 return status;
1442}
1443
1444/**
1445 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1446 * @hw: pointer to hardware structure
1447 *
1448 * Initialize any function pointers that were not able to be
1449 * set during init_shared_code because the PHY/SFP type was
1450 * not known. Perform the SFP init if necessary.
1451 */
1452s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1453{
1454 struct ixgbe_phy_info *phy = &hw->phy;
1455 ixgbe_link_speed speed;
1456 s32 ret_val;
1457
1458 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1459
1460 hw->mac.ops.set_lan_id(hw);
1461
1462 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1463 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1464 ixgbe_setup_mux_ctl(hw);
1465
1466 /* Save NW management interface connected on board. This is used
1467 * to determine internal PHY mode.
1468 */
1469 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1470 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1471 speed = IXGBE_LINK_SPEED_10GB_FULL |
1472 IXGBE_LINK_SPEED_1GB_FULL;
1473 }
1474 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1475 }
1476
1477 /* Identify the PHY or SFP module */
1478 ret_val = phy->ops.identify(hw);
1479 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1480 return ret_val;
1481
1482 /* Setup function pointers based on detected hardware */
1483 ixgbe_init_mac_link_ops_X550em(hw);
1484 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1485 phy->ops.reset = NULL;
1486
1487 /* Set functions pointers based on phy type */
1488 switch (hw->phy.type) {
1489 case ixgbe_phy_x550em_kx4:
1490 phy->ops.setup_link = NULL;
1491 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1492 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1493 break;
1494 case ixgbe_phy_x550em_kr:
1495 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1496 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1497 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1498 break;
1499 case ixgbe_phy_x550em_ext_t:
1500 /* Save NW management interface connected on board. This is used
1501 * to determine internal PHY mode
1502 */
1503 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1504
1505 /* If internal link mode is XFI, then setup iXFI internal link,
1506 * else setup KR now.
1507 */
1508 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1509 phy->ops.setup_internal_link =
1510 ixgbe_setup_internal_phy_t_x550em;
1511 } else {
1512 speed = IXGBE_LINK_SPEED_10GB_FULL |
1513 IXGBE_LINK_SPEED_1GB_FULL;
1514 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1515 }
1516
1517 /* setup SW LPLU only for first revision */
1518 if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
1519 IXGBE_FUSES0_GROUP(0))))
1520 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1521
1522 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1523 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1524 break;
1525 default:
1526 break;
1527 }
1528 return ret_val;
1529}
1530
1531/**
1532 * ixgbe_reset_hw_X550em - Perform hardware reset
1533 * @hw: pointer to hardware structure
1534 *
1535 * Resets the hardware by resetting the transmit and receive units, masks
1536 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1537 * reset.
1538 */
1539s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1540{
1541 ixgbe_link_speed link_speed;
1542 s32 status;
1543 u32 ctrl = 0;
1544 u32 i;
1545 u32 hlreg0;
1546 bool link_up = FALSE;
1547
1548 DEBUGFUNC("ixgbe_reset_hw_X550em");
1549
1550 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1551 status = hw->mac.ops.stop_adapter(hw);
1552 if (status != IXGBE_SUCCESS)
1553 return status;
1554
1555 /* flush pending Tx transactions */
1556 ixgbe_clear_tx_pending(hw);
1557
1558 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1559 /* Config MDIO clock speed before the first MDIO PHY access */
1560 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1561 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1562 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1563 }
1564
1565 /* PHY ops must be identified and initialized prior to reset */
1566 status = hw->phy.ops.init(hw);
1567
1568 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1569 return status;
1570
1571 /* start the external PHY */
1572 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1573 status = ixgbe_init_ext_t_x550em(hw);
1574 if (status)
1575 return status;
1576 }
1577
1578 /* Setup SFP module if there is one present. */
1579 if (hw->phy.sfp_setup_needed) {
1580 status = hw->mac.ops.setup_sfp(hw);
1581 hw->phy.sfp_setup_needed = FALSE;
1582 }
1583
1584 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1585 return status;
1586
1587 /* Reset PHY */
1588 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1589 hw->phy.ops.reset(hw);
1590
1591mac_reset_top:
1592 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1593 * If link reset is used when link is up, it might reset the PHY when
1594 * mng is using it. If link is down or the flag to force full link
1595 * reset is set, then perform link reset.
1596 */
1597 ctrl = IXGBE_CTRL_LNK_RST;
1598 if (!hw->force_full_reset) {
1599 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
1600 if (link_up)
1601 ctrl = IXGBE_CTRL_RST;
1602 }
1603
1604 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1605 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1606 IXGBE_WRITE_FLUSH(hw);
1607
1608 /* Poll for reset bit to self-clear meaning reset is complete */
1609 for (i = 0; i < 10; i++) {
1610 usec_delay(1);
1611 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1612 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1613 break;
1614 }
--- 19 unchanged lines hidden (view full) ---
1634
1635 /* Store MAC address from RAR0, clear receive address registers, and
1636 * clear the multicast table. Also reset num_rar_entries to 128,
1637 * since we modify this value when programming the SAN MAC address.
1638 */
1639 hw->mac.num_rar_entries = 128;
1640 hw->mac.ops.init_rx_addrs(hw);
1641
1642 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1643 ixgbe_setup_mux_ctl(hw);
1644
1645 return status;
1646}
1647
1648/**
1649 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1650 * @hw: pointer to hardware structure
1651 */
1652s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
--- 33 unchanged lines hidden (view full) ---
1686 }
1687
1688 return status;
1689}
1690
1691/**
1692 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1693 * @hw: pointer to hardware structure
1694 *
1695 * Configures the integrated KR PHY.
1696 **/
1697s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1698{
1699 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1700}
1701
1702/**
1703 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1704 * @hw: pointer to hardware structure
1705 *
1706 * Configure the external PHY and the integrated KR PHY for SFP support.
--- 15 unchanged lines hidden (view full) ---
1722 * not excepted in the setup MAC link flow.
1723 */
1724 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1725 return IXGBE_SUCCESS;
1726
1727 if (ret_val != IXGBE_SUCCESS)
1728 return ret_val;
1729
1730 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1731 /* Configure CS4227 LINE side to 10G SR. */
1732 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
1733 (hw->bus.lan_id << 12);
1734 reg_val = IXGBE_CS4227_SPEED_10G;
1735 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1736 reg_val);
1737
1738 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1739 (hw->bus.lan_id << 12);
1740 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1741 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1742 reg_val);
1743
1744 /* Configure CS4227 for HOST connection rate then type. */
1745 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
1746 (hw->bus.lan_id << 12);
1747 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
1748 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1749 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1750 reg_val);
1751
1752 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
1753 (hw->bus.lan_id << 12);
1754 if (setup_linear)
1755 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1756 else
1757 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1758 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1759 reg_val);
1760
1761 /* Setup XFI internal link. */
1762 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1763 } else {
1764 /* Configure internal PHY for KR/KX. */
1765 ixgbe_setup_kr_speed_x550em(hw, speed);
1766
1767 /* Configure CS4227 LINE side to proper mode. */
1768 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1769 (hw->bus.lan_id << 12);
1770 if (setup_linear)
1771 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1772 else
1773 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1774 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1775 reg_val);
1776 }
1777 return ret_val;
1778}
1779
1780/**
1781 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1782 * @hw: pointer to hardware structure
1783 * @speed: the link speed to force
1784 *
1785 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1786 * internal and external PHY at a specific speed, without autonegotiation.
1787 **/
1788static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1789{
1790 s32 status;
1791 u32 reg_val;
1792
1793 /* Disable AN and force speed to 10G Serial. */
1794 status = ixgbe_read_iosf_sb_reg_x550(hw,
1795 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1796 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1797 if (status != IXGBE_SUCCESS)
1798 return status;
1799
1800 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1801 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1802
1803 /* Select forced link speed for internal PHY. */
1804 switch (*speed) {
1805 case IXGBE_LINK_SPEED_10GB_FULL:
1806 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1807 break;
1808 case IXGBE_LINK_SPEED_1GB_FULL:
1809 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1810 break;
1811 default:
1812 /* Other link speeds are not supported by internal KR PHY. */
1813 return IXGBE_ERR_LINK_SETUP;
1814 }
1815
1816 status = ixgbe_write_iosf_sb_reg_x550(hw,
1817 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1818 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1819 if (status != IXGBE_SUCCESS)
1820 return status;
1821
1822 /* Disable training protocol FSM. */
1823 status = ixgbe_read_iosf_sb_reg_x550(hw,
1824 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1825 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1826 if (status != IXGBE_SUCCESS)
1827 return status;
1828 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1829 status = ixgbe_write_iosf_sb_reg_x550(hw,
1830 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1831 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1832 if (status != IXGBE_SUCCESS)
1833 return status;
1834
1835 /* Disable Flex from training TXFFE. */
1836 status = ixgbe_read_iosf_sb_reg_x550(hw,
1837 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1838 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1839 if (status != IXGBE_SUCCESS)
1840 return status;
1841 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1842 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1843 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1844 status = ixgbe_write_iosf_sb_reg_x550(hw,
1845 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1846 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1847 if (status != IXGBE_SUCCESS)
1848 return status;
1849 status = ixgbe_read_iosf_sb_reg_x550(hw,
1850 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1851 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1852 if (status != IXGBE_SUCCESS)
1853 return status;
1854 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1855 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1856 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1857 status = ixgbe_write_iosf_sb_reg_x550(hw,
1858 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1859 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1860 if (status != IXGBE_SUCCESS)
1861 return status;
1862
1863 /* Enable override for coefficients. */
1864 status = ixgbe_read_iosf_sb_reg_x550(hw,
1865 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1866 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1867 if (status != IXGBE_SUCCESS)
1868 return status;
1869 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1870 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1871 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1872 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1873 status = ixgbe_write_iosf_sb_reg_x550(hw,
1874 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1875 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1876 if (status != IXGBE_SUCCESS)
1877 return status;
1878
1879 /* Toggle port SW reset by AN reset. */
1880 status = ixgbe_read_iosf_sb_reg_x550(hw,
1881 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1882 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1883 if (status != IXGBE_SUCCESS)
1884 return status;
1885 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1886 status = ixgbe_write_iosf_sb_reg_x550(hw,
1887 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1888 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1889
1890 return status;
1891}
1892
1893/**
1894 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1895 * @hw: address of hardware structure
1896 * @link_up: address of boolean to indicate link status
1897 *
--- 41 unchanged lines hidden (view full) ---
1939 ixgbe_link_speed force_speed;
1940 bool link_up;
1941 u32 status;
1942 u16 speed;
1943
1944 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1945 return IXGBE_ERR_CONFIG;
1946
1947 /* If link is not up, then there is no setup necessary so return */
1948 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1949 if (status != IXGBE_SUCCESS)
1950 return status;
1951
1952 if (!link_up)
1953 return IXGBE_SUCCESS;
1954
1955 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1956 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1957 &speed);
1958 if (status != IXGBE_SUCCESS)
1959 return status;
1960
1961 /* If link is not still up, then no setup is necessary so return */
1962 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1963 if (status != IXGBE_SUCCESS)
1964 return status;
1965 if (!link_up)
1966 return IXGBE_SUCCESS;
1967
1968 /* clear everything but the speed and duplex bits */
1969 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1970
1971 switch (speed) {
1972 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1973 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1974 break;
1975 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1976 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1977 break;
1978 default:
1979 /* Internal PHY does not support anything else */
1980 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1981 }
1982
1983 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1984}
1985
1986/**
1987 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1988 * @hw: pointer to hardware structure
1989 *
1990 * Configures the integrated KR PHY to use internal loopback mode.
1991 **/
1992s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1993{
1994 s32 status;
1995 u32 reg_val;
1996
1997 /* Disable AN and force speed to 10G Serial. */
1998 status = ixgbe_read_iosf_sb_reg_x550(hw,
1999 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2000 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2001 if (status != IXGBE_SUCCESS)
2002 return status;
2003 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2004 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2005 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2006 status = ixgbe_write_iosf_sb_reg_x550(hw,
2007 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2008 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2009 if (status != IXGBE_SUCCESS)
2010 return status;
2011
2012 /* Set near-end loopback clocks. */
2013 status = ixgbe_read_iosf_sb_reg_x550(hw,
2014 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2015 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2016 if (status != IXGBE_SUCCESS)
2017 return status;
2018 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2019 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2020 status = ixgbe_write_iosf_sb_reg_x550(hw,
2021 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2022 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2023 if (status != IXGBE_SUCCESS)
2024 return status;
2025
2026 /* Set loopback enable. */
2027 status = ixgbe_read_iosf_sb_reg_x550(hw,
2028 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2029 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2030 if (status != IXGBE_SUCCESS)
2031 return status;
2032 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2033 status = ixgbe_write_iosf_sb_reg_x550(hw,
2034 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2035 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2036 if (status != IXGBE_SUCCESS)
2037 return status;
2038
2039 /* Training bypass. */
2040 status = ixgbe_read_iosf_sb_reg_x550(hw,
2041 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2042 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2043 if (status != IXGBE_SUCCESS)
2044 return status;
2045 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2046 status = ixgbe_write_iosf_sb_reg_x550(hw,
2047 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2048 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2049
2050 return status;
2051}
2052
2053/**
2054 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2055 * assuming that the semaphore is already obtained.
2056 * @hw: pointer to hardware structure
2057 * @offset: offset of word in the EEPROM to read
2058 * @data: word read from the EEPROM
2059 *
2060 * Reads a 16 bit word from the EEPROM using the hostif.
2061 **/
2062s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2063 u16 *data)
2064{
2065 s32 status;
2066 struct ixgbe_hic_read_shadow_ram buffer;
2067
2068 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2069 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2070 buffer.hdr.req.buf_lenh = 0;
2071 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2072 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2073
2074 /* convert offset from words to bytes */
2075 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2076 /* one word */
2077 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2078
2079 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2080 sizeof(buffer),
2081 IXGBE_HI_COMMAND_TIMEOUT, FALSE);
2082
2083 if (status)
2084 return status;
2085
2086 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2087 FW_NVM_DATA_OFFSET);
2088
2089 return 0;
2090}
2091
2092/**
2093 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2094 * @hw: pointer to hardware structure
2095 * @offset: offset of word in the EEPROM to read
2096 * @data: word read from the EEPROM
2097 *
2098 * Reads a 16 bit word from the EEPROM using the hostif.
2099 **/
2100s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2101 u16 *data)
2102{
2103 s32 status = IXGBE_SUCCESS;
2104
2105 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2106
2107 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2108 IXGBE_SUCCESS) {
2109 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2110 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2111 } else {
2112 status = IXGBE_ERR_SWFW_SYNC;
2113 }
2114
2115 return status;
2116}
2117
2118/**
2119 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2120 * @hw: pointer to hardware structure
2121 * @offset: offset of word in the EEPROM to read
2122 * @words: number of words
2123 * @data: word(s) read from the EEPROM
2124 *
2125 * Reads a 16 bit word(s) from the EEPROM using the hostif.
2126 **/
2127s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2128 u16 offset, u16 words, u16 *data)
2129{
2130 struct ixgbe_hic_read_shadow_ram buffer;
2131 u32 current_word = 0;
2132 u16 words_to_read;
2133 s32 status;
2134 u32 i;
2135
2136 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2137
2138 /* Take semaphore for the entire operation. */
2139 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2140 if (status) {
2141 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2142 return status;
2143 }
2144 while (words) {
2145 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2146 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2147 else
2148 words_to_read = words;
2149
2150 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2151 buffer.hdr.req.buf_lenh = 0;
2152 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2153 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2154
2155 /* convert offset from words to bytes */
2156 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2157 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2158
2159 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2160 sizeof(buffer),
2161 IXGBE_HI_COMMAND_TIMEOUT,
2162 FALSE);
2163
2164 if (status) {
2165 DEBUGOUT("Host interface command failed\n");
2166 goto out;
2167 }
2168
2169 for (i = 0; i < words_to_read; i++) {
2170 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
--- 8 unchanged lines hidden (view full) ---
2179 data[current_word] = (u16)(value & 0xffff);
2180 current_word++;
2181 }
2182 }
2183 words -= words_to_read;
2184 }
2185
2186out:
2187 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2188 return status;
2189}
2190
2191/**
2192 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2193 * @hw: pointer to hardware structure
2194 * @offset: offset of word in the EEPROM to write
2195 * @data: word write to the EEPROM
--- 376 unchanged lines hidden (view full) ---
2572}
2573
2574/**
2575 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2576 * @hw: pointer to hardware structure
2577 *
2578 * Determines physical layer capabilities of the current configuration.
2579 **/
2580u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2581{
2582 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2583 u16 ext_ability = 0;
2584
2585 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2586
2587 hw->phy.ops.identify(hw);
2588
2589 switch (hw->phy.type) {
2590 case ixgbe_phy_x550em_kr:
2591 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2592 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2593 break;
2594 case ixgbe_phy_x550em_kx4:
2595 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2596 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2597 break;
2598 case ixgbe_phy_x550em_ext_t:
2599 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2600 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2601 &ext_ability);
2602 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2603 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2604 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2605 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2606 break;
2607 default:
2608 break;
2609 }
2610
2611 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2612 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2613
2614 return physical_layer;
--- 75 unchanged lines hidden (view full) ---
2690{
2691 u16 an_10g_cntl_reg, autoneg_reg, speed;
2692 s32 status;
2693 ixgbe_link_speed lcd_speed;
2694 u32 save_autoneg;
2695 bool link_up;
2696
2697 /* SW LPLU not required on later HW revisions. */
2698 if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
2699 return IXGBE_SUCCESS;
2700
2701 /* If blocked by MNG FW, then don't restart AN */
2702 if (ixgbe_check_reset_blocked(hw))
2703 return IXGBE_SUCCESS;
2704
2705 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2706 if (status != IXGBE_SUCCESS)
--- 167 unchanged lines hidden (view full) ---
2874 break;
2875 default:
2876 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2877 "Flow control param set incorrectly\n");
2878 ret_val = IXGBE_ERR_CONFIG;
2879 goto out;
2880 }
2881
2882 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
2883 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2884 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2885 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2886 if (ret_val != IXGBE_SUCCESS)
2887 goto out;
2888 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2889 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2890 if (pause)
2891 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2892 if (asm_dir)
2893 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2894 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2895 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2896 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2897
2898 /* This device does not fully support AN. */
2899 hw->fc.disable_fc_autoneg = TRUE;
2900 }
2901
2902out:
2903 return ret_val;
2904}
2905
2906/**
2907 * ixgbe_set_mux - Set mux for port 1 access with CS4227
2908 * @hw: pointer to hardware structure
2909 * @state: set mux if 1, clear if 0
2910 */
2911static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2912{
2913 u32 esdp;
2914
--- 44 unchanged lines hidden (view full) ---
2959
2960 if (mask & IXGBE_GSSR_I2C_MASK)
2961 ixgbe_set_mux(hw, 0);
2962
2963 ixgbe_release_swfw_sync_X540(hw, mask);
2964}
2965
2966/**
2967 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2968 * @hw: pointer to hardware structure
2969 *
2970 * Handle external Base T PHY interrupt. If high temperature
2971 * failure alarm then return error, else if link status change
2972 * then setup internal/external PHY link
2973 *
2974 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
--- 38 unchanged lines hidden (view full) ---
3013 /* Setup internal/external PHY link speed to iXFI (10G), unless
3014 * only 1G is auto advertised then setup KX link.
3015 */
3016 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3017 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3018 else
3019 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3020
3021 /* If internal link mode is XFI, then setup XFI internal link. */
3022 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3023 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3024
3025 if (status != IXGBE_SUCCESS)
3026 return status;
3027 }
3028
3029 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3030}
--- 6 unchanged lines hidden (view full) ---
3037 * @link_up_wait_to_complete: bool used to wait for link up or not
3038 *
3039 * Check that both the MAC and X557 external PHY have link.
3040 **/
3041s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3042 bool *link_up, bool link_up_wait_to_complete)
3043{
3044 u32 status;
3045 u16 autoneg_status;
3046
3047 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3048 return IXGBE_ERR_CONFIG;
3049
3050 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3051 link_up_wait_to_complete);
3052
3053 /* If check link fails or MAC link is not up, then return */
3054 if (status != IXGBE_SUCCESS || !(*link_up))
3055 return status;
3056
3057 /* MAC link is up, so check external PHY link.
3058 * Read this twice back to back to indicate current status.
3059 */
3060 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3061 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3062 &autoneg_status);
3063
3064 if (status != IXGBE_SUCCESS)
3065 return status;
3066
3067 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3068 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3069 &autoneg_status);
3070
3071 if (status != IXGBE_SUCCESS)
3072 return status;
3073
3074 /* If external PHY link is not up, then indicate link not up */
3075 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3076 *link_up = FALSE;
3077
3078 return IXGBE_SUCCESS;
3079}
3080
3081/**
--- 29 unchanged lines hidden (view full) ---
3111
3112 /* To turn on the LED, set mode to ON. */
3113 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3114 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3115 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3116 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3117 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3118
3119 return IXGBE_SUCCESS;
3120}
3121
3122/**
3123 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3124 * @hw: pointer to hardware structure
3125 * @led_idx: led number to turn off
3126 **/
3127s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
--- 7 unchanged lines hidden (view full) ---
3135
3136 /* To turn on the LED, set mode to ON. */
3137 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3138 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3139 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3140 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3141 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3142
3143 return IXGBE_SUCCESS;
3144}
3145
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_x550.c 295093 2016-01-31 15:14:23Z smh $*/
34
35#include "ixgbe_x550.h"
36#include "ixgbe_x540.h"
37#include "ixgbe_type.h"
38#include "ixgbe_api.h"
39#include "ixgbe_common.h"
40#include "ixgbe_phy.h"
41
42static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
43
44/**
45 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
46 * @hw: pointer to hardware structure
47 *
48 * Initialize the function pointers and assign the MAC type for X550.
49 * Does not touch the hardware.
50 **/
--- 4 unchanged lines hidden (view full) ---
55 s32 ret_val;
56
57 DEBUGFUNC("ixgbe_init_ops_X550");
58
59 ret_val = ixgbe_init_ops_X540(hw);
60 mac->ops.dmac_config = ixgbe_dmac_config_X550;
61 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
62 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
63 mac->ops.setup_eee = ixgbe_setup_eee_X550;
64 mac->ops.set_source_address_pruning =
65 ixgbe_set_source_address_pruning_X550;
66 mac->ops.set_ethertype_anti_spoofing =
67 ixgbe_set_ethertype_anti_spoofing_X550;
68
69 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
70 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
71 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
--- 4 unchanged lines hidden (view full) ---
76 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
77 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
78
79 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
80 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
81 mac->ops.mdd_event = ixgbe_mdd_event_X550;
82 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
83 mac->ops.disable_rx = ixgbe_disable_rx_x550;
84 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
85 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
86 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
87 }
88 return ret_val;
89}
90
91/**
92 * ixgbe_read_cs4227 - Read CS4227 register
93 * @hw: pointer to hardware structure
94 * @reg: register number to write
95 * @value: pointer to receive value read
96 *
97 * Returns status code
98 **/
99static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
100{
101 return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
102}
103
104/**
105 * ixgbe_write_cs4227 - Write CS4227 register
106 * @hw: pointer to hardware structure
107 * @reg: register number to write
108 * @value: value to write to register
109 *
110 * Returns status code
111 **/
112static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
113{
114 return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
115}
116
117/**
118 * ixgbe_read_pe - Read register from port expander
119 * @hw: pointer to hardware structure
120 * @reg: register number to read
121 * @value: pointer to receive read value
122 *
--- 195 unchanged lines hidden (view full) ---
318 esdp |= IXGBE_ESDP_SDP1_DIR;
319 }
320 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
321 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
322 IXGBE_WRITE_FLUSH(hw);
323}
324
325/**
326 * ixgbe_identify_phy_x550em - Get PHY type based on device id
327 * @hw: pointer to hardware structure
328 *
329 * Returns error code
330 */
331static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
332{
333 switch (hw->device_id) {
334 case IXGBE_DEV_ID_X550EM_X_SFP:
335 /* set up for CS4227 usage */
336 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
337 ixgbe_setup_mux_ctl(hw);
338 ixgbe_check_cs4227(hw);
339
340 return ixgbe_identify_module_generic(hw);
341 break;
342 case IXGBE_DEV_ID_X550EM_X_KX4:
343 hw->phy.type = ixgbe_phy_x550em_kx4;
344 break;
345 case IXGBE_DEV_ID_X550EM_X_KR:
346 hw->phy.type = ixgbe_phy_x550em_kr;
347 break;
348 case IXGBE_DEV_ID_X550EM_X_1G_T:
349 case IXGBE_DEV_ID_X550EM_X_10G_T:
350 return ixgbe_identify_phy_generic(hw);
351 default:
352 break;
353 }
354 return IXGBE_SUCCESS;
355}
356
357static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
358 u32 device_type, u16 *phy_data)
359{
360 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
361 return IXGBE_NOT_IMPLEMENTED;
362}
363
364static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
365 u32 device_type, u16 phy_data)
366{
367 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
368 return IXGBE_NOT_IMPLEMENTED;
369}
370
371/**
372* ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
373* @hw: pointer to hardware structure
374*
375* Initialize the function pointers and for MAC type X550EM.
376* Does not touch the hardware.
377**/
378s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
379{
--- 8 unchanged lines hidden (view full) ---
388 ret_val = ixgbe_init_ops_X550(hw);
389
390 /* Since this function eventually calls
391 * ixgbe_init_ops_540 by design, we are setting
392 * the pointers to NULL explicitly here to overwrite
393 * the values being set in the x540 function.
394 */
395
396 /* FCOE not supported in x550EM */
397 mac->ops.get_san_mac_addr = NULL;
398 mac->ops.set_san_mac_addr = NULL;
399 mac->ops.get_wwn_prefix = NULL;
400 mac->ops.get_fcoe_boot_status = NULL;
401
402 /* IPsec not supported in x550EM */
403 mac->ops.disable_sec_rx_path = NULL;
404 mac->ops.enable_sec_rx_path = NULL;
405
406 /* AUTOC register is not present in x550EM. */
407 mac->ops.prot_autoc_read = NULL;
408 mac->ops.prot_autoc_write = NULL;
409
410 /* X550EM bus type is internal*/
411 hw->bus.type = ixgbe_bus_type_internal;
412 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
413
414 if (hw->mac.type == ixgbe_mac_X550EM_x) {
415 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
416 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
417 }
418
419 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
420 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
421 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
422 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
423 mac->ops.get_supported_physical_layer =
424 ixgbe_get_supported_physical_layer_X550em;
425
426 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
427 mac->ops.setup_fc = ixgbe_setup_fc_generic;
428 else
429 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
430
431 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
432 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
433
434 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
435 mac->ops.setup_eee = NULL;
436
437 /* PHY */
438 phy->ops.init = ixgbe_init_phy_ops_X550em;
439 phy->ops.identify = ixgbe_identify_phy_x550em;
440 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
441 phy->ops.set_phy_power = NULL;
442
443
444 /* EEPROM */
445 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
446 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
447 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
448 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
449 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
450 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
451 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
452 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
453
454 return ret_val;
455}
456
457/**
458 * ixgbe_dmac_config_X550
459 * @hw: pointer to hardware structure
460 *
461 * Configure DMA coalescing. If enabling dmac, dmac is activated.
462 * When disabling dmac, dmac enable dmac bit is cleared.
463 **/
464s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
465{
--- 46 unchanged lines hidden (view full) ---
512s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
513{
514 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
515
516 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
517
518 /* Configure DMA coalescing enabled */
519 switch (hw->mac.dmac_config.link_speed) {
520 case IXGBE_LINK_SPEED_100_FULL:
521 pb_headroom = IXGBE_DMACRXT_100M;
522 break;
523 case IXGBE_LINK_SPEED_1GB_FULL:
524 pb_headroom = IXGBE_DMACRXT_1G;
525 break;
526 default:
527 pb_headroom = IXGBE_DMACRXT_10G;
--- 84 unchanged lines hidden (view full) ---
612 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
613 eeprom->type, eeprom->word_size);
614 }
615
616 return IXGBE_SUCCESS;
617}
618
619/**
620 * ixgbe_setup_eee_X550 - Enable/disable EEE support
621 * @hw: pointer to the HW structure
622 * @enable_eee: boolean flag to enable EEE
623 *
624 * Enable/disable EEE based on enable_eee flag.
625 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
626 * are modified.
627 *
628 **/
629s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
630{
631 u32 eeer;
632 u16 autoneg_eee_reg;
633 u32 link_reg;
634 s32 status;
635 u32 fuse;
636
637 DEBUGFUNC("ixgbe_setup_eee_X550");
638
639 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
640 /* Enable or disable EEE per flag */
641 if (enable_eee) {
642 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
643
644 if (hw->mac.type == ixgbe_mac_X550) {
645 /* Advertise EEE capability */
646 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
647 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
648
649 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
650 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
651 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
652
653 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
654 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
655 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
656 /* Not supported on first revision. */
657 fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
658 if (!(fuse & IXGBE_FUSES0_REV1))
659 return IXGBE_SUCCESS;
660
661 status = ixgbe_read_iosf_sb_reg_x550(hw,
662 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
663 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
664 if (status != IXGBE_SUCCESS)
665 return status;
666
667 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
668 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
669
670 /* Don't advertise FEC capability when EEE enabled. */
671 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
672
673 status = ixgbe_write_iosf_sb_reg_x550(hw,
674 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
675 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
676 if (status != IXGBE_SUCCESS)
677 return status;
678 }
679 } else {
680 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
681
682 if (hw->mac.type == ixgbe_mac_X550) {
683 /* Disable advertised EEE capability */
684 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
685 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
686
687 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
688 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
689 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
690
691 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
692 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
693 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
694 status = ixgbe_read_iosf_sb_reg_x550(hw,
695 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
696 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
697 if (status != IXGBE_SUCCESS)
698 return status;
699
700 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
701 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
702
703 /* Advertise FEC capability when EEE is disabled. */
704 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
705
706 status = ixgbe_write_iosf_sb_reg_x550(hw,
707 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
708 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
709 if (status != IXGBE_SUCCESS)
710 return status;
711 }
712 }
713 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
714
715 return IXGBE_SUCCESS;
716}
717
718/**
719 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
720 * @hw: pointer to hardware structure
721 * @enable: enable or disable source address pruning
722 * @pool: Rx pool to set source address pruning for
723 **/
724void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
725 unsigned int pool)
726{
--- 69 unchanged lines hidden (view full) ---
796 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
797 return IXGBE_ERR_PHY;
798 }
799
800 return IXGBE_SUCCESS;
801}
802
803/**
804 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
805 * device
806 * @hw: pointer to hardware structure
807 * @reg_addr: 32 bit PHY register to write
808 * @device_type: 3 bit device type
809 * @data: Data to write to the register
810 **/
811s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
812 u32 device_type, u32 data)
813{
--- 29 unchanged lines hidden (view full) ---
843 }
844
845out:
846 ixgbe_release_swfw_semaphore(hw, gssr);
847 return ret;
848}
849
850/**
851 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
852 * device
853 * @hw: pointer to hardware structure
854 * @reg_addr: 32 bit PHY register to write
855 * @device_type: 3 bit device type
856 * @phy_data: Pointer to read data from the register
857 **/
858s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
859 u32 device_type, u32 *data)
860{
861 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
862 u32 command, error;
863 s32 ret;
864
--- 25 unchanged lines hidden (view full) ---
890 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
891
892out:
893 ixgbe_release_swfw_semaphore(hw, gssr);
894 return ret;
895}
896
897/**
898 * ixgbe_disable_mdd_X550
899 * @hw: pointer to hardware structure
900 *
901 * Disable malicious driver detection
902 **/
903void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
904{
905 u32 reg;
--- 54 unchanged lines hidden (view full) ---
960 num_qs = 8; /* 16 VFs / pools */
961 bitmask = 0x000000FF;
962 break;
963 case IXGBE_MRQC_VMDQRSS32EN:
964 case IXGBE_MRQC_VMDQRT4TCEN:
965 num_qs = 4; /* 32 VFs / pools */
966 bitmask = 0x0000000F;
967 break;
968 default: /* 64 VFs / pools */
969 num_qs = 2;
970 bitmask = 0x00000003;
971 break;
972 }
973 start_q = vf * num_qs;
974
975 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
976 idx = start_q / 32;
--- 71 unchanged lines hidden (view full) ---
1048 enum ixgbe_media_type media_type;
1049
1050 DEBUGFUNC("ixgbe_get_media_type_X550em");
1051
1052 /* Detect if there is a copper PHY attached. */
1053 switch (hw->device_id) {
1054 case IXGBE_DEV_ID_X550EM_X_KR:
1055 case IXGBE_DEV_ID_X550EM_X_KX4:
1056 media_type = ixgbe_media_type_backplane;
1057 break;
1058 case IXGBE_DEV_ID_X550EM_X_SFP:
1059 media_type = ixgbe_media_type_fiber;
1060 break;
1061 case IXGBE_DEV_ID_X550EM_X_1G_T:
1062 case IXGBE_DEV_ID_X550EM_X_10G_T:
1063 media_type = ixgbe_media_type_copper;
1064 break;
1065 default:
1066 media_type = ixgbe_media_type_unknown;
1067 break;
1068 }
1069 return media_type;
1070}
1071
1072/**
--- 75 unchanged lines hidden (view full) ---
1148
1149 ixgbe_init_mac_link_ops_X550em(hw);
1150 hw->phy.ops.reset = NULL;
1151
1152 return IXGBE_SUCCESS;
1153}
1154
1155/**
1156 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1157 * @hw: pointer to hardware structure
1158 */
1159void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1160{
1161 struct ixgbe_mac_info *mac = &hw->mac;
1162
1163 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1164
1165 switch (hw->mac.ops.get_media_type(hw)) {
1166 case ixgbe_media_type_fiber:
1167 /* CS4227 does not support autoneg, so disable the laser control
1168 * functions for SFP+ fiber
1169 */
1170 mac->ops.disable_tx_laser = NULL;
1171 mac->ops.enable_tx_laser = NULL;
1172 mac->ops.flap_tx_laser = NULL;
1173 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1174 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1175 mac->ops.set_rate_select_speed =
1176 ixgbe_set_soft_rate_select_speed;
1177 break;
1178 case ixgbe_media_type_copper:
1179 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1180 mac->ops.check_link = ixgbe_check_link_t_X550em;
1181 break;
1182 default:
1183 break;
1184 }
1185}
1186
1187/**
1188 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1189 * @hw: pointer to hardware structure
1190 * @speed: pointer to link speed
1191 * @autoneg: TRUE when autoneg or autotry is enabled
1192 */
1193s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1194 ixgbe_link_speed *speed,
1195 bool *autoneg)
1196{
1197 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1198
1199 /* SFP */
1200 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1201
1202 /* CS4227 SFP must not enable auto-negotiation */
1203 *autoneg = FALSE;
1204
1205 /* Check if 1G SFP module. */
1206 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
--- 6 unchanged lines hidden (view full) ---
1213
1214 /* Link capabilities are based on SFP */
1215 if (hw->phy.multispeed_fiber)
1216 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1217 IXGBE_LINK_SPEED_1GB_FULL;
1218 else
1219 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1220 } else {
1221 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1222 IXGBE_LINK_SPEED_1GB_FULL;
1223 *autoneg = TRUE;
1224 }
1225
1226 return IXGBE_SUCCESS;
1227}
1228
1229/**
1230 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
--- 99 unchanged lines hidden (view full) ---
1330 u32 status;
1331 u16 reg;
1332 bool lsc;
1333
1334 /* Clear interrupt flags */
1335 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1336
1337 /* Enable link status change alarm */
1338 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1339 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1340
1341 if (status != IXGBE_SUCCESS)
1342 return status;
1343
1344 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1345
1346 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1347 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1348
1349 if (status != IXGBE_SUCCESS)
1350 return status;
1351
1352 /* Enables high temperature failure alarm */
1353 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1354 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1355 ®);
1356
1357 if (status != IXGBE_SUCCESS)
1358 return status;
1359
1360 reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1361
1362 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1363 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1364 reg);
1365
1366 if (status != IXGBE_SUCCESS)
1367 return status;
1368
--- 40 unchanged lines hidden (view full) ---
1409 * Configures the integrated KR PHY.
1410 **/
1411static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1412 ixgbe_link_speed speed)
1413{
1414 s32 status;
1415 u32 reg_val;
1416
1417 status = ixgbe_read_iosf_sb_reg_x550(hw,
1418 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1419 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1420 if (status)
1421 return status;
1422
1423 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1424 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1425 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1426
1427 /* Advertise 10G support. */
1428 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1429 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1430
1431 /* Advertise 1G support. */
1432 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1433 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1434
1435 /* Restart auto-negotiation. */
1436 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1437 status = ixgbe_write_iosf_sb_reg_x550(hw,
1438 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1439 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1440
1441 return status;
1442}
1443
1444/**
1445 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1446 * @hw: pointer to hardware structure
1447 *
1448 * Initialize any function pointers that were not able to be
1449 * set during init_shared_code because the PHY/SFP type was
1450 * not known. Perform the SFP init if necessary.
1451 */
1452s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1453{
1454 struct ixgbe_phy_info *phy = &hw->phy;
1455 ixgbe_link_speed speed;
1456 s32 ret_val;
1457
1458 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1459
1460 hw->mac.ops.set_lan_id(hw);
1461
1462 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1463 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1464 ixgbe_setup_mux_ctl(hw);
1465
1466 /* Save NW management interface connected on board. This is used
1467 * to determine internal PHY mode.
1468 */
1469 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1470 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1471 speed = IXGBE_LINK_SPEED_10GB_FULL |
1472 IXGBE_LINK_SPEED_1GB_FULL;
1473 }
1474 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1475 }
1476
1477 /* Identify the PHY or SFP module */
1478 ret_val = phy->ops.identify(hw);
1479 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1480 return ret_val;
1481
1482 /* Setup function pointers based on detected hardware */
1483 ixgbe_init_mac_link_ops_X550em(hw);
1484 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1485 phy->ops.reset = NULL;
1486
1487 /* Set functions pointers based on phy type */
1488 switch (hw->phy.type) {
1489 case ixgbe_phy_x550em_kx4:
1490 phy->ops.setup_link = NULL;
1491 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1492 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1493 break;
1494 case ixgbe_phy_x550em_kr:
1495 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1496 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1497 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1498 break;
1499 case ixgbe_phy_x550em_ext_t:
1500 /* Save NW management interface connected on board. This is used
1501 * to determine internal PHY mode
1502 */
1503 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1504
1505 /* If internal link mode is XFI, then setup iXFI internal link,
1506 * else setup KR now.
1507 */
1508 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1509 phy->ops.setup_internal_link =
1510 ixgbe_setup_internal_phy_t_x550em;
1511 } else {
1512 speed = IXGBE_LINK_SPEED_10GB_FULL |
1513 IXGBE_LINK_SPEED_1GB_FULL;
1514 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1515 }
1516
1517 /* setup SW LPLU only for first revision */
1518 if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
1519 IXGBE_FUSES0_GROUP(0))))
1520 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1521
1522 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1523 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1524 break;
1525 default:
1526 break;
1527 }
1528 return ret_val;
1529}
1530
1531/**
1532 * ixgbe_reset_hw_X550em - Perform hardware reset
1533 * @hw: pointer to hardware structure
1534 *
1535 * Resets the hardware by resetting the transmit and receive units, masks
1536 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1537 * reset.
1538 */
1539s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1540{
1541 ixgbe_link_speed link_speed;
1542 s32 status;
1543 u32 ctrl = 0;
1544 u32 i;
1545 u32 hlreg0;
1546 bool link_up = FALSE;
1547
1548 DEBUGFUNC("ixgbe_reset_hw_X550em");
1549
1550 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1551 status = hw->mac.ops.stop_adapter(hw);
1552 if (status != IXGBE_SUCCESS)
1553 return status;
1554
1555 /* flush pending Tx transactions */
1556 ixgbe_clear_tx_pending(hw);
1557
1558 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1559 /* Config MDIO clock speed before the first MDIO PHY access */
1560 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1561 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1562 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1563 }
1564
1565 /* PHY ops must be identified and initialized prior to reset */
1566 status = hw->phy.ops.init(hw);
1567
1568 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1569 return status;
1570
1571 /* start the external PHY */
1572 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1573 status = ixgbe_init_ext_t_x550em(hw);
1574 if (status)
1575 return status;
1576 }
1577
1578 /* Setup SFP module if there is one present. */
1579 if (hw->phy.sfp_setup_needed) {
1580 status = hw->mac.ops.setup_sfp(hw);
1581 hw->phy.sfp_setup_needed = FALSE;
1582 }
1583
1584 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1585 return status;
1586
1587 /* Reset PHY */
1588 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1589 hw->phy.ops.reset(hw);
1590
1591mac_reset_top:
1592 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1593 * If link reset is used when link is up, it might reset the PHY when
1594 * mng is using it. If link is down or the flag to force full link
1595 * reset is set, then perform link reset.
1596 */
1597 ctrl = IXGBE_CTRL_LNK_RST;
1598 if (!hw->force_full_reset) {
1599 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
1600 if (link_up)
1601 ctrl = IXGBE_CTRL_RST;
1602 }
1603
1604 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1605 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1606 IXGBE_WRITE_FLUSH(hw);
1607
1608 /* Poll for reset bit to self-clear meaning reset is complete */
1609 for (i = 0; i < 10; i++) {
1610 usec_delay(1);
1611 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1612 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1613 break;
1614 }
--- 19 unchanged lines hidden (view full) ---
1634
1635 /* Store MAC address from RAR0, clear receive address registers, and
1636 * clear the multicast table. Also reset num_rar_entries to 128,
1637 * since we modify this value when programming the SAN MAC address.
1638 */
1639 hw->mac.num_rar_entries = 128;
1640 hw->mac.ops.init_rx_addrs(hw);
1641
1642 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1643 ixgbe_setup_mux_ctl(hw);
1644
1645 return status;
1646}
1647
1648/**
1649 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1650 * @hw: pointer to hardware structure
1651 */
1652s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
--- 33 unchanged lines hidden (view full) ---
1686 }
1687
1688 return status;
1689}
1690
1691/**
1692 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1693 * @hw: pointer to hardware structure
1694 *
1695 * Configures the integrated KR PHY.
1696 **/
1697s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1698{
1699 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1700}
1701
1702/**
1703 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1704 * @hw: pointer to hardware structure
1705 *
1706 * Configure the external PHY and the integrated KR PHY for SFP support.
--- 15 unchanged lines hidden (view full) ---
1722 * not excepted in the setup MAC link flow.
1723 */
1724 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1725 return IXGBE_SUCCESS;
1726
1727 if (ret_val != IXGBE_SUCCESS)
1728 return ret_val;
1729
1730 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1731 /* Configure CS4227 LINE side to 10G SR. */
1732 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
1733 (hw->bus.lan_id << 12);
1734 reg_val = IXGBE_CS4227_SPEED_10G;
1735 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1736 reg_val);
1737
1738 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1739 (hw->bus.lan_id << 12);
1740 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1741 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1742 reg_val);
1743
1744 /* Configure CS4227 for HOST connection rate then type. */
1745 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
1746 (hw->bus.lan_id << 12);
1747 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
1748 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1749 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1750 reg_val);
1751
1752 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
1753 (hw->bus.lan_id << 12);
1754 if (setup_linear)
1755 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1756 else
1757 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1758 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1759 reg_val);
1760
1761 /* Setup XFI internal link. */
1762 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1763 } else {
1764 /* Configure internal PHY for KR/KX. */
1765 ixgbe_setup_kr_speed_x550em(hw, speed);
1766
1767 /* Configure CS4227 LINE side to proper mode. */
1768 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1769 (hw->bus.lan_id << 12);
1770 if (setup_linear)
1771 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1772 else
1773 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1774 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1775 reg_val);
1776 }
1777 return ret_val;
1778}
1779
1780/**
1781 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1782 * @hw: pointer to hardware structure
1783 * @speed: the link speed to force
1784 *
1785 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1786 * internal and external PHY at a specific speed, without autonegotiation.
1787 **/
1788static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1789{
1790 s32 status;
1791 u32 reg_val;
1792
1793 /* Disable AN and force speed to 10G Serial. */
1794 status = ixgbe_read_iosf_sb_reg_x550(hw,
1795 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1796 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1797 if (status != IXGBE_SUCCESS)
1798 return status;
1799
1800 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1801 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1802
1803 /* Select forced link speed for internal PHY. */
1804 switch (*speed) {
1805 case IXGBE_LINK_SPEED_10GB_FULL:
1806 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1807 break;
1808 case IXGBE_LINK_SPEED_1GB_FULL:
1809 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1810 break;
1811 default:
1812 /* Other link speeds are not supported by internal KR PHY. */
1813 return IXGBE_ERR_LINK_SETUP;
1814 }
1815
1816 status = ixgbe_write_iosf_sb_reg_x550(hw,
1817 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1818 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1819 if (status != IXGBE_SUCCESS)
1820 return status;
1821
1822 /* Disable training protocol FSM. */
1823 status = ixgbe_read_iosf_sb_reg_x550(hw,
1824 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1825 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1826 if (status != IXGBE_SUCCESS)
1827 return status;
1828 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1829 status = ixgbe_write_iosf_sb_reg_x550(hw,
1830 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1831 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1832 if (status != IXGBE_SUCCESS)
1833 return status;
1834
1835 /* Disable Flex from training TXFFE. */
1836 status = ixgbe_read_iosf_sb_reg_x550(hw,
1837 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1838 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1839 if (status != IXGBE_SUCCESS)
1840 return status;
1841 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1842 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1843 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1844 status = ixgbe_write_iosf_sb_reg_x550(hw,
1845 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1846 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1847 if (status != IXGBE_SUCCESS)
1848 return status;
1849 status = ixgbe_read_iosf_sb_reg_x550(hw,
1850 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1851 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1852 if (status != IXGBE_SUCCESS)
1853 return status;
1854 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1855 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1856 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1857 status = ixgbe_write_iosf_sb_reg_x550(hw,
1858 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1859 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1860 if (status != IXGBE_SUCCESS)
1861 return status;
1862
1863 /* Enable override for coefficients. */
1864 status = ixgbe_read_iosf_sb_reg_x550(hw,
1865 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1866 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1867 if (status != IXGBE_SUCCESS)
1868 return status;
1869 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1870 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1871 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1872 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1873 status = ixgbe_write_iosf_sb_reg_x550(hw,
1874 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1875 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1876 if (status != IXGBE_SUCCESS)
1877 return status;
1878
1879 /* Toggle port SW reset by AN reset. */
1880 status = ixgbe_read_iosf_sb_reg_x550(hw,
1881 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1882 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1883 if (status != IXGBE_SUCCESS)
1884 return status;
1885 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1886 status = ixgbe_write_iosf_sb_reg_x550(hw,
1887 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1888 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1889
1890 return status;
1891}
1892
1893/**
1894 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1895 * @hw: address of hardware structure
1896 * @link_up: address of boolean to indicate link status
1897 *
--- 41 unchanged lines hidden (view full) ---
1939 ixgbe_link_speed force_speed;
1940 bool link_up;
1941 u32 status;
1942 u16 speed;
1943
1944 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1945 return IXGBE_ERR_CONFIG;
1946
1947 /* If link is not up, then there is no setup necessary so return */
1948 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1949 if (status != IXGBE_SUCCESS)
1950 return status;
1951
1952 if (!link_up)
1953 return IXGBE_SUCCESS;
1954
1955 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1956 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1957 &speed);
1958 if (status != IXGBE_SUCCESS)
1959 return status;
1960
1961 /* If link is not still up, then no setup is necessary so return */
1962 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1963 if (status != IXGBE_SUCCESS)
1964 return status;
1965 if (!link_up)
1966 return IXGBE_SUCCESS;
1967
1968 /* clear everything but the speed and duplex bits */
1969 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1970
1971 switch (speed) {
1972 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1973 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1974 break;
1975 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1976 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1977 break;
1978 default:
1979 /* Internal PHY does not support anything else */
1980 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1981 }
1982
1983 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1984}
1985
1986/**
1987 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1988 * @hw: pointer to hardware structure
1989 *
1990 * Configures the integrated KR PHY to use internal loopback mode.
1991 **/
1992s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1993{
1994 s32 status;
1995 u32 reg_val;
1996
1997 /* Disable AN and force speed to 10G Serial. */
1998 status = ixgbe_read_iosf_sb_reg_x550(hw,
1999 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2000 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2001 if (status != IXGBE_SUCCESS)
2002 return status;
2003 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2004 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2005 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2006 status = ixgbe_write_iosf_sb_reg_x550(hw,
2007 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2008 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2009 if (status != IXGBE_SUCCESS)
2010 return status;
2011
2012 /* Set near-end loopback clocks. */
2013 status = ixgbe_read_iosf_sb_reg_x550(hw,
2014 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2015 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2016 if (status != IXGBE_SUCCESS)
2017 return status;
2018 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2019 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2020 status = ixgbe_write_iosf_sb_reg_x550(hw,
2021 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2022 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2023 if (status != IXGBE_SUCCESS)
2024 return status;
2025
2026 /* Set loopback enable. */
2027 status = ixgbe_read_iosf_sb_reg_x550(hw,
2028 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2029 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2030 if (status != IXGBE_SUCCESS)
2031 return status;
2032 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2033 status = ixgbe_write_iosf_sb_reg_x550(hw,
2034 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2035 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2036 if (status != IXGBE_SUCCESS)
2037 return status;
2038
2039 /* Training bypass. */
2040 status = ixgbe_read_iosf_sb_reg_x550(hw,
2041 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2042 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2043 if (status != IXGBE_SUCCESS)
2044 return status;
2045 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2046 status = ixgbe_write_iosf_sb_reg_x550(hw,
2047 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2048 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2049
2050 return status;
2051}
2052
2053/**
2054 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2055 * assuming that the semaphore is already obtained.
2056 * @hw: pointer to hardware structure
2057 * @offset: offset of word in the EEPROM to read
2058 * @data: word read from the EEPROM
2059 *
2060 * Reads a 16 bit word from the EEPROM using the hostif.
2061 **/
2062s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2063 u16 *data)
2064{
2065 s32 status;
2066 struct ixgbe_hic_read_shadow_ram buffer;
2067
2068 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2069 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2070 buffer.hdr.req.buf_lenh = 0;
2071 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2072 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2073
2074 /* convert offset from words to bytes */
2075 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2076 /* one word */
2077 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2078
2079 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2080 sizeof(buffer),
2081 IXGBE_HI_COMMAND_TIMEOUT, FALSE);
2082
2083 if (status)
2084 return status;
2085
2086 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2087 FW_NVM_DATA_OFFSET);
2088
2089 return 0;
2090}
2091
2092/**
2093 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2094 * @hw: pointer to hardware structure
2095 * @offset: offset of word in the EEPROM to read
2096 * @data: word read from the EEPROM
2097 *
2098 * Reads a 16 bit word from the EEPROM using the hostif.
2099 **/
2100s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2101 u16 *data)
2102{
2103 s32 status = IXGBE_SUCCESS;
2104
2105 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2106
2107 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2108 IXGBE_SUCCESS) {
2109 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2110 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2111 } else {
2112 status = IXGBE_ERR_SWFW_SYNC;
2113 }
2114
2115 return status;
2116}
2117
2118/**
2119 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2120 * @hw: pointer to hardware structure
2121 * @offset: offset of word in the EEPROM to read
2122 * @words: number of words
2123 * @data: word(s) read from the EEPROM
2124 *
2125 * Reads a 16 bit word(s) from the EEPROM using the hostif.
2126 **/
2127s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2128 u16 offset, u16 words, u16 *data)
2129{
2130 struct ixgbe_hic_read_shadow_ram buffer;
2131 u32 current_word = 0;
2132 u16 words_to_read;
2133 s32 status;
2134 u32 i;
2135
2136 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2137
2138 /* Take semaphore for the entire operation. */
2139 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2140 if (status) {
2141 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2142 return status;
2143 }
2144 while (words) {
2145 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2146 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2147 else
2148 words_to_read = words;
2149
2150 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2151 buffer.hdr.req.buf_lenh = 0;
2152 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2153 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2154
2155 /* convert offset from words to bytes */
2156 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2157 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2158
2159 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2160 sizeof(buffer),
2161 IXGBE_HI_COMMAND_TIMEOUT,
2162 FALSE);
2163
2164 if (status) {
2165 DEBUGOUT("Host interface command failed\n");
2166 goto out;
2167 }
2168
2169 for (i = 0; i < words_to_read; i++) {
2170 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
--- 8 unchanged lines hidden (view full) ---
2179 data[current_word] = (u16)(value & 0xffff);
2180 current_word++;
2181 }
2182 }
2183 words -= words_to_read;
2184 }
2185
2186out:
2187 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2188 return status;
2189}
2190
2191/**
2192 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2193 * @hw: pointer to hardware structure
2194 * @offset: offset of word in the EEPROM to write
2195 * @data: word write to the EEPROM
--- 376 unchanged lines hidden (view full) ---
2572}
2573
2574/**
2575 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2576 * @hw: pointer to hardware structure
2577 *
2578 * Determines physical layer capabilities of the current configuration.
2579 **/
2580u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2581{
2582 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2583 u16 ext_ability = 0;
2584
2585 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2586
2587 hw->phy.ops.identify(hw);
2588
2589 switch (hw->phy.type) {
2590 case ixgbe_phy_x550em_kr:
2591 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2592 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2593 break;
2594 case ixgbe_phy_x550em_kx4:
2595 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2596 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2597 break;
2598 case ixgbe_phy_x550em_ext_t:
2599 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2600 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2601 &ext_ability);
2602 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2603 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2604 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2605 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2606 break;
2607 default:
2608 break;
2609 }
2610
2611 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2612 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2613
2614 return physical_layer;
--- 75 unchanged lines hidden (view full) ---
2690{
2691 u16 an_10g_cntl_reg, autoneg_reg, speed;
2692 s32 status;
2693 ixgbe_link_speed lcd_speed;
2694 u32 save_autoneg;
2695 bool link_up;
2696
2697 /* SW LPLU not required on later HW revisions. */
2698 if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
2699 return IXGBE_SUCCESS;
2700
2701 /* If blocked by MNG FW, then don't restart AN */
2702 if (ixgbe_check_reset_blocked(hw))
2703 return IXGBE_SUCCESS;
2704
2705 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2706 if (status != IXGBE_SUCCESS)
--- 167 unchanged lines hidden (view full) ---
2874 break;
2875 default:
2876 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2877 "Flow control param set incorrectly\n");
2878 ret_val = IXGBE_ERR_CONFIG;
2879 goto out;
2880 }
2881
2882 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
2883 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2884 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2885 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2886 if (ret_val != IXGBE_SUCCESS)
2887 goto out;
2888 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2889 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2890 if (pause)
2891 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2892 if (asm_dir)
2893 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2894 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2895 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2896 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2897
2898 /* This device does not fully support AN. */
2899 hw->fc.disable_fc_autoneg = TRUE;
2900 }
2901
2902out:
2903 return ret_val;
2904}
2905
2906/**
2907 * ixgbe_set_mux - Set mux for port 1 access with CS4227
2908 * @hw: pointer to hardware structure
2909 * @state: set mux if 1, clear if 0
2910 */
2911static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2912{
2913 u32 esdp;
2914
--- 44 unchanged lines hidden (view full) ---
2959
2960 if (mask & IXGBE_GSSR_I2C_MASK)
2961 ixgbe_set_mux(hw, 0);
2962
2963 ixgbe_release_swfw_sync_X540(hw, mask);
2964}
2965
2966/**
2967 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2968 * @hw: pointer to hardware structure
2969 *
2970 * Handle external Base T PHY interrupt. If high temperature
2971 * failure alarm then return error, else if link status change
2972 * then setup internal/external PHY link
2973 *
2974 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
--- 38 unchanged lines hidden (view full) ---
3013 /* Setup internal/external PHY link speed to iXFI (10G), unless
3014 * only 1G is auto advertised then setup KX link.
3015 */
3016 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3017 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3018 else
3019 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3020
3021 /* If internal link mode is XFI, then setup XFI internal link. */
3022 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3023 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3024
3025 if (status != IXGBE_SUCCESS)
3026 return status;
3027 }
3028
3029 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3030}
--- 6 unchanged lines hidden (view full) ---
3037 * @link_up_wait_to_complete: bool used to wait for link up or not
3038 *
3039 * Check that both the MAC and X557 external PHY have link.
3040 **/
3041s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3042 bool *link_up, bool link_up_wait_to_complete)
3043{
3044 u32 status;
3045 u16 autoneg_status;
3046
3047 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3048 return IXGBE_ERR_CONFIG;
3049
3050 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3051 link_up_wait_to_complete);
3052
3053 /* If check link fails or MAC link is not up, then return */
3054 if (status != IXGBE_SUCCESS || !(*link_up))
3055 return status;
3056
3057 /* MAC link is up, so check external PHY link.
3058 * Read this twice back to back to indicate current status.
3059 */
3060 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3061 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3062 &autoneg_status);
3063
3064 if (status != IXGBE_SUCCESS)
3065 return status;
3066
3067 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3068 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3069 &autoneg_status);
3070
3071 if (status != IXGBE_SUCCESS)
3072 return status;
3073
3074 /* If external PHY link is not up, then indicate link not up */
3075 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3076 *link_up = FALSE;
3077
3078 return IXGBE_SUCCESS;
3079}
3080
3081/**
--- 29 unchanged lines hidden (view full) ---
3111
3112 /* To turn on the LED, set mode to ON. */
3113 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3114 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3115 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3116 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3117 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3118
3119 return IXGBE_SUCCESS;
3120}
3121
3122/**
3123 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3124 * @hw: pointer to hardware structure
3125 * @led_idx: led number to turn off
3126 **/
3127s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
--- 7 unchanged lines hidden (view full) ---
3135
3136 /* To turn on the LED, set mode to ON. */
3137 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3138 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3139 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3140 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3141 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3142
3143 return IXGBE_SUCCESS;
3144}
3145