Deleted Added
sdiff udiff text old ( 302408 ) new ( 320897 )
full compact
ixgbe_x540.c (302408) ixgbe_x540.c (320897)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
3 Copyright (c) 2001-2017, Intel Corporation
4 All rights reserved.
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
18 this software without specific prior written permission.
19
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_x540.c 295093 2016-01-31 15:14:23Z smh $*/
33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_x540.c 320897 2017-07-11 21:25:07Z erj $*/
34
35#include "ixgbe_x540.h"
36#include "ixgbe_type.h"
37#include "ixgbe_api.h"
38#include "ixgbe_common.h"
39#include "ixgbe_phy.h"
40
41#define IXGBE_X540_MAX_TX_QUEUES 128

--- 53 unchanged lines hidden (view full) ---

95 mac->ops.start_hw = ixgbe_start_hw_X540;
96 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
97 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
98 mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
99 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
100 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
101 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540;
102 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540;
34
35#include "ixgbe_x540.h"
36#include "ixgbe_type.h"
37#include "ixgbe_api.h"
38#include "ixgbe_common.h"
39#include "ixgbe_phy.h"
40
41#define IXGBE_X540_MAX_TX_QUEUES 128

--- 53 unchanged lines hidden (view full) ---

95 mac->ops.start_hw = ixgbe_start_hw_X540;
96 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
97 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
98 mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
99 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
100 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
101 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540;
102 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540;
103 mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540;
103 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
104 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
105
106 /* RAR, Multicast, VLAN */
107 mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
108 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
109 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
110 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;

--- 6 unchanged lines hidden (view full) ---

117 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
118
119 /* Link */
120 mac->ops.get_link_capabilities =
121 ixgbe_get_copper_link_capabilities_generic;
122 mac->ops.setup_link = ixgbe_setup_mac_link_X540;
123 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
124 mac->ops.check_link = ixgbe_check_mac_link_generic;
104 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
105 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
106
107 /* RAR, Multicast, VLAN */
108 mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
109 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
110 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
111 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;

--- 6 unchanged lines hidden (view full) ---

118 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
119
120 /* Link */
121 mac->ops.get_link_capabilities =
122 ixgbe_get_copper_link_capabilities_generic;
123 mac->ops.setup_link = ixgbe_setup_mac_link_X540;
124 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
125 mac->ops.check_link = ixgbe_check_mac_link_generic;
126 mac->ops.bypass_rw = ixgbe_bypass_rw_generic;
127 mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic;
128 mac->ops.bypass_set = ixgbe_bypass_set_generic;
129 mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic;
125
126
127 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
128 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
129 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
130 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
131 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
132 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;

--- 70 unchanged lines hidden (view full) ---

203 *
204 * Resets the hardware by resetting the transmit and receive units, masks
205 * and clears all interrupts, and perform a reset.
206 **/
207s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
208{
209 s32 status;
210 u32 ctrl, i;
130
131
132 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
133 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
134 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
135 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
136 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
137 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;

--- 70 unchanged lines hidden (view full) ---

208 *
209 * Resets the hardware by resetting the transmit and receive units, masks
210 * and clears all interrupts, and perform a reset.
211 **/
212s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
213{
214 s32 status;
215 u32 ctrl, i;
216 u32 swfw_mask = hw->phy.phy_semaphore_mask;
211
212 DEBUGFUNC("ixgbe_reset_hw_X540");
213
214 /* Call adapter stop to disable tx/rx and clear interrupts */
215 status = hw->mac.ops.stop_adapter(hw);
216 if (status != IXGBE_SUCCESS)
217 goto reset_hw_out;
218
219 /* flush pending Tx transactions */
220 ixgbe_clear_tx_pending(hw);
221
222mac_reset_top:
217
218 DEBUGFUNC("ixgbe_reset_hw_X540");
219
220 /* Call adapter stop to disable tx/rx and clear interrupts */
221 status = hw->mac.ops.stop_adapter(hw);
222 if (status != IXGBE_SUCCESS)
223 goto reset_hw_out;
224
225 /* flush pending Tx transactions */
226 ixgbe_clear_tx_pending(hw);
227
228mac_reset_top:
229 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
230 if (status != IXGBE_SUCCESS) {
231 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
232 "semaphore failed with %d", status);
233 return IXGBE_ERR_SWFW_SYNC;
234 }
223 ctrl = IXGBE_CTRL_RST;
224 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
225 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
226 IXGBE_WRITE_FLUSH(hw);
235 ctrl = IXGBE_CTRL_RST;
236 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
237 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
238 IXGBE_WRITE_FLUSH(hw);
239 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
227
228 /* Poll for reset bit to self-clear indicating reset is complete */
229 for (i = 0; i < 10; i++) {
230 usec_delay(1);
231 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
232 if (!(ctrl & IXGBE_CTRL_RST_MASK))
233 break;
234 }

--- 29 unchanged lines hidden (view full) ---

264 hw->mac.num_rar_entries = 128;
265 hw->mac.ops.init_rx_addrs(hw);
266
267 /* Store the permanent SAN mac address */
268 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
269
270 /* Add the SAN MAC address to the RAR only if it's a valid address */
271 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
240
241 /* Poll for reset bit to self-clear indicating reset is complete */
242 for (i = 0; i < 10; i++) {
243 usec_delay(1);
244 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
245 if (!(ctrl & IXGBE_CTRL_RST_MASK))
246 break;
247 }

--- 29 unchanged lines hidden (view full) ---

277 hw->mac.num_rar_entries = 128;
278 hw->mac.ops.init_rx_addrs(hw);
279
280 /* Store the permanent SAN mac address */
281 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
282
283 /* Add the SAN MAC address to the RAR only if it's a valid address */
284 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
272 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
273 hw->mac.san_addr, 0, IXGBE_RAH_AV);
274
275 /* Save the SAN MAC RAR index */
276 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
277
285 /* Save the SAN MAC RAR index */
286 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
287
288 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
289 hw->mac.san_addr, 0, IXGBE_RAH_AV);
290
291 /* clear VMDq pool/queue selection for this RAR */
292 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
293 IXGBE_CLEAR_VMDQ_ALL);
294
278 /* Reserve the last RAR for the SAN MAC address */
279 hw->mac.num_rar_entries--;
280 }
281
282 /* Store the alternative WWNN/WWPN prefix */
283 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
284 &hw->mac.wwpn_prefix);
285

--- 26 unchanged lines hidden (view full) ---

312}
313
314/**
315 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
316 * @hw: pointer to hardware structure
317 *
318 * Determines physical layer capabilities of the current configuration.
319 **/
295 /* Reserve the last RAR for the SAN MAC address */
296 hw->mac.num_rar_entries--;
297 }
298
299 /* Store the alternative WWNN/WWPN prefix */
300 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
301 &hw->mac.wwpn_prefix);
302

--- 26 unchanged lines hidden (view full) ---

329}
330
331/**
332 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
333 * @hw: pointer to hardware structure
334 *
335 * Determines physical layer capabilities of the current configuration.
336 **/
320u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
337u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
321{
338{
322 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
339 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
323 u16 ext_ability = 0;
324
325 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
326
327 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
328 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
329 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
330 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;

--- 151 unchanged lines hidden (view full) ---

482 **/
483s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
484{
485 u16 i, j;
486 u16 checksum = 0;
487 u16 length = 0;
488 u16 pointer = 0;
489 u16 word = 0;
340 u16 ext_ability = 0;
341
342 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
343
344 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
345 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
346 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
347 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;

--- 151 unchanged lines hidden (view full) ---

499 **/
500s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
501{
502 u16 i, j;
503 u16 checksum = 0;
504 u16 length = 0;
505 u16 pointer = 0;
506 u16 word = 0;
490 u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
491 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
492
493 /* Do not use hw->eeprom.ops.read because we do not want to take
494 * the synchronization semaphores here. Instead use
495 * ixgbe_read_eerd_generic
496 */
497
498 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
499
507 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
508
509 /* Do not use hw->eeprom.ops.read because we do not want to take
510 * the synchronization semaphores here. Instead use
511 * ixgbe_read_eerd_generic
512 */
513
514 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
515
500 /* Include 0x0-0x3F in the checksum */
501 for (i = 0; i <= checksum_last_word; i++) {
516 /* Include 0x0 up to IXGBE_EEPROM_CHECKSUM; do not include the
517 * checksum itself
518 */
519 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
502 if (ixgbe_read_eerd_generic(hw, i, &word)) {
503 DEBUGOUT("EEPROM read failed\n");
504 return IXGBE_ERR_EEPROM;
505 }
520 if (ixgbe_read_eerd_generic(hw, i, &word)) {
521 DEBUGOUT("EEPROM read failed\n");
522 return IXGBE_ERR_EEPROM;
523 }
506 if (i != IXGBE_EEPROM_CHECKSUM)
507 checksum += word;
524 checksum += word;
508 }
509
510 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
511 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
512 */
513 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
514 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
515 continue;

--- 250 unchanged lines hidden (view full) ---

766 swmask |= IXGBE_GSSR_SW_MNG_SM;
767
768 swmask |= swi2c_mask;
769 fwmask |= swi2c_mask << 2;
770 for (i = 0; i < timeout; i++) {
771 /* SW NVM semaphore bit is used for access to all
772 * SW_FW_SYNC bits (not just NVM)
773 */
525 }
526
527 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
528 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
529 */
530 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
531 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
532 continue;

--- 250 unchanged lines hidden (view full) ---

783 swmask |= IXGBE_GSSR_SW_MNG_SM;
784
785 swmask |= swi2c_mask;
786 fwmask |= swi2c_mask << 2;
787 for (i = 0; i < timeout; i++) {
788 /* SW NVM semaphore bit is used for access to all
789 * SW_FW_SYNC bits (not just NVM)
790 */
774 if (ixgbe_get_swfw_sync_semaphore(hw))
791 if (ixgbe_get_swfw_sync_semaphore(hw)) {
792 DEBUGOUT("Failed to get NVM access and register semaphore, returning IXGBE_ERR_SWFW_SYNC\n");
775 return IXGBE_ERR_SWFW_SYNC;
793 return IXGBE_ERR_SWFW_SYNC;
794 }
776
777 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
778 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
779 swfw_sync |= swmask;
780 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw),
781 swfw_sync);
782 ixgbe_release_swfw_sync_semaphore(hw);
795
796 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
797 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
798 swfw_sync |= swmask;
799 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw),
800 swfw_sync);
801 ixgbe_release_swfw_sync_semaphore(hw);
783 msec_delay(5);
784 return IXGBE_SUCCESS;
785 }
786 /* Firmware currently using resource (fwmask), hardware
787 * currently using resource (hwmask), or other software
788 * thread currently using resource (swmask)
789 */
790 ixgbe_release_swfw_sync_semaphore(hw);
791 msec_delay(5);
792 }
793
802 return IXGBE_SUCCESS;
803 }
804 /* Firmware currently using resource (fwmask), hardware
805 * currently using resource (hwmask), or other software
806 * thread currently using resource (swmask)
807 */
808 ixgbe_release_swfw_sync_semaphore(hw);
809 msec_delay(5);
810 }
811
794 /* Failed to get SW only semaphore */
795 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
796 ERROR_REPORT1(IXGBE_ERROR_POLLING,
797 "Failed to get SW only semaphore");
798 return IXGBE_ERR_SWFW_SYNC;
799 }
800
801 /* If the resource is not released by the FW/HW the SW can assume that
802 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
803 * of the requested resource(s) while ignoring the corresponding FW/HW
804 * bits in the SW_FW_SYNC register.
805 */
812 /* If the resource is not released by the FW/HW the SW can assume that
813 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
814 * of the requested resource(s) while ignoring the corresponding FW/HW
815 * bits in the SW_FW_SYNC register.
816 */
806 if (ixgbe_get_swfw_sync_semaphore(hw))
817 if (ixgbe_get_swfw_sync_semaphore(hw)) {
818 DEBUGOUT("Failed to get NVM sempahore and register semaphore while forcefully ignoring FW sempahore bit(s) and setting SW semaphore bit(s), returning IXGBE_ERR_SWFW_SYNC\n");
807 return IXGBE_ERR_SWFW_SYNC;
819 return IXGBE_ERR_SWFW_SYNC;
820 }
808 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
809 if (swfw_sync & (fwmask | hwmask)) {
810 swfw_sync |= swmask;
811 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
812 ixgbe_release_swfw_sync_semaphore(hw);
813 msec_delay(5);
814 return IXGBE_SUCCESS;
815 }
816 /* If the resource is not released by other SW the SW can assume that
817 * the other SW malfunctions. In that case the SW should clear all SW
818 * flags that it does not own and then repeat the whole process once
819 * again.
820 */
821 if (swfw_sync & swmask) {
822 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
821 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
822 if (swfw_sync & (fwmask | hwmask)) {
823 swfw_sync |= swmask;
824 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
825 ixgbe_release_swfw_sync_semaphore(hw);
826 msec_delay(5);
827 return IXGBE_SUCCESS;
828 }
829 /* If the resource is not released by other SW the SW can assume that
830 * the other SW malfunctions. In that case the SW should clear all SW
831 * flags that it does not own and then repeat the whole process once
832 * again.
833 */
834 if (swfw_sync & swmask) {
835 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
823 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM;
836 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
837 IXGBE_GSSR_SW_MNG_SM;
824
825 if (swi2c_mask)
826 rmask |= IXGBE_GSSR_I2C_MASK;
827 ixgbe_release_swfw_sync_X540(hw, rmask);
828 ixgbe_release_swfw_sync_semaphore(hw);
838
839 if (swi2c_mask)
840 rmask |= IXGBE_GSSR_I2C_MASK;
841 ixgbe_release_swfw_sync_X540(hw, rmask);
842 ixgbe_release_swfw_sync_semaphore(hw);
843 DEBUGOUT("Resource not released by other SW, returning IXGBE_ERR_SWFW_SYNC\n");
829 return IXGBE_ERR_SWFW_SYNC;
830 }
831 ixgbe_release_swfw_sync_semaphore(hw);
844 return IXGBE_ERR_SWFW_SYNC;
845 }
846 ixgbe_release_swfw_sync_semaphore(hw);
847 DEBUGOUT("Returning error IXGBE_ERR_SWFW_SYNC\n");
832
833 return IXGBE_ERR_SWFW_SYNC;
834}
835
836/**
837 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
838 * @hw: pointer to hardware structure
839 * @mask: Mask to specify which semaphore to release

--- 12 unchanged lines hidden (view full) ---

852 swmask |= mask & IXGBE_GSSR_I2C_MASK;
853 ixgbe_get_swfw_sync_semaphore(hw);
854
855 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
856 swfw_sync &= ~swmask;
857 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
858
859 ixgbe_release_swfw_sync_semaphore(hw);
848
849 return IXGBE_ERR_SWFW_SYNC;
850}
851
852/**
853 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
854 * @hw: pointer to hardware structure
855 * @mask: Mask to specify which semaphore to release

--- 12 unchanged lines hidden (view full) ---

868 swmask |= mask & IXGBE_GSSR_I2C_MASK;
869 ixgbe_get_swfw_sync_semaphore(hw);
870
871 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
872 swfw_sync &= ~swmask;
873 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
874
875 ixgbe_release_swfw_sync_semaphore(hw);
860 msec_delay(5);
876 msec_delay(2);
861}
862
863/**
864 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
865 * @hw: pointer to hardware structure
866 *
867 * Sets the hardware semaphores so SW/FW can gain control of shared resources
868 **/

--- 70 unchanged lines hidden (view full) ---

939 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
940 swsm &= ~IXGBE_SWSM_SMBI;
941 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
942
943 IXGBE_WRITE_FLUSH(hw);
944}
945
946/**
877}
878
879/**
880 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
881 * @hw: pointer to hardware structure
882 *
883 * Sets the hardware semaphores so SW/FW can gain control of shared resources
884 **/

--- 70 unchanged lines hidden (view full) ---

955 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
956 swsm &= ~IXGBE_SWSM_SMBI;
957 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
958
959 IXGBE_WRITE_FLUSH(hw);
960}
961
962/**
963 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore
964 * @hw: pointer to hardware structure
965 *
966 * This function reset hardware semaphore bits for a semaphore that may
967 * have be left locked due to a catastrophic failure.
968 **/
969void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
970{
971 u32 rmask;
972
973 /* First try to grab the semaphore but we don't need to bother
974 * looking to see whether we got the lock or not since we do
975 * the same thing regardless of whether we got the lock or not.
976 * We got the lock - we release it.
977 * We timeout trying to get the lock - we force its release.
978 */
979 ixgbe_get_swfw_sync_semaphore(hw);
980 ixgbe_release_swfw_sync_semaphore(hw);
981
982 /* Acquire and release all software resources. */
983 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
984 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
985 IXGBE_GSSR_SW_MNG_SM;
986
987 rmask |= IXGBE_GSSR_I2C_MASK;
988 ixgbe_acquire_swfw_sync_X540(hw, rmask);
989 ixgbe_release_swfw_sync_X540(hw, rmask);
990}
991
992/**
947 * ixgbe_blink_led_start_X540 - Blink LED based on index.
948 * @hw: pointer to hardware structure
949 * @index: led number to blink
950 *
951 * Devices that implement the version 2 interface:
952 * X540
953 **/
954s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
955{
956 u32 macc_reg;
957 u32 ledctl_reg;
958 ixgbe_link_speed speed;
959 bool link_up;
960
961 DEBUGFUNC("ixgbe_blink_led_start_X540");
962
993 * ixgbe_blink_led_start_X540 - Blink LED based on index.
994 * @hw: pointer to hardware structure
995 * @index: led number to blink
996 *
997 * Devices that implement the version 2 interface:
998 * X540
999 **/
1000s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
1001{
1002 u32 macc_reg;
1003 u32 ledctl_reg;
1004 ixgbe_link_speed speed;
1005 bool link_up;
1006
1007 DEBUGFUNC("ixgbe_blink_led_start_X540");
1008
1009 if (index > 3)
1010 return IXGBE_ERR_PARAM;
1011
963 /*
964 * Link should be up in order for the blink bit in the LED control
965 * register to work. Force link and speed in the MAC if link is down.
966 * This will be reversed when we stop the blinking.
967 */
968 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
969 if (link_up == FALSE) {
970 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);

--- 18 unchanged lines hidden (view full) ---

989 * Devices that implement the version 2 interface:
990 * X540
991 **/
992s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
993{
994 u32 macc_reg;
995 u32 ledctl_reg;
996
1012 /*
1013 * Link should be up in order for the blink bit in the LED control
1014 * register to work. Force link and speed in the MAC if link is down.
1015 * This will be reversed when we stop the blinking.
1016 */
1017 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
1018 if (link_up == FALSE) {
1019 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);

--- 18 unchanged lines hidden (view full) ---

1038 * Devices that implement the version 2 interface:
1039 * X540
1040 **/
1041s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
1042{
1043 u32 macc_reg;
1044 u32 ledctl_reg;
1045
1046 if (index > 3)
1047 return IXGBE_ERR_PARAM;
1048
997 DEBUGFUNC("ixgbe_blink_led_stop_X540");
998
999 /* Restore the LED to its default value. */
1000 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1001 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1002 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
1003 ledctl_reg &= ~IXGBE_LED_BLINK(index);
1004 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1005
1006 /* Unforce link and speed in the MAC. */
1007 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1008 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
1009 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1010 IXGBE_WRITE_FLUSH(hw);
1011
1012 return IXGBE_SUCCESS;
1013}
1049 DEBUGFUNC("ixgbe_blink_led_stop_X540");
1050
1051 /* Restore the LED to its default value. */
1052 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1053 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1054 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
1055 ledctl_reg &= ~IXGBE_LED_BLINK(index);
1056 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1057
1058 /* Unforce link and speed in the MAC. */
1059 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1060 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
1061 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1062 IXGBE_WRITE_FLUSH(hw);
1063
1064 return IXGBE_SUCCESS;
1065}