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ixgbe_type.h (302408) ixgbe_type.h (320897)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
3 Copyright (c) 2001-2017, Intel Corporation
4 All rights reserved.
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
18 this software without specific prior written permission.
19
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_type.h 299200 2016-05-06 22:54:56Z pfg $*/
33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_type.h 320897 2017-07-11 21:25:07Z erj $*/
34
35#ifndef _IXGBE_TYPE_H_
36#define _IXGBE_TYPE_H_
37
38/*
39 * The following is a brief description of the error categories used by the
40 * ERROR_REPORT* macros.
41 *

--- 60 unchanged lines hidden (view full) ---

102#define IXGBE_DEV_ID_82599_CX4 0x10F9
103#define IXGBE_DEV_ID_82599_SFP 0x10FB
104#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
105#define IXGBE_SUBDEV_ID_82599_SFP_WOL0 0x1071
106#define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72
107#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
108#define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470
109#define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B
34
35#ifndef _IXGBE_TYPE_H_
36#define _IXGBE_TYPE_H_
37
38/*
39 * The following is a brief description of the error categories used by the
40 * ERROR_REPORT* macros.
41 *

--- 60 unchanged lines hidden (view full) ---

102#define IXGBE_DEV_ID_82599_CX4 0x10F9
103#define IXGBE_DEV_ID_82599_SFP 0x10FB
104#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
105#define IXGBE_SUBDEV_ID_82599_SFP_WOL0 0x1071
106#define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72
107#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
108#define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470
109#define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B
110#define IXGBE_SUBDEV_ID_82599_LOM_SFP 0x8976
111#define IXGBE_SUBDEV_ID_82599_LOM_SNAP6 0x2159
112#define IXGBE_SUBDEV_ID_82599_SFP_1OCP 0x000D
113#define IXGBE_SUBDEV_ID_82599_SFP_2OCP 0x0008
110#define IXGBE_SUBDEV_ID_82599_LOM_SNAP6 0x2159
111#define IXGBE_SUBDEV_ID_82599_SFP_1OCP 0x000D
112#define IXGBE_SUBDEV_ID_82599_SFP_2OCP 0x0008
114#define IXGBE_SUBDEV_ID_82599_SFP_LOM 0x06EE
113#define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1 0x8976
114#define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2 0x06EE
115#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
116#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
117#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
118#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
119#define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A
120#define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558
121#define IXGBE_DEV_ID_82599EN_SFP 0x1557
122#define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001

--- 4 unchanged lines hidden (view full) ---

127#define IXGBE_DEV_ID_82599_BYPASS 0x155D
128#define IXGBE_DEV_ID_X540T 0x1528
129#define IXGBE_DEV_ID_X540_VF 0x1515
130#define IXGBE_DEV_ID_X540_VF_HV 0x1530
131#define IXGBE_DEV_ID_X540_BYPASS 0x155C
132#define IXGBE_DEV_ID_X540T1 0x1560
133#define IXGBE_DEV_ID_X550T 0x1563
134#define IXGBE_DEV_ID_X550T1 0x15D1
115#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
116#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
117#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
118#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
119#define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A
120#define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558
121#define IXGBE_DEV_ID_82599EN_SFP 0x1557
122#define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001

--- 4 unchanged lines hidden (view full) ---

127#define IXGBE_DEV_ID_82599_BYPASS 0x155D
128#define IXGBE_DEV_ID_X540T 0x1528
129#define IXGBE_DEV_ID_X540_VF 0x1515
130#define IXGBE_DEV_ID_X540_VF_HV 0x1530
131#define IXGBE_DEV_ID_X540_BYPASS 0x155C
132#define IXGBE_DEV_ID_X540T1 0x1560
133#define IXGBE_DEV_ID_X550T 0x1563
134#define IXGBE_DEV_ID_X550T1 0x15D1
135#define IXGBE_DEV_ID_X550EM_A_KR 0x15C2
136#define IXGBE_DEV_ID_X550EM_A_KR_L 0x15C3
137#define IXGBE_DEV_ID_X550EM_A_SFP_N 0x15C4
138#define IXGBE_DEV_ID_X550EM_A_SGMII 0x15C6
139#define IXGBE_DEV_ID_X550EM_A_SGMII_L 0x15C7
140#define IXGBE_DEV_ID_X550EM_A_10G_T 0x15C8
141#define IXGBE_DEV_ID_X550EM_A_QSFP 0x15CA
142#define IXGBE_DEV_ID_X550EM_A_QSFP_N 0x15CC
143#define IXGBE_DEV_ID_X550EM_A_SFP 0x15CE
144#define IXGBE_DEV_ID_X550EM_A_1G_T 0x15E4
145#define IXGBE_DEV_ID_X550EM_A_1G_T_L 0x15E5
135#define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA
136#define IXGBE_DEV_ID_X550EM_X_KR 0x15AB
137#define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC
138#define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD
139#define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE
146#define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA
147#define IXGBE_DEV_ID_X550EM_X_KR 0x15AB
148#define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC
149#define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD
150#define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE
151#define IXGBE_DEV_ID_X550EM_X_XFI 0x15B0
140#define IXGBE_DEV_ID_X550_VF_HV 0x1564
141#define IXGBE_DEV_ID_X550_VF 0x1565
152#define IXGBE_DEV_ID_X550_VF_HV 0x1564
153#define IXGBE_DEV_ID_X550_VF 0x1565
154#define IXGBE_DEV_ID_X550EM_A_VF 0x15C5
155#define IXGBE_DEV_ID_X550EM_A_VF_HV 0x15B4
142#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
143#define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9
144
145#define IXGBE_CAT(r,m) IXGBE_##r##m
146
147#define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)])
148
149/* General Registers */
150#define IXGBE_CTRL 0x00000
151#define IXGBE_STATUS 0x00008
152#define IXGBE_CTRL_EXT 0x00018
153#define IXGBE_ESDP 0x00020
154#define IXGBE_EODSDP 0x00028
155#define IXGBE_I2CCTL_82599 0x00028
156#define IXGBE_I2CCTL IXGBE_I2CCTL_82599
157#define IXGBE_I2CCTL_X540 IXGBE_I2CCTL_82599
158#define IXGBE_I2CCTL_X550 0x15F5C
159#define IXGBE_I2CCTL_X550EM_x IXGBE_I2CCTL_X550
156#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
157#define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9
158
159#define IXGBE_CAT(r,m) IXGBE_##r##m
160
161#define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)])
162
163/* General Registers */
164#define IXGBE_CTRL 0x00000
165#define IXGBE_STATUS 0x00008
166#define IXGBE_CTRL_EXT 0x00018
167#define IXGBE_ESDP 0x00020
168#define IXGBE_EODSDP 0x00028
169#define IXGBE_I2CCTL_82599 0x00028
170#define IXGBE_I2CCTL IXGBE_I2CCTL_82599
171#define IXGBE_I2CCTL_X540 IXGBE_I2CCTL_82599
172#define IXGBE_I2CCTL_X550 0x15F5C
173#define IXGBE_I2CCTL_X550EM_x IXGBE_I2CCTL_X550
174#define IXGBE_I2CCTL_X550EM_a IXGBE_I2CCTL_X550
160#define IXGBE_I2CCTL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2CCTL)
161#define IXGBE_PHY_GPIO 0x00028
162#define IXGBE_MAC_GPIO 0x00030
163#define IXGBE_PHYINT_STATUS0 0x00100
164#define IXGBE_PHYINT_STATUS1 0x00104
165#define IXGBE_PHYINT_STATUS2 0x00108
166#define IXGBE_LEDCTL 0x00200
167#define IXGBE_FRTIMER 0x00048
168#define IXGBE_TCPTIMER 0x0004C
169#define IXGBE_CORESPARE 0x00600
170#define IXGBE_EXVET 0x05078
171
172/* NVM Registers */
173#define IXGBE_EEC 0x10010
174#define IXGBE_EEC_X540 IXGBE_EEC
175#define IXGBE_EEC_X550 IXGBE_EEC
176#define IXGBE_EEC_X550EM_x IXGBE_EEC
175#define IXGBE_I2CCTL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2CCTL)
176#define IXGBE_PHY_GPIO 0x00028
177#define IXGBE_MAC_GPIO 0x00030
178#define IXGBE_PHYINT_STATUS0 0x00100
179#define IXGBE_PHYINT_STATUS1 0x00104
180#define IXGBE_PHYINT_STATUS2 0x00108
181#define IXGBE_LEDCTL 0x00200
182#define IXGBE_FRTIMER 0x00048
183#define IXGBE_TCPTIMER 0x0004C
184#define IXGBE_CORESPARE 0x00600
185#define IXGBE_EXVET 0x05078
186
187/* NVM Registers */
188#define IXGBE_EEC 0x10010
189#define IXGBE_EEC_X540 IXGBE_EEC
190#define IXGBE_EEC_X550 IXGBE_EEC
191#define IXGBE_EEC_X550EM_x IXGBE_EEC
177#define IXGBE_EEC_BY_MAC(_hw) IXGBE_EEC
192#define IXGBE_EEC_X550EM_a 0x15FF8
193#define IXGBE_EEC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EEC)
178
179#define IXGBE_EERD 0x10014
180#define IXGBE_EEWR 0x10018
181
182#define IXGBE_FLA 0x1001C
183#define IXGBE_FLA_X540 IXGBE_FLA
184#define IXGBE_FLA_X550 IXGBE_FLA
185#define IXGBE_FLA_X550EM_x IXGBE_FLA
194
195#define IXGBE_EERD 0x10014
196#define IXGBE_EEWR 0x10018
197
198#define IXGBE_FLA 0x1001C
199#define IXGBE_FLA_X540 IXGBE_FLA
200#define IXGBE_FLA_X550 IXGBE_FLA
201#define IXGBE_FLA_X550EM_x IXGBE_FLA
186#define IXGBE_FLA_BY_MAC(_hw) IXGBE_FLA
202#define IXGBE_FLA_X550EM_a 0x15F68
203#define IXGBE_FLA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FLA)
187
188#define IXGBE_EEMNGCTL 0x10110
189#define IXGBE_EEMNGDATA 0x10114
190#define IXGBE_FLMNGCTL 0x10118
191#define IXGBE_FLMNGDATA 0x1011C
192#define IXGBE_FLMNGCNT 0x10120
193#define IXGBE_FLOP 0x1013C
194
195#define IXGBE_GRC 0x10200
196#define IXGBE_GRC_X540 IXGBE_GRC
197#define IXGBE_GRC_X550 IXGBE_GRC
198#define IXGBE_GRC_X550EM_x IXGBE_GRC
204
205#define IXGBE_EEMNGCTL 0x10110
206#define IXGBE_EEMNGDATA 0x10114
207#define IXGBE_FLMNGCTL 0x10118
208#define IXGBE_FLMNGDATA 0x1011C
209#define IXGBE_FLMNGCNT 0x10120
210#define IXGBE_FLOP 0x1013C
211
212#define IXGBE_GRC 0x10200
213#define IXGBE_GRC_X540 IXGBE_GRC
214#define IXGBE_GRC_X550 IXGBE_GRC
215#define IXGBE_GRC_X550EM_x IXGBE_GRC
199#define IXGBE_GRC_BY_MAC(_hw) IXGBE_GRC
216#define IXGBE_GRC_X550EM_a 0x15F64
217#define IXGBE_GRC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), GRC)
200
201#define IXGBE_SRAMREL 0x10210
202#define IXGBE_SRAMREL_X540 IXGBE_SRAMREL
203#define IXGBE_SRAMREL_X550 IXGBE_SRAMREL
204#define IXGBE_SRAMREL_X550EM_x IXGBE_SRAMREL
218
219#define IXGBE_SRAMREL 0x10210
220#define IXGBE_SRAMREL_X540 IXGBE_SRAMREL
221#define IXGBE_SRAMREL_X550 IXGBE_SRAMREL
222#define IXGBE_SRAMREL_X550EM_x IXGBE_SRAMREL
205#define IXGBE_SRAMREL_BY_MAC(_hw) IXGBE_SRAMREL
223#define IXGBE_SRAMREL_X550EM_a 0x15F6C
224#define IXGBE_SRAMREL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SRAMREL)
206
207#define IXGBE_PHYDBG 0x10218
208
209/* General Receive Control */
210#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
211#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
212
213#define IXGBE_VPDDIAG0 0x10204
214#define IXGBE_VPDDIAG1 0x10208
215
216/* I2CCTL Bit Masks */
217#define IXGBE_I2C_CLK_IN 0x00000001
218#define IXGBE_I2C_CLK_IN_X540 IXGBE_I2C_CLK_IN
219#define IXGBE_I2C_CLK_IN_X550 0x00004000
220#define IXGBE_I2C_CLK_IN_X550EM_x IXGBE_I2C_CLK_IN_X550
225
226#define IXGBE_PHYDBG 0x10218
227
228/* General Receive Control */
229#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
230#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
231
232#define IXGBE_VPDDIAG0 0x10204
233#define IXGBE_VPDDIAG1 0x10208
234
235/* I2CCTL Bit Masks */
236#define IXGBE_I2C_CLK_IN 0x00000001
237#define IXGBE_I2C_CLK_IN_X540 IXGBE_I2C_CLK_IN
238#define IXGBE_I2C_CLK_IN_X550 0x00004000
239#define IXGBE_I2C_CLK_IN_X550EM_x IXGBE_I2C_CLK_IN_X550
240#define IXGBE_I2C_CLK_IN_X550EM_a IXGBE_I2C_CLK_IN_X550
221#define IXGBE_I2C_CLK_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_IN)
222
223#define IXGBE_I2C_CLK_OUT 0x00000002
224#define IXGBE_I2C_CLK_OUT_X540 IXGBE_I2C_CLK_OUT
225#define IXGBE_I2C_CLK_OUT_X550 0x00000200
226#define IXGBE_I2C_CLK_OUT_X550EM_x IXGBE_I2C_CLK_OUT_X550
241#define IXGBE_I2C_CLK_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_IN)
242
243#define IXGBE_I2C_CLK_OUT 0x00000002
244#define IXGBE_I2C_CLK_OUT_X540 IXGBE_I2C_CLK_OUT
245#define IXGBE_I2C_CLK_OUT_X550 0x00000200
246#define IXGBE_I2C_CLK_OUT_X550EM_x IXGBE_I2C_CLK_OUT_X550
247#define IXGBE_I2C_CLK_OUT_X550EM_a IXGBE_I2C_CLK_OUT_X550
227#define IXGBE_I2C_CLK_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OUT)
228
229#define IXGBE_I2C_DATA_IN 0x00000004
230#define IXGBE_I2C_DATA_IN_X540 IXGBE_I2C_DATA_IN
231#define IXGBE_I2C_DATA_IN_X550 0x00001000
232#define IXGBE_I2C_DATA_IN_X550EM_x IXGBE_I2C_DATA_IN_X550
248#define IXGBE_I2C_CLK_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OUT)
249
250#define IXGBE_I2C_DATA_IN 0x00000004
251#define IXGBE_I2C_DATA_IN_X540 IXGBE_I2C_DATA_IN
252#define IXGBE_I2C_DATA_IN_X550 0x00001000
253#define IXGBE_I2C_DATA_IN_X550EM_x IXGBE_I2C_DATA_IN_X550
254#define IXGBE_I2C_DATA_IN_X550EM_a IXGBE_I2C_DATA_IN_X550
233#define IXGBE_I2C_DATA_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_IN)
234
235#define IXGBE_I2C_DATA_OUT 0x00000008
236#define IXGBE_I2C_DATA_OUT_X540 IXGBE_I2C_DATA_OUT
237#define IXGBE_I2C_DATA_OUT_X550 0x00000400
238#define IXGBE_I2C_DATA_OUT_X550EM_x IXGBE_I2C_DATA_OUT_X550
255#define IXGBE_I2C_DATA_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_IN)
256
257#define IXGBE_I2C_DATA_OUT 0x00000008
258#define IXGBE_I2C_DATA_OUT_X540 IXGBE_I2C_DATA_OUT
259#define IXGBE_I2C_DATA_OUT_X550 0x00000400
260#define IXGBE_I2C_DATA_OUT_X550EM_x IXGBE_I2C_DATA_OUT_X550
261#define IXGBE_I2C_DATA_OUT_X550EM_a IXGBE_I2C_DATA_OUT_X550
239#define IXGBE_I2C_DATA_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OUT)
240
241#define IXGBE_I2C_DATA_OE_N_EN 0
242#define IXGBE_I2C_DATA_OE_N_EN_X540 IXGBE_I2C_DATA_OE_N_EN
243#define IXGBE_I2C_DATA_OE_N_EN_X550 0x00000800
244#define IXGBE_I2C_DATA_OE_N_EN_X550EM_x IXGBE_I2C_DATA_OE_N_EN_X550
262#define IXGBE_I2C_DATA_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OUT)
263
264#define IXGBE_I2C_DATA_OE_N_EN 0
265#define IXGBE_I2C_DATA_OE_N_EN_X540 IXGBE_I2C_DATA_OE_N_EN
266#define IXGBE_I2C_DATA_OE_N_EN_X550 0x00000800
267#define IXGBE_I2C_DATA_OE_N_EN_X550EM_x IXGBE_I2C_DATA_OE_N_EN_X550
268#define IXGBE_I2C_DATA_OE_N_EN_X550EM_a IXGBE_I2C_DATA_OE_N_EN_X550
245#define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN)
246
247#define IXGBE_I2C_BB_EN 0
248#define IXGBE_I2C_BB_EN_X540 IXGBE_I2C_BB_EN
249#define IXGBE_I2C_BB_EN_X550 0x00000100
250#define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550
269#define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN)
270
271#define IXGBE_I2C_BB_EN 0
272#define IXGBE_I2C_BB_EN_X540 IXGBE_I2C_BB_EN
273#define IXGBE_I2C_BB_EN_X550 0x00000100
274#define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550
275#define IXGBE_I2C_BB_EN_X550EM_a IXGBE_I2C_BB_EN_X550
251
252#define IXGBE_I2C_BB_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN)
253
254#define IXGBE_I2C_CLK_OE_N_EN 0
255#define IXGBE_I2C_CLK_OE_N_EN_X540 IXGBE_I2C_CLK_OE_N_EN
256#define IXGBE_I2C_CLK_OE_N_EN_X550 0x00002000
257#define IXGBE_I2C_CLK_OE_N_EN_X550EM_x IXGBE_I2C_CLK_OE_N_EN_X550
276
277#define IXGBE_I2C_BB_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN)
278
279#define IXGBE_I2C_CLK_OE_N_EN 0
280#define IXGBE_I2C_CLK_OE_N_EN_X540 IXGBE_I2C_CLK_OE_N_EN
281#define IXGBE_I2C_CLK_OE_N_EN_X550 0x00002000
282#define IXGBE_I2C_CLK_OE_N_EN_X550EM_x IXGBE_I2C_CLK_OE_N_EN_X550
283#define IXGBE_I2C_CLK_OE_N_EN_X550EM_a IXGBE_I2C_CLK_OE_N_EN_X550
258#define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN)
259#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
260
261
262/* Interrupt Registers */
263#define IXGBE_EICR 0x00800
264#define IXGBE_EICS 0x00808
265#define IXGBE_EIMS 0x00880

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517#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
518
519#define IXGBE_WUPL 0x05900
520#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
521#define IXGBE_PROXYS 0x05F60 /* Proxying Status Register */
522#define IXGBE_PROXYFC 0x05F64 /* Proxying Filter Control Register */
523#define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */
524
284#define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN)
285#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
286
287
288/* Interrupt Registers */
289#define IXGBE_EICR 0x00800
290#define IXGBE_EICS 0x00808
291#define IXGBE_EIMS 0x00880

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543#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
544
545#define IXGBE_WUPL 0x05900
546#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
547#define IXGBE_PROXYS 0x05F60 /* Proxying Status Register */
548#define IXGBE_PROXYFC 0x05F64 /* Proxying Filter Control Register */
549#define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */
550
551/* masks for accessing VXLAN and GENEVE UDP ports */
552#define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK 0x0000ffff /* VXLAN port */
553#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK 0xffff0000 /* GENEVE port */
554#define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK 0xffffffff /* GENEVE/VXLAN */
555
556#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT 16
557
525#define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */
526/* Ext Flexible Host Filter Table */
527#define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100))
528#define IXGBE_FHFT_EXT_X550(_n) (0x09600 + ((_n) * 0x100))
529
530/* Four Flexible Filters are supported */
531#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
532

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990#define IXGBE_MANC2H 0x05860
991#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
992#define IXGBE_MIPAF 0x058B0
993#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
994#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
995#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
996#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
997#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
558#define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */
559/* Ext Flexible Host Filter Table */
560#define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100))
561#define IXGBE_FHFT_EXT_X550(_n) (0x09600 + ((_n) * 0x100))
562
563/* Four Flexible Filters are supported */
564#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
565

--- 457 unchanged lines hidden (view full) ---

1023#define IXGBE_MANC2H 0x05860
1024#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
1025#define IXGBE_MIPAF 0x058B0
1026#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
1027#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
1028#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
1029#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
1030#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
998#define IXGBE_LSWFW 0x15014
1031#define IXGBE_LSWFW 0x15F14
999#define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */
1000#define IXGBE_BMCIPVAL 0x05060
1001#define IXGBE_BMCIP_IPADDR_TYPE 0x00000001
1002#define IXGBE_BMCIP_IPADDR_VALID 0x00000002
1003
1004/* Management Bit Fields and Masks */
1005#define IXGBE_MANC_MPROXYE 0x40000000 /* Management Proxy Enable */
1006#define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */

--- 25 unchanged lines hidden (view full) ---

1032#define IXGBE_GCR 0x11000
1033#define IXGBE_GTV 0x11004
1034#define IXGBE_FUNCTAG 0x11008
1035#define IXGBE_GLT 0x1100C
1036#define IXGBE_PCIEPIPEADR 0x11004
1037#define IXGBE_PCIEPIPEDAT 0x11008
1038#define IXGBE_GSCL_1 0x11010
1039#define IXGBE_GSCL_2 0x11014
1032#define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */
1033#define IXGBE_BMCIPVAL 0x05060
1034#define IXGBE_BMCIP_IPADDR_TYPE 0x00000001
1035#define IXGBE_BMCIP_IPADDR_VALID 0x00000002
1036
1037/* Management Bit Fields and Masks */
1038#define IXGBE_MANC_MPROXYE 0x40000000 /* Management Proxy Enable */
1039#define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */

--- 25 unchanged lines hidden (view full) ---

1065#define IXGBE_GCR 0x11000
1066#define IXGBE_GTV 0x11004
1067#define IXGBE_FUNCTAG 0x11008
1068#define IXGBE_GLT 0x1100C
1069#define IXGBE_PCIEPIPEADR 0x11004
1070#define IXGBE_PCIEPIPEDAT 0x11008
1071#define IXGBE_GSCL_1 0x11010
1072#define IXGBE_GSCL_2 0x11014
1073#define IXGBE_GSCL_1_X540 IXGBE_GSCL_1
1074#define IXGBE_GSCL_2_X540 IXGBE_GSCL_2
1040#define IXGBE_GSCL_3 0x11018
1041#define IXGBE_GSCL_4 0x1101C
1042#define IXGBE_GSCN_0 0x11020
1043#define IXGBE_GSCN_1 0x11024
1044#define IXGBE_GSCN_2 0x11028
1045#define IXGBE_GSCN_3 0x1102C
1075#define IXGBE_GSCL_3 0x11018
1076#define IXGBE_GSCL_4 0x1101C
1077#define IXGBE_GSCN_0 0x11020
1078#define IXGBE_GSCN_1 0x11024
1079#define IXGBE_GSCN_2 0x11028
1080#define IXGBE_GSCN_3 0x1102C
1081#define IXGBE_GSCN_0_X540 IXGBE_GSCN_0
1082#define IXGBE_GSCN_1_X540 IXGBE_GSCN_1
1083#define IXGBE_GSCN_2_X540 IXGBE_GSCN_2
1084#define IXGBE_GSCN_3_X540 IXGBE_GSCN_3
1046#define IXGBE_FACTPS 0x10150
1047#define IXGBE_FACTPS_X540 IXGBE_FACTPS
1085#define IXGBE_FACTPS 0x10150
1086#define IXGBE_FACTPS_X540 IXGBE_FACTPS
1087#define IXGBE_GSCL_1_X550 0x11800
1088#define IXGBE_GSCL_2_X550 0x11804
1089#define IXGBE_GSCL_1_X550EM_x IXGBE_GSCL_1_X550
1090#define IXGBE_GSCL_2_X550EM_x IXGBE_GSCL_2_X550
1091#define IXGBE_GSCN_0_X550 0x11820
1092#define IXGBE_GSCN_1_X550 0x11824
1093#define IXGBE_GSCN_2_X550 0x11828
1094#define IXGBE_GSCN_3_X550 0x1182C
1095#define IXGBE_GSCN_0_X550EM_x IXGBE_GSCN_0_X550
1096#define IXGBE_GSCN_1_X550EM_x IXGBE_GSCN_1_X550
1097#define IXGBE_GSCN_2_X550EM_x IXGBE_GSCN_2_X550
1098#define IXGBE_GSCN_3_X550EM_x IXGBE_GSCN_3_X550
1048#define IXGBE_FACTPS_X550 IXGBE_FACTPS
1049#define IXGBE_FACTPS_X550EM_x IXGBE_FACTPS
1099#define IXGBE_FACTPS_X550 IXGBE_FACTPS
1100#define IXGBE_FACTPS_X550EM_x IXGBE_FACTPS
1050#define IXGBE_FACTPS_BY_MAC(_hw) IXGBE_FACTPS
1101#define IXGBE_GSCL_1_X550EM_a IXGBE_GSCL_1_X550
1102#define IXGBE_GSCL_2_X550EM_a IXGBE_GSCL_2_X550
1103#define IXGBE_GSCN_0_X550EM_a IXGBE_GSCN_0_X550
1104#define IXGBE_GSCN_1_X550EM_a IXGBE_GSCN_1_X550
1105#define IXGBE_GSCN_2_X550EM_a IXGBE_GSCN_2_X550
1106#define IXGBE_GSCN_3_X550EM_a IXGBE_GSCN_3_X550
1107#define IXGBE_FACTPS_X550EM_a 0x15FEC
1108#define IXGBE_FACTPS_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FACTPS)
1051
1052#define IXGBE_PCIEANACTL 0x11040
1053#define IXGBE_SWSM 0x10140
1054#define IXGBE_SWSM_X540 IXGBE_SWSM
1055#define IXGBE_SWSM_X550 IXGBE_SWSM
1056#define IXGBE_SWSM_X550EM_x IXGBE_SWSM
1109
1110#define IXGBE_PCIEANACTL 0x11040
1111#define IXGBE_SWSM 0x10140
1112#define IXGBE_SWSM_X540 IXGBE_SWSM
1113#define IXGBE_SWSM_X550 IXGBE_SWSM
1114#define IXGBE_SWSM_X550EM_x IXGBE_SWSM
1057#define IXGBE_SWSM_BY_MAC(_hw) IXGBE_SWSM
1115#define IXGBE_SWSM_X550EM_a 0x15F70
1116#define IXGBE_SWSM_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SWSM)
1058
1059#define IXGBE_FWSM 0x10148
1060#define IXGBE_FWSM_X540 IXGBE_FWSM
1061#define IXGBE_FWSM_X550 IXGBE_FWSM
1062#define IXGBE_FWSM_X550EM_x IXGBE_FWSM
1117
1118#define IXGBE_FWSM 0x10148
1119#define IXGBE_FWSM_X540 IXGBE_FWSM
1120#define IXGBE_FWSM_X550 IXGBE_FWSM
1121#define IXGBE_FWSM_X550EM_x IXGBE_FWSM
1063#define IXGBE_FWSM_BY_MAC(_hw) IXGBE_FWSM
1122#define IXGBE_FWSM_X550EM_a 0x15F74
1123#define IXGBE_FWSM_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FWSM)
1064
1065#define IXGBE_SWFW_SYNC IXGBE_GSSR
1066#define IXGBE_SWFW_SYNC_X540 IXGBE_SWFW_SYNC
1067#define IXGBE_SWFW_SYNC_X550 IXGBE_SWFW_SYNC
1068#define IXGBE_SWFW_SYNC_X550EM_x IXGBE_SWFW_SYNC
1124
1125#define IXGBE_SWFW_SYNC IXGBE_GSSR
1126#define IXGBE_SWFW_SYNC_X540 IXGBE_SWFW_SYNC
1127#define IXGBE_SWFW_SYNC_X550 IXGBE_SWFW_SYNC
1128#define IXGBE_SWFW_SYNC_X550EM_x IXGBE_SWFW_SYNC
1069#define IXGBE_SWFW_SYNC_BY_MAC(_hw) IXGBE_SWFW_SYNC
1129#define IXGBE_SWFW_SYNC_X550EM_a 0x15F78
1130#define IXGBE_SWFW_SYNC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SWFW_SYNC)
1070
1071#define IXGBE_GSSR 0x10160
1072#define IXGBE_MREVID 0x11064
1073#define IXGBE_DCA_ID 0x11070
1074#define IXGBE_DCA_CTRL 0x11074
1075
1076/* PCI-E registers 82599-Specific */
1077#define IXGBE_GCR_EXT 0x11050
1078#define IXGBE_GSCL_5_82599 0x11030
1079#define IXGBE_GSCL_6_82599 0x11034
1080#define IXGBE_GSCL_7_82599 0x11038
1081#define IXGBE_GSCL_8_82599 0x1103C
1131
1132#define IXGBE_GSSR 0x10160
1133#define IXGBE_MREVID 0x11064
1134#define IXGBE_DCA_ID 0x11070
1135#define IXGBE_DCA_CTRL 0x11074
1136
1137/* PCI-E registers 82599-Specific */
1138#define IXGBE_GCR_EXT 0x11050
1139#define IXGBE_GSCL_5_82599 0x11030
1140#define IXGBE_GSCL_6_82599 0x11034
1141#define IXGBE_GSCL_7_82599 0x11038
1142#define IXGBE_GSCL_8_82599 0x1103C
1143#define IXGBE_GSCL_5_X540 IXGBE_GSCL_5_82599
1144#define IXGBE_GSCL_6_X540 IXGBE_GSCL_6_82599
1145#define IXGBE_GSCL_7_X540 IXGBE_GSCL_7_82599
1146#define IXGBE_GSCL_8_X540 IXGBE_GSCL_8_82599
1082#define IXGBE_PHYADR_82599 0x11040
1083#define IXGBE_PHYDAT_82599 0x11044
1084#define IXGBE_PHYCTL_82599 0x11048
1085#define IXGBE_PBACLR_82599 0x11068
1086#define IXGBE_CIAA 0x11088
1087#define IXGBE_CIAD 0x1108C
1088#define IXGBE_CIAA_82599 IXGBE_CIAA
1089#define IXGBE_CIAD_82599 IXGBE_CIAD
1090#define IXGBE_CIAA_X540 IXGBE_CIAA
1091#define IXGBE_CIAD_X540 IXGBE_CIAD
1147#define IXGBE_PHYADR_82599 0x11040
1148#define IXGBE_PHYDAT_82599 0x11044
1149#define IXGBE_PHYCTL_82599 0x11048
1150#define IXGBE_PBACLR_82599 0x11068
1151#define IXGBE_CIAA 0x11088
1152#define IXGBE_CIAD 0x1108C
1153#define IXGBE_CIAA_82599 IXGBE_CIAA
1154#define IXGBE_CIAD_82599 IXGBE_CIAD
1155#define IXGBE_CIAA_X540 IXGBE_CIAA
1156#define IXGBE_CIAD_X540 IXGBE_CIAD
1157#define IXGBE_GSCL_5_X550 0x11810
1158#define IXGBE_GSCL_6_X550 0x11814
1159#define IXGBE_GSCL_7_X550 0x11818
1160#define IXGBE_GSCL_8_X550 0x1181C
1161#define IXGBE_GSCL_5_X550EM_x IXGBE_GSCL_5_X550
1162#define IXGBE_GSCL_6_X550EM_x IXGBE_GSCL_6_X550
1163#define IXGBE_GSCL_7_X550EM_x IXGBE_GSCL_7_X550
1164#define IXGBE_GSCL_8_X550EM_x IXGBE_GSCL_8_X550
1092#define IXGBE_CIAA_X550 0x11508
1093#define IXGBE_CIAD_X550 0x11510
1094#define IXGBE_CIAA_X550EM_x IXGBE_CIAA_X550
1095#define IXGBE_CIAD_X550EM_x IXGBE_CIAD_X550
1165#define IXGBE_CIAA_X550 0x11508
1166#define IXGBE_CIAD_X550 0x11510
1167#define IXGBE_CIAA_X550EM_x IXGBE_CIAA_X550
1168#define IXGBE_CIAD_X550EM_x IXGBE_CIAD_X550
1169#define IXGBE_GSCL_5_X550EM_a IXGBE_GSCL_5_X550
1170#define IXGBE_GSCL_6_X550EM_a IXGBE_GSCL_6_X550
1171#define IXGBE_GSCL_7_X550EM_a IXGBE_GSCL_7_X550
1172#define IXGBE_GSCL_8_X550EM_a IXGBE_GSCL_8_X550
1173#define IXGBE_CIAA_X550EM_a IXGBE_CIAA_X550
1174#define IXGBE_CIAD_X550EM_a IXGBE_CIAD_X550
1096#define IXGBE_CIAA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAA)
1097#define IXGBE_CIAD_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAD)
1098#define IXGBE_PICAUSE 0x110B0
1099#define IXGBE_PIENA 0x110B8
1100#define IXGBE_CDQ_MBR_82599 0x110B4
1101#define IXGBE_PCIESPARE 0x110BC
1102#define IXGBE_MISC_REG_82599 0x110F0
1103#define IXGBE_ECC_CTRL_0_82599 0x11100

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1233#define IXGBE_MHADD 0x04268
1234#define IXGBE_MAXFRS 0x04268
1235#define IXGBE_TREG 0x0426C
1236#define IXGBE_PCSS1 0x04288
1237#define IXGBE_PCSS2 0x0428C
1238#define IXGBE_XPCSS 0x04290
1239#define IXGBE_MFLCN 0x04294
1240#define IXGBE_SERDESC 0x04298
1175#define IXGBE_CIAA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAA)
1176#define IXGBE_CIAD_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAD)
1177#define IXGBE_PICAUSE 0x110B0
1178#define IXGBE_PIENA 0x110B8
1179#define IXGBE_CDQ_MBR_82599 0x110B4
1180#define IXGBE_PCIESPARE 0x110BC
1181#define IXGBE_MISC_REG_82599 0x110F0
1182#define IXGBE_ECC_CTRL_0_82599 0x11100

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1312#define IXGBE_MHADD 0x04268
1313#define IXGBE_MAXFRS 0x04268
1314#define IXGBE_TREG 0x0426C
1315#define IXGBE_PCSS1 0x04288
1316#define IXGBE_PCSS2 0x0428C
1317#define IXGBE_XPCSS 0x04290
1318#define IXGBE_MFLCN 0x04294
1319#define IXGBE_SERDESC 0x04298
1320#define IXGBE_MAC_SGMII_BUSY 0x04298
1241#define IXGBE_MACS 0x0429C
1242#define IXGBE_AUTOC 0x042A0
1243#define IXGBE_LINKS 0x042A4
1244#define IXGBE_LINKS2 0x04324
1245#define IXGBE_AUTOC2 0x042A8
1246#define IXGBE_AUTOC3 0x042AC
1247#define IXGBE_ANLP1 0x042B0
1248#define IXGBE_ANLP2 0x042B4

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1419#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
1420#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
1421#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
1422
1423/* Omer bit masks */
1424#define IXGBE_CORECTL_WRITE_CMD 0x00010000
1425
1426/* Device Type definitions for new protocol MDIO commands */
1321#define IXGBE_MACS 0x0429C
1322#define IXGBE_AUTOC 0x042A0
1323#define IXGBE_LINKS 0x042A4
1324#define IXGBE_LINKS2 0x04324
1325#define IXGBE_AUTOC2 0x042A8
1326#define IXGBE_AUTOC3 0x042AC
1327#define IXGBE_ANLP1 0x042B0
1328#define IXGBE_ANLP2 0x042B4

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1499#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
1500#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
1501#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
1502
1503/* Omer bit masks */
1504#define IXGBE_CORECTL_WRITE_CMD 0x00010000
1505
1506/* Device Type definitions for new protocol MDIO commands */
1507#define IXGBE_MDIO_ZERO_DEV_TYPE 0x0
1427#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
1428#define IXGBE_MDIO_PCS_DEV_TYPE 0x3
1429#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
1430#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
1431#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
1432#define IXGBE_TWINAX_DEV 1
1433
1434#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */

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1476#define IXGBE_MDIO_POWER_UP_STALL 0x8000 /* Power Up Stall */
1477#define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK 0xFF00 /* int std mask */
1478#define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG 0xFC00 /* chip std int flag */
1479#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK 0xFF01 /* int chip-wide mask */
1480#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG 0xFC01 /* int chip-wide mask */
1481#define IXGBE_MDIO_GLOBAL_ALARM_1 0xCC00 /* Global alarm 1 */
1482#define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT 0x0010 /* device fault */
1483#define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL 0x4000 /* high temp failure */
1508#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
1509#define IXGBE_MDIO_PCS_DEV_TYPE 0x3
1510#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
1511#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
1512#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
1513#define IXGBE_TWINAX_DEV 1
1514
1515#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */

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1557#define IXGBE_MDIO_POWER_UP_STALL 0x8000 /* Power Up Stall */
1558#define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK 0xFF00 /* int std mask */
1559#define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG 0xFC00 /* chip std int flag */
1560#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK 0xFF01 /* int chip-wide mask */
1561#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG 0xFC01 /* int chip-wide mask */
1562#define IXGBE_MDIO_GLOBAL_ALARM_1 0xCC00 /* Global alarm 1 */
1563#define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT 0x0010 /* device fault */
1564#define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL 0x4000 /* high temp failure */
1484#define IXGBE_MDIO_GLOBAL_FAULT_MSG 0xC850 /* Global Fault Message */
1565#define IXGBE_MDIO_GLOBAL_FAULT_MSG 0xC850 /* Global Fault Message */
1485#define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP 0x8007 /* high temp failure */
1486#define IXGBE_MDIO_GLOBAL_INT_MASK 0xD400 /* Global int mask */
1487#define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN 0x1000 /* autoneg vendor alarm int enable */
1488#define IXGBE_MDIO_GLOBAL_ALARM_1_INT 0x4 /* int in Global alarm 1 */
1489#define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN 0x1 /* vendor alarm int enable */
1490#define IXGBE_MDIO_GLOBAL_STD_ALM2_INT 0x200 /* vendor alarm2 int mask */
1491#define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN 0x4000 /* int high temp enable */
1566#define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP 0x8007 /* high temp failure */
1567#define IXGBE_MDIO_GLOBAL_INT_MASK 0xD400 /* Global int mask */
1568#define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN 0x1000 /* autoneg vendor alarm int enable */
1569#define IXGBE_MDIO_GLOBAL_ALARM_1_INT 0x4 /* int in Global alarm 1 */
1570#define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN 0x1 /* vendor alarm int enable */
1571#define IXGBE_MDIO_GLOBAL_STD_ALM2_INT 0x200 /* vendor alarm2 int mask */
1572#define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN 0x4000 /* int high temp enable */
1573#define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN 0x0010 /* int dev fault enable */
1492#define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */
1493#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
1494#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
1495#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
1496#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */
1497#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN 0x1 /* PHY TX Vendor LASI enable */
1498#define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */
1499#define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */

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1543
1544#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
1545#define IXGBE_MAX_PHY_ADDR 32
1546
1547/* PHY IDs*/
1548#define TN1010_PHY_ID 0x00A19410
1549#define TNX_FW_REV 0xB
1550#define X540_PHY_ID 0x01540200
1574#define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */
1575#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
1576#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
1577#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
1578#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */
1579#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN 0x1 /* PHY TX Vendor LASI enable */
1580#define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */
1581#define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */

--- 43 unchanged lines hidden (view full) ---

1625
1626#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
1627#define IXGBE_MAX_PHY_ADDR 32
1628
1629/* PHY IDs*/
1630#define TN1010_PHY_ID 0x00A19410
1631#define TNX_FW_REV 0xB
1632#define X540_PHY_ID 0x01540200
1551#define X550_PHY_ID1 0x01540220
1552#define X550_PHY_ID2 0x01540223
1553#define X550_PHY_ID3 0x01540221
1554#define X557_PHY_ID 0x01540240
1633#define X550_PHY_ID2 0x01540223
1634#define X550_PHY_ID3 0x01540221
1635#define X557_PHY_ID 0x01540240
1636#define X557_PHY_ID2 0x01540250
1555#define AQ_FW_REV 0x20
1556#define QT2022_PHY_ID 0x0043A400
1557#define ATH_PHY_ID 0x03429050
1558
1559/* PHY Types */
1637#define AQ_FW_REV 0x20
1638#define QT2022_PHY_ID 0x0043A400
1639#define ATH_PHY_ID 0x03429050
1640
1641/* PHY Types */
1560#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
1642#define IXGBE_M88E1500_E_PHY_ID 0x01410DD0
1643#define IXGBE_M88E1543_E_PHY_ID 0x01410EA0
1561
1562/* Special PHY Init Routine */
1563#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1564#define IXGBE_PHY_INIT_END_NL 0xFFFF
1565#define IXGBE_CONTROL_MASK_NL 0xF000
1566#define IXGBE_DATA_MASK_NL 0x0FFF
1567#define IXGBE_CONTROL_SHIFT_NL 12
1568#define IXGBE_DELAY_NL 0

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1579#define IXGBE_SDP1_GPIEN_X540 0x00000004 /* SDP1 on X540 and X550 */
1580#define IXGBE_SDP2_GPIEN_X540 0x00000008 /* SDP2 on X540 and X550 */
1581#define IXGBE_SDP0_GPIEN_X550 IXGBE_SDP0_GPIEN_X540
1582#define IXGBE_SDP1_GPIEN_X550 IXGBE_SDP1_GPIEN_X540
1583#define IXGBE_SDP2_GPIEN_X550 IXGBE_SDP2_GPIEN_X540
1584#define IXGBE_SDP0_GPIEN_X550EM_x IXGBE_SDP0_GPIEN_X540
1585#define IXGBE_SDP1_GPIEN_X550EM_x IXGBE_SDP1_GPIEN_X540
1586#define IXGBE_SDP2_GPIEN_X550EM_x IXGBE_SDP2_GPIEN_X540
1644
1645/* Special PHY Init Routine */
1646#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1647#define IXGBE_PHY_INIT_END_NL 0xFFFF
1648#define IXGBE_CONTROL_MASK_NL 0xF000
1649#define IXGBE_DATA_MASK_NL 0x0FFF
1650#define IXGBE_CONTROL_SHIFT_NL 12
1651#define IXGBE_DELAY_NL 0

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1662#define IXGBE_SDP1_GPIEN_X540 0x00000004 /* SDP1 on X540 and X550 */
1663#define IXGBE_SDP2_GPIEN_X540 0x00000008 /* SDP2 on X540 and X550 */
1664#define IXGBE_SDP0_GPIEN_X550 IXGBE_SDP0_GPIEN_X540
1665#define IXGBE_SDP1_GPIEN_X550 IXGBE_SDP1_GPIEN_X540
1666#define IXGBE_SDP2_GPIEN_X550 IXGBE_SDP2_GPIEN_X540
1667#define IXGBE_SDP0_GPIEN_X550EM_x IXGBE_SDP0_GPIEN_X540
1668#define IXGBE_SDP1_GPIEN_X550EM_x IXGBE_SDP1_GPIEN_X540
1669#define IXGBE_SDP2_GPIEN_X550EM_x IXGBE_SDP2_GPIEN_X540
1670#define IXGBE_SDP0_GPIEN_X550EM_a IXGBE_SDP0_GPIEN_X540
1671#define IXGBE_SDP1_GPIEN_X550EM_a IXGBE_SDP1_GPIEN_X540
1672#define IXGBE_SDP2_GPIEN_X550EM_a IXGBE_SDP2_GPIEN_X540
1587#define IXGBE_SDP0_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP0_GPIEN)
1588#define IXGBE_SDP1_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP1_GPIEN)
1589#define IXGBE_SDP2_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP2_GPIEN)
1590
1591#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
1592#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
1593#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
1594#define IXGBE_GPIE_EIAME 0x40000000

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1664/* VT_CTL bitmasks */
1665#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */
1666#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */
1667#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */
1668#define IXGBE_VT_CTL_POOL_SHIFT 7
1669#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1670
1671/* VMOLR bitmasks */
1673#define IXGBE_SDP0_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP0_GPIEN)
1674#define IXGBE_SDP1_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP1_GPIEN)
1675#define IXGBE_SDP2_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP2_GPIEN)
1676
1677#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
1678#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
1679#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
1680#define IXGBE_GPIE_EIAME 0x40000000

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1750/* VT_CTL bitmasks */
1751#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */
1752#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */
1753#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */
1754#define IXGBE_VT_CTL_POOL_SHIFT 7
1755#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1756
1757/* VMOLR bitmasks */
1758#define IXGBE_VMOLR_UPE 0x00400000 /* unicast promiscuous */
1759#define IXGBE_VMOLR_VPE 0x00800000 /* VLAN promiscuous */
1672#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */
1673#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */
1674#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */
1675#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */
1676#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */
1677
1678/* VFRE bitmask */
1679#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF

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1769#define IXGBE_EICR_GPI_SDP1_X540 0x04000000 /* Gen Purpose Interrupt on SDP1 */
1770#define IXGBE_EICR_GPI_SDP2_X540 0x08000000 /* Gen Purpose Interrupt on SDP2 */
1771#define IXGBE_EICR_GPI_SDP0_X550 IXGBE_EICR_GPI_SDP0_X540
1772#define IXGBE_EICR_GPI_SDP1_X550 IXGBE_EICR_GPI_SDP1_X540
1773#define IXGBE_EICR_GPI_SDP2_X550 IXGBE_EICR_GPI_SDP2_X540
1774#define IXGBE_EICR_GPI_SDP0_X550EM_x IXGBE_EICR_GPI_SDP0_X540
1775#define IXGBE_EICR_GPI_SDP1_X550EM_x IXGBE_EICR_GPI_SDP1_X540
1776#define IXGBE_EICR_GPI_SDP2_X550EM_x IXGBE_EICR_GPI_SDP2_X540
1760#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */
1761#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */
1762#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */
1763#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */
1764#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */
1765
1766/* VFRE bitmask */
1767#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF

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1857#define IXGBE_EICR_GPI_SDP1_X540 0x04000000 /* Gen Purpose Interrupt on SDP1 */
1858#define IXGBE_EICR_GPI_SDP2_X540 0x08000000 /* Gen Purpose Interrupt on SDP2 */
1859#define IXGBE_EICR_GPI_SDP0_X550 IXGBE_EICR_GPI_SDP0_X540
1860#define IXGBE_EICR_GPI_SDP1_X550 IXGBE_EICR_GPI_SDP1_X540
1861#define IXGBE_EICR_GPI_SDP2_X550 IXGBE_EICR_GPI_SDP2_X540
1862#define IXGBE_EICR_GPI_SDP0_X550EM_x IXGBE_EICR_GPI_SDP0_X540
1863#define IXGBE_EICR_GPI_SDP1_X550EM_x IXGBE_EICR_GPI_SDP1_X540
1864#define IXGBE_EICR_GPI_SDP2_X550EM_x IXGBE_EICR_GPI_SDP2_X540
1865#define IXGBE_EICR_GPI_SDP0_X550EM_a IXGBE_EICR_GPI_SDP0_X540
1866#define IXGBE_EICR_GPI_SDP1_X550EM_a IXGBE_EICR_GPI_SDP1_X540
1867#define IXGBE_EICR_GPI_SDP2_X550EM_a IXGBE_EICR_GPI_SDP2_X540
1777#define IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP0)
1778#define IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP1)
1779#define IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP2)
1780
1781#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
1782#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
1783#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
1784#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */

--- 314 unchanged lines hidden (view full) ---

2099#define IXGBE_LINKS_TL_FAULT 0x00001000
2100#define IXGBE_LINKS_SIGNAL 0x00000F00
2101
2102#define IXGBE_LINKS_SPEED_NON_STD 0x08000000
2103#define IXGBE_LINKS_SPEED_82599 0x30000000
2104#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
2105#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
2106#define IXGBE_LINKS_SPEED_100_82599 0x10000000
1868#define IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP0)
1869#define IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP1)
1870#define IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP2)
1871
1872#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
1873#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
1874#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
1875#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */

--- 314 unchanged lines hidden (view full) ---

2190#define IXGBE_LINKS_TL_FAULT 0x00001000
2191#define IXGBE_LINKS_SIGNAL 0x00000F00
2192
2193#define IXGBE_LINKS_SPEED_NON_STD 0x08000000
2194#define IXGBE_LINKS_SPEED_82599 0x30000000
2195#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
2196#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
2197#define IXGBE_LINKS_SPEED_100_82599 0x10000000
2198#define IXGBE_LINKS_SPEED_10_X550EM_A 0x00000000
2107#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
2108#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
2109
2110#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
2111
2112/* PCS1GLSTA Bit Masks */
2113#define IXGBE_PCS1GLSTA_LINK_OK 1
2114#define IXGBE_PCS1GLSTA_SYNK_OK 0x10

--- 29 unchanged lines hidden (view full) ---

2144/* SW_FW_SYNC/GSSR definitions */
2145#define IXGBE_GSSR_EEP_SM 0x0001
2146#define IXGBE_GSSR_PHY0_SM 0x0002
2147#define IXGBE_GSSR_PHY1_SM 0x0004
2148#define IXGBE_GSSR_MAC_CSR_SM 0x0008
2149#define IXGBE_GSSR_FLASH_SM 0x0010
2150#define IXGBE_GSSR_NVM_UPDATE_SM 0x0200
2151#define IXGBE_GSSR_SW_MNG_SM 0x0400
2199#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
2200#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
2201
2202#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
2203
2204/* PCS1GLSTA Bit Masks */
2205#define IXGBE_PCS1GLSTA_LINK_OK 1
2206#define IXGBE_PCS1GLSTA_SYNK_OK 0x10

--- 29 unchanged lines hidden (view full) ---

2236/* SW_FW_SYNC/GSSR definitions */
2237#define IXGBE_GSSR_EEP_SM 0x0001
2238#define IXGBE_GSSR_PHY0_SM 0x0002
2239#define IXGBE_GSSR_PHY1_SM 0x0004
2240#define IXGBE_GSSR_MAC_CSR_SM 0x0008
2241#define IXGBE_GSSR_FLASH_SM 0x0010
2242#define IXGBE_GSSR_NVM_UPDATE_SM 0x0200
2243#define IXGBE_GSSR_SW_MNG_SM 0x0400
2244#define IXGBE_GSSR_TOKEN_SM 0x40000000 /* SW bit for shared access */
2152#define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys and both I2Cs */
2153#define IXGBE_GSSR_I2C_MASK 0x1800
2154#define IXGBE_GSSR_NVM_PHY_MASK 0xF
2155
2156/* FW Status register bitmask */
2157#define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */
2158
2159/* EEC Register */

--- 26 unchanged lines hidden (view full) ---

2186
2187/* Part Number String Length */
2188#define IXGBE_PBANUM_LENGTH 11
2189
2190/* Checksum and EEPROM pointers */
2191#define IXGBE_PBANUM_PTR_GUARD 0xFAFA
2192#define IXGBE_EEPROM_CHECKSUM 0x3F
2193#define IXGBE_EEPROM_SUM 0xBABA
2245#define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys and both I2Cs */
2246#define IXGBE_GSSR_I2C_MASK 0x1800
2247#define IXGBE_GSSR_NVM_PHY_MASK 0xF
2248
2249/* FW Status register bitmask */
2250#define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */
2251
2252/* EEC Register */

--- 26 unchanged lines hidden (view full) ---

2279
2280/* Part Number String Length */
2281#define IXGBE_PBANUM_LENGTH 11
2282
2283/* Checksum and EEPROM pointers */
2284#define IXGBE_PBANUM_PTR_GUARD 0xFAFA
2285#define IXGBE_EEPROM_CHECKSUM 0x3F
2286#define IXGBE_EEPROM_SUM 0xBABA
2287#define IXGBE_EEPROM_CTRL_4 0x45
2288#define IXGBE_EE_CTRL_4_INST_ID 0x10
2289#define IXGBE_EE_CTRL_4_INST_ID_SHIFT 4
2194#define IXGBE_PCIE_ANALOG_PTR 0x03
2195#define IXGBE_ATLAS0_CONFIG_PTR 0x04
2196#define IXGBE_PHY_PTR 0x04
2197#define IXGBE_ATLAS1_CONFIG_PTR 0x05
2198#define IXGBE_OPTION_ROM_PTR 0x05
2199#define IXGBE_PCIE_GENERAL_PTR 0x06
2200#define IXGBE_PCIE_CONFIG0_PTR 0x07
2201#define IXGBE_PCIE_CONFIG1_PTR 0x08

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2213#define IXGBE_FW_PTR 0x0F
2214#define IXGBE_PBANUM0_PTR 0x15
2215#define IXGBE_PBANUM1_PTR 0x16
2216#define IXGBE_ALT_MAC_ADDR_PTR 0x37
2217#define IXGBE_FREE_SPACE_PTR 0X3E
2218
2219#define IXGBE_SAN_MAC_ADDR_PTR 0x28
2220#define IXGBE_DEVICE_CAPS 0x2C
2290#define IXGBE_PCIE_ANALOG_PTR 0x03
2291#define IXGBE_ATLAS0_CONFIG_PTR 0x04
2292#define IXGBE_PHY_PTR 0x04
2293#define IXGBE_ATLAS1_CONFIG_PTR 0x05
2294#define IXGBE_OPTION_ROM_PTR 0x05
2295#define IXGBE_PCIE_GENERAL_PTR 0x06
2296#define IXGBE_PCIE_CONFIG0_PTR 0x07
2297#define IXGBE_PCIE_CONFIG1_PTR 0x08

--- 11 unchanged lines hidden (view full) ---

2309#define IXGBE_FW_PTR 0x0F
2310#define IXGBE_PBANUM0_PTR 0x15
2311#define IXGBE_PBANUM1_PTR 0x16
2312#define IXGBE_ALT_MAC_ADDR_PTR 0x37
2313#define IXGBE_FREE_SPACE_PTR 0X3E
2314
2315#define IXGBE_SAN_MAC_ADDR_PTR 0x28
2316#define IXGBE_DEVICE_CAPS 0x2C
2221#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
2317#define IXGBE_82599_SERIAL_NUMBER_MAC_ADDR 0x11
2318#define IXGBE_X550_SERIAL_NUMBER_MAC_ADDR 0x04
2319
2222#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
2223#define IXGBE_MAX_MSIX_VECTORS_82599 0x40
2224#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
2225#define IXGBE_MAX_MSIX_VECTORS_82598 0x13
2226
2227/* MSI-X capability fields masks */
2228#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
2229

--- 53 unchanged lines hidden (view full) ---

2283#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */
2284#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */
2285#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */
2286
2287#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
2288#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
2289#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
2290#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
2320#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
2321#define IXGBE_MAX_MSIX_VECTORS_82599 0x40
2322#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
2323#define IXGBE_MAX_MSIX_VECTORS_82598 0x13
2324
2325/* MSI-X capability fields masks */
2326#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
2327

--- 53 unchanged lines hidden (view full) ---

2381#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */
2382#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */
2383#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */
2384
2385#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
2386#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
2387#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
2388#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
2389#define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR (1 << 7)
2291#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
2292#define IXGBE_FW_LESM_STATE_1 0x1
2293#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */
2294#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
2295#define IXGBE_FW_PATCH_VERSION_4 0x7
2296#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */
2297#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */
2298#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */

--- 187 unchanged lines hidden (view full) ---

2486#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
2487#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */
2488#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */
2489#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */
2490#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */
2491#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
2492#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
2493#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
2390#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
2391#define IXGBE_FW_LESM_STATE_1 0x1
2392#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */
2393#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
2394#define IXGBE_FW_PATCH_VERSION_4 0x7
2395#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */
2396#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */
2397#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */

--- 187 unchanged lines hidden (view full) ---

2585#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
2586#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */
2587#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */
2588#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */
2589#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */
2590#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
2591#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
2592#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
2593#define IXGBE_MRQC_L3L4TXSWEN 0x00008000 /* Enable L3/L4 Tx switch */
2494#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
2495#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
2496#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
2497#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
2498#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
2499#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
2500#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
2501#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000

--- 155 unchanged lines hidden (view full) ---

2657#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
2658#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
2659#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
2660#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
2661#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
2662#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
2663#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
2664#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
2594#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
2595#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
2596#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
2597#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
2598#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
2599#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
2600#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
2601#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000

--- 155 unchanged lines hidden (view full) ---

2757#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
2758#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
2759#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
2760#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
2761#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
2762#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
2763#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
2764#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
2765#define IXGBE_RXDADV_PKTTYPE_GENEVE 0x00000800 /* GENEVE hdr present */
2665#define IXGBE_RXDADV_PKTTYPE_VXLAN 0x00000800 /* VXLAN hdr present */
2666#define IXGBE_RXDADV_PKTTYPE_TUNNEL 0x00010000 /* Tunnel type */
2667#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
2668#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
2669#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
2670#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
2671#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
2672#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */

--- 72 unchanged lines hidden (view full) ---

2745 : (0x0D018 + (0x40 * ((P) - 64))))
2746#define IXGBE_PVFRXDCTL(P) ((P < 64) ? (0x01028 + (0x40 * (P))) \
2747 : (0x0D028 + (0x40 * ((P) - 64))))
2748#define IXGBE_PVFSRRCTL(P) ((P < 64) ? (0x01014 + (0x40 * (P))) \
2749 : (0x0D014 + (0x40 * ((P) - 64))))
2750#define IXGBE_PVFPSRTYPE(P) (0x0EA00 + (4 * (P)))
2751#define IXGBE_PVFTDBAL(P) (0x06000 + (0x40 * (P)))
2752#define IXGBE_PVFTDBAH(P) (0x06004 + (0x40 * (P)))
2766#define IXGBE_RXDADV_PKTTYPE_VXLAN 0x00000800 /* VXLAN hdr present */
2767#define IXGBE_RXDADV_PKTTYPE_TUNNEL 0x00010000 /* Tunnel type */
2768#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
2769#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
2770#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
2771#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
2772#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
2773#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */

--- 72 unchanged lines hidden (view full) ---

2846 : (0x0D018 + (0x40 * ((P) - 64))))
2847#define IXGBE_PVFRXDCTL(P) ((P < 64) ? (0x01028 + (0x40 * (P))) \
2848 : (0x0D028 + (0x40 * ((P) - 64))))
2849#define IXGBE_PVFSRRCTL(P) ((P < 64) ? (0x01014 + (0x40 * (P))) \
2850 : (0x0D014 + (0x40 * ((P) - 64))))
2851#define IXGBE_PVFPSRTYPE(P) (0x0EA00 + (4 * (P)))
2852#define IXGBE_PVFTDBAL(P) (0x06000 + (0x40 * (P)))
2853#define IXGBE_PVFTDBAH(P) (0x06004 + (0x40 * (P)))
2753#define IXGBE_PVFTTDLEN(P) (0x06008 + (0x40 * (P)))
2854#define IXGBE_PVFTDLEN(P) (0x06008 + (0x40 * (P)))
2754#define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P)))
2755#define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P)))
2756#define IXGBE_PVFTXDCTL(P) (0x06028 + (0x40 * (P)))
2757#define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P)))
2758#define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P)))
2759#define IXGBE_PVFDCA_RXCTRL(P) (((P) < 64) ? (0x0100C + (0x40 * (P))) \
2760 : (0x0D00C + (0x40 * ((P) - 64))))
2761#define IXGBE_PVFDCA_TXCTRL(P) (0x0600C + (0x40 * (P)))

--- 138 unchanged lines hidden (view full) ---

2900/* CEM Support */
2901#define FW_CEM_HDR_LEN 0x4
2902#define FW_CEM_CMD_DRIVER_INFO 0xDD
2903#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5
2904#define FW_CEM_CMD_RESERVED 0X0
2905#define FW_CEM_UNUSED_VER 0x0
2906#define FW_CEM_MAX_RETRIES 3
2907#define FW_CEM_RESP_STATUS_SUCCESS 0x1
2855#define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P)))
2856#define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P)))
2857#define IXGBE_PVFTXDCTL(P) (0x06028 + (0x40 * (P)))
2858#define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P)))
2859#define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P)))
2860#define IXGBE_PVFDCA_RXCTRL(P) (((P) < 64) ? (0x0100C + (0x40 * (P))) \
2861 : (0x0D00C + (0x40 * ((P) - 64))))
2862#define IXGBE_PVFDCA_TXCTRL(P) (0x0600C + (0x40 * (P)))

--- 138 unchanged lines hidden (view full) ---

3001/* CEM Support */
3002#define FW_CEM_HDR_LEN 0x4
3003#define FW_CEM_CMD_DRIVER_INFO 0xDD
3004#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5
3005#define FW_CEM_CMD_RESERVED 0X0
3006#define FW_CEM_UNUSED_VER 0x0
3007#define FW_CEM_MAX_RETRIES 3
3008#define FW_CEM_RESP_STATUS_SUCCESS 0x1
3009#define FW_CEM_DRIVER_VERSION_SIZE 39 /* +9 would send 48 bytes to fw */
2908#define FW_READ_SHADOW_RAM_CMD 0x31
2909#define FW_READ_SHADOW_RAM_LEN 0x6
2910#define FW_WRITE_SHADOW_RAM_CMD 0x33
2911#define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */
2912#define FW_SHADOW_RAM_DUMP_CMD 0x36
2913#define FW_SHADOW_RAM_DUMP_LEN 0
2914#define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
2915#define FW_NVM_DATA_OFFSET 3
2916#define FW_MAX_READ_BUFFER_SIZE 1024
2917#define FW_DISABLE_RXEN_CMD 0xDE
2918#define FW_DISABLE_RXEN_LEN 0x1
2919#define FW_PHY_MGMT_REQ_CMD 0x20
3010#define FW_READ_SHADOW_RAM_CMD 0x31
3011#define FW_READ_SHADOW_RAM_LEN 0x6
3012#define FW_WRITE_SHADOW_RAM_CMD 0x33
3013#define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */
3014#define FW_SHADOW_RAM_DUMP_CMD 0x36
3015#define FW_SHADOW_RAM_DUMP_LEN 0
3016#define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
3017#define FW_NVM_DATA_OFFSET 3
3018#define FW_MAX_READ_BUFFER_SIZE 1024
3019#define FW_DISABLE_RXEN_CMD 0xDE
3020#define FW_DISABLE_RXEN_LEN 0x1
3021#define FW_PHY_MGMT_REQ_CMD 0x20
3022#define FW_PHY_TOKEN_REQ_CMD 0xA
3023#define FW_PHY_TOKEN_REQ_LEN 2
3024#define FW_PHY_TOKEN_REQ 0
3025#define FW_PHY_TOKEN_REL 1
3026#define FW_PHY_TOKEN_OK 1
3027#define FW_PHY_TOKEN_RETRY 0x80
3028#define FW_PHY_TOKEN_DELAY 5 /* milliseconds */
3029#define FW_PHY_TOKEN_WAIT 5 /* seconds */
3030#define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY)
2920#define FW_INT_PHY_REQ_CMD 0xB
2921#define FW_INT_PHY_REQ_LEN 10
2922#define FW_INT_PHY_REQ_READ 0
2923#define FW_INT_PHY_REQ_WRITE 1
3031#define FW_INT_PHY_REQ_CMD 0xB
3032#define FW_INT_PHY_REQ_LEN 10
3033#define FW_INT_PHY_REQ_READ 0
3034#define FW_INT_PHY_REQ_WRITE 1
3035#define FW_PHY_ACT_REQ_CMD 5
3036#define FW_PHY_ACT_DATA_COUNT 4
3037#define FW_PHY_ACT_REQ_LEN (4 + 4 * FW_PHY_ACT_DATA_COUNT)
3038#define FW_PHY_ACT_INIT_PHY 1
3039#define FW_PHY_ACT_SETUP_LINK 2
3040#define FW_PHY_ACT_LINK_SPEED_10 (1u << 0)
3041#define FW_PHY_ACT_LINK_SPEED_100 (1u << 1)
3042#define FW_PHY_ACT_LINK_SPEED_1G (1u << 2)
3043#define FW_PHY_ACT_LINK_SPEED_2_5G (1u << 3)
3044#define FW_PHY_ACT_LINK_SPEED_5G (1u << 4)
3045#define FW_PHY_ACT_LINK_SPEED_10G (1u << 5)
3046#define FW_PHY_ACT_LINK_SPEED_20G (1u << 6)
3047#define FW_PHY_ACT_LINK_SPEED_25G (1u << 7)
3048#define FW_PHY_ACT_LINK_SPEED_40G (1u << 8)
3049#define FW_PHY_ACT_LINK_SPEED_50G (1u << 9)
3050#define FW_PHY_ACT_LINK_SPEED_100G (1u << 10)
3051#define FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT 16
3052#define FW_PHY_ACT_SETUP_LINK_PAUSE_MASK (3u << \
3053 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT)
3054#define FW_PHY_ACT_SETUP_LINK_PAUSE_NONE 0u
3055#define FW_PHY_ACT_SETUP_LINK_PAUSE_TX 1u
3056#define FW_PHY_ACT_SETUP_LINK_PAUSE_RX 2u
3057#define FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 3u
3058#define FW_PHY_ACT_SETUP_LINK_LP (1u << 18)
3059#define FW_PHY_ACT_SETUP_LINK_HP (1u << 19)
3060#define FW_PHY_ACT_SETUP_LINK_EEE (1u << 20)
3061#define FW_PHY_ACT_SETUP_LINK_AN (1u << 22)
3062#define FW_PHY_ACT_SETUP_LINK_RSP_DOWN (1u << 0)
3063#define FW_PHY_ACT_GET_LINK_INFO 3
3064#define FW_PHY_ACT_GET_LINK_INFO_EEE (1u << 19)
3065#define FW_PHY_ACT_GET_LINK_INFO_FC_TX (1u << 20)
3066#define FW_PHY_ACT_GET_LINK_INFO_FC_RX (1u << 21)
3067#define FW_PHY_ACT_GET_LINK_INFO_POWER (1u << 22)
3068#define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE (1u << 24)
3069#define FW_PHY_ACT_GET_LINK_INFO_TEMP (1u << 25)
3070#define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX (1u << 28)
3071#define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX (1u << 29)
3072#define FW_PHY_ACT_FORCE_LINK_DOWN 4
3073#define FW_PHY_ACT_FORCE_LINK_DOWN_OFF (1u << 0)
3074#define FW_PHY_ACT_PHY_SW_RESET 5
3075#define FW_PHY_ACT_PHY_HW_RESET 6
3076#define FW_PHY_ACT_GET_PHY_INFO 7
3077#define FW_PHY_ACT_UD_2 0x1002
3078#define FW_PHY_ACT_UD_2_10G_KR_EEE (1u << 6)
3079#define FW_PHY_ACT_UD_2_10G_KX4_EEE (1u << 5)
3080#define FW_PHY_ACT_UD_2_1G_KX_EEE (1u << 4)
3081#define FW_PHY_ACT_UD_2_10G_T_EEE (1u << 3)
3082#define FW_PHY_ACT_UD_2_1G_T_EEE (1u << 2)
3083#define FW_PHY_ACT_UD_2_100M_TX_EEE (1u << 1)
3084#define FW_PHY_ACT_RETRIES 50
3085#define FW_PHY_INFO_SPEED_MASK 0xFFFu
3086#define FW_PHY_INFO_ID_HI_MASK 0xFFFF0000u
3087#define FW_PHY_INFO_ID_LO_MASK 0x0000FFFFu
2924
2925/* Host Interface Command Structures */
2926
3088
3089/* Host Interface Command Structures */
3090
3091#pragma pack(push, 1)
3092
2927struct ixgbe_hic_hdr {
2928 u8 cmd;
2929 u8 buf_len;
2930 union {
2931 u8 cmd_resv;
2932 u8 ret_status;
2933 } cmd_or_resp;
2934 u8 checksum;

--- 24 unchanged lines hidden (view full) ---

2959 u8 ver_sub;
2960 u8 ver_build;
2961 u8 ver_min;
2962 u8 ver_maj;
2963 u8 pad; /* end spacing to ensure length is mult. of dword */
2964 u16 pad2; /* end spacing to ensure length is mult. of dword2 */
2965};
2966
3093struct ixgbe_hic_hdr {
3094 u8 cmd;
3095 u8 buf_len;
3096 union {
3097 u8 cmd_resv;
3098 u8 ret_status;
3099 } cmd_or_resp;
3100 u8 checksum;

--- 24 unchanged lines hidden (view full) ---

3125 u8 ver_sub;
3126 u8 ver_build;
3127 u8 ver_min;
3128 u8 ver_maj;
3129 u8 pad; /* end spacing to ensure length is mult. of dword */
3130 u16 pad2; /* end spacing to ensure length is mult. of dword2 */
3131};
3132
3133struct ixgbe_hic_drv_info2 {
3134 struct ixgbe_hic_hdr hdr;
3135 u8 port_num;
3136 u8 ver_sub;
3137 u8 ver_build;
3138 u8 ver_min;
3139 u8 ver_maj;
3140 char driver_string[FW_CEM_DRIVER_VERSION_SIZE];
3141};
3142
2967/* These need to be dword aligned */
2968struct ixgbe_hic_read_shadow_ram {
2969 union ixgbe_hic_hdr2 hdr;
2970 u32 address;
2971 u16 length;
2972 u16 pad2;
2973 u16 data;
2974 u16 pad3;

--- 10 unchanged lines hidden (view full) ---

2985
2986struct ixgbe_hic_disable_rxen {
2987 struct ixgbe_hic_hdr hdr;
2988 u8 port_number;
2989 u8 pad2;
2990 u16 pad3;
2991};
2992
3143/* These need to be dword aligned */
3144struct ixgbe_hic_read_shadow_ram {
3145 union ixgbe_hic_hdr2 hdr;
3146 u32 address;
3147 u16 length;
3148 u16 pad2;
3149 u16 data;
3150 u16 pad3;

--- 10 unchanged lines hidden (view full) ---

3161
3162struct ixgbe_hic_disable_rxen {
3163 struct ixgbe_hic_hdr hdr;
3164 u8 port_number;
3165 u8 pad2;
3166 u16 pad3;
3167};
3168
3169struct ixgbe_hic_phy_token_req {
3170 struct ixgbe_hic_hdr hdr;
3171 u8 port_number;
3172 u8 command_type;
3173 u16 pad;
3174};
3175
2993struct ixgbe_hic_internal_phy_req {
2994 struct ixgbe_hic_hdr hdr;
2995 u8 port_number;
2996 u8 command_type;
3176struct ixgbe_hic_internal_phy_req {
3177 struct ixgbe_hic_hdr hdr;
3178 u8 port_number;
3179 u8 command_type;
2997 u16 address;
3180 __be16 address;
2998 u16 rsv1;
3181 u16 rsv1;
2999 u32 write_data;
3182 __be32 write_data;
3000 u16 pad;
3001};
3002
3003struct ixgbe_hic_internal_phy_resp {
3004 struct ixgbe_hic_hdr hdr;
3183 u16 pad;
3184};
3185
3186struct ixgbe_hic_internal_phy_resp {
3187 struct ixgbe_hic_hdr hdr;
3005 u32 read_data;
3188 __be32 read_data;
3006};
3007
3189};
3190
3191struct ixgbe_hic_phy_activity_req {
3192 struct ixgbe_hic_hdr hdr;
3193 u8 port_number;
3194 u8 pad;
3195 __le16 activity_id;
3196 __be32 data[FW_PHY_ACT_DATA_COUNT];
3197};
3008
3198
3199struct ixgbe_hic_phy_activity_resp {
3200 struct ixgbe_hic_hdr hdr;
3201 __be32 data[FW_PHY_ACT_DATA_COUNT];
3202};
3203
3204#pragma pack(pop)
3205
3009/* Transmit Descriptor - Legacy */
3010struct ixgbe_legacy_tx_desc {
3011 u64 buffer_addr; /* Address of the descriptor's data buffer */
3012 union {
3013 __le32 data;
3014 struct {
3015 __le16 length; /* Data buffer length */
3016 u8 cso; /* Checksum offset */

--- 108 unchanged lines hidden (view full) ---

3125#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
3126#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
3127#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
3128#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
3129#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
3130#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
3131#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
3132#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
3206/* Transmit Descriptor - Legacy */
3207struct ixgbe_legacy_tx_desc {
3208 u64 buffer_addr; /* Address of the descriptor's data buffer */
3209 union {
3210 __le32 data;
3211 struct {
3212 __le16 length; /* Data buffer length */
3213 u8 cso; /* Checksum offset */

--- 108 unchanged lines hidden (view full) ---

3322#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
3323#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
3324#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
3325#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
3326#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
3327#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
3328#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
3329#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
3330#define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* RSV L4 Packet TYPE */
3133#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* req Markers and CRC */
3134#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
3135#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
3136#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
3137#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */
3138#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */
3139#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */
3140#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */

--- 6 unchanged lines hidden (view full) ---

3147#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
3148#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
3149
3150#define IXGBE_ADVTXD_OUTER_IPLEN 16 /* Adv ctxt OUTERIPLEN shift */
3151#define IXGBE_ADVTXD_TUNNEL_LEN 24 /* Adv ctxt TUNNELLEN shift */
3152#define IXGBE_ADVTXD_TUNNEL_TYPE_SHIFT 16 /* Adv Tx Desc Tunnel Type shift */
3153#define IXGBE_ADVTXD_OUTERIPCS_SHIFT 17 /* Adv Tx Desc OUTERIPCS Shift */
3154#define IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE 1 /* Adv Tx Desc Tunnel Type NVGRE */
3331#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* req Markers and CRC */
3332#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
3333#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
3334#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
3335#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */
3336#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */
3337#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */
3338#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */

--- 6 unchanged lines hidden (view full) ---

3345#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
3346#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
3347
3348#define IXGBE_ADVTXD_OUTER_IPLEN 16 /* Adv ctxt OUTERIPLEN shift */
3349#define IXGBE_ADVTXD_TUNNEL_LEN 24 /* Adv ctxt TUNNELLEN shift */
3350#define IXGBE_ADVTXD_TUNNEL_TYPE_SHIFT 16 /* Adv Tx Desc Tunnel Type shift */
3351#define IXGBE_ADVTXD_OUTERIPCS_SHIFT 17 /* Adv Tx Desc OUTERIPCS Shift */
3352#define IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE 1 /* Adv Tx Desc Tunnel Type NVGRE */
3155
3353/* Adv Tx Desc OUTERIPCS Shift for X550EM_a */
3354#define IXGBE_ADVTXD_OUTERIPCS_SHIFT_X550EM_a 26
3156/* Autonegotiation advertised speeds */
3157typedef u32 ixgbe_autoneg_advertised;
3158/* Link speed */
3159typedef u32 ixgbe_link_speed;
3160#define IXGBE_LINK_SPEED_UNKNOWN 0
3355/* Autonegotiation advertised speeds */
3356typedef u32 ixgbe_autoneg_advertised;
3357/* Link speed */
3358typedef u32 ixgbe_link_speed;
3359#define IXGBE_LINK_SPEED_UNKNOWN 0
3360#define IXGBE_LINK_SPEED_10_FULL 0x0002
3161#define IXGBE_LINK_SPEED_100_FULL 0x0008
3162#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
3163#define IXGBE_LINK_SPEED_2_5GB_FULL 0x0400
3164#define IXGBE_LINK_SPEED_5GB_FULL 0x0800
3165#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
3166#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
3167 IXGBE_LINK_SPEED_10GB_FULL)
3168#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
3169 IXGBE_LINK_SPEED_1GB_FULL | \
3170 IXGBE_LINK_SPEED_10GB_FULL)
3171
3172/* Physical layer type */
3361#define IXGBE_LINK_SPEED_100_FULL 0x0008
3362#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
3363#define IXGBE_LINK_SPEED_2_5GB_FULL 0x0400
3364#define IXGBE_LINK_SPEED_5GB_FULL 0x0800
3365#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
3366#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
3367 IXGBE_LINK_SPEED_10GB_FULL)
3368#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
3369 IXGBE_LINK_SPEED_1GB_FULL | \
3370 IXGBE_LINK_SPEED_10GB_FULL)
3371
3372/* Physical layer type */
3173typedef u32 ixgbe_physical_layer;
3373typedef u64 ixgbe_physical_layer;
3174#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
3374#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
3175#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
3176#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
3177#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004
3178#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
3179#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
3180#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
3181#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
3182#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
3183#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
3184#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
3185#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
3186#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
3187#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
3188#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
3189#define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x4000
3375#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x00001
3376#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x00002
3377#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x00004
3378#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x00008
3379#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x00010
3380#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x00020
3381#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x00040
3382#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x00080
3383#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x00100
3384#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x00200
3385#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x00400
3386#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x00800
3387#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x01000
3388#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x02000
3389#define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x04000
3390#define IXGBE_PHYSICAL_LAYER_10BASE_T 0x08000
3391#define IXGBE_PHYSICAL_LAYER_2500BASE_KX 0x10000
3190
3191/* Flow Control Data Sheet defined values
3192 * Calculation and defines taken from 802.1bb Annex O
3193 */
3194
3195/* BitTimes (BT) conversion */
3196#define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
3197#define IXGBE_B2BT(BT) (BT * 8)

--- 188 unchanged lines hidden (view full) ---

3386 ixgbe_mac_unknown = 0,
3387 ixgbe_mac_82598EB,
3388 ixgbe_mac_82599EB,
3389 ixgbe_mac_82599_vf,
3390 ixgbe_mac_X540,
3391 ixgbe_mac_X540_vf,
3392 ixgbe_mac_X550,
3393 ixgbe_mac_X550EM_x,
3392
3393/* Flow Control Data Sheet defined values
3394 * Calculation and defines taken from 802.1bb Annex O
3395 */
3396
3397/* BitTimes (BT) conversion */
3398#define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
3399#define IXGBE_B2BT(BT) (BT * 8)

--- 188 unchanged lines hidden (view full) ---

3588 ixgbe_mac_unknown = 0,
3589 ixgbe_mac_82598EB,
3590 ixgbe_mac_82599EB,
3591 ixgbe_mac_82599_vf,
3592 ixgbe_mac_X540,
3593 ixgbe_mac_X540_vf,
3594 ixgbe_mac_X550,
3595 ixgbe_mac_X550EM_x,
3596 ixgbe_mac_X550EM_a,
3394 ixgbe_mac_X550_vf,
3395 ixgbe_mac_X550EM_x_vf,
3597 ixgbe_mac_X550_vf,
3598 ixgbe_mac_X550EM_x_vf,
3599 ixgbe_mac_X550EM_a_vf,
3396 ixgbe_num_macs
3397};
3398
3399enum ixgbe_phy_type {
3400 ixgbe_phy_unknown = 0,
3401 ixgbe_phy_none,
3402 ixgbe_phy_tn,
3403 ixgbe_phy_aq,
3404 ixgbe_phy_x550em_kr,
3405 ixgbe_phy_x550em_kx4,
3600 ixgbe_num_macs
3601};
3602
3603enum ixgbe_phy_type {
3604 ixgbe_phy_unknown = 0,
3605 ixgbe_phy_none,
3606 ixgbe_phy_tn,
3607 ixgbe_phy_aq,
3608 ixgbe_phy_x550em_kr,
3609 ixgbe_phy_x550em_kx4,
3610 ixgbe_phy_x550em_xfi,
3406 ixgbe_phy_x550em_ext_t,
3611 ixgbe_phy_x550em_ext_t,
3612 ixgbe_phy_ext_1g_t,
3407 ixgbe_phy_cu_unknown,
3408 ixgbe_phy_qt,
3409 ixgbe_phy_xaui,
3410 ixgbe_phy_nl,
3411 ixgbe_phy_sfp_passive_tyco,
3412 ixgbe_phy_sfp_passive_unknown,
3413 ixgbe_phy_sfp_active_unknown,
3414 ixgbe_phy_sfp_avago,
3415 ixgbe_phy_sfp_ftl,
3416 ixgbe_phy_sfp_ftl_active,
3417 ixgbe_phy_sfp_unknown,
3418 ixgbe_phy_sfp_intel,
3419 ixgbe_phy_qsfp_passive_unknown,
3420 ixgbe_phy_qsfp_active_unknown,
3421 ixgbe_phy_qsfp_intel,
3422 ixgbe_phy_qsfp_unknown,
3423 ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/
3613 ixgbe_phy_cu_unknown,
3614 ixgbe_phy_qt,
3615 ixgbe_phy_xaui,
3616 ixgbe_phy_nl,
3617 ixgbe_phy_sfp_passive_tyco,
3618 ixgbe_phy_sfp_passive_unknown,
3619 ixgbe_phy_sfp_active_unknown,
3620 ixgbe_phy_sfp_avago,
3621 ixgbe_phy_sfp_ftl,
3622 ixgbe_phy_sfp_ftl_active,
3623 ixgbe_phy_sfp_unknown,
3624 ixgbe_phy_sfp_intel,
3625 ixgbe_phy_qsfp_passive_unknown,
3626 ixgbe_phy_qsfp_active_unknown,
3627 ixgbe_phy_qsfp_intel,
3628 ixgbe_phy_qsfp_unknown,
3629 ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/
3630 ixgbe_phy_sgmii,
3631 ixgbe_phy_fw,
3424 ixgbe_phy_generic
3425};
3426
3427/*
3428 * SFP+ module type IDs:
3429 *
3430 * ID Module Type
3431 * =============

--- 99 unchanged lines hidden (view full) ---

3531
3532/* Bus parameters */
3533struct ixgbe_bus_info {
3534 enum ixgbe_bus_speed speed;
3535 enum ixgbe_bus_width width;
3536 enum ixgbe_bus_type type;
3537
3538 u16 func;
3632 ixgbe_phy_generic
3633};
3634
3635/*
3636 * SFP+ module type IDs:
3637 *
3638 * ID Module Type
3639 * =============

--- 99 unchanged lines hidden (view full) ---

3739
3740/* Bus parameters */
3741struct ixgbe_bus_info {
3742 enum ixgbe_bus_speed speed;
3743 enum ixgbe_bus_width width;
3744 enum ixgbe_bus_type type;
3745
3746 u16 func;
3539 u16 lan_id;
3747 u8 lan_id;
3748 u16 instance_id;
3540};
3541
3542/* Flow control parameters */
3543struct ixgbe_fc_info {
3544 u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */
3545 u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */
3546 u16 pause_time; /* Flow Control Pause timer */
3547 bool send_xon; /* Flow control send XON */

--- 105 unchanged lines hidden (view full) ---

3653
3654struct ixgbe_mac_operations {
3655 s32 (*init_hw)(struct ixgbe_hw *);
3656 s32 (*reset_hw)(struct ixgbe_hw *);
3657 s32 (*start_hw)(struct ixgbe_hw *);
3658 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
3659 void (*enable_relaxed_ordering)(struct ixgbe_hw *);
3660 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
3749};
3750
3751/* Flow control parameters */
3752struct ixgbe_fc_info {
3753 u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */
3754 u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */
3755 u16 pause_time; /* Flow Control Pause timer */
3756 bool send_xon; /* Flow control send XON */

--- 105 unchanged lines hidden (view full) ---

3862
3863struct ixgbe_mac_operations {
3864 s32 (*init_hw)(struct ixgbe_hw *);
3865 s32 (*reset_hw)(struct ixgbe_hw *);
3866 s32 (*start_hw)(struct ixgbe_hw *);
3867 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
3868 void (*enable_relaxed_ordering)(struct ixgbe_hw *);
3869 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
3661 u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
3870 u64 (*get_supported_physical_layer)(struct ixgbe_hw *);
3662 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
3663 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
3664 s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *);
3665 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
3666 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
3667 s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *);
3668 s32 (*stop_adapter)(struct ixgbe_hw *);
3669 s32 (*get_bus_info)(struct ixgbe_hw *);
3871 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
3872 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
3873 s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *);
3874 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
3875 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
3876 s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *);
3877 s32 (*stop_adapter)(struct ixgbe_hw *);
3878 s32 (*get_bus_info)(struct ixgbe_hw *);
3879 s32 (*negotiate_api_version)(struct ixgbe_hw *, int);
3670 void (*set_lan_id)(struct ixgbe_hw *);
3671 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
3672 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
3673 s32 (*setup_sfp)(struct ixgbe_hw *);
3674 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
3675 s32 (*disable_sec_rx_path)(struct ixgbe_hw *);
3676 s32 (*enable_sec_rx_path)(struct ixgbe_hw *);
3677 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32);
3678 void (*release_swfw_sync)(struct ixgbe_hw *, u32);
3880 void (*set_lan_id)(struct ixgbe_hw *);
3881 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
3882 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
3883 s32 (*setup_sfp)(struct ixgbe_hw *);
3884 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
3885 s32 (*disable_sec_rx_path)(struct ixgbe_hw *);
3886 s32 (*enable_sec_rx_path)(struct ixgbe_hw *);
3887 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32);
3888 void (*release_swfw_sync)(struct ixgbe_hw *, u32);
3889 void (*init_swfw_sync)(struct ixgbe_hw *);
3679 s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
3680 s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
3681
3682 /* Link */
3683 void (*disable_tx_laser)(struct ixgbe_hw *);
3684 void (*enable_tx_laser)(struct ixgbe_hw *);
3685 void (*flap_tx_laser)(struct ixgbe_hw *);
3686 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);

--- 6 unchanged lines hidden (view full) ---

3693 /* Packet Buffer manipulation */
3694 void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int);
3695
3696 /* LED */
3697 s32 (*led_on)(struct ixgbe_hw *, u32);
3698 s32 (*led_off)(struct ixgbe_hw *, u32);
3699 s32 (*blink_led_start)(struct ixgbe_hw *, u32);
3700 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
3890 s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
3891 s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
3892
3893 /* Link */
3894 void (*disable_tx_laser)(struct ixgbe_hw *);
3895 void (*enable_tx_laser)(struct ixgbe_hw *);
3896 void (*flap_tx_laser)(struct ixgbe_hw *);
3897 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);

--- 6 unchanged lines hidden (view full) ---

3904 /* Packet Buffer manipulation */
3905 void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int);
3906
3907 /* LED */
3908 s32 (*led_on)(struct ixgbe_hw *, u32);
3909 s32 (*led_off)(struct ixgbe_hw *, u32);
3910 s32 (*blink_led_start)(struct ixgbe_hw *, u32);
3911 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
3912 s32 (*init_led_link_act)(struct ixgbe_hw *);
3701
3702 /* RAR, Multicast, VLAN */
3703 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
3704 s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);
3705 s32 (*clear_rar)(struct ixgbe_hw *, u32);
3706 s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);
3707 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
3708 s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
3709 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
3710 s32 (*init_rx_addrs)(struct ixgbe_hw *);
3711 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
3712 ixgbe_mc_addr_itr);
3713 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
3714 ixgbe_mc_addr_itr, bool clear);
3913
3914 /* RAR, Multicast, VLAN */
3915 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
3916 s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);
3917 s32 (*clear_rar)(struct ixgbe_hw *, u32);
3918 s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);
3919 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
3920 s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
3921 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
3922 s32 (*init_rx_addrs)(struct ixgbe_hw *);
3923 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
3924 ixgbe_mc_addr_itr);
3925 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
3926 ixgbe_mc_addr_itr, bool clear);
3927 s32 (*update_xcast_mode)(struct ixgbe_hw *, int);
3715 s32 (*enable_mc)(struct ixgbe_hw *);
3716 s32 (*disable_mc)(struct ixgbe_hw *);
3717 s32 (*clear_vfta)(struct ixgbe_hw *);
3928 s32 (*enable_mc)(struct ixgbe_hw *);
3929 s32 (*disable_mc)(struct ixgbe_hw *);
3930 s32 (*clear_vfta)(struct ixgbe_hw *);
3718 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
3719 s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, bool *);
3931 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool);
3932 s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, u32 *, u32,
3933 bool);
3934 s32 (*set_rlpml)(struct ixgbe_hw *, u16);
3720 s32 (*init_uta_tables)(struct ixgbe_hw *);
3721 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
3722 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
3723
3724 /* Flow Control */
3725 s32 (*fc_enable)(struct ixgbe_hw *);
3726 s32 (*setup_fc)(struct ixgbe_hw *);
3935 s32 (*init_uta_tables)(struct ixgbe_hw *);
3936 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
3937 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
3938
3939 /* Flow Control */
3940 s32 (*fc_enable)(struct ixgbe_hw *);
3941 s32 (*setup_fc)(struct ixgbe_hw *);
3942 void (*fc_autoneg)(struct ixgbe_hw *);
3727
3728 /* Manageability interface */
3943
3944 /* Manageability interface */
3729 s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
3945 s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8, u16,
3946 const char *);
3947 s32 (*bypass_rw) (struct ixgbe_hw *hw, u32 cmd, u32 *status);
3948 bool (*bypass_valid_rd) (u32 in_reg, u32 out_reg);
3949 s32 (*bypass_set) (struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action);
3950 s32 (*bypass_rd_eep) (struct ixgbe_hw *hw, u32 addr, u8 *value);
3730 void (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map);
3731 void (*disable_rx)(struct ixgbe_hw *hw);
3732 void (*enable_rx)(struct ixgbe_hw *hw);
3733 void (*set_source_address_pruning)(struct ixgbe_hw *, bool,
3734 unsigned int);
3735 void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int);
3736 s32 (*dmac_update_tcs)(struct ixgbe_hw *hw);
3737 s32 (*dmac_config_tcs)(struct ixgbe_hw *hw);

--- 22 unchanged lines hidden (view full) ---

3760 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
3761 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
3762 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
3763 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
3764 s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);
3765 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
3766 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
3767 void (*i2c_bus_clear)(struct ixgbe_hw *);
3951 void (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map);
3952 void (*disable_rx)(struct ixgbe_hw *hw);
3953 void (*enable_rx)(struct ixgbe_hw *hw);
3954 void (*set_source_address_pruning)(struct ixgbe_hw *, bool,
3955 unsigned int);
3956 void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int);
3957 s32 (*dmac_update_tcs)(struct ixgbe_hw *hw);
3958 s32 (*dmac_config_tcs)(struct ixgbe_hw *hw);

--- 22 unchanged lines hidden (view full) ---

3981 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
3982 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
3983 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
3984 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
3985 s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);
3986 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
3987 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
3988 void (*i2c_bus_clear)(struct ixgbe_hw *);
3768 s32 (*read_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);
3769 s32 (*write_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);
3770 s32 (*check_overtemp)(struct ixgbe_hw *);
3771 s32 (*set_phy_power)(struct ixgbe_hw *, bool on);
3772 s32 (*enter_lplu)(struct ixgbe_hw *);
3773 s32 (*handle_lasi)(struct ixgbe_hw *hw);
3989 s32 (*check_overtemp)(struct ixgbe_hw *);
3990 s32 (*set_phy_power)(struct ixgbe_hw *, bool on);
3991 s32 (*enter_lplu)(struct ixgbe_hw *);
3992 s32 (*handle_lasi)(struct ixgbe_hw *hw);
3774 s32 (*read_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
3775 u16 *value);
3776 s32 (*write_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
3777 u16 value);
3778 s32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
3779 u8 *value);
3780 s32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
3781 u8 value);
3782};
3783
3993 s32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
3994 u8 *value);
3995 s32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
3996 u8 value);
3997};
3998
3999struct ixgbe_link_operations {
4000 s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);
4001 s32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
4002 u16 *val);
4003 s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);
4004 s32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
4005 u16 val);
4006};
4007
4008struct ixgbe_link_info {
4009 struct ixgbe_link_operations ops;
4010 u8 addr;
4011};
4012
3784struct ixgbe_eeprom_info {
3785 struct ixgbe_eeprom_operations ops;
3786 enum ixgbe_eeprom_type type;
3787 u32 semaphore_delay;
3788 u16 word_size;
3789 u16 address_bits;
3790 u16 word_page_size;
3791 u16 ctrl_word_3;

--- 27 unchanged lines hidden (view full) ---

3819 u16 max_msix_vectors;
3820 bool arc_subsystem_valid;
3821 bool orig_link_settings_stored;
3822 bool autotry_restart;
3823 u8 flags;
3824 struct ixgbe_dmac_config dmac_config;
3825 bool set_lben;
3826 u32 max_link_up_time;
4013struct ixgbe_eeprom_info {
4014 struct ixgbe_eeprom_operations ops;
4015 enum ixgbe_eeprom_type type;
4016 u32 semaphore_delay;
4017 u16 word_size;
4018 u16 address_bits;
4019 u16 word_page_size;
4020 u16 ctrl_word_3;

--- 27 unchanged lines hidden (view full) ---

4048 u16 max_msix_vectors;
4049 bool arc_subsystem_valid;
4050 bool orig_link_settings_stored;
4051 bool autotry_restart;
4052 u8 flags;
4053 struct ixgbe_dmac_config dmac_config;
4054 bool set_lben;
4055 u32 max_link_up_time;
4056 u8 led_link_act;
3827};
3828
3829struct ixgbe_phy_info {
3830 struct ixgbe_phy_operations ops;
3831 enum ixgbe_phy_type type;
3832 u32 addr;
3833 u32 id;
3834 enum ixgbe_sfp_type sfp_type;
3835 bool sfp_setup_needed;
3836 u32 revision;
3837 enum ixgbe_media_type media_type;
3838 u32 phy_semaphore_mask;
3839 bool reset_disable;
3840 ixgbe_autoneg_advertised autoneg_advertised;
3841 ixgbe_link_speed speeds_supported;
4057};
4058
4059struct ixgbe_phy_info {
4060 struct ixgbe_phy_operations ops;
4061 enum ixgbe_phy_type type;
4062 u32 addr;
4063 u32 id;
4064 enum ixgbe_sfp_type sfp_type;
4065 bool sfp_setup_needed;
4066 u32 revision;
4067 enum ixgbe_media_type media_type;
4068 u32 phy_semaphore_mask;
4069 bool reset_disable;
4070 ixgbe_autoneg_advertised autoneg_advertised;
4071 ixgbe_link_speed speeds_supported;
4072 ixgbe_link_speed eee_speeds_supported;
4073 ixgbe_link_speed eee_speeds_advertised;
3842 enum ixgbe_smart_speed smart_speed;
3843 bool smart_speed_active;
3844 bool multispeed_fiber;
3845 bool reset_if_overtemp;
3846 bool qsfp_shared_i2c_bus;
3847 u32 nw_mng_if_sel;
3848};
3849

--- 30 unchanged lines hidden (view full) ---

3880
3881struct ixgbe_hw {
3882 u8 IOMEM *hw_addr;
3883 void *back;
3884 struct ixgbe_mac_info mac;
3885 struct ixgbe_addr_filter_info addr_ctrl;
3886 struct ixgbe_fc_info fc;
3887 struct ixgbe_phy_info phy;
4074 enum ixgbe_smart_speed smart_speed;
4075 bool smart_speed_active;
4076 bool multispeed_fiber;
4077 bool reset_if_overtemp;
4078 bool qsfp_shared_i2c_bus;
4079 u32 nw_mng_if_sel;
4080};
4081

--- 30 unchanged lines hidden (view full) ---

4112
4113struct ixgbe_hw {
4114 u8 IOMEM *hw_addr;
4115 void *back;
4116 struct ixgbe_mac_info mac;
4117 struct ixgbe_addr_filter_info addr_ctrl;
4118 struct ixgbe_fc_info fc;
4119 struct ixgbe_phy_info phy;
4120 struct ixgbe_link_info link;
3888 struct ixgbe_eeprom_info eeprom;
3889 struct ixgbe_bus_info bus;
3890 struct ixgbe_mbx_info mbx;
3891 const u32 *mvals;
3892 u16 device_id;
3893 u16 vendor_id;
3894 u16 subsystem_device_id;
3895 u16 subsystem_vendor_id;
3896 u8 revision_id;
3897 bool adapter_stopped;
3898 int api_version;
3899 bool force_full_reset;
3900 bool allow_unsupported_sfp;
3901 bool wol_enabled;
4121 struct ixgbe_eeprom_info eeprom;
4122 struct ixgbe_bus_info bus;
4123 struct ixgbe_mbx_info mbx;
4124 const u32 *mvals;
4125 u16 device_id;
4126 u16 vendor_id;
4127 u16 subsystem_device_id;
4128 u16 subsystem_vendor_id;
4129 u8 revision_id;
4130 bool adapter_stopped;
4131 int api_version;
4132 bool force_full_reset;
4133 bool allow_unsupported_sfp;
4134 bool wol_enabled;
4135 bool need_crosstalk_fix;
3902};
3903
3904#define ixgbe_call_func(hw, func, params, error) \
3905 (func != NULL) ? func params : error
3906
3907
3908/* Error Codes */
3909#define IXGBE_SUCCESS 0

--- 25 unchanged lines hidden (view full) ---

3935#define IXGBE_ERR_OVERTEMP -26
3936#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
3937#define IXGBE_ERR_FC_NOT_SUPPORTED -28
3938#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
3939#define IXGBE_ERR_PBA_SECTION -31
3940#define IXGBE_ERR_INVALID_ARGUMENT -32
3941#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
3942#define IXGBE_ERR_OUT_OF_MEM -34
4136};
4137
4138#define ixgbe_call_func(hw, func, params, error) \
4139 (func != NULL) ? func params : error
4140
4141
4142/* Error Codes */
4143#define IXGBE_SUCCESS 0

--- 25 unchanged lines hidden (view full) ---

4169#define IXGBE_ERR_OVERTEMP -26
4170#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
4171#define IXGBE_ERR_FC_NOT_SUPPORTED -28
4172#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
4173#define IXGBE_ERR_PBA_SECTION -31
4174#define IXGBE_ERR_INVALID_ARGUMENT -32
4175#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
4176#define IXGBE_ERR_OUT_OF_MEM -34
4177#define IXGBE_BYPASS_FW_WRITE_FAILURE -35
3943#define IXGBE_ERR_FEATURE_NOT_SUPPORTED -36
3944#define IXGBE_ERR_EEPROM_PROTECTED_REGION -37
3945#define IXGBE_ERR_FDIR_CMD_INCOMPLETE -38
4178#define IXGBE_ERR_FEATURE_NOT_SUPPORTED -36
4179#define IXGBE_ERR_EEPROM_PROTECTED_REGION -37
4180#define IXGBE_ERR_FDIR_CMD_INCOMPLETE -38
4181#define IXGBE_ERR_FW_RESP_INVALID -39
4182#define IXGBE_ERR_TOKEN_RETRY -40
3946
3947#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
3948
3949
4183
4184#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
4185
4186
4187#define BYPASS_PAGE_CTL0 0x00000000
4188#define BYPASS_PAGE_CTL1 0x40000000
4189#define BYPASS_PAGE_CTL2 0x80000000
4190#define BYPASS_PAGE_M 0xc0000000
4191#define BYPASS_WE 0x20000000
4192
4193#define BYPASS_AUTO 0x0
4194#define BYPASS_NOP 0x0
4195#define BYPASS_NORM 0x1
4196#define BYPASS_BYPASS 0x2
4197#define BYPASS_ISOLATE 0x3
4198
4199#define BYPASS_EVENT_MAIN_ON 0x1
4200#define BYPASS_EVENT_AUX_ON 0x2
4201#define BYPASS_EVENT_MAIN_OFF 0x3
4202#define BYPASS_EVENT_AUX_OFF 0x4
4203#define BYPASS_EVENT_WDT_TO 0x5
4204#define BYPASS_EVENT_USR 0x6
4205
4206#define BYPASS_MODE_OFF_M 0x00000003
4207#define BYPASS_STATUS_OFF_M 0x0000000c
4208#define BYPASS_AUX_ON_M 0x00000030
4209#define BYPASS_MAIN_ON_M 0x000000c0
4210#define BYPASS_MAIN_OFF_M 0x00000300
4211#define BYPASS_AUX_OFF_M 0x00000c00
4212#define BYPASS_WDTIMEOUT_M 0x00003000
4213#define BYPASS_WDT_ENABLE_M 0x00004000
4214#define BYPASS_WDT_VALUE_M 0x00070000
4215
4216#define BYPASS_MODE_OFF_SHIFT 0
4217#define BYPASS_STATUS_OFF_SHIFT 2
4218#define BYPASS_AUX_ON_SHIFT 4
4219#define BYPASS_MAIN_ON_SHIFT 6
4220#define BYPASS_MAIN_OFF_SHIFT 8
4221#define BYPASS_AUX_OFF_SHIFT 10
4222#define BYPASS_WDTIMEOUT_SHIFT 12
4223#define BYPASS_WDT_ENABLE_SHIFT 14
4224#define BYPASS_WDT_TIME_SHIFT 16
4225
4226#define BYPASS_WDT_1 0x0
4227#define BYPASS_WDT_1_5 0x1
4228#define BYPASS_WDT_2 0x2
4229#define BYPASS_WDT_3 0x3
4230#define BYPASS_WDT_4 0x4
4231#define BYPASS_WDT_8 0x5
4232#define BYPASS_WDT_16 0x6
4233#define BYPASS_WDT_32 0x7
4234#define BYPASS_WDT_OFF 0xffff
4235
4236#define BYPASS_CTL1_TIME_M 0x01ffffff
4237#define BYPASS_CTL1_VALID_M 0x02000000
4238#define BYPASS_CTL1_OFFTRST_M 0x04000000
4239#define BYPASS_CTL1_WDT_PET_M 0x08000000
4240
4241#define BYPASS_CTL1_VALID 0x02000000
4242#define BYPASS_CTL1_OFFTRST 0x04000000
4243#define BYPASS_CTL1_WDT_PET 0x08000000
4244
4245#define BYPASS_CTL2_DATA_M 0x000000ff
4246#define BYPASS_CTL2_OFFSET_M 0x0000ff00
4247#define BYPASS_CTL2_RW_M 0x00010000
4248#define BYPASS_CTL2_HEAD_M 0x0ff00000
4249
4250#define BYPASS_CTL2_OFFSET_SHIFT 8
4251#define BYPASS_CTL2_HEAD_SHIFT 20
4252
4253#define BYPASS_CTL2_RW 0x00010000
4254
4255struct ixgbe_bypass_eeprom {
4256 u32 logs;
4257 u32 clear_off;
4258 u8 actions;
4259};
4260
4261#define BYPASS_MAX_LOGS 43
4262#define BYPASS_LOG_SIZE 5
4263#define BYPASS_LOG_LINE_SIZE 37
4264
4265#define BYPASS_EEPROM_VER_ADD 0x02
4266
4267#define BYPASS_LOG_TIME_M 0x01ffffff
4268#define BYPASS_LOG_TIME_VALID_M 0x02000000
4269#define BYPASS_LOG_HEAD_M 0x04000000
4270#define BYPASS_LOG_CLEAR_M 0x08000000
4271#define BYPASS_LOG_EVENT_M 0xf0000000
4272#define BYPASS_LOG_ACTION_M 0x03
4273
4274#define BYPASS_LOG_EVENT_SHIFT 28
4275#define BYPASS_LOG_CLEAR_SHIFT 24 /* bit offset */
4276
4277
3950#define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4))
3951#define IXGBE_FUSES0_300MHZ (1 << 5)
4278#define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4))
4279#define IXGBE_FUSES0_300MHZ (1 << 5)
3952#define IXGBE_FUSES0_REV1 (1 << 6)
4280#define IXGBE_FUSES0_REV_MASK (3 << 6)
3953
3954#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)
4281
4282#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)
4283#define IXGBE_KRM_LINK_S1(P) ((P) ? 0x8200 : 0x4200)
3955#define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)
3956#define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C)
4284#define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)
4285#define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C)
4286#define IXGBE_KRM_AN_CNTL_4(P) ((P) ? 0x8238 : 0x4238)
4287#define IXGBE_KRM_AN_CNTL_8(P) ((P) ? 0x8248 : 0x4248)
4288#define IXGBE_KRM_PCS_KX_AN(P) ((P) ? 0x9918 : 0x5918)
4289#define IXGBE_KRM_PCS_KX_AN_LP(P) ((P) ? 0x991C : 0x591C)
4290#define IXGBE_KRM_SGMII_CTRL(P) ((P) ? 0x82A0 : 0x42A0)
4291#define IXGBE_KRM_LP_BASE_PAGE_HIGH(P) ((P) ? 0x836C : 0x436C)
3957#define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634)
3958#define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638)
3959#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00)
3960#define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00)
4292#define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634)
4293#define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638)
4294#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00)
4295#define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00)
4296#define IXGBE_KRM_PMD_FLX_MASK_ST20(P) ((P) ? 0x9054 : 0x5054)
3961#define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520)
3962#define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00)
3963
4297#define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520)
4298#define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00)
4299
4300#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA ~(0x3 << 20)
4301#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR (1u << 20)
4302#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_LR (0x2 << 20)
4303#define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN (1u << 25)
4304#define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN (1u << 26)
4305#define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN (1u << 27)
4306#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M ~(0x7 << 28)
4307#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M (1u << 28)
4308#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G (0x2 << 28)
4309#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G (0x3 << 28)
4310#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN (0x4 << 28)
4311#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G (0x7 << 28)
4312#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK (0x7 << 28)
4313#define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART (1u << 31)
4314
3964#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9)
3965#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11)
3966
3967#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8)
3968#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8)
3969#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8)
4315#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9)
4316#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11)
4317
4318#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8)
4319#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8)
4320#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8)
4321#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN (1 << 12)
4322#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN (1 << 13)
3970#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14)
3971#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15)
3972#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16)
3973#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18)
3974#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24)
3975#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26)
4323#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14)
4324#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15)
4325#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16)
4326#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18)
4327#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24)
4328#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26)
4329#define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE (1 << 28)
3976#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29)
3977#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31)
3978
3979#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE (1 << 28)
3980#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE (1 << 29)
4330#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29)
4331#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31)
4332
4333#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE (1 << 28)
4334#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE (1 << 29)
4335#define IXGBE_KRM_PCS_KX_AN_SYM_PAUSE (1 << 1)
4336#define IXGBE_KRM_PCS_KX_AN_ASM_PAUSE (1 << 2)
4337#define IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE (1 << 2)
4338#define IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE (1 << 3)
4339#define IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73 (1 << 29)
4340#define IXGBE_KRM_AN_CNTL_8_LINEAR (1 << 0)
4341#define IXGBE_KRM_AN_CNTL_8_LIMITING (1 << 1)
3981
4342
4343#define IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE (1 << 10)
4344#define IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE (1 << 11)
4345
4346#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D (1 << 12)
4347#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D (1 << 19)
4348
3982#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6)
3983#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15)
3984#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16)
3985
3986#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4)
3987#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2)
3988
3989#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16)

--- 16 unchanged lines hidden (view full) ---

4006 (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
4007#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28
4008#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7
4009#define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31
4010#define IXGBE_SB_IOSF_CTRL_BUSY (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
4011#define IXGBE_SB_IOSF_TARGET_KR_PHY 0
4012
4013#define IXGBE_NW_MNG_IF_SEL 0x00011178
4349#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6)
4350#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15)
4351#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16)
4352
4353#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4)
4354#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2)
4355
4356#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16)

--- 16 unchanged lines hidden (view full) ---

4373 (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
4374#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28
4375#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7
4376#define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31
4377#define IXGBE_SB_IOSF_CTRL_BUSY (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
4378#define IXGBE_SB_IOSF_TARGET_KR_PHY 0
4379
4380#define IXGBE_NW_MNG_IF_SEL 0x00011178
4014#define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24)
4381#define IXGBE_NW_MNG_IF_SEL_MDIO_ACT (1u << 1)
4382#define IXGBE_NW_MNG_IF_SEL_MDIO_IF_MODE (1u << 2)
4383#define IXGBE_NW_MNG_IF_SEL_EN_SHARED_MDIO (1u << 13)
4384#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M (1u << 17)
4385#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M (1u << 18)
4386#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G (1u << 19)
4387#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G (1u << 20)
4388#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G (1u << 21)
4389#define IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE (1u << 25)
4390#define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24) /* X552 reg field only */
4391#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3
4392#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \
4393 (0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)
4015
4016#endif /* _IXGBE_TYPE_H_ */
4394
4395#endif /* _IXGBE_TYPE_H_ */