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ixgbe_type.h (238149) ixgbe_type.h (247822)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
3 Copyright (c) 2001-2013, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 238149 2012-07-05 20:51:44Z jfv $*/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 247822 2013-03-04 23:07:40Z jfv $*/
34
35#ifndef _IXGBE_TYPE_H_
36#define _IXGBE_TYPE_H_
37
38#include "ixgbe_osdep.h"
39
40
34
35#ifndef _IXGBE_TYPE_H_
36#define _IXGBE_TYPE_H_
37
38#include "ixgbe_osdep.h"
39
40
41/* Vendor ID */
42#define IXGBE_INTEL_VENDOR_ID 0x8086
43
44/* Device IDs */
45#define IXGBE_DEV_ID_82598 0x10B6
46#define IXGBE_DEV_ID_82598_BX 0x1508
47#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
48#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
49#define IXGBE_DEV_ID_82598AT 0x10C8
50#define IXGBE_DEV_ID_82598AT2 0x150B
51#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB

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57#define IXGBE_DEV_ID_82599_KX4 0x10F7
58#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
59#define IXGBE_DEV_ID_82599_KR 0x1517
60#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
61#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
62#define IXGBE_DEV_ID_82599_CX4 0x10F9
63#define IXGBE_DEV_ID_82599_SFP 0x10FB
64#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
41/* Device IDs */
42#define IXGBE_DEV_ID_82598 0x10B6
43#define IXGBE_DEV_ID_82598_BX 0x1508
44#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
45#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
46#define IXGBE_DEV_ID_82598AT 0x10C8
47#define IXGBE_DEV_ID_82598AT2 0x150B
48#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB

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54#define IXGBE_DEV_ID_82599_KX4 0x10F7
55#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
56#define IXGBE_DEV_ID_82599_KR 0x1517
57#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
58#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
59#define IXGBE_DEV_ID_82599_CX4 0x10F9
60#define IXGBE_DEV_ID_82599_SFP 0x10FB
61#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
62#define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72
65#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
63#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
64#define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470
66#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
67#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
68#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
69#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
65#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
66#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
67#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
68#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
69#define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A
70#define IXGBE_DEV_ID_82599EN_SFP 0x1557
71#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
72#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
73#define IXGBE_DEV_ID_82599_VF 0x10ED
70#define IXGBE_DEV_ID_82599EN_SFP 0x1557
71#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
72#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
73#define IXGBE_DEV_ID_82599_VF 0x10ED
74#define IXGBE_DEV_ID_X540_VF 0x1515
74#define IXGBE_DEV_ID_82599_VF_HV 0x152E
75#define IXGBE_DEV_ID_82599_BYPASS 0x155D
75#define IXGBE_DEV_ID_X540T 0x1528
76#define IXGBE_DEV_ID_X540T 0x1528
76#define IXGBE_DEV_ID_X540T1 0x1560
77#define IXGBE_DEV_ID_X540_VF 0x1515
78#define IXGBE_DEV_ID_X540_VF_HV 0x1530
79#define IXGBE_DEV_ID_X540_BYPASS 0x155C
77
78/* General Registers */
79#define IXGBE_CTRL 0x00000
80#define IXGBE_STATUS 0x00008
81#define IXGBE_CTRL_EXT 0x00018
82#define IXGBE_ESDP 0x00020
83#define IXGBE_EODSDP 0x00028
84#define IXGBE_I2CCTL 0x00028

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275#define IXGBE_LLITHRESH 0x0EC90
276#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
277#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
278#define IXGBE_IMIRVP 0x05AC0
279#define IXGBE_VMD_CTL 0x0581C
280#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
281#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
282
80
81/* General Registers */
82#define IXGBE_CTRL 0x00000
83#define IXGBE_STATUS 0x00008
84#define IXGBE_CTRL_EXT 0x00018
85#define IXGBE_ESDP 0x00020
86#define IXGBE_EODSDP 0x00028
87#define IXGBE_I2CCTL 0x00028

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278#define IXGBE_LLITHRESH 0x0EC90
279#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
280#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
281#define IXGBE_IMIRVP 0x05AC0
282#define IXGBE_VMD_CTL 0x0581C
283#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
284#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
285
286
283/* Flow Director registers */
284#define IXGBE_FDIRCTRL 0x0EE00
285#define IXGBE_FDIRHKEY 0x0EE68
286#define IXGBE_FDIRSKEY 0x0EE6C
287#define IXGBE_FDIRDIP4M 0x0EE3C
288#define IXGBE_FDIRSIP4M 0x0EE40
289#define IXGBE_FDIRTCPM 0x0EE44
290#define IXGBE_FDIRUDPM 0x0EE48

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355#define IXGBE_WUFC 0x05808
356#define IXGBE_WUS 0x05810
357#define IXGBE_IPAV 0x05838
358#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
359#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
360
361#define IXGBE_WUPL 0x05900
362#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
287/* Flow Director registers */
288#define IXGBE_FDIRCTRL 0x0EE00
289#define IXGBE_FDIRHKEY 0x0EE68
290#define IXGBE_FDIRSKEY 0x0EE6C
291#define IXGBE_FDIRDIP4M 0x0EE3C
292#define IXGBE_FDIRSIP4M 0x0EE40
293#define IXGBE_FDIRTCPM 0x0EE44
294#define IXGBE_FDIRUDPM 0x0EE48

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359#define IXGBE_WUFC 0x05808
360#define IXGBE_WUS 0x05810
361#define IXGBE_IPAV 0x05838
362#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
363#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
364
365#define IXGBE_WUPL 0x05900
366#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
367
363#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
364/* Ext Flexible Host Filter Table */
365#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100))
366
368#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
369/* Ext Flexible Host Filter Table */
370#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100))
371
372/* Four Flexible Filters are supported */
367#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
373#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
374
375/* Six Flexible Filters are supported */
376#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6 6
368#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
369
370/* Each Flexible Filter is at most 128 (0x80) bytes in length */
371#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
372#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
373#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
374
375/* Definitions for power management and wakeup registers */

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391
392#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
393#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
394#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
395#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
396#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
397#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
398#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
377#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
378
379/* Each Flexible Filter is at most 128 (0x80) bytes in length */
380#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
381#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
382#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
383
384/* Definitions for power management and wakeup registers */

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400
401#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
402#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
403#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
404#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
405#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
406#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
407#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
399#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
408#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
400/* Mask for Ext. flex filters */
401#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000
409/* Mask for Ext. flex filters */
410#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000
402#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */
411#define IXGBE_WUFC_ALL_FILTERS 0x000F00FF /* Mask all 4 flex filters */
412#define IXGBE_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask all 6 flex filters */
403#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
404
405/* Wake Up Status */
406#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
407#define IXGBE_WUS_MAG IXGBE_WUFC_MAG
408#define IXGBE_WUS_EX IXGBE_WUFC_EX
409#define IXGBE_WUS_MC IXGBE_WUFC_MC
410#define IXGBE_WUS_BC IXGBE_WUFC_BC

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415#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
416#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
417#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
418#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
419#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
420#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
421#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
422
413#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
414
415/* Wake Up Status */
416#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
417#define IXGBE_WUS_MAG IXGBE_WUFC_MAG
418#define IXGBE_WUS_EX IXGBE_WUFC_EX
419#define IXGBE_WUS_MC IXGBE_WUFC_MC
420#define IXGBE_WUS_BC IXGBE_WUFC_BC

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425#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
426#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
427#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
428#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
429#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
430#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
431#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
432
423/* Wake Up Packet Length */
424#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
425
426/* DCB registers */
427#define IXGBE_DCB_MAX_TRAFFIC_CLASS 8
428#define IXGBE_RMCS 0x03D00
429#define IXGBE_DPMCS 0x07F40
430#define IXGBE_PDPMCS 0x0CD00
431#define IXGBE_RUPPBMR 0x050A0

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569#define IXGBE_RTTBCNACL 0x08B08
570#define IXGBE_RTTBCNTG 0x04A90
571#define IXGBE_RTTBCNIDX 0x08B0C
572#define IXGBE_RTTBCNCP 0x08B10
573#define IXGBE_RTFRTIMER 0x08B14
574#define IXGBE_RTTBCNRTT 0x05150
575#define IXGBE_RTTBCNRD 0x0498C
576
433#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
434
435/* DCB registers */
436#define IXGBE_DCB_MAX_TRAFFIC_CLASS 8
437#define IXGBE_RMCS 0x03D00
438#define IXGBE_DPMCS 0x07F40
439#define IXGBE_PDPMCS 0x0CD00
440#define IXGBE_RUPPBMR 0x050A0

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578#define IXGBE_RTTBCNACL 0x08B08
579#define IXGBE_RTTBCNTG 0x04A90
580#define IXGBE_RTTBCNIDX 0x08B0C
581#define IXGBE_RTTBCNCP 0x08B10
582#define IXGBE_RTFRTIMER 0x08B14
583#define IXGBE_RTTBCNRTT 0x05150
584#define IXGBE_RTTBCNRD 0x0498C
585
586
577/* FCoE DMA Context Registers */
578#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
579#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
580#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
581#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
582#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0*/
583#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
584#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */

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749#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
750#define IXGBE_LSWFW 0x15014
751#define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */
752#define IXGBE_BMCIPVAL 0x05060
753#define IXGBE_BMCIP_IPADDR_TYPE 0x00000001
754#define IXGBE_BMCIP_IPADDR_VALID 0x00000002
755
756/* Management Bit Fields and Masks */
587/* FCoE DMA Context Registers */
588#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
589#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
590#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
591#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
592#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0*/
593#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
594#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */

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759#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
760#define IXGBE_LSWFW 0x15014
761#define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */
762#define IXGBE_BMCIPVAL 0x05060
763#define IXGBE_BMCIP_IPADDR_TYPE 0x00000001
764#define IXGBE_BMCIP_IPADDR_VALID 0x00000002
765
766/* Management Bit Fields and Masks */
767#define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */
757#define IXGBE_MANC_EN_BMC2OS 0x10000000 /* Ena BMC2OS and OS2BMC traffic */
758#define IXGBE_MANC_EN_BMC2OS_SHIFT 28
759
760/* Firmware Semaphore Register */
761#define IXGBE_FWSM_MODE_MASK 0xE
768#define IXGBE_MANC_EN_BMC2OS 0x10000000 /* Ena BMC2OS and OS2BMC traffic */
769#define IXGBE_MANC_EN_BMC2OS_SHIFT 28
770
771/* Firmware Semaphore Register */
772#define IXGBE_FWSM_MODE_MASK 0xE
773#define IXGBE_FWSM_TS_ENABLED 0x1
774#define IXGBE_FWSM_FW_MODE_PT 0x4
762
763/* ARC Subsystem registers */
764#define IXGBE_HICR 0x15F00
765#define IXGBE_FWSTS 0x15F0C
766#define IXGBE_HSMC0R 0x15F04
767#define IXGBE_HSMC1R 0x15F08
768#define IXGBE_SWSR 0x15F10
769#define IXGBE_HFDR 0x15FE8

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1009#define IXGBE_BARCTRL_CSRSIZE 0x2000
1010
1011/* RSCCTL Bit Masks */
1012#define IXGBE_RSCCTL_RSCEN 0x01
1013#define IXGBE_RSCCTL_MAXDESC_1 0x00
1014#define IXGBE_RSCCTL_MAXDESC_4 0x04
1015#define IXGBE_RSCCTL_MAXDESC_8 0x08
1016#define IXGBE_RSCCTL_MAXDESC_16 0x0C
775
776/* ARC Subsystem registers */
777#define IXGBE_HICR 0x15F00
778#define IXGBE_FWSTS 0x15F0C
779#define IXGBE_HSMC0R 0x15F04
780#define IXGBE_HSMC1R 0x15F08
781#define IXGBE_SWSR 0x15F10
782#define IXGBE_HFDR 0x15FE8

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1022#define IXGBE_BARCTRL_CSRSIZE 0x2000
1023
1024/* RSCCTL Bit Masks */
1025#define IXGBE_RSCCTL_RSCEN 0x01
1026#define IXGBE_RSCCTL_MAXDESC_1 0x00
1027#define IXGBE_RSCCTL_MAXDESC_4 0x04
1028#define IXGBE_RSCCTL_MAXDESC_8 0x08
1029#define IXGBE_RSCCTL_MAXDESC_16 0x0C
1030#define IXGBE_RSCCTL_TS_DIS 0x02
1017
1018/* RSCDBU Bit Masks */
1019#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F
1020#define IXGBE_RSCDBU_RSCACKDIS 0x00000080
1021
1022/* RDRXCTL Bit Masks */
1023#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min THLD Size */
1024#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
1025#define IXGBE_RDRXCTL_MVMEN 0x00000020
1026#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
1027#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
1028#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */
1031
1032/* RSCDBU Bit Masks */
1033#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F
1034#define IXGBE_RSCDBU_RSCACKDIS 0x00000080
1035
1036/* RDRXCTL Bit Masks */
1037#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min THLD Size */
1038#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
1039#define IXGBE_RDRXCTL_MVMEN 0x00000020
1040#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
1041#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
1042#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */
1029#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disabl RSC compl on LLI */
1043#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI*/
1030#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC ena */
1031#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC ena */
1032
1033/* RQTC Bit Masks and Shifts */
1034#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
1035#define IXGBE_RQTC_TC0_MASK (0x7 << 0)
1036#define IXGBE_RQTC_TC1_MASK (0x7 << 4)
1037#define IXGBE_RQTC_TC2_MASK (0x7 << 8)

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1047
1048/* CTRL Bit Masks */
1049#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
1050#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
1051#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
1052#define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1053
1054/* FACTPS */
1044#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC ena */
1045#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC ena */
1046
1047/* RQTC Bit Masks and Shifts */
1048#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
1049#define IXGBE_RQTC_TC0_MASK (0x7 << 0)
1050#define IXGBE_RQTC_TC1_MASK (0x7 << 4)
1051#define IXGBE_RQTC_TC2_MASK (0x7 << 8)

--- 9 unchanged lines hidden (view full) ---

1061
1062/* CTRL Bit Masks */
1063#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
1064#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
1065#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
1066#define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1067
1068/* FACTPS */
1069#define IXGBE_FACTPS_MNGCG 0x20000000 /* Manageblility Clock Gated */
1055#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
1056
1057/* MHADD Bit Masks */
1058#define IXGBE_MHADD_MFS_MASK 0xFFFF0000
1059#define IXGBE_MHADD_MFS_SHIFT 16
1060
1061/* Extended Device Control */
1062#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */

--- 522 unchanged lines hidden (view full) ---

1585#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
1586#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
1587#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1588#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1589#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
1590#define IXGBE_ESDP_SDP7 0x00000080 /* SDP7 Data Value */
1591#define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */
1592#define IXGBE_ESDP_SDP1_DIR 0x00000200 /* SDP1 IO direction */
1070#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
1071
1072/* MHADD Bit Masks */
1073#define IXGBE_MHADD_MFS_MASK 0xFFFF0000
1074#define IXGBE_MHADD_MFS_SHIFT 16
1075
1076/* Extended Device Control */
1077#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */

--- 522 unchanged lines hidden (view full) ---

1600#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
1601#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
1602#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1603#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1604#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
1605#define IXGBE_ESDP_SDP7 0x00000080 /* SDP7 Data Value */
1606#define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */
1607#define IXGBE_ESDP_SDP1_DIR 0x00000200 /* SDP1 IO direction */
1608#define IXGBE_ESDP_SDP2_DIR 0x00000400 /* SDP1 IO direction */
1593#define IXGBE_ESDP_SDP3_DIR 0x00000800 /* SDP3 IO direction */
1594#define IXGBE_ESDP_SDP4_DIR 0x00001000 /* SDP4 IO direction */
1595#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
1596#define IXGBE_ESDP_SDP6_DIR 0x00004000 /* SDP6 IO direction */
1597#define IXGBE_ESDP_SDP7_DIR 0x00008000 /* SDP7 IO direction */
1598#define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 IO mode */
1599#define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */
1600

--- 62 unchanged lines hidden (view full) ---

1663#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1664
1665#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1666#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
1667#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1668#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1669#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1670#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1609#define IXGBE_ESDP_SDP3_DIR 0x00000800 /* SDP3 IO direction */
1610#define IXGBE_ESDP_SDP4_DIR 0x00001000 /* SDP4 IO direction */
1611#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
1612#define IXGBE_ESDP_SDP6_DIR 0x00004000 /* SDP6 IO direction */
1613#define IXGBE_ESDP_SDP7_DIR 0x00008000 /* SDP7 IO direction */
1614#define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 IO mode */
1615#define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */
1616

--- 62 unchanged lines hidden (view full) ---

1679#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1680
1681#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1682#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
1683#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1684#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1685#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1686#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1687#define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000
1671
1672#define IXGBE_MACC_FLU 0x00000001
1673#define IXGBE_MACC_FSV_10G 0x00030000
1674#define IXGBE_MACC_FS 0x00040000
1675#define IXGBE_MAC_RX2TX_LPBK 0x00000002
1676
1677/* LINKS Bit Masks */
1678#define IXGBE_LINKS_KX_AN_COMP 0x80000000

--- 154 unchanged lines hidden (view full) ---

1833#define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */
1834#define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1835#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for wr complete */
1836#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for rd complete */
1837
1838#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
1839
1840#define IXGBE_EEPROM_PAGE_SIZE_MAX 128
1688
1689#define IXGBE_MACC_FLU 0x00000001
1690#define IXGBE_MACC_FSV_10G 0x00030000
1691#define IXGBE_MACC_FS 0x00040000
1692#define IXGBE_MAC_RX2TX_LPBK 0x00000002
1693
1694/* LINKS Bit Masks */
1695#define IXGBE_LINKS_KX_AN_COMP 0x80000000

--- 154 unchanged lines hidden (view full) ---

1850#define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */
1851#define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1852#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for wr complete */
1853#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for rd complete */
1854
1855#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
1856
1857#define IXGBE_EEPROM_PAGE_SIZE_MAX 128
1841#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* words rd in burst */
1858#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 256 /* words rd in burst */
1842#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* words wr in burst */
1843
1844#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
1845#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM attempts to gain grant */
1846#endif
1847
1848/* Number of 5 microseconds we wait for EERD read and
1849 * EERW write to complete */

--- 669 unchanged lines hidden (view full) ---

2519#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
2520#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
2521#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
2522 IXGBE_LINK_SPEED_10GB_FULL)
2523#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
2524 IXGBE_LINK_SPEED_1GB_FULL | \
2525 IXGBE_LINK_SPEED_10GB_FULL)
2526
1859#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* words wr in burst */
1860
1861#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
1862#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM attempts to gain grant */
1863#endif
1864
1865/* Number of 5 microseconds we wait for EERD read and
1866 * EERW write to complete */

--- 669 unchanged lines hidden (view full) ---

2536#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
2537#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
2538#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
2539 IXGBE_LINK_SPEED_10GB_FULL)
2540#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
2541 IXGBE_LINK_SPEED_1GB_FULL | \
2542 IXGBE_LINK_SPEED_10GB_FULL)
2543
2527
2528/* Physical layer type */
2529typedef u32 ixgbe_physical_layer;
2530#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
2531#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
2532#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
2533#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004
2534#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
2535#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010

--- 216 unchanged lines hidden (view full) ---

2752 ixgbe_sfp_type_1g_sx_core1 = 12,
2753 ixgbe_sfp_type_not_present = 0xFFFE,
2754 ixgbe_sfp_type_unknown = 0xFFFF
2755};
2756
2757enum ixgbe_media_type {
2758 ixgbe_media_type_unknown = 0,
2759 ixgbe_media_type_fiber,
2544/* Physical layer type */
2545typedef u32 ixgbe_physical_layer;
2546#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
2547#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
2548#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
2549#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004
2550#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
2551#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010

--- 216 unchanged lines hidden (view full) ---

2768 ixgbe_sfp_type_1g_sx_core1 = 12,
2769 ixgbe_sfp_type_not_present = 0xFFFE,
2770 ixgbe_sfp_type_unknown = 0xFFFF
2771};
2772
2773enum ixgbe_media_type {
2774 ixgbe_media_type_unknown = 0,
2775 ixgbe_media_type_fiber,
2776 ixgbe_media_type_fiber_fixed,
2760 ixgbe_media_type_copper,
2761 ixgbe_media_type_backplane,
2762 ixgbe_media_type_cx4,
2763 ixgbe_media_type_virtual
2764};
2765
2766/* Flow Control Settings */
2767enum ixgbe_fc_mode {

--- 202 unchanged lines hidden (view full) ---

2970 s32 (*enable_sec_rx_path)(struct ixgbe_hw *);
2971 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
2972 void (*release_swfw_sync)(struct ixgbe_hw *, u16);
2973
2974 /* Link */
2975 void (*disable_tx_laser)(struct ixgbe_hw *);
2976 void (*enable_tx_laser)(struct ixgbe_hw *);
2977 void (*flap_tx_laser)(struct ixgbe_hw *);
2777 ixgbe_media_type_copper,
2778 ixgbe_media_type_backplane,
2779 ixgbe_media_type_cx4,
2780 ixgbe_media_type_virtual
2781};
2782
2783/* Flow Control Settings */
2784enum ixgbe_fc_mode {

--- 202 unchanged lines hidden (view full) ---

2987 s32 (*enable_sec_rx_path)(struct ixgbe_hw *);
2988 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
2989 void (*release_swfw_sync)(struct ixgbe_hw *, u16);
2990
2991 /* Link */
2992 void (*disable_tx_laser)(struct ixgbe_hw *);
2993 void (*enable_tx_laser)(struct ixgbe_hw *);
2994 void (*flap_tx_laser)(struct ixgbe_hw *);
2978 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
2995 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
2979 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
2980 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
2981 bool *);
2982
2983 /* Packet Buffer manipulation */
2984 void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int);
2985
2986 /* LED */

--- 34 unchanged lines hidden (view full) ---

3021struct ixgbe_phy_operations {
3022 s32 (*identify)(struct ixgbe_hw *);
3023 s32 (*identify_sfp)(struct ixgbe_hw *);
3024 s32 (*init)(struct ixgbe_hw *);
3025 s32 (*reset)(struct ixgbe_hw *);
3026 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
3027 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
3028 s32 (*setup_link)(struct ixgbe_hw *);
2996 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
2997 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
2998 bool *);
2999
3000 /* Packet Buffer manipulation */
3001 void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int);
3002
3003 /* LED */

--- 34 unchanged lines hidden (view full) ---

3038struct ixgbe_phy_operations {
3039 s32 (*identify)(struct ixgbe_hw *);
3040 s32 (*identify_sfp)(struct ixgbe_hw *);
3041 s32 (*init)(struct ixgbe_hw *);
3042 s32 (*reset)(struct ixgbe_hw *);
3043 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
3044 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
3045 s32 (*setup_link)(struct ixgbe_hw *);
3029 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
3030 bool);
3046 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3031 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
3032 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
3033 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
3034 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
3047 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
3048 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
3049 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
3050 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
3051 s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);
3035 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
3036 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
3037 void (*i2c_bus_clear)(struct ixgbe_hw *);
3038 s32 (*check_overtemp)(struct ixgbe_hw *);
3039};
3040
3041struct ixgbe_eeprom_info {
3042 struct ixgbe_eeprom_operations ops;

--- 21 unchanged lines hidden (view full) ---

3064 u32 mcft_size;
3065 u32 vft_size;
3066 u32 num_rar_entries;
3067 u32 rar_highwater;
3068 u32 rx_pb_size;
3069 u32 max_tx_queues;
3070 u32 max_rx_queues;
3071 u32 orig_autoc;
3052 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
3053 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
3054 void (*i2c_bus_clear)(struct ixgbe_hw *);
3055 s32 (*check_overtemp)(struct ixgbe_hw *);
3056};
3057
3058struct ixgbe_eeprom_info {
3059 struct ixgbe_eeprom_operations ops;

--- 21 unchanged lines hidden (view full) ---

3081 u32 mcft_size;
3082 u32 vft_size;
3083 u32 num_rar_entries;
3084 u32 rar_highwater;
3085 u32 rx_pb_size;
3086 u32 max_tx_queues;
3087 u32 max_rx_queues;
3088 u32 orig_autoc;
3089 u32 cached_autoc;
3072 u8 san_mac_rar_index;
3090 u8 san_mac_rar_index;
3091 bool get_link_status;
3073 u32 orig_autoc2;
3074 u16 max_msix_vectors;
3075 bool arc_subsystem_valid;
3076 bool orig_link_settings_stored;
3077 bool autotry_restart;
3078 u8 flags;
3079};
3080

--- 56 unchanged lines hidden (view full) ---

3137 struct ixgbe_bus_info bus;
3138 struct ixgbe_mbx_info mbx;
3139 u16 device_id;
3140 u16 vendor_id;
3141 u16 subsystem_device_id;
3142 u16 subsystem_vendor_id;
3143 u8 revision_id;
3144 bool adapter_stopped;
3092 u32 orig_autoc2;
3093 u16 max_msix_vectors;
3094 bool arc_subsystem_valid;
3095 bool orig_link_settings_stored;
3096 bool autotry_restart;
3097 u8 flags;
3098};
3099

--- 56 unchanged lines hidden (view full) ---

3156 struct ixgbe_bus_info bus;
3157 struct ixgbe_mbx_info mbx;
3158 u16 device_id;
3159 u16 vendor_id;
3160 u16 subsystem_device_id;
3161 u16 subsystem_vendor_id;
3162 u8 revision_id;
3163 bool adapter_stopped;
3164 int api_version;
3145 bool force_full_reset;
3146 bool allow_unsupported_sfp;
3147};
3148
3149#define ixgbe_call_func(hw, func, params, error) \
3150 (func != NULL) ? func params : error
3151
3152

--- 27 unchanged lines hidden (view full) ---

3180#define IXGBE_ERR_OVERTEMP -26
3181#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
3182#define IXGBE_ERR_FC_NOT_SUPPORTED -28
3183#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
3184#define IXGBE_ERR_PBA_SECTION -31
3185#define IXGBE_ERR_INVALID_ARGUMENT -32
3186#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
3187#define IXGBE_ERR_OUT_OF_MEM -34
3165 bool force_full_reset;
3166 bool allow_unsupported_sfp;
3167};
3168
3169#define ixgbe_call_func(hw, func, params, error) \
3170 (func != NULL) ? func params : error
3171
3172

--- 27 unchanged lines hidden (view full) ---

3200#define IXGBE_ERR_OVERTEMP -26
3201#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
3202#define IXGBE_ERR_FC_NOT_SUPPORTED -28
3203#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
3204#define IXGBE_ERR_PBA_SECTION -31
3205#define IXGBE_ERR_INVALID_ARGUMENT -32
3206#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
3207#define IXGBE_ERR_OUT_OF_MEM -34
3208#define IXGBE_ERR_FEATURE_NOT_SUPPORTED -36
3188
3189#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
3190
3191
3192#endif /* _IXGBE_TYPE_H_ */
3209
3210#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
3211
3212
3213#endif /* _IXGBE_TYPE_H_ */