Cross Reference: /freebsd-11-stable/sys/dev/ixgbe/ixgbe

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1/******************************************************************************
2

5
6 Redistribution and use in source and binary forms, with or without

7 modification, are permitted provided that the following conditions are met:

8
9 1. Redistributions of source code must retain the above copyright notice,

10 this list of conditions and the following disclaimer.

11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the

14 documentation and/or other materials provided with the distribution.

15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from

18 this software without specific prior written permission.

20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/

33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_type.h 299200 2016-05-06 22:54:56Z pfg $*/

33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_type.h 320897 2017-07-11 21:25:07Z erj $*/

34
35#ifndef _IXGBE_TYPE_H_
36#define _IXGBE_TYPE_H_
37
38/*
39 * The following is a brief description of the error categories used by the
40 * ERROR_REPORT* macros.
41 *
42 * - IXGBE_ERROR_INVALID_STATE
43 * This category is for errors which represent a serious failure state that is
44 * unexpected, and could be potentially harmful to device operation. It should
45 * not be used for errors relating to issues that can be worked around or
46 * ignored.
47 *
48 * - IXGBE_ERROR_POLLING
49 * This category is for errors related to polling/timeout issues and should be
50 * used in any case where the timeout occurred, or a failure to obtain a lock, or
51 * failure to receive data within the time limit.
52 *
53 * - IXGBE_ERROR_CAUTION
54 * This category should be used for reporting issues that may be the cause of
55 * other errors, such as temperature warnings. It should indicate an event which
56 * could be serious, but hasn't necessarily caused problems yet.
57 *
58 * - IXGBE_ERROR_SOFTWARE
59 * This category is intended for errors due to software state preventing
60 * something. The category is not intended for errors due to bad arguments, or
61 * due to unsupported features. It should be used when a state occurs which
62 * prevents action but is not a serious issue.
63 *
64 * - IXGBE_ERROR_ARGUMENT
65 * This category is for when a bad or invalid argument is passed. It should be
66 * used whenever a function is called and error checking has detected the
67 * argument is wrong or incorrect.
68 *
69 * - IXGBE_ERROR_UNSUPPORTED
70 * This category is for errors which are due to unsupported circumstances or
71 * configuration issues. It should not be used when the issue is due to an
72 * invalid argument, but for when something has occurred that is unsupported
73 * (Ex: Flow control autonegotiation or an unsupported SFP+ module.)
74 */
75
76#include "ixgbe_osdep.h"
77
78/* Override this by setting IOMEM in your ixgbe_osdep.h header */
79#define IOMEM
80
81/* Vendor ID */
82#define IXGBE_INTEL_VENDOR_ID 0x8086
83
84/* Device IDs */
85#define IXGBE_DEV_ID_82598 0x10B6
86#define IXGBE_DEV_ID_82598_BX 0x1508
87#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
88#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
89#define IXGBE_DEV_ID_82598AT 0x10C8
90#define IXGBE_DEV_ID_82598AT2 0x150B
91#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
92#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
93#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
94#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
95#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
96#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
97#define IXGBE_DEV_ID_82599_KX4 0x10F7
98#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
99#define IXGBE_DEV_ID_82599_KR 0x1517
100#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
101#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
102#define IXGBE_DEV_ID_82599_CX4 0x10F9
103#define IXGBE_DEV_ID_82599_SFP 0x10FB
104#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
105#define IXGBE_SUBDEV_ID_82599_SFP_WOL0 0x1071
106#define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72
107#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
108#define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470
109#define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B

~~110~~#define IXGBE_SUBDEV_ID_82599_LOM_SFP 0x8976

110#define IXGBE_SUBDEV_ID_82599_LOM_SNAP6 0x2159
111#define IXGBE_SUBDEV_ID_82599_SFP_1OCP 0x000D
112#define IXGBE_SUBDEV_ID_82599_SFP_2OCP 0x0008

~~114~~#define IXGBE_SUBDEV_ID_82599_SFP_LOM 0x06EE

113#define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1 0x8976
114#define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2 0x06EE

115#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
116#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
117#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
118#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
119#define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A
120#define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558
121#define IXGBE_DEV_ID_82599EN_SFP 0x1557
122#define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001
123#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
124#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
125#define IXGBE_DEV_ID_82599_VF 0x10ED
126#define IXGBE_DEV_ID_82599_VF_HV 0x152E
127#define IXGBE_DEV_ID_82599_BYPASS 0x155D
128#define IXGBE_DEV_ID_X540T 0x1528
129#define IXGBE_DEV_ID_X540_VF 0x1515
130#define IXGBE_DEV_ID_X540_VF_HV 0x1530
131#define IXGBE_DEV_ID_X540_BYPASS 0x155C
132#define IXGBE_DEV_ID_X540T1 0x1560
133#define IXGBE_DEV_ID_X550T 0x1563
134#define IXGBE_DEV_ID_X550T1 0x15D1

135#define IXGBE_DEV_ID_X550EM_A_KR 0x15C2
136#define IXGBE_DEV_ID_X550EM_A_KR_L 0x15C3
137#define IXGBE_DEV_ID_X550EM_A_SFP_N 0x15C4
138#define IXGBE_DEV_ID_X550EM_A_SGMII 0x15C6
139#define IXGBE_DEV_ID_X550EM_A_SGMII_L 0x15C7
140#define IXGBE_DEV_ID_X550EM_A_10G_T 0x15C8
141#define IXGBE_DEV_ID_X550EM_A_QSFP 0x15CA
142#define IXGBE_DEV_ID_X550EM_A_QSFP_N 0x15CC
143#define IXGBE_DEV_ID_X550EM_A_SFP 0x15CE
144#define IXGBE_DEV_ID_X550EM_A_1G_T 0x15E4
145#define IXGBE_DEV_ID_X550EM_A_1G_T_L 0x15E5

146#define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA
147#define IXGBE_DEV_ID_X550EM_X_KR 0x15AB
148#define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC
149#define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD
150#define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE

151#define IXGBE_DEV_ID_X550EM_X_XFI 0x15B0

152#define IXGBE_DEV_ID_X550_VF_HV 0x1564
153#define IXGBE_DEV_ID_X550_VF 0x1565

154#define IXGBE_DEV_ID_X550EM_A_VF 0x15C5
155#define IXGBE_DEV_ID_X550EM_A_VF_HV 0x15B4

156#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
157#define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9
158
159#define IXGBE_CAT(r,m) IXGBE_##r##m
160
161#define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)])
162
163/* General Registers */
164#define IXGBE_CTRL 0x00000
165#define IXGBE_STATUS 0x00008
166#define IXGBE_CTRL_EXT 0x00018
167#define IXGBE_ESDP 0x00020
168#define IXGBE_EODSDP 0x00028
169#define IXGBE_I2CCTL_82599 0x00028
170#define IXGBE_I2CCTL IXGBE_I2CCTL_82599
171#define IXGBE_I2CCTL_X540 IXGBE_I2CCTL_82599
172#define IXGBE_I2CCTL_X550 0x15F5C
173#define IXGBE_I2CCTL_X550EM_x IXGBE_I2CCTL_X550

174#define IXGBE_I2CCTL_X550EM_a IXGBE_I2CCTL_X550

175#define IXGBE_I2CCTL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2CCTL)
176#define IXGBE_PHY_GPIO 0x00028
177#define IXGBE_MAC_GPIO 0x00030
178#define IXGBE_PHYINT_STATUS0 0x00100
179#define IXGBE_PHYINT_STATUS1 0x00104
180#define IXGBE_PHYINT_STATUS2 0x00108
181#define IXGBE_LEDCTL 0x00200
182#define IXGBE_FRTIMER 0x00048
183#define IXGBE_TCPTIMER 0x0004C
184#define IXGBE_CORESPARE 0x00600
185#define IXGBE_EXVET 0x05078
186
187/* NVM Registers */
188#define IXGBE_EEC 0x10010
189#define IXGBE_EEC_X540 IXGBE_EEC
190#define IXGBE_EEC_X550 IXGBE_EEC
191#define IXGBE_EEC_X550EM_x IXGBE_EEC

~~177~~#define IXGBE_EEC_BY_MAC(_hw) IXGBE_EEC

192#define IXGBE_EEC_X550EM_a 0x15FF8
193#define IXGBE_EEC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EEC)

194
195#define IXGBE_EERD 0x10014
196#define IXGBE_EEWR 0x10018
197
198#define IXGBE_FLA 0x1001C
199#define IXGBE_FLA_X540 IXGBE_FLA
200#define IXGBE_FLA_X550 IXGBE_FLA
201#define IXGBE_FLA_X550EM_x IXGBE_FLA

~~186~~#define IXGBE_FLA_BY_MAC(_hw) IXGBE_FLA

202#define IXGBE_FLA_X550EM_a 0x15F68
203#define IXGBE_FLA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FLA)

204
205#define IXGBE_EEMNGCTL 0x10110
206#define IXGBE_EEMNGDATA 0x10114
207#define IXGBE_FLMNGCTL 0x10118
208#define IXGBE_FLMNGDATA 0x1011C
209#define IXGBE_FLMNGCNT 0x10120
210#define IXGBE_FLOP 0x1013C
211
212#define IXGBE_GRC 0x10200
213#define IXGBE_GRC_X540 IXGBE_GRC
214#define IXGBE_GRC_X550 IXGBE_GRC
215#define IXGBE_GRC_X550EM_x IXGBE_GRC

~~199~~#define IXGBE_GRC_BY_MAC(_hw) IXGBE_GRC

216#define IXGBE_GRC_X550EM_a 0x15F64
217#define IXGBE_GRC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), GRC)

218
219#define IXGBE_SRAMREL 0x10210
220#define IXGBE_SRAMREL_X540 IXGBE_SRAMREL
221#define IXGBE_SRAMREL_X550 IXGBE_SRAMREL
222#define IXGBE_SRAMREL_X550EM_x IXGBE_SRAMREL

~~205~~#define IXGBE_SRAMREL_BY_MAC(_hw) IXGBE_SRAMREL

223#define IXGBE_SRAMREL_X550EM_a 0x15F6C
224#define IXGBE_SRAMREL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SRAMREL)

225
226#define IXGBE_PHYDBG 0x10218
227
228/* General Receive Control */
229#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
230#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
231
232#define IXGBE_VPDDIAG0 0x10204
233#define IXGBE_VPDDIAG1 0x10208
234
235/* I2CCTL Bit Masks */
236#define IXGBE_I2C_CLK_IN 0x00000001
237#define IXGBE_I2C_CLK_IN_X540 IXGBE_I2C_CLK_IN
238#define IXGBE_I2C_CLK_IN_X550 0x00004000
239#define IXGBE_I2C_CLK_IN_X550EM_x IXGBE_I2C_CLK_IN_X550

240#define IXGBE_I2C_CLK_IN_X550EM_a IXGBE_I2C_CLK_IN_X550

241#define IXGBE_I2C_CLK_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_IN)
242
243#define IXGBE_I2C_CLK_OUT 0x00000002
244#define IXGBE_I2C_CLK_OUT_X540 IXGBE_I2C_CLK_OUT
245#define IXGBE_I2C_CLK_OUT_X550 0x00000200
246#define IXGBE_I2C_CLK_OUT_X550EM_x IXGBE_I2C_CLK_OUT_X550

247#define IXGBE_I2C_CLK_OUT_X550EM_a IXGBE_I2C_CLK_OUT_X550

248#define IXGBE_I2C_CLK_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OUT)
249
250#define IXGBE_I2C_DATA_IN 0x00000004
251#define IXGBE_I2C_DATA_IN_X540 IXGBE_I2C_DATA_IN
252#define IXGBE_I2C_DATA_IN_X550 0x00001000
253#define IXGBE_I2C_DATA_IN_X550EM_x IXGBE_I2C_DATA_IN_X550

254#define IXGBE_I2C_DATA_IN_X550EM_a IXGBE_I2C_DATA_IN_X550

255#define IXGBE_I2C_DATA_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_IN)
256
257#define IXGBE_I2C_DATA_OUT 0x00000008
258#define IXGBE_I2C_DATA_OUT_X540 IXGBE_I2C_DATA_OUT
259#define IXGBE_I2C_DATA_OUT_X550 0x00000400
260#define IXGBE_I2C_DATA_OUT_X550EM_x IXGBE_I2C_DATA_OUT_X550

261#define IXGBE_I2C_DATA_OUT_X550EM_a IXGBE_I2C_DATA_OUT_X550

262#define IXGBE_I2C_DATA_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OUT)
263
264#define IXGBE_I2C_DATA_OE_N_EN 0
265#define IXGBE_I2C_DATA_OE_N_EN_X540 IXGBE_I2C_DATA_OE_N_EN
266#define IXGBE_I2C_DATA_OE_N_EN_X550 0x00000800
267#define IXGBE_I2C_DATA_OE_N_EN_X550EM_x IXGBE_I2C_DATA_OE_N_EN_X550

268#define IXGBE_I2C_DATA_OE_N_EN_X550EM_a IXGBE_I2C_DATA_OE_N_EN_X550

269#define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN)
270
271#define IXGBE_I2C_BB_EN 0
272#define IXGBE_I2C_BB_EN_X540 IXGBE_I2C_BB_EN
273#define IXGBE_I2C_BB_EN_X550 0x00000100
274#define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550

275#define IXGBE_I2C_BB_EN_X550EM_a IXGBE_I2C_BB_EN_X550

276
277#define IXGBE_I2C_BB_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN)
278
279#define IXGBE_I2C_CLK_OE_N_EN 0
280#define IXGBE_I2C_CLK_OE_N_EN_X540 IXGBE_I2C_CLK_OE_N_EN
281#define IXGBE_I2C_CLK_OE_N_EN_X550 0x00002000
282#define IXGBE_I2C_CLK_OE_N_EN_X550EM_x IXGBE_I2C_CLK_OE_N_EN_X550

283#define IXGBE_I2C_CLK_OE_N_EN_X550EM_a IXGBE_I2C_CLK_OE_N_EN_X550

284#define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN)
285#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
286
287
288/* Interrupt Registers */
289#define IXGBE_EICR 0x00800
290#define IXGBE_EICS 0x00808
291#define IXGBE_EIMS 0x00880
292#define IXGBE_EIMC 0x00888
293#define IXGBE_EIAC 0x00810
294#define IXGBE_EIAM 0x00890
295#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
296#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
297#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
298#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
299/* 82599 EITR is only 12 bits, with the lower 3 always zero */
300/*
301 * 82598 EITR is 16 bits but set the limits based on the max
302 * supported by all ixgbe hardware
303 */
304#define IXGBE_MAX_INT_RATE 488281
305#define IXGBE_MIN_INT_RATE 956
306#define IXGBE_MAX_EITR 0x00000FF8
307#define IXGBE_MIN_EITR 8
308#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
309 (0x012300 + (((_i) - 24) * 4)))
310#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
311#define IXGBE_EITR_LLI_MOD 0x00008000
312#define IXGBE_EITR_CNT_WDIS 0x80000000
313#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
314#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
315#define IXGBE_EITRSEL 0x00894
316#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
317#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
318#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
319#define IXGBE_GPIE 0x00898
320
321/* Flow Control Registers */
322#define IXGBE_FCADBUL 0x03210
323#define IXGBE_FCADBUH 0x03214
324#define IXGBE_FCAMACL 0x04328
325#define IXGBE_FCAMACH 0x0432C
326#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
327#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
328#define IXGBE_PFCTOP 0x03008
329#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
330#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
331#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
332#define IXGBE_FCRTV 0x032A0
333#define IXGBE_FCCFG 0x03D00
334#define IXGBE_TFCS 0x0CE00
335
336/* Receive DMA Registers */
337#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
338 (0x0D000 + (((_i) - 64) * 0x40)))
339#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
340 (0x0D004 + (((_i) - 64) * 0x40)))
341#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
342 (0x0D008 + (((_i) - 64) * 0x40)))
343#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
344 (0x0D010 + (((_i) - 64) * 0x40)))
345#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
346 (0x0D018 + (((_i) - 64) * 0x40)))
347#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
348 (0x0D028 + (((_i) - 64) * 0x40)))
349#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
350 (0x0D02C + (((_i) - 64) * 0x40)))
351#define IXGBE_RSCDBU 0x03028
352#define IXGBE_RDDCC 0x02F20
353#define IXGBE_RXMEMWRAP 0x03190
354#define IXGBE_STARCTRL 0x03024
355/*
356 * Split and Replication Receive Control Registers
357 * 00-15 : 0x02100 + n*4
358 * 16-64 : 0x01014 + n*0x40
359 * 64-127: 0x0D014 + (n-64)*0x40
360 */
361#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
362 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
363 (0x0D014 + (((_i) - 64) * 0x40))))
364/*
365 * Rx DCA Control Register:
366 * 00-15 : 0x02200 + n*4
367 * 16-64 : 0x0100C + n*0x40
368 * 64-127: 0x0D00C + (n-64)*0x40
369 */
370#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
371 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
372 (0x0D00C + (((_i) - 64) * 0x40))))
373#define IXGBE_RDRXCTL 0x02F00
374/* 8 of these 0x03C00 - 0x03C1C */
375#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
376#define IXGBE_RXCTRL 0x03000
377#define IXGBE_DROPEN 0x03D04
378#define IXGBE_RXPBSIZE_SHIFT 10
379#define IXGBE_RXPBSIZE_MASK 0x000FFC00
380
381/* Receive Registers */
382#define IXGBE_RXCSUM 0x05000
383#define IXGBE_RFCTL 0x05008
384#define IXGBE_DRECCCTL 0x02F08
385#define IXGBE_DRECCCTL_DISABLE 0
386#define IXGBE_DRECCCTL2 0x02F8C
387
388/* Multicast Table Array - 128 entries */
389#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
390#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
391 (0x0A200 + ((_i) * 8)))
392#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
393 (0x0A204 + ((_i) * 8)))
394#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
395#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
396/* Packet split receive type */
397#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
398 (0x0EA00 + ((_i) * 4)))
399/* array of 4096 1-bit vlan filters */
400#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
401/*array of 4096 4-bit vlan vmdq indices */
402#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
403#define IXGBE_FCTRL 0x05080
404#define IXGBE_VLNCTRL 0x05088
405#define IXGBE_MCSTCTRL 0x05090
406#define IXGBE_MRQC 0x05818
407#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
408#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
409#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
410#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
411#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */
412#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
413#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */
414#define IXGBE_RQTC 0x0EC70
415#define IXGBE_MTQC 0x08120
416#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
417#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
418#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */
419#define IXGBE_PFFLPL 0x050B0
420#define IXGBE_PFFLPH 0x050B4
421#define IXGBE_VT_CTL 0x051B0
422#define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */
423/* 64 Mailboxes, 16 DW each */
424#define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i)))
425#define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */
426#define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */
427#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
428#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
429#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
430#define IXGBE_QDE 0x2F04
431#define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */
432#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
433#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
434#define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4))
435#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
436#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
437#define IXGBE_LVMMC_RX 0x2FA8
438#define IXGBE_LVMMC_TX 0x8108
439#define IXGBE_LMVM_RX 0x2FA4
440#define IXGBE_LMVM_TX 0x8124
441#define IXGBE_WQBR_RX(_i) (0x2FB0 + ((_i) * 4)) /* 4 total */
442#define IXGBE_WQBR_TX(_i) (0x8130 + ((_i) * 4)) /* 4 total */
443#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
444#define IXGBE_RXFECCERR0 0x051B8
445#define IXGBE_LLITHRESH 0x0EC90
446#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
447#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
448#define IXGBE_IMIRVP 0x05AC0
449#define IXGBE_VMD_CTL 0x0581C
450#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
451#define IXGBE_ERETA(_i) (0x0EE80 + ((_i) * 4)) /* 96 of these (0-95) */
452#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
453
454/* Registers for setting up RSS on X550 with SRIOV
455 * _p - pool number (0..63)
456 * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA)
457 */
458#define IXGBE_PFVFMRQC(_p) (0x03400 + ((_p) * 4))
459#define IXGBE_PFVFRSSRK(_i, _p) (0x018000 + ((_i) * 4) + ((_p) * 0x40))
460#define IXGBE_PFVFRETA(_i, _p) (0x019000 + ((_i) * 4) + ((_p) * 0x40))
461
462/* Flow Director registers */
463#define IXGBE_FDIRCTRL 0x0EE00
464#define IXGBE_FDIRHKEY 0x0EE68
465#define IXGBE_FDIRSKEY 0x0EE6C
466#define IXGBE_FDIRDIP4M 0x0EE3C
467#define IXGBE_FDIRSIP4M 0x0EE40
468#define IXGBE_FDIRTCPM 0x0EE44
469#define IXGBE_FDIRUDPM 0x0EE48
470#define IXGBE_FDIRSCTPM 0x0EE78
471#define IXGBE_FDIRIP6M 0x0EE74
472#define IXGBE_FDIRM 0x0EE70
473
474/* Flow Director Stats registers */
475#define IXGBE_FDIRFREE 0x0EE38
476#define IXGBE_FDIRLEN 0x0EE4C
477#define IXGBE_FDIRUSTAT 0x0EE50
478#define IXGBE_FDIRFSTAT 0x0EE54
479#define IXGBE_FDIRMATCH 0x0EE58
480#define IXGBE_FDIRMISS 0x0EE5C
481
482/* Flow Director Programming registers */
483#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
484#define IXGBE_FDIRIPSA 0x0EE18
485#define IXGBE_FDIRIPDA 0x0EE1C
486#define IXGBE_FDIRPORT 0x0EE20
487#define IXGBE_FDIRVLAN 0x0EE24
488#define IXGBE_FDIRHASH 0x0EE28
489#define IXGBE_FDIRCMD 0x0EE2C
490
491/* Transmit DMA registers */
492#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of them (0-31)*/
493#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
494#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
495#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
496#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
497#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
498#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
499#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
500#define IXGBE_DTXCTL 0x07E00
501
502#define IXGBE_DMATXCTL 0x04A80
503#define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
504#define IXGBE_PFDTXGSWC 0x08220
505#define IXGBE_DTXMXSZRQ 0x08100
506#define IXGBE_DTXTCPFLGL 0x04A88
507#define IXGBE_DTXTCPFLGH 0x04A8C
508#define IXGBE_LBDRPEN 0x0CA00
509#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
510
511#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
512#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
513#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
514#define IXGBE_DMATXCTL_MDP_EN 0x20 /* Bit 5 */
515#define IXGBE_DMATXCTL_MBINTEN 0x40 /* Bit 6 */
516#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
517
518#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
519
520/* Anti-spoofing defines */
521#define IXGBE_SPOOF_MACAS_MASK 0xFF
522#define IXGBE_SPOOF_VLANAS_MASK 0xFF00
523#define IXGBE_SPOOF_VLANAS_SHIFT 8
524#define IXGBE_SPOOF_ETHERTYPEAS 0xFF000000
525#define IXGBE_SPOOF_ETHERTYPEAS_SHIFT 16
526#define IXGBE_PFVFSPOOF_REG_COUNT 8
527/* 16 of these (0-15) */
528#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4))
529/* Tx DCA Control register : 128 of these (0-127) */
530#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
531#define IXGBE_TIPG 0x0CB00
532#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
533#define IXGBE_MNGTXMAP 0x0CD10
534#define IXGBE_TIPG_FIBER_DEFAULT 3
535#define IXGBE_TXPBSIZE_SHIFT 10
536
537/* Wake up registers */
538#define IXGBE_WUC 0x05800
539#define IXGBE_WUFC 0x05808
540#define IXGBE_WUS 0x05810
541#define IXGBE_IPAV 0x05838
542#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
543#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
544
545#define IXGBE_WUPL 0x05900
546#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
547#define IXGBE_PROXYS 0x05F60 /* Proxying Status Register */
548#define IXGBE_PROXYFC 0x05F64 /* Proxying Filter Control Register */
549#define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */
550

551/* masks for accessing VXLAN and GENEVE UDP ports */
552#define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK 0x0000ffff /* VXLAN port */
553#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK 0xffff0000 /* GENEVE port */
554#define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK 0xffffffff /* GENEVE/VXLAN */
555
556#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT 16
557

558#define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */
559/* Ext Flexible Host Filter Table */
560#define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100))
561#define IXGBE_FHFT_EXT_X550(_n) (0x09600 + ((_n) * 0x100))
562
563/* Four Flexible Filters are supported */
564#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
565
566/* Six Flexible Filters are supported */
567#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6 6
568/* Eight Flexible Filters are supported */
569#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_8 8
570#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
571
572/* Each Flexible Filter is at most 128 (0x80) bytes in length */
573#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
574#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
575#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
576
577/* Definitions for power management and wakeup registers */
578/* Wake Up Control */
579#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
580#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
581#define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */
582
583/* Wake Up Filter Control */
584#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
585#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
586#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
587#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
588#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
589#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
590#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
591#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
592#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
593
594#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
595#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
596#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
597#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
598#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
599#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
600#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
601#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
602#define IXGBE_WUFC_FLX_FILTERS_6 0x003F0000 /* Mask for 6 flex filters */
603#define IXGBE_WUFC_FLX_FILTERS_8 0x00FF0000 /* Mask for 8 flex filters */
604#define IXGBE_WUFC_FW_RST_WK 0x80000000 /* Ena wake on FW reset assertion */
605/* Mask for Ext. flex filters */
606#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000
607#define IXGBE_WUFC_ALL_FILTERS 0x000F00FF /* Mask all 4 flex filters */
608#define IXGBE_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask all 6 flex filters */
609#define IXGBE_WUFC_ALL_FILTERS_8 0x00FF00FF /* Mask all 8 flex filters */
610#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
611
612/* Wake Up Status */
613#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
614#define IXGBE_WUS_MAG IXGBE_WUFC_MAG
615#define IXGBE_WUS_EX IXGBE_WUFC_EX
616#define IXGBE_WUS_MC IXGBE_WUFC_MC
617#define IXGBE_WUS_BC IXGBE_WUFC_BC
618#define IXGBE_WUS_ARP IXGBE_WUFC_ARP
619#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
620#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
621#define IXGBE_WUS_MNG IXGBE_WUFC_MNG
622#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
623#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
624#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
625#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
626#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
627#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
628#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
629#define IXGBE_WUS_FW_RST_WK IXGBE_WUFC_FW_RST_WK
630/* Proxy Status */
631#define IXGBE_PROXYS_EX 0x00000004 /* Exact packet received */
632#define IXGBE_PROXYS_ARP_DIR 0x00000020 /* ARP w/filter match received */
633#define IXGBE_PROXYS_NS 0x00000200 /* IPV6 NS received */
634#define IXGBE_PROXYS_NS_DIR 0x00000400 /* IPV6 NS w/DA match received */
635#define IXGBE_PROXYS_ARP 0x00000800 /* ARP request packet received */
636#define IXGBE_PROXYS_MLD 0x00001000 /* IPv6 MLD packet received */
637
638/* Proxying Filter Control */
639#define IXGBE_PROXYFC_ENABLE 0x00000001 /* Port Proxying Enable */
640#define IXGBE_PROXYFC_EX 0x00000004 /* Directed Exact Proxy Enable */
641#define IXGBE_PROXYFC_ARP_DIR 0x00000020 /* Directed ARP Proxy Enable */
642#define IXGBE_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */
643#define IXGBE_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Enable */
644#define IXGBE_PROXYFC_MLD 0x00000800 /* IPv6 MLD Proxy Enable */
645#define IXGBE_PROXYFC_NO_TCO 0x00008000 /* Ignore TCO packets */
646
647#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
648
649/* DCB registers */
650#define IXGBE_DCB_MAX_TRAFFIC_CLASS 8
651#define IXGBE_RMCS 0x03D00
652#define IXGBE_DPMCS 0x07F40
653#define IXGBE_PDPMCS 0x0CD00
654#define IXGBE_RUPPBMR 0x050A0
655#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
656#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
657#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
658#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
659#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
660#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
661
662/* Power Management */
663/* DMA Coalescing configuration */
664struct ixgbe_dmac_config {
665 u16 watchdog_timer; /* usec units */
666 bool fcoe_en;
667 u32 link_speed;
668 u8 fcoe_tc;
669 u8 num_tcs;
670};
671
672/*
673 * DMA Coalescing threshold Rx PB TC[n] value in Kilobyte by link speed.
674 * DMACRXT = 10Gbps = 10,000 bits / usec = 1250 bytes / usec 70 * 1250 ==
675 * 87500 bytes [85KB]
676 */
677#define IXGBE_DMACRXT_10G 0x55
678#define IXGBE_DMACRXT_1G 0x09
679#define IXGBE_DMACRXT_100M 0x01
680
681/* DMA Coalescing registers */
682#define IXGBE_DMCMNGTH 0x15F20 /* Management Threshold */
683#define IXGBE_DMACR 0x02400 /* Control register */
684#define IXGBE_DMCTH(_i) (0x03300 + ((_i) * 4)) /* 8 of these */
685#define IXGBE_DMCTLX 0x02404 /* Time to Lx request */
686/* DMA Coalescing register fields */
687#define IXGBE_DMCMNGTH_DMCMNGTH_MASK 0x000FFFF0 /* Mng Threshold mask */
688#define IXGBE_DMCMNGTH_DMCMNGTH_SHIFT 4 /* Management Threshold shift */
689#define IXGBE_DMACR_DMACWT_MASK 0x0000FFFF /* Watchdog Timer mask */
690#define IXGBE_DMACR_HIGH_PRI_TC_MASK 0x00FF0000
691#define IXGBE_DMACR_HIGH_PRI_TC_SHIFT 16
692#define IXGBE_DMACR_EN_MNG_IND 0x10000000 /* Enable Mng Indications */
693#define IXGBE_DMACR_LX_COAL_IND 0x40000000 /* Lx Coalescing indicate */
694#define IXGBE_DMACR_DMAC_EN 0x80000000 /* DMA Coalescing Enable */
695#define IXGBE_DMCTH_DMACRXT_MASK 0x000001FF /* Receive Threshold mask */
696#define IXGBE_DMCTLX_TTLX_MASK 0x00000FFF /* Time to Lx request mask */
697
698/* EEE registers */
699#define IXGBE_EEER 0x043A0 /* EEE register */
700#define IXGBE_EEE_STAT 0x04398 /* EEE Status */
701#define IXGBE_EEE_SU 0x04380 /* EEE Set up */
702#define IXGBE_EEE_SU_TEEE_DLY_SHIFT 26
703#define IXGBE_TLPIC 0x041F4 /* EEE Tx LPI count */
704#define IXGBE_RLPIC 0x041F8 /* EEE Rx LPI count */
705
706/* EEE register fields */
707#define IXGBE_EEER_TX_LPI_EN 0x00010000 /* Enable EEE LPI TX path */
708#define IXGBE_EEER_RX_LPI_EN 0x00020000 /* Enable EEE LPI RX path */
709#define IXGBE_EEE_STAT_NEG 0x20000000 /* EEE support neg on link */
710#define IXGBE_EEE_RX_LPI_STATUS 0x40000000 /* RX Link in LPI status */
711#define IXGBE_EEE_TX_LPI_STATUS 0x80000000 /* TX Link in LPI status */
712
713
714
715/* Security Control Registers */
716#define IXGBE_SECTXCTRL 0x08800
717#define IXGBE_SECTXSTAT 0x08804
718#define IXGBE_SECTXBUFFAF 0x08808
719#define IXGBE_SECTXMINIFG 0x08810
720#define IXGBE_SECRXCTRL 0x08D00
721#define IXGBE_SECRXSTAT 0x08D04
722
723/* Security Bit Fields and Masks */
724#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
725#define IXGBE_SECTXCTRL_TX_DIS 0x00000002
726#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
727
728#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
729#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
730
731#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
732#define IXGBE_SECRXCTRL_RX_DIS 0x00000002
733
734#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
735#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
736
737/* LinkSec (MacSec) Registers */
738#define IXGBE_LSECTXCAP 0x08A00
739#define IXGBE_LSECRXCAP 0x08F00
740#define IXGBE_LSECTXCTRL 0x08A04
741#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
742#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
743#define IXGBE_LSECTXSA 0x08A10
744#define IXGBE_LSECTXPN0 0x08A14
745#define IXGBE_LSECTXPN1 0x08A18
746#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
747#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
748#define IXGBE_LSECRXCTRL 0x08F04
749#define IXGBE_LSECRXSCL 0x08F08
750#define IXGBE_LSECRXSCH 0x08F0C
751#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
752#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
753#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
754#define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */
755#define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */
756#define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */
757#define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */
758#define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */
759#define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */
760#define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */
761#define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */
762#define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */
763#define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */
764#define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */
765#define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */
766#define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */
767#define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */
768#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */
769#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
770#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
771#define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */
772#define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */
773
774/* LinkSec (MacSec) Bit Fields and Masks */
775#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
776#define IXGBE_LSECTXCAP_SUM_SHIFT 16
777#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
778#define IXGBE_LSECRXCAP_SUM_SHIFT 16
779
780#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
781#define IXGBE_LSECTXCTRL_DISABLE 0x0
782#define IXGBE_LSECTXCTRL_AUTH 0x1
783#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
784#define IXGBE_LSECTXCTRL_AISCI 0x00000020
785#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
786#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
787
788#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
789#define IXGBE_LSECRXCTRL_EN_SHIFT 2
790#define IXGBE_LSECRXCTRL_DISABLE 0x0
791#define IXGBE_LSECRXCTRL_CHECK 0x1
792#define IXGBE_LSECRXCTRL_STRICT 0x2
793#define IXGBE_LSECRXCTRL_DROP 0x3
794#define IXGBE_LSECRXCTRL_PLSH 0x00000040
795#define IXGBE_LSECRXCTRL_RP 0x00000080
796#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
797
798/* IpSec Registers */
799#define IXGBE_IPSTXIDX 0x08900
800#define IXGBE_IPSTXSALT 0x08904
801#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
802#define IXGBE_IPSRXIDX 0x08E00
803#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
804#define IXGBE_IPSRXSPI 0x08E14
805#define IXGBE_IPSRXIPIDX 0x08E18
806#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
807#define IXGBE_IPSRXSALT 0x08E2C
808#define IXGBE_IPSRXMOD 0x08E30
809
810#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
811
812/* DCB registers */
813#define IXGBE_RTRPCS 0x02430
814#define IXGBE_RTTDCS 0x04900
815#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */
816#define IXGBE_RTTPCS 0x0CD00
817#define IXGBE_RTRUP2TC 0x03020
818#define IXGBE_RTTUP2TC 0x0C800
819#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
820#define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */
821#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
822#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
823#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
824#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
825#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
826#define IXGBE_RTTDQSEL 0x04904
827#define IXGBE_RTTDT1C 0x04908
828#define IXGBE_RTTDT1S 0x0490C
829#define IXGBE_RTTDTECC 0x04990
830#define IXGBE_RTTDTECC_NO_BCN 0x00000100
831
832#define IXGBE_RTTBCNRC 0x04984
833#define IXGBE_RTTBCNRC_RS_ENA 0x80000000
834#define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF
835#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14
836#define IXGBE_RTTBCNRC_RF_INT_MASK \
837 (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
838#define IXGBE_RTTBCNRM 0x04980
839
840/* BCN (for DCB) Registers */
841#define IXGBE_RTTBCNRS 0x04988
842#define IXGBE_RTTBCNCR 0x08B00
843#define IXGBE_RTTBCNACH 0x08B04
844#define IXGBE_RTTBCNACL 0x08B08
845#define IXGBE_RTTBCNTG 0x04A90
846#define IXGBE_RTTBCNIDX 0x08B0C
847#define IXGBE_RTTBCNCP 0x08B10
848#define IXGBE_RTFRTIMER 0x08B14
849#define IXGBE_RTTBCNRTT 0x05150
850#define IXGBE_RTTBCNRD 0x0498C
851
852
853/* FCoE DMA Context Registers */
854/* FCoE Direct DMA Context */
855#define IXGBE_FCDDC(_i, _j) (0x20000 + ((_i) * 0x4) + ((_j) * 0x10))
856#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
857#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
858#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
859#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
860#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */
861#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */
862#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */
863#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */
864#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */
865#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
866#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
867#define IXGBE_FCBUFF_OFFSET_SHIFT 16
868#define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */
869#define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */
870#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */
871#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */
872#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
873/* FCoE SOF/EOF */
874#define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */
875#define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */
876#define IXGBE_REOFF 0x05158 /* Rx FC EOF */
877#define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */
878/* FCoE Filter Context Registers */
879#define IXGBE_FCD_ID 0x05114 /* FCoE D_ID */
880#define IXGBE_FCSMAC 0x0510C /* FCoE Source MAC */
881#define IXGBE_FCFLTRW_SMAC_HIGH_SHIFT 16
882/* FCoE Direct Filter Context */
883#define IXGBE_FCDFC(_i, _j) (0x28000 + ((_i) * 0x4) + ((_j) * 0x10))
884#define IXGBE_FCDFCD(_i) (0x30000 + ((_i) * 0x4))
885#define IXGBE_FCFLT 0x05108 /* FC FLT Context */
886#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */
887#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */
888#define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */
889#define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */
890#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */
891#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */
892#define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */
893#define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */
894#define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */
895/* FCoE Receive Control */
896#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */
897#define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */
898#define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */
899#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */
900#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */
901#define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */
902#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */
903#define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */
904#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */
905#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */
906#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
907/* FCoE Redirection */
908#define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */
909#define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */
910#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
911#define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */
912#define IXGBE_FCRETASEL_ENA 0x2 /* FCoE FCRETASEL bit */
913#define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */
914#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
915#define IXGBE_FCRETA_SIZE_X550 32 /* Max entries in FCRETA */
916/* Higher 7 bits for the queue index */
917#define IXGBE_FCRETA_ENTRY_HIGH_MASK 0x007F0000
918#define IXGBE_FCRETA_ENTRY_HIGH_SHIFT 16
919
920/* Stats registers */
921#define IXGBE_CRCERRS 0x04000
922#define IXGBE_ILLERRC 0x04004
923#define IXGBE_ERRBC 0x04008
924#define IXGBE_MSPDC 0x04010
925#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
926#define IXGBE_MLFC 0x04034
927#define IXGBE_MRFC 0x04038
928#define IXGBE_RLEC 0x04040
929#define IXGBE_LXONTXC 0x03F60
930#define IXGBE_LXONRXC 0x0CF60
931#define IXGBE_LXOFFTXC 0x03F68
932#define IXGBE_LXOFFRXC 0x0CF68
933#define IXGBE_LXONRXCNT 0x041A4
934#define IXGBE_LXOFFRXCNT 0x041A8
935#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */
936#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */
937#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */
938#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
939#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
940#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
941#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
942#define IXGBE_PRC64 0x0405C
943#define IXGBE_PRC127 0x04060
944#define IXGBE_PRC255 0x04064
945#define IXGBE_PRC511 0x04068
946#define IXGBE_PRC1023 0x0406C
947#define IXGBE_PRC1522 0x04070
948#define IXGBE_GPRC 0x04074
949#define IXGBE_BPRC 0x04078
950#define IXGBE_MPRC 0x0407C
951#define IXGBE_GPTC 0x04080
952#define IXGBE_GORCL 0x04088
953#define IXGBE_GORCH 0x0408C
954#define IXGBE_GOTCL 0x04090
955#define IXGBE_GOTCH 0x04094
956#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
957#define IXGBE_RUC 0x040A4
958#define IXGBE_RFC 0x040A8
959#define IXGBE_ROC 0x040AC
960#define IXGBE_RJC 0x040B0
961#define IXGBE_MNGPRC 0x040B4
962#define IXGBE_MNGPDC 0x040B8
963#define IXGBE_MNGPTC 0x0CF90
964#define IXGBE_TORL 0x040C0
965#define IXGBE_TORH 0x040C4
966#define IXGBE_TPR 0x040D0
967#define IXGBE_TPT 0x040D4
968#define IXGBE_PTC64 0x040D8
969#define IXGBE_PTC127 0x040DC
970#define IXGBE_PTC255 0x040E0
971#define IXGBE_PTC511 0x040E4
972#define IXGBE_PTC1023 0x040E8
973#define IXGBE_PTC1522 0x040EC
974#define IXGBE_MPTC 0x040F0
975#define IXGBE_BPTC 0x040F4
976#define IXGBE_XEC 0x04120
977#define IXGBE_SSVPC 0x08780
978
979#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
980#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
981 (0x08600 + ((_i) * 4)))
982#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
983
984#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
985#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
986#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
987#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
988#define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
989#define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
990#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
991#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
992#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
993#define IXGBE_FCCRC 0x05118 /* Num of Good Eth CRC w/ Bad FC CRC */
994#define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */
995#define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */
996#define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */
997#define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */
998#define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */
999#define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */
1000#define IXGBE_FCCRC_CNT_MASK 0x0000FFFF /* CRC_CNT: bit 0 - 15 */
1001#define IXGBE_FCLAST_CNT_MASK 0x0000FFFF /* Last_CNT: bit 0 - 15 */
1002#define IXGBE_O2BGPTC 0x041C4
1003#define IXGBE_O2BSPC 0x087B0
1004#define IXGBE_B2OSPC 0x041C0
1005#define IXGBE_B2OGPRC 0x02F90
1006#define IXGBE_BUPRC 0x04180
1007#define IXGBE_BMPRC 0x04184
1008#define IXGBE_BBPRC 0x04188
1009#define IXGBE_BUPTC 0x0418C
1010#define IXGBE_BMPTC 0x04190
1011#define IXGBE_BBPTC 0x04194
1012#define IXGBE_BCRCERRS 0x04198
1013#define IXGBE_BXONRXC 0x0419C
1014#define IXGBE_BXOFFRXC 0x041E0
1015#define IXGBE_BXONTXC 0x041E4
1016#define IXGBE_BXOFFTXC 0x041E8
1017
1018/* Management */
1019#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
1020#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
1021#define IXGBE_MANC 0x05820
1022#define IXGBE_MFVAL 0x05824
1023#define IXGBE_MANC2H 0x05860
1024#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
1025#define IXGBE_MIPAF 0x058B0
1026#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
1027#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
1028#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
1029#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
1030#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */

~~998~~#define IXGBE_LSWFW 0x15014

1031#define IXGBE_LSWFW 0x15F14

1032#define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */
1033#define IXGBE_BMCIPVAL 0x05060
1034#define IXGBE_BMCIP_IPADDR_TYPE 0x00000001
1035#define IXGBE_BMCIP_IPADDR_VALID 0x00000002
1036
1037/* Management Bit Fields and Masks */
1038#define IXGBE_MANC_MPROXYE 0x40000000 /* Management Proxy Enable */
1039#define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */
1040#define IXGBE_MANC_EN_BMC2OS 0x10000000 /* Ena BMC2OS and OS2BMC traffic */
1041#define IXGBE_MANC_EN_BMC2OS_SHIFT 28
1042
1043/* Firmware Semaphore Register */
1044#define IXGBE_FWSM_MODE_MASK 0xE
1045#define IXGBE_FWSM_TS_ENABLED 0x1
1046#define IXGBE_FWSM_FW_MODE_PT 0x4
1047
1048/* ARC Subsystem registers */
1049#define IXGBE_HICR 0x15F00
1050#define IXGBE_FWSTS 0x15F0C
1051#define IXGBE_HSMC0R 0x15F04
1052#define IXGBE_HSMC1R 0x15F08
1053#define IXGBE_SWSR 0x15F10
1054#define IXGBE_HFDR 0x15FE8
1055#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */
1056
1057#define IXGBE_HICR_EN 0x01 /* Enable bit - RO */
1058/* Driver sets this bit when done to put command in RAM */
1059#define IXGBE_HICR_C 0x02
1060#define IXGBE_HICR_SV 0x04 /* Status Validity */
1061#define IXGBE_HICR_FW_RESET_ENABLE 0x40
1062#define IXGBE_HICR_FW_RESET 0x80
1063
1064/* PCI-E registers */
1065#define IXGBE_GCR 0x11000
1066#define IXGBE_GTV 0x11004
1067#define IXGBE_FUNCTAG 0x11008
1068#define IXGBE_GLT 0x1100C
1069#define IXGBE_PCIEPIPEADR 0x11004
1070#define IXGBE_PCIEPIPEDAT 0x11008
1071#define IXGBE_GSCL_1 0x11010
1072#define IXGBE_GSCL_2 0x11014

1073#define IXGBE_GSCL_1_X540 IXGBE_GSCL_1
1074#define IXGBE_GSCL_2_X540 IXGBE_GSCL_2

1075#define IXGBE_GSCL_3 0x11018
1076#define IXGBE_GSCL_4 0x1101C
1077#define IXGBE_GSCN_0 0x11020
1078#define IXGBE_GSCN_1 0x11024
1079#define IXGBE_GSCN_2 0x11028
1080#define IXGBE_GSCN_3 0x1102C

1081#define IXGBE_GSCN_0_X540 IXGBE_GSCN_0
1082#define IXGBE_GSCN_1_X540 IXGBE_GSCN_1
1083#define IXGBE_GSCN_2_X540 IXGBE_GSCN_2
1084#define IXGBE_GSCN_3_X540 IXGBE_GSCN_3

1085#define IXGBE_FACTPS 0x10150
1086#define IXGBE_FACTPS_X540 IXGBE_FACTPS

1087#define IXGBE_GSCL_1_X550 0x11800
1088#define IXGBE_GSCL_2_X550 0x11804
1089#define IXGBE_GSCL_1_X550EM_x IXGBE_GSCL_1_X550
1090#define IXGBE_GSCL_2_X550EM_x IXGBE_GSCL_2_X550
1091#define IXGBE_GSCN_0_X550 0x11820
1092#define IXGBE_GSCN_1_X550 0x11824
1093#define IXGBE_GSCN_2_X550 0x11828
1094#define IXGBE_GSCN_3_X550 0x1182C
1095#define IXGBE_GSCN_0_X550EM_x IXGBE_GSCN_0_X550
1096#define IXGBE_GSCN_1_X550EM_x IXGBE_GSCN_1_X550
1097#define IXGBE_GSCN_2_X550EM_x IXGBE_GSCN_2_X550
1098#define IXGBE_GSCN_3_X550EM_x IXGBE_GSCN_3_X550

1099#define IXGBE_FACTPS_X550 IXGBE_FACTPS
1100#define IXGBE_FACTPS_X550EM_x IXGBE_FACTPS

~~1050~~#define IXGBE_FACTPS_BY_MAC(_hw) IXGBE_FACTPS

1101#define IXGBE_GSCL_1_X550EM_a IXGBE_GSCL_1_X550
1102#define IXGBE_GSCL_2_X550EM_a IXGBE_GSCL_2_X550
1103#define IXGBE_GSCN_0_X550EM_a IXGBE_GSCN_0_X550
1104#define IXGBE_GSCN_1_X550EM_a IXGBE_GSCN_1_X550
1105#define IXGBE_GSCN_2_X550EM_a IXGBE_GSCN_2_X550
1106#define IXGBE_GSCN_3_X550EM_a IXGBE_GSCN_3_X550
1107#define IXGBE_FACTPS_X550EM_a 0x15FEC
1108#define IXGBE_FACTPS_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FACTPS)

1109
1110#define IXGBE_PCIEANACTL 0x11040
1111#define IXGBE_SWSM 0x10140
1112#define IXGBE_SWSM_X540 IXGBE_SWSM
1113#define IXGBE_SWSM_X550 IXGBE_SWSM
1114#define IXGBE_SWSM_X550EM_x IXGBE_SWSM

~~1057~~#define IXGBE_SWSM_BY_MAC(_hw) IXGBE_SWSM

1115#define IXGBE_SWSM_X550EM_a 0x15F70
1116#define IXGBE_SWSM_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SWSM)

1117
1118#define IXGBE_FWSM 0x10148
1119#define IXGBE_FWSM_X540 IXGBE_FWSM
1120#define IXGBE_FWSM_X550 IXGBE_FWSM
1121#define IXGBE_FWSM_X550EM_x IXGBE_FWSM

~~1063~~#define IXGBE_FWSM_BY_MAC(_hw) IXGBE_FWSM

1122#define IXGBE_FWSM_X550EM_a 0x15F74
1123#define IXGBE_FWSM_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FWSM)

1124
1125#define IXGBE_SWFW_SYNC IXGBE_GSSR
1126#define IXGBE_SWFW_SYNC_X540 IXGBE_SWFW_SYNC
1127#define IXGBE_SWFW_SYNC_X550 IXGBE_SWFW_SYNC
1128#define IXGBE_SWFW_SYNC_X550EM_x IXGBE_SWFW_SYNC

~~1069~~#define IXGBE_SWFW_SYNC_BY_MAC(_hw) IXGBE_SWFW_SYNC

1129#define IXGBE_SWFW_SYNC_X550EM_a 0x15F78
1130#define IXGBE_SWFW_SYNC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SWFW_SYNC)

1131
1132#define IXGBE_GSSR 0x10160
1133#define IXGBE_MREVID 0x11064
1134#define IXGBE_DCA_ID 0x11070
1135#define IXGBE_DCA_CTRL 0x11074
1136
1137/* PCI-E registers 82599-Specific */
1138#define IXGBE_GCR_EXT 0x11050
1139#define IXGBE_GSCL_5_82599 0x11030
1140#define IXGBE_GSCL_6_82599 0x11034
1141#define IXGBE_GSCL_7_82599 0x11038
1142#define IXGBE_GSCL_8_82599 0x1103C

1143#define IXGBE_GSCL_5_X540 IXGBE_GSCL_5_82599
1144#define IXGBE_GSCL_6_X540 IXGBE_GSCL_6_82599
1145#define IXGBE_GSCL_7_X540 IXGBE_GSCL_7_82599
1146#define IXGBE_GSCL_8_X540 IXGBE_GSCL_8_82599

1147#define IXGBE_PHYADR_82599 0x11040
1148#define IXGBE_PHYDAT_82599 0x11044
1149#define IXGBE_PHYCTL_82599 0x11048
1150#define IXGBE_PBACLR_82599 0x11068
1151#define IXGBE_CIAA 0x11088
1152#define IXGBE_CIAD 0x1108C
1153#define IXGBE_CIAA_82599 IXGBE_CIAA
1154#define IXGBE_CIAD_82599 IXGBE_CIAD
1155#define IXGBE_CIAA_X540 IXGBE_CIAA
1156#define IXGBE_CIAD_X540 IXGBE_CIAD

1157#define IXGBE_GSCL_5_X550 0x11810
1158#define IXGBE_GSCL_6_X550 0x11814
1159#define IXGBE_GSCL_7_X550 0x11818
1160#define IXGBE_GSCL_8_X550 0x1181C
1161#define IXGBE_GSCL_5_X550EM_x IXGBE_GSCL_5_X550
1162#define IXGBE_GSCL_6_X550EM_x IXGBE_GSCL_6_X550
1163#define IXGBE_GSCL_7_X550EM_x IXGBE_GSCL_7_X550
1164#define IXGBE_GSCL_8_X550EM_x IXGBE_GSCL_8_X550

1165#define IXGBE_CIAA_X550 0x11508
1166#define IXGBE_CIAD_X550 0x11510
1167#define IXGBE_CIAA_X550EM_x IXGBE_CIAA_X550
1168#define IXGBE_CIAD_X550EM_x IXGBE_CIAD_X550

1169#define IXGBE_GSCL_5_X550EM_a IXGBE_GSCL_5_X550
1170#define IXGBE_GSCL_6_X550EM_a IXGBE_GSCL_6_X550
1171#define IXGBE_GSCL_7_X550EM_a IXGBE_GSCL_7_X550
1172#define IXGBE_GSCL_8_X550EM_a IXGBE_GSCL_8_X550
1173#define IXGBE_CIAA_X550EM_a IXGBE_CIAA_X550
1174#define IXGBE_CIAD_X550EM_a IXGBE_CIAD_X550

1175#define IXGBE_CIAA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAA)
1176#define IXGBE_CIAD_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAD)
1177#define IXGBE_PICAUSE 0x110B0
1178#define IXGBE_PIENA 0x110B8
1179#define IXGBE_CDQ_MBR_82599 0x110B4
1180#define IXGBE_PCIESPARE 0x110BC
1181#define IXGBE_MISC_REG_82599 0x110F0
1182#define IXGBE_ECC_CTRL_0_82599 0x11100
1183#define IXGBE_ECC_CTRL_1_82599 0x11104
1184#define IXGBE_ECC_STATUS_82599 0x110E0
1185#define IXGBE_BAR_CTRL_82599 0x110F4
1186
1187/* PCI Express Control */
1188#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
1189#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
1190#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
1191#define IXGBE_GCR_CAP_VER2 0x00040000
1192
1193#define IXGBE_GCR_EXT_MSIX_EN 0x80000000
1194#define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000
1195#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
1196#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
1197#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
1198#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
1199 IXGBE_GCR_EXT_VT_MODE_64)
1200#define IXGBE_GCR_EXT_VT_MODE_MASK 0x00000003
1201/* Time Sync Registers */
1202#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
1203#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
1204#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */
1205#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */
1206#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */
1207#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */
1208#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */
1209#define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */
1210#define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */
1211#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */
1212#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */
1213#define IXGBE_SYSTIMR 0x08C58 /* System time register Residue - RO */
1214#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
1215#define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */
1216#define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */
1217#define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */
1218#define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */
1219#define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */
1220#define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */
1221#define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */
1222#define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */
1223#define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */
1224#define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */
1225#define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */
1226#define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
1227#define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
1228#define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
1229#define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
1230#define IXGBE_TSIM 0x08C68 /* TimeSync Interrupt Mask Register - RW */
1231#define IXGBE_TSICR 0x08C60 /* TimeSync Interrupt Cause Register - WO */
1232#define IXGBE_TSSDP 0x0003C /* TimeSync SDP Configuration Register - RW */
1233
1234/* Diagnostic Registers */
1235#define IXGBE_RDSTATCTL 0x02C20
1236#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
1237#define IXGBE_RDHMPN 0x02F08
1238#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
1239#define IXGBE_RDPROBE 0x02F20
1240#define IXGBE_RDMAM 0x02F30
1241#define IXGBE_RDMAD 0x02F34
1242#define IXGBE_TDHMPN 0x07F08
1243#define IXGBE_TDHMPN2 0x082FC
1244#define IXGBE_TXDESCIC 0x082CC
1245#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
1246#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
1247#define IXGBE_TDPROBE 0x07F20
1248#define IXGBE_TXBUFCTRL 0x0C600
1249#define IXGBE_TXBUFDATA0 0x0C610
1250#define IXGBE_TXBUFDATA1 0x0C614
1251#define IXGBE_TXBUFDATA2 0x0C618
1252#define IXGBE_TXBUFDATA3 0x0C61C
1253#define IXGBE_RXBUFCTRL 0x03600
1254#define IXGBE_RXBUFDATA0 0x03610
1255#define IXGBE_RXBUFDATA1 0x03614
1256#define IXGBE_RXBUFDATA2 0x03618
1257#define IXGBE_RXBUFDATA3 0x0361C
1258#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
1259#define IXGBE_RFVAL 0x050A4
1260#define IXGBE_MDFTC1 0x042B8
1261#define IXGBE_MDFTC2 0x042C0
1262#define IXGBE_MDFTFIFO1 0x042C4
1263#define IXGBE_MDFTFIFO2 0x042C8
1264#define IXGBE_MDFTS 0x042CC
1265#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
1266#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
1267#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
1268#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
1269#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
1270#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
1271#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
1272#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
1273#define IXGBE_PCIEECCCTL 0x1106C
1274#define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
1275#define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
1276#define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
1277#define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
1278#define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
1279#define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
1280#define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
1281#define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
1282#define IXGBE_PCIEECCCTL0 0x11100
1283#define IXGBE_PCIEECCCTL1 0x11104
1284#define IXGBE_RXDBUECC 0x03F70
1285#define IXGBE_TXDBUECC 0x0CF70
1286#define IXGBE_RXDBUEST 0x03F74
1287#define IXGBE_TXDBUEST 0x0CF74
1288#define IXGBE_PBTXECC 0x0C300
1289#define IXGBE_PBRXECC 0x03300
1290#define IXGBE_GHECCR 0x110B0
1291
1292/* MAC Registers */
1293#define IXGBE_PCS1GCFIG 0x04200
1294#define IXGBE_PCS1GLCTL 0x04208
1295#define IXGBE_PCS1GLSTA 0x0420C
1296#define IXGBE_PCS1GDBG0 0x04210
1297#define IXGBE_PCS1GDBG1 0x04214
1298#define IXGBE_PCS1GANA 0x04218
1299#define IXGBE_PCS1GANLP 0x0421C
1300#define IXGBE_PCS1GANNP 0x04220
1301#define IXGBE_PCS1GANLPNP 0x04224
1302#define IXGBE_HLREG0 0x04240
1303#define IXGBE_HLREG1 0x04244
1304#define IXGBE_PAP 0x04248
1305#define IXGBE_MACA 0x0424C
1306#define IXGBE_APAE 0x04250
1307#define IXGBE_ARD 0x04254
1308#define IXGBE_AIS 0x04258
1309#define IXGBE_MSCA 0x0425C
1310#define IXGBE_MSRWD 0x04260
1311#define IXGBE_MLADD 0x04264
1312#define IXGBE_MHADD 0x04268
1313#define IXGBE_MAXFRS 0x04268
1314#define IXGBE_TREG 0x0426C
1315#define IXGBE_PCSS1 0x04288
1316#define IXGBE_PCSS2 0x0428C
1317#define IXGBE_XPCSS 0x04290
1318#define IXGBE_MFLCN 0x04294
1319#define IXGBE_SERDESC 0x04298

1320#define IXGBE_MAC_SGMII_BUSY 0x04298

1321#define IXGBE_MACS 0x0429C
1322#define IXGBE_AUTOC 0x042A0
1323#define IXGBE_LINKS 0x042A4
1324#define IXGBE_LINKS2 0x04324
1325#define IXGBE_AUTOC2 0x042A8
1326#define IXGBE_AUTOC3 0x042AC
1327#define IXGBE_ANLP1 0x042B0
1328#define IXGBE_ANLP2 0x042B4
1329#define IXGBE_MACC 0x04330
1330#define IXGBE_ATLASCTL 0x04800
1331#define IXGBE_MMNGC 0x042D0
1332#define IXGBE_ANLPNP1 0x042D4
1333#define IXGBE_ANLPNP2 0x042D8
1334#define IXGBE_KRPCSFC 0x042E0
1335#define IXGBE_KRPCSS 0x042E4
1336#define IXGBE_FECS1 0x042E8
1337#define IXGBE_FECS2 0x042EC
1338#define IXGBE_SMADARCTL 0x14F10
1339#define IXGBE_MPVC 0x04318
1340#define IXGBE_SGMIIC 0x04314
1341
1342/* Statistics Registers */
1343#define IXGBE_RXNFGPC 0x041B0
1344#define IXGBE_RXNFGBCL 0x041B4
1345#define IXGBE_RXNFGBCH 0x041B8
1346#define IXGBE_RXDGPC 0x02F50
1347#define IXGBE_RXDGBCL 0x02F54
1348#define IXGBE_RXDGBCH 0x02F58
1349#define IXGBE_RXDDGPC 0x02F5C
1350#define IXGBE_RXDDGBCL 0x02F60
1351#define IXGBE_RXDDGBCH 0x02F64
1352#define IXGBE_RXLPBKGPC 0x02F68
1353#define IXGBE_RXLPBKGBCL 0x02F6C
1354#define IXGBE_RXLPBKGBCH 0x02F70
1355#define IXGBE_RXDLPBKGPC 0x02F74
1356#define IXGBE_RXDLPBKGBCL 0x02F78
1357#define IXGBE_RXDLPBKGBCH 0x02F7C
1358#define IXGBE_TXDGPC 0x087A0
1359#define IXGBE_TXDGBCL 0x087A4
1360#define IXGBE_TXDGBCH 0x087A8
1361
1362#define IXGBE_RXDSTATCTRL 0x02F40
1363
1364/* Copper Pond 2 link timeout */
1365#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
1366
1367/* Omer CORECTL */
1368#define IXGBE_CORECTL 0x014F00
1369/* BARCTRL */
1370#define IXGBE_BARCTRL 0x110F4
1371#define IXGBE_BARCTRL_FLSIZE 0x0700
1372#define IXGBE_BARCTRL_FLSIZE_SHIFT 8
1373#define IXGBE_BARCTRL_CSRSIZE 0x2000
1374
1375/* RSCCTL Bit Masks */
1376#define IXGBE_RSCCTL_RSCEN 0x01
1377#define IXGBE_RSCCTL_MAXDESC_1 0x00
1378#define IXGBE_RSCCTL_MAXDESC_4 0x04
1379#define IXGBE_RSCCTL_MAXDESC_8 0x08
1380#define IXGBE_RSCCTL_MAXDESC_16 0x0C
1381#define IXGBE_RSCCTL_TS_DIS 0x02
1382
1383/* RSCDBU Bit Masks */
1384#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F
1385#define IXGBE_RSCDBU_RSCACKDIS 0x00000080
1386
1387/* RDRXCTL Bit Masks */
1388#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min THLD Size */
1389#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
1390#define IXGBE_RDRXCTL_PSP 0x00000004 /* Pad Small Packet */
1391#define IXGBE_RDRXCTL_MVMEN 0x00000020
1392#define IXGBE_RDRXCTL_RSC_PUSH_DIS 0x00000020
1393#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
1394#define IXGBE_RDRXCTL_RSC_PUSH 0x00000080
1395#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
1396#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */
1397#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI*/
1398#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC ena */
1399#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC ena */
1400#define IXGBE_RDRXCTL_MBINTEN 0x10000000
1401#define IXGBE_RDRXCTL_MDP_EN 0x20000000
1402
1403/* RQTC Bit Masks and Shifts */
1404#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
1405#define IXGBE_RQTC_TC0_MASK (0x7 << 0)
1406#define IXGBE_RQTC_TC1_MASK (0x7 << 4)
1407#define IXGBE_RQTC_TC2_MASK (0x7 << 8)
1408#define IXGBE_RQTC_TC3_MASK (0x7 << 12)
1409#define IXGBE_RQTC_TC4_MASK (0x7 << 16)
1410#define IXGBE_RQTC_TC5_MASK (0x7 << 20)
1411#define IXGBE_RQTC_TC6_MASK (0x7 << 24)
1412#define IXGBE_RQTC_TC7_MASK (0x7 << 28)
1413
1414/* PSRTYPE.RQPL Bit masks and shift */
1415#define IXGBE_PSRTYPE_RQPL_MASK 0x7
1416#define IXGBE_PSRTYPE_RQPL_SHIFT 29
1417
1418/* CTRL Bit Masks */
1419#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
1420#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
1421#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
1422#define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1423
1424/* FACTPS */
1425#define IXGBE_FACTPS_MNGCG 0x20000000 /* Manageblility Clock Gated */
1426#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
1427
1428/* MHADD Bit Masks */
1429#define IXGBE_MHADD_MFS_MASK 0xFFFF0000
1430#define IXGBE_MHADD_MFS_SHIFT 16
1431
1432/* Extended Device Control */
1433#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */
1434#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
1435#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
1436#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1437
1438/* Direct Cache Access (DCA) definitions */
1439#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
1440#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
1441
1442#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
1443#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
1444
1445#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
1446#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
1447#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
1448#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* Rx Desc enable */
1449#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* Rx Desc header ena */
1450#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* Rx Desc payload ena */
1451#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* Rx rd Desc Relax Order */
1452#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */
1453#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */
1454
1455#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
1456#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
1457#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
1458#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
1459#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
1460#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */
1461#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
1462#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
1463
1464/* MSCA Bit Masks */
1465#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Addr (new prot) */
1466#define IXGBE_MSCA_NP_ADDR_SHIFT 0
1467#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Dev Type (new prot) */
1468#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old prot */
1469#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */
1470#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/
1471#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */
1472#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
1473#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
1474#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (wr) */
1475#define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (rd) */
1476#define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (rd auto inc)*/
1477#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */
1478#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */
1479#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new prot) */
1480#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old prot) */
1481#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */
1482#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress ena */
1483
1484/* MSRWD bit masks */
1485#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
1486#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
1487#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
1488#define IXGBE_MSRWD_READ_DATA_SHIFT 16
1489
1490/* Atlas registers */
1491#define IXGBE_ATLAS_PDN_LPBK 0x24
1492#define IXGBE_ATLAS_PDN_10G 0xB
1493#define IXGBE_ATLAS_PDN_1G 0xC
1494#define IXGBE_ATLAS_PDN_AN 0xD
1495
1496/* Atlas bit masks */
1497#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
1498#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
1499#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
1500#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
1501#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
1502
1503/* Omer bit masks */
1504#define IXGBE_CORECTL_WRITE_CMD 0x00010000
1505
1506/* Device Type definitions for new protocol MDIO commands */

1507#define IXGBE_MDIO_ZERO_DEV_TYPE 0x0

1508#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
1509#define IXGBE_MDIO_PCS_DEV_TYPE 0x3
1510#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
1511#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
1512#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
1513#define IXGBE_TWINAX_DEV 1
1514
1515#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
1516
1517#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Ctrl Reg */
1518#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
1519#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
1520#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0-10G, 1-1G */
1521#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
1522#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
1523
1524#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
1525#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
1526#define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT 0xC800 /* AUTO_NEG Vendor Status Reg */
1527#define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM 0xCC00 /* AUTO_NEG Vendor TX Reg */
1528#define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */
1529#define IXGBE_MDIO_AUTO_NEG_VEN_LSC 0x1 /* AUTO_NEG Vendor Tx LSC */
1530#define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */
1531#define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */
1532#define IXGBE_MDIO_AUTO_NEG_EEE_ADVT 0x3C /* AUTO_NEG EEE Advt Reg */
1533#define IXGBE_AUTO_NEG_10GBASE_EEE_ADVT 0x8 /* AUTO NEG EEE 10GBaseT Advt */
1534#define IXGBE_AUTO_NEG_1000BASE_EEE_ADVT 0x4 /* AUTO NEG EEE 1000BaseT Advt */
1535#define IXGBE_AUTO_NEG_100BASE_EEE_ADVT 0x2 /* AUTO NEG EEE 100BaseT Advt */
1536#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
1537#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
1538#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
1539#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
1540#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */
1541#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
1542#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
1543#define IXGBE_MDIO_PHY_SPEED_100M 0x0020 /* 100M capable */
1544#define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */
1545#define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */
1546#define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */
1547#define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */
1548#define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */
1549#define IXGBE_AUTO_NEG_LP_STATUS 0xE820 /* AUTO NEG Rx LP Status Reg */
1550#define IXGBE_AUTO_NEG_LP_1000BASE_CAP 0x8000 /* AUTO NEG Rx LP 1000BaseT Cap */
1551#define IXGBE_AUTO_NEG_LP_10GBASE_CAP 0x0800 /* AUTO NEG Rx LP 10GBaseT Cap */
1552#define IXGBE_AUTO_NEG_10GBASET_STAT 0x0021 /* AUTO NEG 10G BaseT Stat */
1553
1554#define IXGBE_MDIO_TX_VENDOR_ALARMS_3 0xCC02 /* Vendor Alarms 3 Reg */
1555#define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK 0x3 /* PHY Reset Complete Mask */
1556#define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */
1557#define IXGBE_MDIO_POWER_UP_STALL 0x8000 /* Power Up Stall */
1558#define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK 0xFF00 /* int std mask */
1559#define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG 0xFC00 /* chip std int flag */
1560#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK 0xFF01 /* int chip-wide mask */
1561#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG 0xFC01 /* int chip-wide mask */
1562#define IXGBE_MDIO_GLOBAL_ALARM_1 0xCC00 /* Global alarm 1 */
1563#define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT 0x0010 /* device fault */
1564#define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL 0x4000 /* high temp failure */

~~1484~~#define IXGBE_MDIO_GLOBAL_FAULT_MSG 0xC850 /* Global Fault Message */

1565#define IXGBE_MDIO_GLOBAL_FAULT_MSG 0xC850 /* Global Fault Message */

1566#define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP 0x8007 /* high temp failure */
1567#define IXGBE_MDIO_GLOBAL_INT_MASK 0xD400 /* Global int mask */
1568#define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN 0x1000 /* autoneg vendor alarm int enable */
1569#define IXGBE_MDIO_GLOBAL_ALARM_1_INT 0x4 /* int in Global alarm 1 */
1570#define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN 0x1 /* vendor alarm int enable */
1571#define IXGBE_MDIO_GLOBAL_STD_ALM2_INT 0x200 /* vendor alarm2 int mask */
1572#define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN 0x4000 /* int high temp enable */

1573#define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN 0x0010 /* int dev fault enable */

1574#define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */
1575#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
1576#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
1577#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
1578#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */
1579#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN 0x1 /* PHY TX Vendor LASI enable */
1580#define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */
1581#define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */
1582
1583#define IXGBE_PCRC8ECL 0x0E810 /* PCR CRC-8 Error Count Lo */
1584#define IXGBE_PCRC8ECH 0x0E811 /* PCR CRC-8 Error Count Hi */
1585#define IXGBE_PCRC8ECH_MASK 0x1F
1586#define IXGBE_LDPCECL 0x0E820 /* PCR Uncorrected Error Count Lo */
1587#define IXGBE_LDPCECH 0x0E821 /* PCR Uncorrected Error Count Hi */
1588
1589/* MII clause 22/28 definitions */
1590#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
1591
1592#define IXGBE_MDIO_XENPAK_LASI_STATUS 0x9005 /* XENPAK LASI Status register*/
1593#define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM 0x1 /* Link Status Alarm change */
1594
1595#define IXGBE_MDIO_AUTO_NEG_LINK_STATUS 0x4 /* Indicates if link is up */
1596
1597#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK 0x7 /* Speed/Duplex Mask */
1598#define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK 0x6 /* Speed Mask */
1599#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF 0x0 /* 10Mb/s Half Duplex */
1600#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL 0x1 /* 10Mb/s Full Duplex */
1601#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF 0x2 /* 100Mb/s Half Duplex */
1602#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL 0x3 /* 100Mb/s Full Duplex */
1603#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF 0x4 /* 1Gb/s Half Duplex */
1604#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL 0x5 /* 1Gb/s Full Duplex */
1605#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF 0x6 /* 10Gb/s Half Duplex */
1606#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7 /* 10Gb/s Full Duplex */
1607#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB 0x4 /* 1Gb/s */
1608#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB 0x6 /* 10Gb/s */
1609
1610#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */
1611#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
1612#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */
1613#define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */
1614#define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/
1615#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/
1616#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/
1617#define IXGBE_MII_2_5GBASE_T_ADVERTISE 0x0400
1618#define IXGBE_MII_5GBASE_T_ADVERTISE 0x0800
1619#define IXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */
1620#define IXGBE_MII_100BASE_T_ADVERTISE_HALF 0x0080 /* half duplex, bit:7 */
1621#define IXGBE_MII_RESTART 0x200
1622#define IXGBE_MII_AUTONEG_COMPLETE 0x20
1623#define IXGBE_MII_AUTONEG_LINK_UP 0x04
1624#define IXGBE_MII_AUTONEG_REG 0x0
1625
1626#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
1627#define IXGBE_MAX_PHY_ADDR 32
1628
1629/* PHY IDs*/
1630#define TN1010_PHY_ID 0x00A19410
1631#define TNX_FW_REV 0xB
1632#define X540_PHY_ID 0x01540200

~~1551~~#define X550_PHY_ID1 0x01540220

1633#define X550_PHY_ID2 0x01540223
1634#define X550_PHY_ID3 0x01540221
1635#define X557_PHY_ID 0x01540240

1636#define X557_PHY_ID2 0x01540250

1637#define AQ_FW_REV 0x20
1638#define QT2022_PHY_ID 0x0043A400
1639#define ATH_PHY_ID 0x03429050
1640
1641/* PHY Types */

~~1560~~#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0

1642#define IXGBE_M88E1500_E_PHY_ID 0x01410DD0
1643#define IXGBE_M88E1543_E_PHY_ID 0x01410EA0

1644
1645/* Special PHY Init Routine */
1646#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1647#define IXGBE_PHY_INIT_END_NL 0xFFFF
1648#define IXGBE_CONTROL_MASK_NL 0xF000
1649#define IXGBE_DATA_MASK_NL 0x0FFF
1650#define IXGBE_CONTROL_SHIFT_NL 12
1651#define IXGBE_DELAY_NL 0
1652#define IXGBE_DATA_NL 1
1653#define IXGBE_CONTROL_NL 0x000F
1654#define IXGBE_CONTROL_EOL_NL 0x0FFF
1655#define IXGBE_CONTROL_SOL_NL 0x0000
1656
1657/* General purpose Interrupt Enable */
1658#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
1659#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
1660#define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */
1661#define IXGBE_SDP0_GPIEN_X540 0x00000002 /* SDP0 on X540 and X550 */
1662#define IXGBE_SDP1_GPIEN_X540 0x00000004 /* SDP1 on X540 and X550 */
1663#define IXGBE_SDP2_GPIEN_X540 0x00000008 /* SDP2 on X540 and X550 */
1664#define IXGBE_SDP0_GPIEN_X550 IXGBE_SDP0_GPIEN_X540
1665#define IXGBE_SDP1_GPIEN_X550 IXGBE_SDP1_GPIEN_X540
1666#define IXGBE_SDP2_GPIEN_X550 IXGBE_SDP2_GPIEN_X540
1667#define IXGBE_SDP0_GPIEN_X550EM_x IXGBE_SDP0_GPIEN_X540
1668#define IXGBE_SDP1_GPIEN_X550EM_x IXGBE_SDP1_GPIEN_X540
1669#define IXGBE_SDP2_GPIEN_X550EM_x IXGBE_SDP2_GPIEN_X540

1670#define IXGBE_SDP0_GPIEN_X550EM_a IXGBE_SDP0_GPIEN_X540
1671#define IXGBE_SDP1_GPIEN_X550EM_a IXGBE_SDP1_GPIEN_X540
1672#define IXGBE_SDP2_GPIEN_X550EM_a IXGBE_SDP2_GPIEN_X540

1673#define IXGBE_SDP0_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP0_GPIEN)
1674#define IXGBE_SDP1_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP1_GPIEN)
1675#define IXGBE_SDP2_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP2_GPIEN)
1676
1677#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
1678#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
1679#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
1680#define IXGBE_GPIE_EIAME 0x40000000
1681#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
1682#define IXGBE_GPIE_RSC_DELAY_SHIFT 11
1683#define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */
1684#define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */
1685#define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */
1686#define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */
1687
1688/* Packet Buffer Initialization */
1689#define IXGBE_MAX_PACKET_BUFFERS 8
1690
1691#define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */
1692#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */
1693#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */
1694#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */
1695#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */
1696#define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */
1697#define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer */
1698#define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer */
1699
1700#define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
1701#define IXGBE_MAX_PB 8
1702
1703/* Packet buffer allocation strategies */
1704enum {
1705 PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */
1706#define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL
1707 PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */
1708#define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED
1709};
1710
1711/* Transmit Flow Control status */
1712#define IXGBE_TFCS_TXOFF 0x00000001
1713#define IXGBE_TFCS_TXOFF0 0x00000100
1714#define IXGBE_TFCS_TXOFF1 0x00000200
1715#define IXGBE_TFCS_TXOFF2 0x00000400
1716#define IXGBE_TFCS_TXOFF3 0x00000800
1717#define IXGBE_TFCS_TXOFF4 0x00001000
1718#define IXGBE_TFCS_TXOFF5 0x00002000
1719#define IXGBE_TFCS_TXOFF6 0x00004000
1720#define IXGBE_TFCS_TXOFF7 0x00008000
1721
1722/* TCP Timer */
1723#define IXGBE_TCPTIMER_KS 0x00000100
1724#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
1725#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
1726#define IXGBE_TCPTIMER_LOOP 0x00000800
1727#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
1728
1729/* HLREG0 Bit Masks */
1730#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */
1731#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */
1732#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */
1733#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */
1734#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */
1735#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */
1736#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */
1737#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */
1738#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */
1739#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */
1740#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */
1741#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */
1742#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */
1743#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */
1744#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */
1745
1746/* VMD_CTL bitmasks */
1747#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
1748#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
1749
1750/* VT_CTL bitmasks */
1751#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */
1752#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */
1753#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */
1754#define IXGBE_VT_CTL_POOL_SHIFT 7
1755#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1756
1757/* VMOLR bitmasks */

1758#define IXGBE_VMOLR_UPE 0x00400000 /* unicast promiscuous */
1759#define IXGBE_VMOLR_VPE 0x00800000 /* VLAN promiscuous */

1760#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */
1761#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */
1762#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */
1763#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */
1764#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */
1765
1766/* VFRE bitmask */
1767#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
1768
1769#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
1770
1771/* RDHMPN and TDHMPN bitmasks */
1772#define IXGBE_RDHMPN_RDICADDR 0x007FF800
1773#define IXGBE_RDHMPN_RDICRDREQ 0x00800000
1774#define IXGBE_RDHMPN_RDICADDR_SHIFT 11
1775#define IXGBE_TDHMPN_TDICADDR 0x003FF800
1776#define IXGBE_TDHMPN_TDICRDREQ 0x00800000
1777#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
1778
1779#define IXGBE_RDMAM_MEM_SEL_SHIFT 13
1780#define IXGBE_RDMAM_DWORD_SHIFT 9
1781#define IXGBE_RDMAM_DESC_COMP_FIFO 1
1782#define IXGBE_RDMAM_DFC_CMD_FIFO 2
1783#define IXGBE_RDMAM_RSC_HEADER_ADDR 3
1784#define IXGBE_RDMAM_TCN_STATUS_RAM 4
1785#define IXGBE_RDMAM_WB_COLL_FIFO 5
1786#define IXGBE_RDMAM_QSC_CNT_RAM 6
1787#define IXGBE_RDMAM_QSC_FCOE_RAM 7
1788#define IXGBE_RDMAM_QSC_QUEUE_CNT 8
1789#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
1790#define IXGBE_RDMAM_QSC_RSC_RAM 0xB
1791#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
1792#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
1793#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
1794#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
1795#define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE 32
1796#define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT 4
1797#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
1798#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
1799#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
1800#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
1801#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
1802#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
1803#define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE 512
1804#define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT 5
1805#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
1806#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
1807#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
1808#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
1809#define IXGBE_RDMAM_QSC_RSC_RAM_RANGE 32
1810#define IXGBE_RDMAM_QSC_RSC_RAM_COUNT 8
1811
1812#define IXGBE_TXDESCIC_READY 0x80000000
1813
1814/* Receive Checksum Control */
1815#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1816#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1817
1818/* FCRTL Bit Masks */
1819#define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */
1820#define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */
1821
1822/* PAP bit masks*/
1823#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
1824
1825/* RMCS Bit Masks */
1826#define IXGBE_RMCS_RRM 0x00000002 /* Rx Recycle Mode enable */
1827/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
1828#define IXGBE_RMCS_RAC 0x00000004
1829/* Deficit Fixed Prio ena */
1830#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC
1831#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */
1832#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
1833#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
1834
1835/* FCCFG Bit Masks */
1836#define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */
1837#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */
1838
1839/* Interrupt register bitmasks */
1840
1841/* Extended Interrupt Cause Read */
1842#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
1843#define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */
1844#define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */
1845#define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */
1846#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
1847#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
1848#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */
1849#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
1850#define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */
1851#define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */
1852#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
1853#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
1854#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */
1855#define IXGBE_EICR_ECC 0x10000000 /* ECC Error */
1856#define IXGBE_EICR_GPI_SDP0_X540 0x02000000 /* Gen Purpose Interrupt on SDP0 */
1857#define IXGBE_EICR_GPI_SDP1_X540 0x04000000 /* Gen Purpose Interrupt on SDP1 */
1858#define IXGBE_EICR_GPI_SDP2_X540 0x08000000 /* Gen Purpose Interrupt on SDP2 */
1859#define IXGBE_EICR_GPI_SDP0_X550 IXGBE_EICR_GPI_SDP0_X540
1860#define IXGBE_EICR_GPI_SDP1_X550 IXGBE_EICR_GPI_SDP1_X540
1861#define IXGBE_EICR_GPI_SDP2_X550 IXGBE_EICR_GPI_SDP2_X540
1862#define IXGBE_EICR_GPI_SDP0_X550EM_x IXGBE_EICR_GPI_SDP0_X540
1863#define IXGBE_EICR_GPI_SDP1_X550EM_x IXGBE_EICR_GPI_SDP1_X540
1864#define IXGBE_EICR_GPI_SDP2_X550EM_x IXGBE_EICR_GPI_SDP2_X540

1865#define IXGBE_EICR_GPI_SDP0_X550EM_a IXGBE_EICR_GPI_SDP0_X540
1866#define IXGBE_EICR_GPI_SDP1_X550EM_a IXGBE_EICR_GPI_SDP1_X540
1867#define IXGBE_EICR_GPI_SDP2_X550EM_a IXGBE_EICR_GPI_SDP2_X540

1868#define IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP0)
1869#define IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP1)
1870#define IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP2)
1871
1872#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
1873#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
1874#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
1875#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
1876
1877/* Extended Interrupt Cause Set */
1878#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1879#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1880#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */
1881#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */
1882#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1883#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
1884#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1885#define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
1886#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1887#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1888#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1889#define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */
1890#define IXGBE_EICS_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)
1891#define IXGBE_EICS_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)
1892#define IXGBE_EICS_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)
1893#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1894#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
1895#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1896#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1897
1898/* Extended Interrupt Mask Set */
1899#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1900#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1901#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1902#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */
1903#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1904#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
1905#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1906#define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermal Sensor Event */
1907#define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
1908#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1909#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1910#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1911#define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */
1912#define IXGBE_EIMS_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)
1913#define IXGBE_EIMS_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)
1914#define IXGBE_EIMS_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)
1915#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1916#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
1917#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1918#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1919
1920/* Extended Interrupt Mask Clear */
1921#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1922#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1923#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1924#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */
1925#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1926#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
1927#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1928#define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
1929#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1930#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1931#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1932#define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */
1933#define IXGBE_EIMC_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)
1934#define IXGBE_EIMC_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)
1935#define IXGBE_EIMC_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)
1936#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1937#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
1938#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1939#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1940
1941#define IXGBE_EIMS_ENABLE_MASK ( \
1942 IXGBE_EIMS_RTX_QUEUE | \
1943 IXGBE_EIMS_LSC | \
1944 IXGBE_EIMS_TCP_TIMER | \
1945 IXGBE_EIMS_OTHER)
1946
1947/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
1948#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
1949#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
1950#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
1951#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
1952#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
1953#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
1954#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
1955#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
1956#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
1957#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */
1958#define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */
1959#define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
1960#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
1961#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
1962#define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
1963#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
1964#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
1965#define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass chk of ctrl bits */
1966#define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */
1967#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */
1968#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
1969#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */
1970#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */
1971
1972#define IXGBE_MAX_FTQF_FILTERS 128
1973#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
1974#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
1975#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
1976#define IXGBE_FTQF_PROTOCOL_SCTP 2
1977#define IXGBE_FTQF_PRIORITY_MASK 0x00000007
1978#define IXGBE_FTQF_PRIORITY_SHIFT 2
1979#define IXGBE_FTQF_POOL_MASK 0x0000003F
1980#define IXGBE_FTQF_POOL_SHIFT 8
1981#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
1982#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
1983#define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E
1984#define IXGBE_FTQF_DEST_ADDR_MASK 0x1D
1985#define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B
1986#define IXGBE_FTQF_DEST_PORT_MASK 0x17
1987#define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F
1988#define IXGBE_FTQF_POOL_MASK_EN 0x40000000
1989#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
1990
1991/* Interrupt clear mask */
1992#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
1993
1994/* Interrupt Vector Allocation Registers */
1995#define IXGBE_IVAR_REG_NUM 25
1996#define IXGBE_IVAR_REG_NUM_82599 64
1997#define IXGBE_IVAR_TXRX_ENTRY 96
1998#define IXGBE_IVAR_RX_ENTRY 64
1999#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
2000#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
2001#define IXGBE_IVAR_TX_ENTRY 32
2002
2003#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */
2004#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */
2005
2006#define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
2007
2008#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
2009
2010/* ETYPE Queue Filter/Select Bit Masks */
2011#define IXGBE_MAX_ETQF_FILTERS 8
2012#define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */
2013#define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */
2014#define IXGBE_ETQF_TX_ANTISPOOF 0x20000000 /* bit 29 */
2015#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
2016#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
2017#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
2018#define IXGBE_ETQF_POOL_SHIFT 20
2019
2020#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
2021#define IXGBE_ETQS_RX_QUEUE_SHIFT 16
2022#define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */
2023#define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */
2024
2025/*
2026 * ETQF filter list: one static filter per filter consumer. This is
2027 * to avoid filter collisions later. Add new filters
2028 * here!!
2029 *
2030 * Current filters:
2031 * EAPOL 802.1x (0x888e): Filter 0
2032 * FCoE (0x8906): Filter 2
2033 * 1588 (0x88f7): Filter 3
2034 * FIP (0x8914): Filter 4
2035 * LLDP (0x88CC): Filter 5
2036 * LACP (0x8809): Filter 6
2037 * FC (0x8808): Filter 7
2038 */
2039#define IXGBE_ETQF_FILTER_EAPOL 0
2040#define IXGBE_ETQF_FILTER_FCOE 2
2041#define IXGBE_ETQF_FILTER_1588 3
2042#define IXGBE_ETQF_FILTER_FIP 4
2043#define IXGBE_ETQF_FILTER_LLDP 5
2044#define IXGBE_ETQF_FILTER_LACP 6
2045#define IXGBE_ETQF_FILTER_FC 7
2046/* VLAN Control Bit Masks */
2047#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
2048#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
2049#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
2050#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
2051#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
2052
2053/* VLAN pool filtering masks */
2054#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */
2055#define IXGBE_VLVF_ENTRIES 64
2056#define IXGBE_VLVF_VLANID_MASK 0x00000FFF
2057/* Per VF Port VLAN insertion rules */
2058#define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
2059#define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
2060
2061#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
2062
2063/* STATUS Bit Masks */
2064#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
2065#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
2066#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Ena Status */
2067
2068#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
2069#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
2070
2071/* ESDP Bit Masks */
2072#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
2073#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
2074#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
2075#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
2076#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
2077#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
2078#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
2079#define IXGBE_ESDP_SDP7 0x00000080 /* SDP7 Data Value */
2080#define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */
2081#define IXGBE_ESDP_SDP1_DIR 0x00000200 /* SDP1 IO direction */
2082#define IXGBE_ESDP_SDP2_DIR 0x00000400 /* SDP1 IO direction */
2083#define IXGBE_ESDP_SDP3_DIR 0x00000800 /* SDP3 IO direction */
2084#define IXGBE_ESDP_SDP4_DIR 0x00001000 /* SDP4 IO direction */
2085#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
2086#define IXGBE_ESDP_SDP6_DIR 0x00004000 /* SDP6 IO direction */
2087#define IXGBE_ESDP_SDP7_DIR 0x00008000 /* SDP7 IO direction */
2088#define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 IO mode */
2089#define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */
2090
2091
2092/* LEDCTL Bit Masks */
2093#define IXGBE_LED_IVRT_BASE 0x00000040
2094#define IXGBE_LED_BLINK_BASE 0x00000080
2095#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
2096#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
2097#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
2098#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
2099#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
2100#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
2101#define IXGBE_X557_LED_MANUAL_SET_MASK (1 << 8)
2102#define IXGBE_X557_MAX_LED_INDEX 3
2103#define IXGBE_X557_LED_PROVISIONING 0xC430
2104
2105/* LED modes */
2106#define IXGBE_LED_LINK_UP 0x0
2107#define IXGBE_LED_LINK_10G 0x1
2108#define IXGBE_LED_MAC 0x2
2109#define IXGBE_LED_FILTER 0x3
2110#define IXGBE_LED_LINK_ACTIVE 0x4
2111#define IXGBE_LED_LINK_1G 0x5
2112#define IXGBE_LED_ON 0xE
2113#define IXGBE_LED_OFF 0xF
2114
2115/* AUTOC Bit Masks */
2116#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
2117#define IXGBE_AUTOC_KX4_SUPP 0x80000000
2118#define IXGBE_AUTOC_KX_SUPP 0x40000000
2119#define IXGBE_AUTOC_PAUSE 0x30000000
2120#define IXGBE_AUTOC_ASM_PAUSE 0x20000000
2121#define IXGBE_AUTOC_SYM_PAUSE 0x10000000
2122#define IXGBE_AUTOC_RF 0x08000000
2123#define IXGBE_AUTOC_PD_TMR 0x06000000
2124#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
2125#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
2126#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
2127#define IXGBE_AUTOC_FECA 0x00040000
2128#define IXGBE_AUTOC_FECR 0x00020000
2129#define IXGBE_AUTOC_KR_SUPP 0x00010000
2130#define IXGBE_AUTOC_AN_RESTART 0x00001000
2131#define IXGBE_AUTOC_FLU 0x00000001
2132#define IXGBE_AUTOC_LMS_SHIFT 13
2133#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
2134#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)
2135#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)
2136#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
2137#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
2138#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
2139#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
2140#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
2141#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
2142#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
2143#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
2144#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2145
2146#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
2147#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
2148#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
2149#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
2150#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2151#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2152#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2153#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2154#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2155#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2156#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2157
2158#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
2159#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
2160#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
2161#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
2162#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
2163#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
2164#define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000
2165#define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000
2166
2167#define IXGBE_MACC_FLU 0x00000001
2168#define IXGBE_MACC_FSV_10G 0x00030000
2169#define IXGBE_MACC_FS 0x00040000
2170#define IXGBE_MAC_RX2TX_LPBK 0x00000002
2171
2172/* Veto Bit definition */
2173#define IXGBE_MMNGC_MNG_VETO 0x00000001
2174
2175/* LINKS Bit Masks */
2176#define IXGBE_LINKS_KX_AN_COMP 0x80000000
2177#define IXGBE_LINKS_UP 0x40000000
2178#define IXGBE_LINKS_SPEED 0x20000000
2179#define IXGBE_LINKS_MODE 0x18000000
2180#define IXGBE_LINKS_RX_MODE 0x06000000
2181#define IXGBE_LINKS_TX_MODE 0x01800000
2182#define IXGBE_LINKS_XGXS_EN 0x00400000
2183#define IXGBE_LINKS_SGMII_EN 0x02000000
2184#define IXGBE_LINKS_PCS_1G_EN 0x00200000
2185#define IXGBE_LINKS_1G_AN_EN 0x00100000
2186#define IXGBE_LINKS_KX_AN_IDLE 0x00080000
2187#define IXGBE_LINKS_1G_SYNC 0x00040000
2188#define IXGBE_LINKS_10G_ALIGN 0x00020000
2189#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
2190#define IXGBE_LINKS_TL_FAULT 0x00001000
2191#define IXGBE_LINKS_SIGNAL 0x00000F00
2192
2193#define IXGBE_LINKS_SPEED_NON_STD 0x08000000
2194#define IXGBE_LINKS_SPEED_82599 0x30000000
2195#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
2196#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
2197#define IXGBE_LINKS_SPEED_100_82599 0x10000000

2198#define IXGBE_LINKS_SPEED_10_X550EM_A 0x00000000

2199#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
2200#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
2201
2202#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
2203
2204/* PCS1GLSTA Bit Masks */
2205#define IXGBE_PCS1GLSTA_LINK_OK 1
2206#define IXGBE_PCS1GLSTA_SYNK_OK 0x10
2207#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
2208#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
2209#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
2210#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
2211#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
2212
2213#define IXGBE_PCS1GANA_SYM_PAUSE 0x80
2214#define IXGBE_PCS1GANA_ASM_PAUSE 0x100
2215
2216/* PCS1GLCTL Bit Masks */
2217#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */
2218#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
2219#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
2220#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
2221#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
2222#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
2223
2224/* ANLP1 Bit Masks */
2225#define IXGBE_ANLP1_PAUSE 0x0C00
2226#define IXGBE_ANLP1_SYM_PAUSE 0x0400
2227#define IXGBE_ANLP1_ASM_PAUSE 0x0800
2228#define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000
2229
2230/* SW Semaphore Register bitmasks */
2231#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
2232#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
2233#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
2234#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
2235
2236/* SW_FW_SYNC/GSSR definitions */
2237#define IXGBE_GSSR_EEP_SM 0x0001
2238#define IXGBE_GSSR_PHY0_SM 0x0002
2239#define IXGBE_GSSR_PHY1_SM 0x0004
2240#define IXGBE_GSSR_MAC_CSR_SM 0x0008
2241#define IXGBE_GSSR_FLASH_SM 0x0010
2242#define IXGBE_GSSR_NVM_UPDATE_SM 0x0200
2243#define IXGBE_GSSR_SW_MNG_SM 0x0400

2244#define IXGBE_GSSR_TOKEN_SM 0x40000000 /* SW bit for shared access */

2245#define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys and both I2Cs */
2246#define IXGBE_GSSR_I2C_MASK 0x1800
2247#define IXGBE_GSSR_NVM_PHY_MASK 0xF
2248
2249/* FW Status register bitmask */
2250#define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */
2251
2252/* EEC Register */
2253#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */
2254#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */
2255#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */
2256#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */
2257#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */
2258#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
2259#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
2260#define IXGBE_EEC_FWE_SHIFT 4
2261#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
2262#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
2263#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
2264#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
2265#define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */
2266#define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */
2267#define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */
2268/* EEPROM Addressing bits based on type (0-small, 1-large) */
2269#define IXGBE_EEC_ADDR_SIZE 0x00000400
2270#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
2271#define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */
2272
2273#define IXGBE_EEC_SIZE_SHIFT 11
2274#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
2275#define IXGBE_EEPROM_OPCODE_BITS 8
2276
2277/* FLA Register */
2278#define IXGBE_FLA_LOCKED 0x00000040
2279
2280/* Part Number String Length */
2281#define IXGBE_PBANUM_LENGTH 11
2282
2283/* Checksum and EEPROM pointers */
2284#define IXGBE_PBANUM_PTR_GUARD 0xFAFA
2285#define IXGBE_EEPROM_CHECKSUM 0x3F
2286#define IXGBE_EEPROM_SUM 0xBABA

2287#define IXGBE_EEPROM_CTRL_4 0x45
2288#define IXGBE_EE_CTRL_4_INST_ID 0x10
2289#define IXGBE_EE_CTRL_4_INST_ID_SHIFT 4

2290#define IXGBE_PCIE_ANALOG_PTR 0x03
2291#define IXGBE_ATLAS0_CONFIG_PTR 0x04
2292#define IXGBE_PHY_PTR 0x04
2293#define IXGBE_ATLAS1_CONFIG_PTR 0x05
2294#define IXGBE_OPTION_ROM_PTR 0x05
2295#define IXGBE_PCIE_GENERAL_PTR 0x06
2296#define IXGBE_PCIE_CONFIG0_PTR 0x07
2297#define IXGBE_PCIE_CONFIG1_PTR 0x08
2298#define IXGBE_CORE0_PTR 0x09
2299#define IXGBE_CORE1_PTR 0x0A
2300#define IXGBE_MAC0_PTR 0x0B
2301#define IXGBE_MAC1_PTR 0x0C
2302#define IXGBE_CSR0_CONFIG_PTR 0x0D
2303#define IXGBE_CSR1_CONFIG_PTR 0x0E
2304#define IXGBE_PCIE_ANALOG_PTR_X550 0x02
2305#define IXGBE_SHADOW_RAM_SIZE_X550 0x4000
2306#define IXGBE_IXGBE_PCIE_GENERAL_SIZE 0x24
2307#define IXGBE_PCIE_CONFIG_SIZE 0x08
2308#define IXGBE_EEPROM_LAST_WORD 0x41
2309#define IXGBE_FW_PTR 0x0F
2310#define IXGBE_PBANUM0_PTR 0x15
2311#define IXGBE_PBANUM1_PTR 0x16
2312#define IXGBE_ALT_MAC_ADDR_PTR 0x37
2313#define IXGBE_FREE_SPACE_PTR 0X3E
2314
2315#define IXGBE_SAN_MAC_ADDR_PTR 0x28
2316#define IXGBE_DEVICE_CAPS 0x2C

~~2221~~#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11

2317#define IXGBE_82599_SERIAL_NUMBER_MAC_ADDR 0x11
2318#define IXGBE_X550_SERIAL_NUMBER_MAC_ADDR 0x04
2319

2320#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
2321#define IXGBE_MAX_MSIX_VECTORS_82599 0x40
2322#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
2323#define IXGBE_MAX_MSIX_VECTORS_82598 0x13
2324
2325/* MSI-X capability fields masks */
2326#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
2327
2328/* Legacy EEPROM word offsets */
2329#define IXGBE_ISCSI_BOOT_CAPS 0x0033
2330#define IXGBE_ISCSI_SETUP_PORT_0 0x0030
2331#define IXGBE_ISCSI_SETUP_PORT_1 0x0034
2332
2333/* EEPROM Commands - SPI */
2334#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
2335#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
2336#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
2337#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
2338#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
2339#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
2340/* EEPROM reset Write Enable latch */
2341#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
2342#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
2343#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
2344#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
2345#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
2346#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
2347
2348/* EEPROM Read Register */
2349#define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */
2350#define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */
2351#define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */
2352#define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
2353#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for wr complete */
2354#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for rd complete */
2355
2356#define NVM_INIT_CTRL_3 0x38
2357#define NVM_INIT_CTRL_3_LPLU 0x8
2358#define NVM_INIT_CTRL_3_D10GMP_PORT0 0x40
2359#define NVM_INIT_CTRL_3_D10GMP_PORT1 0x100
2360
2361#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
2362
2363#define IXGBE_EEPROM_PAGE_SIZE_MAX 128
2364#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 256 /* words rd in burst */
2365#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* words wr in burst */
2366#define IXGBE_EEPROM_CTRL_2 1 /* EEPROM CTRL word 2 */
2367#define IXGBE_EEPROM_CCD_BIT 2
2368
2369#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
2370#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM attempts to gain grant */
2371#endif
2372
2373/* Number of 5 microseconds we wait for EERD read and
2374 * EERW write to complete */
2375#define IXGBE_EERD_EEWR_ATTEMPTS 100000
2376
2377/* # attempts we wait for flush update to complete */
2378#define IXGBE_FLUDONE_ATTEMPTS 20000
2379
2380#define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */
2381#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */
2382#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */
2383#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */
2384
2385#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
2386#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
2387#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
2388#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2

2389#define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR (1 << 7)

2390#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
2391#define IXGBE_FW_LESM_STATE_1 0x1
2392#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */
2393#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
2394#define IXGBE_FW_PATCH_VERSION_4 0x7
2395#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */
2396#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */
2397#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */
2398#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */
2399#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */
2400#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */
2401#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt SAN MAC capability */
2402#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt SAN MAC 0 offset */
2403#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt SAN MAC 1 offset */
2404#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt WWNN prefix offset */
2405#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt WWPN prefix offset */
2406#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt SAN MAC exists */
2407#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt WWN base exists */
2408
2409/* FW header offset */
2410#define IXGBE_X540_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
2411#define IXGBE_X540_FW_MODULE_MASK 0x7FFF
2412/* 4KB multiplier */
2413#define IXGBE_X540_FW_MODULE_LENGTH 0x1000
2414/* version word 2 (month & day) */
2415#define IXGBE_X540_FW_PATCH_VERSION_2 0x5
2416/* version word 3 (silicon compatibility & year) */
2417#define IXGBE_X540_FW_PATCH_VERSION_3 0x6
2418/* version word 4 (major & minor numbers) */
2419#define IXGBE_X540_FW_PATCH_VERSION_4 0x7
2420
2421#define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */
2422#define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */
2423#define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */
2424
2425/* PCI Bus Info */
2426#define IXGBE_PCI_DEVICE_STATUS 0xAA
2427#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
2428#define IXGBE_PCI_LINK_STATUS 0xB2
2429#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
2430#define IXGBE_PCI_LINK_WIDTH 0x3F0
2431#define IXGBE_PCI_LINK_WIDTH_1 0x10
2432#define IXGBE_PCI_LINK_WIDTH_2 0x20
2433#define IXGBE_PCI_LINK_WIDTH_4 0x40
2434#define IXGBE_PCI_LINK_WIDTH_8 0x80
2435#define IXGBE_PCI_LINK_SPEED 0xF
2436#define IXGBE_PCI_LINK_SPEED_2500 0x1
2437#define IXGBE_PCI_LINK_SPEED_5000 0x2
2438#define IXGBE_PCI_LINK_SPEED_8000 0x3
2439#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
2440#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
2441#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
2442
2443#define IXGBE_PCIDEVCTRL2_TIMEO_MASK 0xf
2444#define IXGBE_PCIDEVCTRL2_16_32ms_def 0x0
2445#define IXGBE_PCIDEVCTRL2_50_100us 0x1
2446#define IXGBE_PCIDEVCTRL2_1_2ms 0x2
2447#define IXGBE_PCIDEVCTRL2_16_32ms 0x5
2448#define IXGBE_PCIDEVCTRL2_65_130ms 0x6
2449#define IXGBE_PCIDEVCTRL2_260_520ms 0x9
2450#define IXGBE_PCIDEVCTRL2_1_2s 0xa
2451#define IXGBE_PCIDEVCTRL2_4_8s 0xd
2452#define IXGBE_PCIDEVCTRL2_17_34s 0xe
2453
2454/* Number of 100 microseconds we wait for PCI Express master disable */
2455#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
2456
2457/* Check whether address is multicast. This is little-endian specific check.*/
2458#define IXGBE_IS_MULTICAST(Address) \
2459 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
2460
2461/* Check whether an address is broadcast. */
2462#define IXGBE_IS_BROADCAST(Address) \
2463 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
2464 (((u8 *)(Address))[1] == ((u8)0xff)))
2465
2466/* RAH */
2467#define IXGBE_RAH_VIND_MASK 0x003C0000
2468#define IXGBE_RAH_VIND_SHIFT 18
2469#define IXGBE_RAH_AV 0x80000000
2470#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
2471
2472/* Header split receive */
2473#define IXGBE_RFCTL_ISCSI_DIS 0x00000001
2474#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
2475#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
2476#define IXGBE_RFCTL_RSC_DIS 0x00000020
2477#define IXGBE_RFCTL_NFSW_DIS 0x00000040
2478#define IXGBE_RFCTL_NFSR_DIS 0x00000080
2479#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
2480#define IXGBE_RFCTL_NFS_VER_SHIFT 8
2481#define IXGBE_RFCTL_NFS_VER_2 0
2482#define IXGBE_RFCTL_NFS_VER_3 1
2483#define IXGBE_RFCTL_NFS_VER_4 2
2484#define IXGBE_RFCTL_IPV6_DIS 0x00000400
2485#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
2486#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
2487#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
2488#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
2489
2490/* Transmit Config masks */
2491#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue */
2492#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */
2493#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
2494/* Enable short packet padding to 64 bytes */
2495#define IXGBE_TX_PAD_ENABLE 0x00000400
2496#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
2497/* This allows for 16K packets + 4k for vlan */
2498#define IXGBE_MAX_FRAME_SZ 0x40040000
2499
2500#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */
2501#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */
2502
2503/* Receive Config masks */
2504#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
2505#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Desc Monitor Bypass */
2506#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Ena specific Rx Queue */
2507#define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc wr-bk flushing */
2508#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* X540 supported only */
2509#define IXGBE_RXDCTL_RLPML_EN 0x00008000
2510#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
2511
2512#define IXGBE_TSAUXC_EN_CLK 0x00000004
2513#define IXGBE_TSAUXC_SYNCLK 0x00000008
2514#define IXGBE_TSAUXC_SDP0_INT 0x00000040
2515#define IXGBE_TSAUXC_EN_TT0 0x00000001
2516#define IXGBE_TSAUXC_EN_TT1 0x00000002
2517#define IXGBE_TSAUXC_ST0 0x00000010
2518#define IXGBE_TSAUXC_DISABLE_SYSTIME 0x80000000
2519
2520#define IXGBE_TSSDP_TS_SDP0_SEL_MASK 0x000000C0
2521#define IXGBE_TSSDP_TS_SDP0_CLK0 0x00000080
2522#define IXGBE_TSSDP_TS_SDP0_EN 0x00000100
2523
2524#define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
2525#define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */
2526
2527#define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
2528#define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
2529#define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00
2530#define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02
2531#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
2532#define IXGBE_TSYNCRXCTL_TYPE_ALL 0x08
2533#define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
2534#define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */
2535#define IXGBE_TSYNCRXCTL_TSIP_UT_EN 0x00800000 /* Rx Timestamp in Packet */
2536#define IXGBE_TSYNCRXCTL_TSIP_UP_MASK 0xFF000000 /* Rx Timestamp UP Mask */
2537
2538#define IXGBE_TSIM_SYS_WRAP 0x00000001
2539#define IXGBE_TSIM_TXTS 0x00000002
2540#define IXGBE_TSIM_TADJ 0x00000080
2541
2542#define IXGBE_TSICR_SYS_WRAP IXGBE_TSIM_SYS_WRAP
2543#define IXGBE_TSICR_TXTS IXGBE_TSIM_TXTS
2544#define IXGBE_TSICR_TADJ IXGBE_TSIM_TADJ
2545
2546#define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF
2547#define IXGBE_RXMTRL_V1_SYNC_MSG 0x00
2548#define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01
2549#define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02
2550#define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03
2551#define IXGBE_RXMTRL_V1_MGMT_MSG 0x04
2552
2553#define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00
2554#define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000
2555#define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100
2556#define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200
2557#define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300
2558#define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800
2559#define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900
2560#define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00
2561#define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00
2562#define IXGBE_RXMTRL_V2_SIGNALLING_MSG 0x0C00
2563#define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00
2564
2565#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
2566#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
2567#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
2568#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
2569#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
2570#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
2571/* Receive Priority Flow Control Enable */
2572#define IXGBE_FCTRL_RPFCE 0x00004000
2573#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
2574#define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */
2575#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */
2576#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
2577#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
2578#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Rx Priority FC bitmap mask */
2579#define IXGBE_MFLCN_RPFCE_SHIFT 4 /* Rx Priority FC bitmap shift */
2580
2581/* Multiple Receive Queue Control */
2582#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
2583#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */
2584#define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */
2585#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
2586#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */
2587#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */
2588#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */
2589#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */
2590#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
2591#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
2592#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */

2593#define IXGBE_MRQC_L3L4TXSWEN 0x00008000 /* Enable L3/L4 Tx switch */

2594#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
2595#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
2596#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
2597#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
2598#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
2599#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
2600#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
2601#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
2602#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
2603#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
2604#define IXGBE_MRQC_MULTIPLE_RSS 0x00002000
2605#define IXGBE_MRQC_L3L4TXSWEN 0x00008000
2606
2607/* Queue Drop Enable */
2608#define IXGBE_QDE_ENABLE 0x00000001
2609#define IXGBE_QDE_HIDE_VLAN 0x00000002
2610#define IXGBE_QDE_IDX_MASK 0x00007F00
2611#define IXGBE_QDE_IDX_SHIFT 8
2612#define IXGBE_QDE_WRITE 0x00010000
2613#define IXGBE_QDE_READ 0x00020000
2614
2615#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
2616#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
2617#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
2618#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
2619#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
2620#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
2621#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
2622#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
2623#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
2624
2625#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000
2626#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
2627#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
2628#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000
2629#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
2630/* Multiple Transmit Queue Command Register */
2631#define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */
2632#define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */
2633#define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */
2634#define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */
2635#define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */
2636#define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA and VT_ENA */
2637#define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
2638
2639/* Receive Descriptor bit definitions */
2640#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
2641#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
2642#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */
2643#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
2644#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
2645#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
2646#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
2647#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
2648#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
2649#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
2650#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
2651#define IXGBE_RXD_STAT_OUTERIPCS 0x100 /* Cloud IP xsum calculated */
2652#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
2653#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
2654#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
2655#define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */
2656#define IXGBE_RXD_STAT_TSIP 0x08000 /* Time Stamp in packet buffer */
2657#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
2658#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
2659#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
2660#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
2661#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
2662#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
2663#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
2664#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
2665#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
2666#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
2667#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
2668#define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */
2669#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
2670#define IXGBE_RXDADV_ERR_OUTERIPER 0x04000000 /* CRC IP Header error */
2671#define IXGBE_RXDADV_ERR_RXE 0x20000000 /* Any MAC Error */
2672#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCEOFe/IPE */
2673#define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */
2674#define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */
2675#define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */
2676#define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */
2677#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
2678#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
2679#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
2680#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
2681#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
2682#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
2683#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
2684#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
2685#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
2686#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
2687#define IXGBE_RXD_PRI_SHIFT 13
2688#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
2689#define IXGBE_RXD_CFI_SHIFT 12
2690
2691#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
2692#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
2693#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */
2694#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */
2695#define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */
2696#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */
2697#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */
2698#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
2699#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */
2700#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
2701#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */
2702#define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE1588 Time Stamp */
2703#define IXGBE_RXDADV_STAT_TSIP 0x00008000 /* Time Stamp in packet buffer */
2704
2705/* PSRTYPE bit definitions */
2706#define IXGBE_PSRTYPE_TCPHDR 0x00000010
2707#define IXGBE_PSRTYPE_UDPHDR 0x00000020
2708#define IXGBE_PSRTYPE_IPV4HDR 0x00000100
2709#define IXGBE_PSRTYPE_IPV6HDR 0x00000200
2710#define IXGBE_PSRTYPE_L2HDR 0x00001000
2711
2712/* SRRCTL bit definitions */
2713#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
2714#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* 64byte resolution (>> 6)
2715 * + at bit 8 offset (<< 8)
2716 * = (<< 2)
2717 */
2718#define IXGBE_SRRCTL_RDMTS_SHIFT 22
2719#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
2720#define IXGBE_SRRCTL_DROP_EN 0x10000000
2721#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
2722#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
2723#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
2724#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
2725#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
2726#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
2727#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
2728#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
2729
2730#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
2731#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
2732
2733#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
2734#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
2735#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
2736#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
2737#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
2738#define IXGBE_RXDADV_RSCCNT_SHIFT 17
2739#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
2740#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
2741#define IXGBE_RXDADV_SPH 0x8000
2742
2743/* RSS Hash results */
2744#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
2745#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
2746#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
2747#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
2748#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
2749#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
2750#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
2751#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
2752#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
2753#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
2754
2755/* RSS Packet Types as indicated in the receive descriptor. */
2756#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
2757#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
2758#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
2759#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
2760#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
2761#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
2762#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
2763#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
2764#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */

2765#define IXGBE_RXDADV_PKTTYPE_GENEVE 0x00000800 /* GENEVE hdr present */

2766#define IXGBE_RXDADV_PKTTYPE_VXLAN 0x00000800 /* VXLAN hdr present */
2767#define IXGBE_RXDADV_PKTTYPE_TUNNEL 0x00010000 /* Tunnel type */
2768#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
2769#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
2770#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
2771#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
2772#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
2773#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
2774
2775/* Security Processing bit Indication */
2776#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000
2777#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
2778#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
2779#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
2780#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
2781
2782/* Masks to determine if packets should be dropped due to frame errors */
2783#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
2784 IXGBE_RXD_ERR_CE | \
2785 IXGBE_RXD_ERR_LE | \
2786 IXGBE_RXD_ERR_PE | \
2787 IXGBE_RXD_ERR_OSE | \
2788 IXGBE_RXD_ERR_USE)
2789
2790#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
2791 IXGBE_RXDADV_ERR_CE | \
2792 IXGBE_RXDADV_ERR_LE | \
2793 IXGBE_RXDADV_ERR_PE | \
2794 IXGBE_RXDADV_ERR_OSE | \
2795 IXGBE_RXDADV_ERR_USE)
2796
2797#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK_82599 IXGBE_RXDADV_ERR_RXE
2798
2799/* Multicast bit mask */
2800#define IXGBE_MCSTCTRL_MFE 0x4
2801
2802/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2803#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
2804#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
2805#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
2806
2807/* Vlan-specific macros */
2808#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
2809#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
2810#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
2811#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2812
2813/* SR-IOV specific macros */
2814#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4)
2815#define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4))
2816#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600))
2817#define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4))
2818/* Translated register #defines */
2819#define IXGBE_PVFCTRL(P) (0x00300 + (4 * (P)))
2820#define IXGBE_PVFSTATUS(P) (0x00008 + (0 * (P)))
2821#define IXGBE_PVFLINKS(P) (0x042A4 + (0 * (P)))
2822#define IXGBE_PVFRTIMER(P) (0x00048 + (0 * (P)))
2823#define IXGBE_PVFMAILBOX(P) (0x04C00 + (4 * (P)))
2824#define IXGBE_PVFRXMEMWRAP(P) (0x03190 + (0 * (P)))
2825#define IXGBE_PVTEICR(P) (0x00B00 + (4 * (P)))
2826#define IXGBE_PVTEICS(P) (0x00C00 + (4 * (P)))
2827#define IXGBE_PVTEIMS(P) (0x00D00 + (4 * (P)))
2828#define IXGBE_PVTEIMC(P) (0x00E00 + (4 * (P)))
2829#define IXGBE_PVTEIAC(P) (0x00F00 + (4 * (P)))
2830#define IXGBE_PVTEIAM(P) (0x04D00 + (4 * (P)))
2831#define IXGBE_PVTEITR(P) (((P) < 24) ? (0x00820 + ((P) * 4)) : \
2832 (0x012300 + (((P) - 24) * 4)))
2833#define IXGBE_PVTIVAR(P) (0x12500 + (4 * (P)))
2834#define IXGBE_PVTIVAR_MISC(P) (0x04E00 + (4 * (P)))
2835#define IXGBE_PVTRSCINT(P) (0x12000 + (4 * (P)))
2836#define IXGBE_VFPBACL(P) (0x110C8 + (4 * (P)))
2837#define IXGBE_PVFRDBAL(P) ((P < 64) ? (0x01000 + (0x40 * (P))) \
2838 : (0x0D000 + (0x40 * ((P) - 64))))
2839#define IXGBE_PVFRDBAH(P) ((P < 64) ? (0x01004 + (0x40 * (P))) \
2840 : (0x0D004 + (0x40 * ((P) - 64))))
2841#define IXGBE_PVFRDLEN(P) ((P < 64) ? (0x01008 + (0x40 * (P))) \
2842 : (0x0D008 + (0x40 * ((P) - 64))))
2843#define IXGBE_PVFRDH(P) ((P < 64) ? (0x01010 + (0x40 * (P))) \
2844 : (0x0D010 + (0x40 * ((P) - 64))))
2845#define IXGBE_PVFRDT(P) ((P < 64) ? (0x01018 + (0x40 * (P))) \
2846 : (0x0D018 + (0x40 * ((P) - 64))))
2847#define IXGBE_PVFRXDCTL(P) ((P < 64) ? (0x01028 + (0x40 * (P))) \
2848 : (0x0D028 + (0x40 * ((P) - 64))))
2849#define IXGBE_PVFSRRCTL(P) ((P < 64) ? (0x01014 + (0x40 * (P))) \
2850 : (0x0D014 + (0x40 * ((P) - 64))))
2851#define IXGBE_PVFPSRTYPE(P) (0x0EA00 + (4 * (P)))
2852#define IXGBE_PVFTDBAL(P) (0x06000 + (0x40 * (P)))
2853#define IXGBE_PVFTDBAH(P) (0x06004 + (0x40 * (P)))

~~2753~~#define IXGBE_PVFTTDLEN(P) (0x06008 + (0x40 * (P)))

2854#define IXGBE_PVFTDLEN(P) (0x06008 + (0x40 * (P)))

2855#define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P)))
2856#define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P)))
2857#define IXGBE_PVFTXDCTL(P) (0x06028 + (0x40 * (P)))
2858#define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P)))
2859#define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P)))
2860#define IXGBE_PVFDCA_RXCTRL(P) (((P) < 64) ? (0x0100C + (0x40 * (P))) \
2861 : (0x0D00C + (0x40 * ((P) - 64))))
2862#define IXGBE_PVFDCA_TXCTRL(P) (0x0600C + (0x40 * (P)))
2863#define IXGBE_PVFGPRC(x) (0x0101C + (0x40 * (x)))
2864#define IXGBE_PVFGPTC(x) (0x08300 + (0x04 * (x)))
2865#define IXGBE_PVFGORC_LSB(x) (0x01020 + (0x40 * (x)))
2866#define IXGBE_PVFGORC_MSB(x) (0x0D020 + (0x40 * (x)))
2867#define IXGBE_PVFGOTC_LSB(x) (0x08400 + (0x08 * (x)))
2868#define IXGBE_PVFGOTC_MSB(x) (0x08404 + (0x08 * (x)))
2869#define IXGBE_PVFMPRC(x) (0x0D01C + (0x40 * (x)))
2870
2871#define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \
2872 (IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))
2873#define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \
2874 (IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))
2875
2876#define IXGBE_PVFTDHn(q_per_pool, vf_number, vf_q_index) \
2877 (IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))
2878#define IXGBE_PVFTDTn(q_per_pool, vf_number, vf_q_index) \
2879 (IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))
2880
2881/* Little Endian defines */
2882#ifndef __le16
2883#define __le16 u16
2884#endif
2885#ifndef __le32
2886#define __le32 u32
2887#endif
2888#ifndef __le64
2889#define __le64 u64
2890
2891#endif
2892#ifndef __be16
2893/* Big Endian defines */
2894#define __be16 u16
2895#define __be32 u32
2896#define __be64 u64
2897
2898#endif
2899enum ixgbe_fdir_pballoc_type {
2900 IXGBE_FDIR_PBALLOC_NONE = 0,
2901 IXGBE_FDIR_PBALLOC_64K = 1,
2902 IXGBE_FDIR_PBALLOC_128K = 2,
2903 IXGBE_FDIR_PBALLOC_256K = 3,
2904};
2905
2906/* Flow Director register values */
2907#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001
2908#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002
2909#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003
2910#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008
2911#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010
2912#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020
2913#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
2914#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
2915#define IXGBE_FDIRCTRL_DROP_Q_MASK 0x00007F00
2916#define IXGBE_FDIRCTRL_FLEX_SHIFT 16
2917#define IXGBE_FDIRCTRL_DROP_NO_MATCH 0x00008000
2918#define IXGBE_FDIRCTRL_FILTERMODE_SHIFT 21
2919#define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN 0x0001 /* bit 23:21, 001b */
2920#define IXGBE_FDIRCTRL_FILTERMODE_CLOUD 0x0002 /* bit 23:21, 010b */
2921#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
2922#define IXGBE_FDIRCTRL_FILTERMODE_MASK 0x00E00000
2923#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
2924#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
2925#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28
2926
2927#define IXGBE_FDIRTCPM_DPORTM_SHIFT 16
2928#define IXGBE_FDIRUDPM_DPORTM_SHIFT 16
2929#define IXGBE_FDIRIP6M_DIPM_SHIFT 16
2930#define IXGBE_FDIRM_VLANID 0x00000001
2931#define IXGBE_FDIRM_VLANP 0x00000002
2932#define IXGBE_FDIRM_POOL 0x00000004
2933#define IXGBE_FDIRM_L4P 0x00000008
2934#define IXGBE_FDIRM_FLEX 0x00000010
2935#define IXGBE_FDIRM_DIPv6 0x00000020
2936#define IXGBE_FDIRM_L3P 0x00000040
2937
2938#define IXGBE_FDIRIP6M_INNER_MAC 0x03F0 /* bit 9:4 */
2939#define IXGBE_FDIRIP6M_TUNNEL_TYPE 0x0800 /* bit 11 */
2940#define IXGBE_FDIRIP6M_TNI_VNI 0xF000 /* bit 15:12 */
2941#define IXGBE_FDIRIP6M_TNI_VNI_24 0x1000 /* bit 12 */
2942#define IXGBE_FDIRIP6M_ALWAYS_MASK 0x040F /* bit 10, 3:0 */
2943
2944#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF
2945#define IXGBE_FDIRFREE_FREE_SHIFT 0
2946#define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000
2947#define IXGBE_FDIRFREE_COLL_SHIFT 16
2948#define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F
2949#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0
2950#define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000
2951#define IXGBE_FDIRLEN_MAXHASH_SHIFT 16
2952#define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF
2953#define IXGBE_FDIRUSTAT_ADD_SHIFT 0
2954#define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000
2955#define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16
2956#define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF
2957#define IXGBE_FDIRFSTAT_FADD_SHIFT 0
2958#define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00
2959#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8
2960#define IXGBE_FDIRPORT_DESTINATION_SHIFT 16
2961#define IXGBE_FDIRVLAN_FLEX_SHIFT 16
2962#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15
2963#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16
2964
2965#define IXGBE_FDIRCMD_CMD_MASK 0x00000003
2966#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001
2967#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002
2968#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003
2969#define IXGBE_FDIRCMD_FILTER_VALID 0x00000004
2970#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008
2971#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010
2972#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020
2973#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040
2974#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
2975#define IXGBE_FDIRCMD_IPV6 0x00000080
2976#define IXGBE_FDIRCMD_CLEARHT 0x00000100
2977#define IXGBE_FDIRCMD_DROP 0x00000200
2978#define IXGBE_FDIRCMD_INT 0x00000400
2979#define IXGBE_FDIRCMD_LAST 0x00000800
2980#define IXGBE_FDIRCMD_COLLISION 0x00001000
2981#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
2982#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5
2983#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
2984#define IXGBE_FDIRCMD_TUNNEL_FILTER_SHIFT 23
2985#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
2986#define IXGBE_FDIR_INIT_DONE_POLL 10
2987#define IXGBE_FDIRCMD_CMD_POLL 10
2988#define IXGBE_FDIRCMD_TUNNEL_FILTER 0x00800000
2989#define IXGBE_FDIR_DROP_QUEUE 127
2990
2991
2992/* Manageablility Host Interface defines */
2993#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */
2994#define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
2995#define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */
2996#define IXGBE_HI_FLASH_ERASE_TIMEOUT 1000 /* Process Erase command limit */
2997#define IXGBE_HI_FLASH_UPDATE_TIMEOUT 5000 /* Process Update command limit */
2998#define IXGBE_HI_FLASH_APPLY_TIMEOUT 0 /* Process Apply command limit */
2999#define IXGBE_HI_PHY_MGMT_REQ_TIMEOUT 2000 /* Wait up to 2 seconds */
3000
3001/* CEM Support */
3002#define FW_CEM_HDR_LEN 0x4
3003#define FW_CEM_CMD_DRIVER_INFO 0xDD
3004#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5
3005#define FW_CEM_CMD_RESERVED 0X0
3006#define FW_CEM_UNUSED_VER 0x0
3007#define FW_CEM_MAX_RETRIES 3
3008#define FW_CEM_RESP_STATUS_SUCCESS 0x1

3009#define FW_CEM_DRIVER_VERSION_SIZE 39 /* +9 would send 48 bytes to fw */

3010#define FW_READ_SHADOW_RAM_CMD 0x31
3011#define FW_READ_SHADOW_RAM_LEN 0x6
3012#define FW_WRITE_SHADOW_RAM_CMD 0x33
3013#define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */
3014#define FW_SHADOW_RAM_DUMP_CMD 0x36
3015#define FW_SHADOW_RAM_DUMP_LEN 0
3016#define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
3017#define FW_NVM_DATA_OFFSET 3
3018#define FW_MAX_READ_BUFFER_SIZE 1024
3019#define FW_DISABLE_RXEN_CMD 0xDE
3020#define FW_DISABLE_RXEN_LEN 0x1
3021#define FW_PHY_MGMT_REQ_CMD 0x20

3022#define FW_PHY_TOKEN_REQ_CMD 0xA
3023#define FW_PHY_TOKEN_REQ_LEN 2
3024#define FW_PHY_TOKEN_REQ 0
3025#define FW_PHY_TOKEN_REL 1
3026#define FW_PHY_TOKEN_OK 1
3027#define FW_PHY_TOKEN_RETRY 0x80
3028#define FW_PHY_TOKEN_DELAY 5 /* milliseconds */
3029#define FW_PHY_TOKEN_WAIT 5 /* seconds */
3030#define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY)

3031#define FW_INT_PHY_REQ_CMD 0xB
3032#define FW_INT_PHY_REQ_LEN 10
3033#define FW_INT_PHY_REQ_READ 0
3034#define FW_INT_PHY_REQ_WRITE 1

3035#define FW_PHY_ACT_REQ_CMD 5
3036#define FW_PHY_ACT_DATA_COUNT 4
3037#define FW_PHY_ACT_REQ_LEN (4 + 4 * FW_PHY_ACT_DATA_COUNT)
3038#define FW_PHY_ACT_INIT_PHY 1
3039#define FW_PHY_ACT_SETUP_LINK 2
3040#define FW_PHY_ACT_LINK_SPEED_10 (1u << 0)
3041#define FW_PHY_ACT_LINK_SPEED_100 (1u << 1)
3042#define FW_PHY_ACT_LINK_SPEED_1G (1u << 2)
3043#define FW_PHY_ACT_LINK_SPEED_2_5G (1u << 3)
3044#define FW_PHY_ACT_LINK_SPEED_5G (1u << 4)
3045#define FW_PHY_ACT_LINK_SPEED_10G (1u << 5)
3046#define FW_PHY_ACT_LINK_SPEED_20G (1u << 6)
3047#define FW_PHY_ACT_LINK_SPEED_25G (1u << 7)
3048#define FW_PHY_ACT_LINK_SPEED_40G (1u << 8)
3049#define FW_PHY_ACT_LINK_SPEED_50G (1u << 9)
3050#define FW_PHY_ACT_LINK_SPEED_100G (1u << 10)
3051#define FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT 16
3052#define FW_PHY_ACT_SETUP_LINK_PAUSE_MASK (3u << \
3053 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT)
3054#define FW_PHY_ACT_SETUP_LINK_PAUSE_NONE 0u
3055#define FW_PHY_ACT_SETUP_LINK_PAUSE_TX 1u
3056#define FW_PHY_ACT_SETUP_LINK_PAUSE_RX 2u
3057#define FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 3u
3058#define FW_PHY_ACT_SETUP_LINK_LP (1u << 18)
3059#define FW_PHY_ACT_SETUP_LINK_HP (1u << 19)
3060#define FW_PHY_ACT_SETUP_LINK_EEE (1u << 20)
3061#define FW_PHY_ACT_SETUP_LINK_AN (1u << 22)
3062#define FW_PHY_ACT_SETUP_LINK_RSP_DOWN (1u << 0)
3063#define FW_PHY_ACT_GET_LINK_INFO 3
3064#define FW_PHY_ACT_GET_LINK_INFO_EEE (1u << 19)
3065#define FW_PHY_ACT_GET_LINK_INFO_FC_TX (1u << 20)
3066#define FW_PHY_ACT_GET_LINK_INFO_FC_RX (1u << 21)
3067#define FW_PHY_ACT_GET_LINK_INFO_POWER (1u << 22)
3068#define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE (1u << 24)
3069#define FW_PHY_ACT_GET_LINK_INFO_TEMP (1u << 25)
3070#define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX (1u << 28)
3071#define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX (1u << 29)
3072#define FW_PHY_ACT_FORCE_LINK_DOWN 4
3073#define FW_PHY_ACT_FORCE_LINK_DOWN_OFF (1u << 0)
3074#define FW_PHY_ACT_PHY_SW_RESET 5
3075#define FW_PHY_ACT_PHY_HW_RESET 6
3076#define FW_PHY_ACT_GET_PHY_INFO 7
3077#define FW_PHY_ACT_UD_2 0x1002
3078#define FW_PHY_ACT_UD_2_10G_KR_EEE (1u << 6)
3079#define FW_PHY_ACT_UD_2_10G_KX4_EEE (1u << 5)
3080#define FW_PHY_ACT_UD_2_1G_KX_EEE (1u << 4)
3081#define FW_PHY_ACT_UD_2_10G_T_EEE (1u << 3)
3082#define FW_PHY_ACT_UD_2_1G_T_EEE (1u << 2)
3083#define FW_PHY_ACT_UD_2_100M_TX_EEE (1u << 1)
3084#define FW_PHY_ACT_RETRIES 50
3085#define FW_PHY_INFO_SPEED_MASK 0xFFFu
3086#define FW_PHY_INFO_ID_HI_MASK 0xFFFF0000u
3087#define FW_PHY_INFO_ID_LO_MASK 0x0000FFFFu

3088
3089/* Host Interface Command Structures */
3090

3091#pragma pack(push, 1)
3092

3093struct ixgbe_hic_hdr {
3094 u8 cmd;
3095 u8 buf_len;
3096 union {
3097 u8 cmd_resv;
3098 u8 ret_status;
3099 } cmd_or_resp;
3100 u8 checksum;
3101};
3102
3103struct ixgbe_hic_hdr2_req {
3104 u8 cmd;
3105 u8 buf_lenh;
3106 u8 buf_lenl;
3107 u8 checksum;
3108};
3109
3110struct ixgbe_hic_hdr2_rsp {
3111 u8 cmd;
3112 u8 buf_lenl;
3113 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */
3114 u8 checksum;
3115};
3116
3117union ixgbe_hic_hdr2 {
3118 struct ixgbe_hic_hdr2_req req;
3119 struct ixgbe_hic_hdr2_rsp rsp;
3120};
3121
3122struct ixgbe_hic_drv_info {
3123 struct ixgbe_hic_hdr hdr;
3124 u8 port_num;
3125 u8 ver_sub;
3126 u8 ver_build;
3127 u8 ver_min;
3128 u8 ver_maj;
3129 u8 pad; /* end spacing to ensure length is mult. of dword */
3130 u16 pad2; /* end spacing to ensure length is mult. of dword2 */
3131};
3132

3133struct ixgbe_hic_drv_info2 {
3134 struct ixgbe_hic_hdr hdr;
3135 u8 port_num;
3136 u8 ver_sub;
3137 u8 ver_build;
3138 u8 ver_min;
3139 u8 ver_maj;
3140 char driver_string[FW_CEM_DRIVER_VERSION_SIZE];
3141};
3142

3143/* These need to be dword aligned */
3144struct ixgbe_hic_read_shadow_ram {
3145 union ixgbe_hic_hdr2 hdr;
3146 u32 address;
3147 u16 length;
3148 u16 pad2;
3149 u16 data;
3150 u16 pad3;
3151};
3152
3153struct ixgbe_hic_write_shadow_ram {
3154 union ixgbe_hic_hdr2 hdr;
3155 u32 address;
3156 u16 length;
3157 u16 pad2;
3158 u16 data;
3159 u16 pad3;
3160};
3161
3162struct ixgbe_hic_disable_rxen {
3163 struct ixgbe_hic_hdr hdr;
3164 u8 port_number;
3165 u8 pad2;
3166 u16 pad3;
3167};
3168

3169struct ixgbe_hic_phy_token_req {
3170 struct ixgbe_hic_hdr hdr;
3171 u8 port_number;
3172 u8 command_type;
3173 u16 pad;
3174};
3175

3176struct ixgbe_hic_internal_phy_req {
3177 struct ixgbe_hic_hdr hdr;
3178 u8 port_number;
3179 u8 command_type;

~~2997~~ u16 address;

3180 __be16 address;

3181 u16 rsv1;

~~2999~~ u32 write_data;

3182 __be32 write_data;

3183 u16 pad;
3184};
3185
3186struct ixgbe_hic_internal_phy_resp {
3187 struct ixgbe_hic_hdr hdr;

~~3005~~ u32 read_data;

3188 __be32 read_data;

3189};
3190

3191struct ixgbe_hic_phy_activity_req {
3192 struct ixgbe_hic_hdr hdr;
3193 u8 port_number;
3194 u8 pad;
3195 __le16 activity_id;
3196 __be32 data[FW_PHY_ACT_DATA_COUNT];
3197};

3198

3199struct ixgbe_hic_phy_activity_resp {
3200 struct ixgbe_hic_hdr hdr;
3201 __be32 data[FW_PHY_ACT_DATA_COUNT];
3202};
3203
3204#pragma pack(pop)
3205

3206/* Transmit Descriptor - Legacy */
3207struct ixgbe_legacy_tx_desc {
3208 u64 buffer_addr; /* Address of the descriptor's data buffer */
3209 union {
3210 __le32 data;
3211 struct {
3212 __le16 length; /* Data buffer length */
3213 u8 cso; /* Checksum offset */
3214 u8 cmd; /* Descriptor control */
3215 } flags;
3216 } lower;
3217 union {
3218 __le32 data;
3219 struct {
3220 u8 status; /* Descriptor status */
3221 u8 css; /* Checksum start */
3222 __le16 vlan;
3223 } fields;
3224 } upper;
3225};
3226
3227/* Transmit Descriptor - Advanced */
3228union ixgbe_adv_tx_desc {
3229 struct {
3230 __le64 buffer_addr; /* Address of descriptor's data buf */
3231 __le32 cmd_type_len;
3232 __le32 olinfo_status;
3233 } read;
3234 struct {
3235 __le64 rsvd; /* Reserved */
3236 __le32 nxtseq_seed;
3237 __le32 status;
3238 } wb;
3239};
3240
3241/* Receive Descriptor - Legacy */
3242struct ixgbe_legacy_rx_desc {
3243 __le64 buffer_addr; /* Address of the descriptor's data buffer */
3244 __le16 length; /* Length of data DMAed into data buffer */
3245 __le16 csum; /* Packet checksum */
3246 u8 status; /* Descriptor status */
3247 u8 errors; /* Descriptor Errors */
3248 __le16 vlan;
3249};
3250
3251/* Receive Descriptor - Advanced */
3252union ixgbe_adv_rx_desc {
3253 struct {
3254 __le64 pkt_addr; /* Packet buffer address */
3255 __le64 hdr_addr; /* Header buffer address */
3256 } read;
3257 struct {
3258 struct {
3259 union {
3260 __le32 data;
3261 struct {
3262 __le16 pkt_info; /* RSS, Pkt type */
3263 __le16 hdr_info; /* Splithdr, hdrlen */
3264 } hs_rss;
3265 } lo_dword;
3266 union {
3267 __le32 rss; /* RSS Hash */
3268 struct {
3269 __le16 ip_id; /* IP id */
3270 __le16 csum; /* Packet Checksum */
3271 } csum_ip;
3272 } hi_dword;
3273 } lower;
3274 struct {
3275 __le32 status_error; /* ext status/error */
3276 __le16 length; /* Packet length */
3277 __le16 vlan; /* VLAN tag */
3278 } upper;
3279 } wb; /* writeback */
3280};
3281
3282/* Context descriptors */
3283struct ixgbe_adv_tx_context_desc {
3284 __le32 vlan_macip_lens;
3285 __le32 seqnum_seed;
3286 __le32 type_tucmd_mlhl;
3287 __le32 mss_l4len_idx;
3288};
3289
3290/* Adv Transmit Descriptor Config Masks */
3291#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */
3292#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */
3293#define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 time stamp */
3294#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */
3295#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */
3296#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
3297#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Adv Context Desc */
3298#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Adv Data Descriptor */
3299#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
3300#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
3301#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
3302#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
3303#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext 1=Adv */
3304#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
3305#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
3306#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
3307#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */
3308#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
3309#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
3310#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */
3311#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
3312#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
3313 IXGBE_ADVTXD_POPTS_SHIFT)
3314#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
3315 IXGBE_ADVTXD_POPTS_SHIFT)
3316#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
3317#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
3318#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
3319/* 1st&Last TSO-full iSCSI PDU */
3320#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800
3321#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
3322#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
3323#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
3324#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
3325#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
3326#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
3327#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
3328#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
3329#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */

3330#define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* RSV L4 Packet TYPE */

3331#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* req Markers and CRC */
3332#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
3333#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
3334#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
3335#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */
3336#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */
3337#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */
3338#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */
3339#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation End */
3340#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation Start */
3341#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */
3342#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */
3343#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */
3344#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */
3345#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
3346#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
3347
3348#define IXGBE_ADVTXD_OUTER_IPLEN 16 /* Adv ctxt OUTERIPLEN shift */
3349#define IXGBE_ADVTXD_TUNNEL_LEN 24 /* Adv ctxt TUNNELLEN shift */
3350#define IXGBE_ADVTXD_TUNNEL_TYPE_SHIFT 16 /* Adv Tx Desc Tunnel Type shift */
3351#define IXGBE_ADVTXD_OUTERIPCS_SHIFT 17 /* Adv Tx Desc OUTERIPCS Shift */
3352#define IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE 1 /* Adv Tx Desc Tunnel Type NVGRE */

~~3155~~

3353/* Adv Tx Desc OUTERIPCS Shift for X550EM_a */
3354#define IXGBE_ADVTXD_OUTERIPCS_SHIFT_X550EM_a 26

3355/* Autonegotiation advertised speeds */
3356typedef u32 ixgbe_autoneg_advertised;
3357/* Link speed */
3358typedef u32 ixgbe_link_speed;
3359#define IXGBE_LINK_SPEED_UNKNOWN 0

3360#define IXGBE_LINK_SPEED_10_FULL 0x0002

3361#define IXGBE_LINK_SPEED_100_FULL 0x0008
3362#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
3363#define IXGBE_LINK_SPEED_2_5GB_FULL 0x0400
3364#define IXGBE_LINK_SPEED_5GB_FULL 0x0800
3365#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
3366#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
3367 IXGBE_LINK_SPEED_10GB_FULL)
3368#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
3369 IXGBE_LINK_SPEED_1GB_FULL | \
3370 IXGBE_LINK_SPEED_10GB_FULL)
3371
3372/* Physical layer type */

~~3173~~typedef u32 ixgbe_physical_layer;

3373typedef u64 ixgbe_physical_layer;

3374#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0

~~3175~~#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
~~3176~~#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
~~3177~~#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004
~~3178~~#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
~~3179~~#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
~~3180~~#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
~~3181~~#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
~~3182~~#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
~~3183~~#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
~~3184~~#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
~~3185~~#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
~~3186~~#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
~~3187~~#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
~~3188~~#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
~~3189~~#define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x4000

3375#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x00001
3376#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x00002
3377#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x00004
3378#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x00008
3379#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x00010
3380#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x00020
3381#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x00040
3382#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x00080
3383#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x00100
3384#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x00200
3385#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x00400
3386#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x00800
3387#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x01000
3388#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x02000
3389#define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x04000
3390#define IXGBE_PHYSICAL_LAYER_10BASE_T 0x08000
3391#define IXGBE_PHYSICAL_LAYER_2500BASE_KX 0x10000

3392
3393/* Flow Control Data Sheet defined values
3394 * Calculation and defines taken from 802.1bb Annex O
3395 */
3396
3397/* BitTimes (BT) conversion */
3398#define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
3399#define IXGBE_B2BT(BT) (BT * 8)
3400
3401/* Calculate Delay to respond to PFC */
3402#define IXGBE_PFC_D 672
3403
3404/* Calculate Cable Delay */
3405#define IXGBE_CABLE_DC 5556 /* Delay Copper */
3406#define IXGBE_CABLE_DO 5000 /* Delay Optical */
3407
3408/* Calculate Interface Delay X540 */
3409#define IXGBE_PHY_DC 25600 /* Delay 10G BASET */
3410#define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */
3411#define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */
3412
3413#define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)
3414
3415/* Calculate Interface Delay 82598, 82599 */
3416#define IXGBE_PHY_D 12800
3417#define IXGBE_MAC_D 4096
3418#define IXGBE_XAUI_D (2 * 1024)
3419
3420#define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)
3421
3422/* Calculate Delay incurred from higher layer */
3423#define IXGBE_HD 6144
3424
3425/* Calculate PCI Bus delay for low thresholds */
3426#define IXGBE_PCI_DELAY 10000
3427
3428/* Calculate X540 delay value in bit times */
3429#define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
3430 ((36 * \
3431 (IXGBE_B2BT(_max_frame_link) + \
3432 IXGBE_PFC_D + \
3433 (2 * IXGBE_CABLE_DC) + \
3434 (2 * IXGBE_ID_X540) + \
3435 IXGBE_HD) / 25 + 1) + \
3436 2 * IXGBE_B2BT(_max_frame_tc))
3437
3438/* Calculate 82599, 82598 delay value in bit times */
3439#define IXGBE_DV(_max_frame_link, _max_frame_tc) \
3440 ((36 * \
3441 (IXGBE_B2BT(_max_frame_link) + \
3442 IXGBE_PFC_D + \
3443 (2 * IXGBE_CABLE_DC) + \
3444 (2 * IXGBE_ID) + \
3445 IXGBE_HD) / 25 + 1) + \
3446 2 * IXGBE_B2BT(_max_frame_tc))
3447
3448/* Calculate low threshold delay values */
3449#define IXGBE_LOW_DV_X540(_max_frame_tc) \
3450 (2 * IXGBE_B2BT(_max_frame_tc) + \
3451 (36 * IXGBE_PCI_DELAY / 25) + 1)
3452#define IXGBE_LOW_DV(_max_frame_tc) \
3453 (2 * IXGBE_LOW_DV_X540(_max_frame_tc))
3454
3455/* Software ATR hash keys */
3456#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
3457#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
3458
3459/* Software ATR input stream values and masks */
3460#define IXGBE_ATR_HASH_MASK 0x7fff
3461#define IXGBE_ATR_L4TYPE_MASK 0x3
3462#define IXGBE_ATR_L4TYPE_UDP 0x1
3463#define IXGBE_ATR_L4TYPE_TCP 0x2
3464#define IXGBE_ATR_L4TYPE_SCTP 0x3
3465#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
3466#define IXGBE_ATR_L4TYPE_TUNNEL_MASK 0x10
3467enum ixgbe_atr_flow_type {
3468 IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
3469 IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
3470 IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2,
3471 IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
3472 IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4,
3473 IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
3474 IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
3475 IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
3476 IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4 = 0x10,
3477 IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4 = 0x11,
3478 IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4 = 0x12,
3479 IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4 = 0x13,
3480 IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6 = 0x14,
3481 IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6 = 0x15,
3482 IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6 = 0x16,
3483 IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6 = 0x17,
3484};
3485
3486/* Flow Director ATR input struct. */
3487union ixgbe_atr_input {
3488 /*
3489 * Byte layout in order, all values with MSB first:
3490 *
3491 * vm_pool - 1 byte
3492 * flow_type - 1 byte
3493 * vlan_id - 2 bytes
3494 * src_ip - 16 bytes
3495 * inner_mac - 6 bytes
3496 * cloud_mode - 2 bytes
3497 * tni_vni - 4 bytes
3498 * dst_ip - 16 bytes
3499 * src_port - 2 bytes
3500 * dst_port - 2 bytes
3501 * flex_bytes - 2 bytes
3502 * bkt_hash - 2 bytes
3503 */
3504 struct {
3505 u8 vm_pool;
3506 u8 flow_type;
3507 __be16 vlan_id;
3508 __be32 dst_ip[4];
3509 __be32 src_ip[4];
3510 u8 inner_mac[6];
3511 __be16 tunnel_type;
3512 __be32 tni_vni;
3513 __be16 src_port;
3514 __be16 dst_port;
3515 __be16 flex_bytes;
3516 __be16 bkt_hash;
3517 } formatted;
3518 __be32 dword_stream[14];
3519};
3520
3521/* Flow Director compressed ATR hash input struct */
3522union ixgbe_atr_hash_dword {
3523 struct {
3524 u8 vm_pool;
3525 u8 flow_type;
3526 __be16 vlan_id;
3527 } formatted;
3528 __be32 ip;
3529 struct {
3530 __be16 src;
3531 __be16 dst;
3532 } port;
3533 __be16 flex_bytes;
3534 __be32 dword;
3535};
3536
3537
3538#define IXGBE_MVALS_INIT(m) \
3539 IXGBE_CAT(EEC, m), \
3540 IXGBE_CAT(FLA, m), \
3541 IXGBE_CAT(GRC, m), \
3542 IXGBE_CAT(SRAMREL, m), \
3543 IXGBE_CAT(FACTPS, m), \
3544 IXGBE_CAT(SWSM, m), \
3545 IXGBE_CAT(SWFW_SYNC, m), \
3546 IXGBE_CAT(FWSM, m), \
3547 IXGBE_CAT(SDP0_GPIEN, m), \
3548 IXGBE_CAT(SDP1_GPIEN, m), \
3549 IXGBE_CAT(SDP2_GPIEN, m), \
3550 IXGBE_CAT(EICR_GPI_SDP0, m), \
3551 IXGBE_CAT(EICR_GPI_SDP1, m), \
3552 IXGBE_CAT(EICR_GPI_SDP2, m), \
3553 IXGBE_CAT(CIAA, m), \
3554 IXGBE_CAT(CIAD, m), \
3555 IXGBE_CAT(I2C_CLK_IN, m), \
3556 IXGBE_CAT(I2C_CLK_OUT, m), \
3557 IXGBE_CAT(I2C_DATA_IN, m), \
3558 IXGBE_CAT(I2C_DATA_OUT, m), \
3559 IXGBE_CAT(I2C_DATA_OE_N_EN, m), \
3560 IXGBE_CAT(I2C_BB_EN, m), \
3561 IXGBE_CAT(I2C_CLK_OE_N_EN, m), \
3562 IXGBE_CAT(I2CCTL, m)
3563
3564enum ixgbe_mvals {
3565 IXGBE_MVALS_INIT(_IDX),
3566 IXGBE_MVALS_IDX_LIMIT
3567};
3568
3569/*
3570 * Unavailable: The FCoE Boot Option ROM is not present in the flash.
3571 * Disabled: Present; boot order is not set for any targets on the port.
3572 * Enabled: Present; boot order is set for at least one target on the port.
3573 */
3574enum ixgbe_fcoe_boot_status {
3575 ixgbe_fcoe_bootstatus_disabled = 0,
3576 ixgbe_fcoe_bootstatus_enabled = 1,
3577 ixgbe_fcoe_bootstatus_unavailable = 0xFFFF
3578};
3579
3580enum ixgbe_eeprom_type {
3581 ixgbe_eeprom_uninitialized = 0,
3582 ixgbe_eeprom_spi,
3583 ixgbe_flash,
3584 ixgbe_eeprom_none /* No NVM support */
3585};
3586
3587enum ixgbe_mac_type {
3588 ixgbe_mac_unknown = 0,
3589 ixgbe_mac_82598EB,
3590 ixgbe_mac_82599EB,
3591 ixgbe_mac_82599_vf,
3592 ixgbe_mac_X540,
3593 ixgbe_mac_X540_vf,
3594 ixgbe_mac_X550,
3595 ixgbe_mac_X550EM_x,

3596 ixgbe_mac_X550EM_a,

3597 ixgbe_mac_X550_vf,
3598 ixgbe_mac_X550EM_x_vf,

3599 ixgbe_mac_X550EM_a_vf,

3600 ixgbe_num_macs
3601};
3602
3603enum ixgbe_phy_type {
3604 ixgbe_phy_unknown = 0,
3605 ixgbe_phy_none,
3606 ixgbe_phy_tn,
3607 ixgbe_phy_aq,
3608 ixgbe_phy_x550em_kr,
3609 ixgbe_phy_x550em_kx4,

3610 ixgbe_phy_x550em_xfi,

3611 ixgbe_phy_x550em_ext_t,

3612 ixgbe_phy_ext_1g_t,

3613 ixgbe_phy_cu_unknown,
3614 ixgbe_phy_qt,
3615 ixgbe_phy_xaui,
3616 ixgbe_phy_nl,
3617 ixgbe_phy_sfp_passive_tyco,
3618 ixgbe_phy_sfp_passive_unknown,
3619 ixgbe_phy_sfp_active_unknown,
3620 ixgbe_phy_sfp_avago,
3621 ixgbe_phy_sfp_ftl,
3622 ixgbe_phy_sfp_ftl_active,
3623 ixgbe_phy_sfp_unknown,
3624 ixgbe_phy_sfp_intel,
3625 ixgbe_phy_qsfp_passive_unknown,
3626 ixgbe_phy_qsfp_active_unknown,
3627 ixgbe_phy_qsfp_intel,
3628 ixgbe_phy_qsfp_unknown,
3629 ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/

3630 ixgbe_phy_sgmii,
3631 ixgbe_phy_fw,

3632 ixgbe_phy_generic
3633};
3634
3635/*
3636 * SFP+ module type IDs:
3637 *
3638 * ID Module Type
3639 * =============
3640 * 0 SFP_DA_CU
3641 * 1 SFP_SR
3642 * 2 SFP_LR
3643 * 3 SFP_DA_CU_CORE0 - 82599-specific
3644 * 4 SFP_DA_CU_CORE1 - 82599-specific
3645 * 5 SFP_SR/LR_CORE0 - 82599-specific
3646 * 6 SFP_SR/LR_CORE1 - 82599-specific
3647 */
3648enum ixgbe_sfp_type {
3649 ixgbe_sfp_type_da_cu = 0,
3650 ixgbe_sfp_type_sr = 1,
3651 ixgbe_sfp_type_lr = 2,
3652 ixgbe_sfp_type_da_cu_core0 = 3,
3653 ixgbe_sfp_type_da_cu_core1 = 4,
3654 ixgbe_sfp_type_srlr_core0 = 5,
3655 ixgbe_sfp_type_srlr_core1 = 6,
3656 ixgbe_sfp_type_da_act_lmt_core0 = 7,
3657 ixgbe_sfp_type_da_act_lmt_core1 = 8,
3658 ixgbe_sfp_type_1g_cu_core0 = 9,
3659 ixgbe_sfp_type_1g_cu_core1 = 10,
3660 ixgbe_sfp_type_1g_sx_core0 = 11,
3661 ixgbe_sfp_type_1g_sx_core1 = 12,
3662 ixgbe_sfp_type_1g_lx_core0 = 13,
3663 ixgbe_sfp_type_1g_lx_core1 = 14,
3664 ixgbe_sfp_type_not_present = 0xFFFE,
3665 ixgbe_sfp_type_unknown = 0xFFFF
3666};
3667
3668enum ixgbe_media_type {
3669 ixgbe_media_type_unknown = 0,
3670 ixgbe_media_type_fiber,
3671 ixgbe_media_type_fiber_fixed,
3672 ixgbe_media_type_fiber_qsfp,
3673 ixgbe_media_type_copper,
3674 ixgbe_media_type_backplane,
3675 ixgbe_media_type_cx4,
3676 ixgbe_media_type_virtual
3677};
3678
3679/* Flow Control Settings */
3680enum ixgbe_fc_mode {
3681 ixgbe_fc_none = 0,
3682 ixgbe_fc_rx_pause,
3683 ixgbe_fc_tx_pause,
3684 ixgbe_fc_full,
3685 ixgbe_fc_default
3686};
3687
3688/* Smart Speed Settings */
3689#define IXGBE_SMARTSPEED_MAX_RETRIES 3
3690enum ixgbe_smart_speed {
3691 ixgbe_smart_speed_auto = 0,
3692 ixgbe_smart_speed_on,
3693 ixgbe_smart_speed_off
3694};
3695
3696/* PCI bus types */
3697enum ixgbe_bus_type {
3698 ixgbe_bus_type_unknown = 0,
3699 ixgbe_bus_type_pci,
3700 ixgbe_bus_type_pcix,
3701 ixgbe_bus_type_pci_express,
3702 ixgbe_bus_type_internal,
3703 ixgbe_bus_type_reserved
3704};
3705
3706/* PCI bus speeds */
3707enum ixgbe_bus_speed {
3708 ixgbe_bus_speed_unknown = 0,
3709 ixgbe_bus_speed_33 = 33,
3710 ixgbe_bus_speed_66 = 66,
3711 ixgbe_bus_speed_100 = 100,
3712 ixgbe_bus_speed_120 = 120,
3713 ixgbe_bus_speed_133 = 133,
3714 ixgbe_bus_speed_2500 = 2500,
3715 ixgbe_bus_speed_5000 = 5000,
3716 ixgbe_bus_speed_8000 = 8000,
3717 ixgbe_bus_speed_reserved
3718};
3719
3720/* PCI bus widths */
3721enum ixgbe_bus_width {
3722 ixgbe_bus_width_unknown = 0,
3723 ixgbe_bus_width_pcie_x1 = 1,
3724 ixgbe_bus_width_pcie_x2 = 2,
3725 ixgbe_bus_width_pcie_x4 = 4,
3726 ixgbe_bus_width_pcie_x8 = 8,
3727 ixgbe_bus_width_32 = 32,
3728 ixgbe_bus_width_64 = 64,
3729 ixgbe_bus_width_reserved
3730};
3731
3732struct ixgbe_addr_filter_info {
3733 u32 num_mc_addrs;
3734 u32 rar_used_count;
3735 u32 mta_in_use;
3736 u32 overflow_promisc;
3737 bool user_set_promisc;
3738};
3739
3740/* Bus parameters */
3741struct ixgbe_bus_info {
3742 enum ixgbe_bus_speed speed;
3743 enum ixgbe_bus_width width;
3744 enum ixgbe_bus_type type;
3745
3746 u16 func;

~~3539~~ u16 lan_id;

3747 u8 lan_id;
3748 u16 instance_id;

3749};
3750
3751/* Flow control parameters */
3752struct ixgbe_fc_info {
3753 u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */
3754 u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */
3755 u16 pause_time; /* Flow Control Pause timer */
3756 bool send_xon; /* Flow control send XON */
3757 bool strict_ieee; /* Strict IEEE mode */
3758 bool disable_fc_autoneg; /* Do not autonegotiate FC */
3759 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
3760 enum ixgbe_fc_mode current_mode; /* FC mode in effect */
3761 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
3762};
3763
3764/* Statistics counters collected by the MAC */
3765struct ixgbe_hw_stats {
3766 u64 crcerrs;
3767 u64 illerrc;
3768 u64 errbc;
3769 u64 mspdc;
3770 u64 mpctotal;
3771 u64 mpc[8];
3772 u64 mlfc;
3773 u64 mrfc;
3774 u64 rlec;
3775 u64 lxontxc;
3776 u64 lxonrxc;
3777 u64 lxofftxc;
3778 u64 lxoffrxc;
3779 u64 pxontxc[8];
3780 u64 pxonrxc[8];
3781 u64 pxofftxc[8];
3782 u64 pxoffrxc[8];
3783 u64 prc64;
3784 u64 prc127;
3785 u64 prc255;
3786 u64 prc511;
3787 u64 prc1023;
3788 u64 prc1522;
3789 u64 gprc;
3790 u64 bprc;
3791 u64 mprc;
3792 u64 gptc;
3793 u64 gorc;
3794 u64 gotc;
3795 u64 rnbc[8];
3796 u64 ruc;
3797 u64 rfc;
3798 u64 roc;
3799 u64 rjc;
3800 u64 mngprc;
3801 u64 mngpdc;
3802 u64 mngptc;
3803 u64 tor;
3804 u64 tpr;
3805 u64 tpt;
3806 u64 ptc64;
3807 u64 ptc127;
3808 u64 ptc255;
3809 u64 ptc511;
3810 u64 ptc1023;
3811 u64 ptc1522;
3812 u64 mptc;
3813 u64 bptc;
3814 u64 xec;
3815 u64 qprc[16];
3816 u64 qptc[16];
3817 u64 qbrc[16];
3818 u64 qbtc[16];
3819 u64 qprdc[16];
3820 u64 pxon2offc[8];
3821 u64 fdirustat_add;
3822 u64 fdirustat_remove;
3823 u64 fdirfstat_fadd;
3824 u64 fdirfstat_fremove;
3825 u64 fdirmatch;
3826 u64 fdirmiss;
3827 u64 fccrc;
3828 u64 fclast;
3829 u64 fcoerpdc;
3830 u64 fcoeprc;
3831 u64 fcoeptc;
3832 u64 fcoedwrc;
3833 u64 fcoedwtc;
3834 u64 fcoe_noddp;
3835 u64 fcoe_noddp_ext_buff;
3836 u64 ldpcec;
3837 u64 pcrc8ec;
3838 u64 b2ospc;
3839 u64 b2ogprc;
3840 u64 o2bgptc;
3841 u64 o2bspc;
3842};
3843
3844/* forward declaration */
3845struct ixgbe_hw;
3846
3847/* iterator type for walking multicast address lists */
3848typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
3849 u32 *vmdq);
3850
3851/* Function pointer table */
3852struct ixgbe_eeprom_operations {
3853 s32 (*init_params)(struct ixgbe_hw *);
3854 s32 (*read)(struct ixgbe_hw *, u16, u16 *);
3855 s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
3856 s32 (*write)(struct ixgbe_hw *, u16, u16);
3857 s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
3858 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
3859 s32 (*update_checksum)(struct ixgbe_hw *);
3860 s32 (*calc_checksum)(struct ixgbe_hw *);
3861};
3862
3863struct ixgbe_mac_operations {
3864 s32 (*init_hw)(struct ixgbe_hw *);
3865 s32 (*reset_hw)(struct ixgbe_hw *);
3866 s32 (*start_hw)(struct ixgbe_hw *);
3867 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
3868 void (*enable_relaxed_ordering)(struct ixgbe_hw *);
3869 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);

~~3661~~ u32 (*get_supported_physical_layer)(struct ixgbe_hw *);

3870 u64 (*get_supported_physical_layer)(struct ixgbe_hw *);

3871 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
3872 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
3873 s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *);
3874 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
3875 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
3876 s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *);
3877 s32 (*stop_adapter)(struct ixgbe_hw *);
3878 s32 (*get_bus_info)(struct ixgbe_hw *);

3879 s32 (*negotiate_api_version)(struct ixgbe_hw *, int);

3880 void (*set_lan_id)(struct ixgbe_hw *);
3881 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
3882 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
3883 s32 (*setup_sfp)(struct ixgbe_hw *);
3884 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
3885 s32 (*disable_sec_rx_path)(struct ixgbe_hw *);
3886 s32 (*enable_sec_rx_path)(struct ixgbe_hw *);
3887 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32);
3888 void (*release_swfw_sync)(struct ixgbe_hw *, u32);

3889 void (*init_swfw_sync)(struct ixgbe_hw *);

3890 s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
3891 s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
3892
3893 /* Link */
3894 void (*disable_tx_laser)(struct ixgbe_hw *);
3895 void (*enable_tx_laser)(struct ixgbe_hw *);
3896 void (*flap_tx_laser)(struct ixgbe_hw *);
3897 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3898 s32 (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3899 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
3900 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
3901 bool *);
3902 void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed);
3903
3904 /* Packet Buffer manipulation */
3905 void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int);
3906
3907 /* LED */
3908 s32 (*led_on)(struct ixgbe_hw *, u32);
3909 s32 (*led_off)(struct ixgbe_hw *, u32);
3910 s32 (*blink_led_start)(struct ixgbe_hw *, u32);
3911 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);

3912 s32 (*init_led_link_act)(struct ixgbe_hw *);

3913
3914 /* RAR, Multicast, VLAN */
3915 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
3916 s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);
3917 s32 (*clear_rar)(struct ixgbe_hw *, u32);
3918 s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);
3919 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
3920 s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
3921 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
3922 s32 (*init_rx_addrs)(struct ixgbe_hw *);
3923 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
3924 ixgbe_mc_addr_itr);
3925 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
3926 ixgbe_mc_addr_itr, bool clear);

3927 s32 (*update_xcast_mode)(struct ixgbe_hw *, int);

3928 s32 (*enable_mc)(struct ixgbe_hw *);
3929 s32 (*disable_mc)(struct ixgbe_hw *);
3930 s32 (*clear_vfta)(struct ixgbe_hw *);

~~3718~~ s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
~~3719~~ s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, bool *);

3931 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool);
3932 s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, u32 *, u32,
3933 bool);
3934 s32 (*set_rlpml)(struct ixgbe_hw *, u16);

3935 s32 (*init_uta_tables)(struct ixgbe_hw *);
3936 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
3937 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
3938
3939 /* Flow Control */
3940 s32 (*fc_enable)(struct ixgbe_hw *);
3941 s32 (*setup_fc)(struct ixgbe_hw *);

3942 void (*fc_autoneg)(struct ixgbe_hw *);

3943
3944 /* Manageability interface */

~~3729~~ s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);

3945 s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8, u16,
3946 const char *);
3947 s32 (*bypass_rw) (struct ixgbe_hw *hw, u32 cmd, u32 *status);
3948 bool (*bypass_valid_rd) (u32 in_reg, u32 out_reg);
3949 s32 (*bypass_set) (struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action);
3950 s32 (*bypass_rd_eep) (struct ixgbe_hw *hw, u32 addr, u8 *value);

3951 void (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map);
3952 void (*disable_rx)(struct ixgbe_hw *hw);
3953 void (*enable_rx)(struct ixgbe_hw *hw);
3954 void (*set_source_address_pruning)(struct ixgbe_hw *, bool,
3955 unsigned int);
3956 void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int);
3957 s32 (*dmac_update_tcs)(struct ixgbe_hw *hw);
3958 s32 (*dmac_config_tcs)(struct ixgbe_hw *hw);
3959 s32 (*dmac_config)(struct ixgbe_hw *hw);
3960 s32 (*setup_eee)(struct ixgbe_hw *hw, bool enable_eee);
3961 s32 (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *);
3962 s32 (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32);
3963 void (*disable_mdd)(struct ixgbe_hw *hw);
3964 void (*enable_mdd)(struct ixgbe_hw *hw);
3965 void (*mdd_event)(struct ixgbe_hw *hw, u32 *vf_bitmap);
3966 void (*restore_mdd_vf)(struct ixgbe_hw *hw, u32 vf);
3967};
3968
3969struct ixgbe_phy_operations {
3970 s32 (*identify)(struct ixgbe_hw *);
3971 s32 (*identify_sfp)(struct ixgbe_hw *);
3972 s32 (*init)(struct ixgbe_hw *);
3973 s32 (*reset)(struct ixgbe_hw *);
3974 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
3975 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
3976 s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);
3977 s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);
3978 s32 (*setup_link)(struct ixgbe_hw *);
3979 s32 (*setup_internal_link)(struct ixgbe_hw *);
3980 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3981 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
3982 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
3983 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
3984 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
3985 s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);
3986 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
3987 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
3988 void (*i2c_bus_clear)(struct ixgbe_hw *);

~~3768~~ s32 (*read_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);
~~3769~~ s32 (*write_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);

3989 s32 (*check_overtemp)(struct ixgbe_hw *);
3990 s32 (*set_phy_power)(struct ixgbe_hw *, bool on);
3991 s32 (*enter_lplu)(struct ixgbe_hw *);
3992 s32 (*handle_lasi)(struct ixgbe_hw *hw);

~~3774~~ s32 (*read_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
~~3775~~ u16 *value);
~~3776~~ s32 (*write_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
~~3777~~ u16 value);

3993 s32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
3994 u8 *value);
3995 s32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
3996 u8 value);
3997};
3998

3999struct ixgbe_link_operations {
4000 s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);
4001 s32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
4002 u16 *val);
4003 s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);
4004 s32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
4005 u16 val);
4006};
4007
4008struct ixgbe_link_info {
4009 struct ixgbe_link_operations ops;
4010 u8 addr;
4011};
4012

4013struct ixgbe_eeprom_info {
4014 struct ixgbe_eeprom_operations ops;
4015 enum ixgbe_eeprom_type type;
4016 u32 semaphore_delay;
4017 u16 word_size;
4018 u16 address_bits;
4019 u16 word_page_size;
4020 u16 ctrl_word_3;
4021};
4022
4023#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
4024struct ixgbe_mac_info {
4025 struct ixgbe_mac_operations ops;
4026 enum ixgbe_mac_type type;
4027 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
4028 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
4029 u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
4030 /* prefix for World Wide Node Name (WWNN) */
4031 u16 wwnn_prefix;
4032 /* prefix for World Wide Port Name (WWPN) */
4033 u16 wwpn_prefix;
4034#define IXGBE_MAX_MTA 128
4035 u32 mta_shadow[IXGBE_MAX_MTA];
4036 s32 mc_filter_type;
4037 u32 mcft_size;
4038 u32 vft_size;
4039 u32 num_rar_entries;
4040 u32 rar_highwater;
4041 u32 rx_pb_size;
4042 u32 max_tx_queues;
4043 u32 max_rx_queues;
4044 u32 orig_autoc;
4045 u8 san_mac_rar_index;
4046 bool get_link_status;
4047 u32 orig_autoc2;
4048 u16 max_msix_vectors;
4049 bool arc_subsystem_valid;
4050 bool orig_link_settings_stored;
4051 bool autotry_restart;
4052 u8 flags;
4053 struct ixgbe_dmac_config dmac_config;
4054 bool set_lben;
4055 u32 max_link_up_time;

4056 u8 led_link_act;

4057};
4058
4059struct ixgbe_phy_info {
4060 struct ixgbe_phy_operations ops;
4061 enum ixgbe_phy_type type;
4062 u32 addr;
4063 u32 id;
4064 enum ixgbe_sfp_type sfp_type;
4065 bool sfp_setup_needed;
4066 u32 revision;
4067 enum ixgbe_media_type media_type;
4068 u32 phy_semaphore_mask;
4069 bool reset_disable;
4070 ixgbe_autoneg_advertised autoneg_advertised;
4071 ixgbe_link_speed speeds_supported;

4072 ixgbe_link_speed eee_speeds_supported;
4073 ixgbe_link_speed eee_speeds_advertised;

4074 enum ixgbe_smart_speed smart_speed;
4075 bool smart_speed_active;
4076 bool multispeed_fiber;
4077 bool reset_if_overtemp;
4078 bool qsfp_shared_i2c_bus;
4079 u32 nw_mng_if_sel;
4080};
4081
4082#include "ixgbe_mbx.h"
4083
4084struct ixgbe_mbx_operations {
4085 void (*init_params)(struct ixgbe_hw *hw);
4086 s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);
4087 s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
4088 s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);
4089 s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
4090 s32 (*check_for_msg)(struct ixgbe_hw *, u16);
4091 s32 (*check_for_ack)(struct ixgbe_hw *, u16);
4092 s32 (*check_for_rst)(struct ixgbe_hw *, u16);
4093};
4094
4095struct ixgbe_mbx_stats {
4096 u32 msgs_tx;
4097 u32 msgs_rx;
4098
4099 u32 acks;
4100 u32 reqs;
4101 u32 rsts;
4102};
4103
4104struct ixgbe_mbx_info {
4105 struct ixgbe_mbx_operations ops;
4106 struct ixgbe_mbx_stats stats;
4107 u32 timeout;
4108 u32 usec_delay;
4109 u32 v2p_mailbox;
4110 u16 size;
4111};
4112
4113struct ixgbe_hw {
4114 u8 IOMEM *hw_addr;
4115 void *back;
4116 struct ixgbe_mac_info mac;
4117 struct ixgbe_addr_filter_info addr_ctrl;
4118 struct ixgbe_fc_info fc;
4119 struct ixgbe_phy_info phy;

4120 struct ixgbe_link_info link;

4121 struct ixgbe_eeprom_info eeprom;
4122 struct ixgbe_bus_info bus;
4123 struct ixgbe_mbx_info mbx;
4124 const u32 *mvals;
4125 u16 device_id;
4126 u16 vendor_id;
4127 u16 subsystem_device_id;
4128 u16 subsystem_vendor_id;
4129 u8 revision_id;
4130 bool adapter_stopped;
4131 int api_version;
4132 bool force_full_reset;
4133 bool allow_unsupported_sfp;
4134 bool wol_enabled;

4135 bool need_crosstalk_fix;

4136};
4137
4138#define ixgbe_call_func(hw, func, params, error) \
4139 (func != NULL) ? func params : error
4140
4141
4142/* Error Codes */
4143#define IXGBE_SUCCESS 0
4144#define IXGBE_ERR_EEPROM -1
4145#define IXGBE_ERR_EEPROM_CHECKSUM -2
4146#define IXGBE_ERR_PHY -3
4147#define IXGBE_ERR_CONFIG -4
4148#define IXGBE_ERR_PARAM -5
4149#define IXGBE_ERR_MAC_TYPE -6
4150#define IXGBE_ERR_UNKNOWN_PHY -7
4151#define IXGBE_ERR_LINK_SETUP -8
4152#define IXGBE_ERR_ADAPTER_STOPPED -9
4153#define IXGBE_ERR_INVALID_MAC_ADDR -10
4154#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
4155#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
4156#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
4157#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
4158#define IXGBE_ERR_RESET_FAILED -15
4159#define IXGBE_ERR_SWFW_SYNC -16
4160#define IXGBE_ERR_PHY_ADDR_INVALID -17
4161#define IXGBE_ERR_I2C -18
4162#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
4163#define IXGBE_ERR_SFP_NOT_PRESENT -20
4164#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
4165#define IXGBE_ERR_NO_SAN_ADDR_PTR -22
4166#define IXGBE_ERR_FDIR_REINIT_FAILED -23
4167#define IXGBE_ERR_EEPROM_VERSION -24
4168#define IXGBE_ERR_NO_SPACE -25
4169#define IXGBE_ERR_OVERTEMP -26
4170#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
4171#define IXGBE_ERR_FC_NOT_SUPPORTED -28
4172#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
4173#define IXGBE_ERR_PBA_SECTION -31
4174#define IXGBE_ERR_INVALID_ARGUMENT -32
4175#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
4176#define IXGBE_ERR_OUT_OF_MEM -34

4177#define IXGBE_BYPASS_FW_WRITE_FAILURE -35

4178#define IXGBE_ERR_FEATURE_NOT_SUPPORTED -36
4179#define IXGBE_ERR_EEPROM_PROTECTED_REGION -37
4180#define IXGBE_ERR_FDIR_CMD_INCOMPLETE -38

4181#define IXGBE_ERR_FW_RESP_INVALID -39
4182#define IXGBE_ERR_TOKEN_RETRY -40

4183
4184#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
4185
4186

4187#define BYPASS_PAGE_CTL0 0x00000000
4188#define BYPASS_PAGE_CTL1 0x40000000
4189#define BYPASS_PAGE_CTL2 0x80000000
4190#define BYPASS_PAGE_M 0xc0000000
4191#define BYPASS_WE 0x20000000
4192
4193#define BYPASS_AUTO 0x0
4194#define BYPASS_NOP 0x0
4195#define BYPASS_NORM 0x1
4196#define BYPASS_BYPASS 0x2
4197#define BYPASS_ISOLATE 0x3
4198
4199#define BYPASS_EVENT_MAIN_ON 0x1
4200#define BYPASS_EVENT_AUX_ON 0x2
4201#define BYPASS_EVENT_MAIN_OFF 0x3
4202#define BYPASS_EVENT_AUX_OFF 0x4
4203#define BYPASS_EVENT_WDT_TO 0x5
4204#define BYPASS_EVENT_USR 0x6
4205
4206#define BYPASS_MODE_OFF_M 0x00000003
4207#define BYPASS_STATUS_OFF_M 0x0000000c
4208#define BYPASS_AUX_ON_M 0x00000030
4209#define BYPASS_MAIN_ON_M 0x000000c0
4210#define BYPASS_MAIN_OFF_M 0x00000300
4211#define BYPASS_AUX_OFF_M 0x00000c00
4212#define BYPASS_WDTIMEOUT_M 0x00003000
4213#define BYPASS_WDT_ENABLE_M 0x00004000
4214#define BYPASS_WDT_VALUE_M 0x00070000
4215
4216#define BYPASS_MODE_OFF_SHIFT 0
4217#define BYPASS_STATUS_OFF_SHIFT 2
4218#define BYPASS_AUX_ON_SHIFT 4
4219#define BYPASS_MAIN_ON_SHIFT 6
4220#define BYPASS_MAIN_OFF_SHIFT 8
4221#define BYPASS_AUX_OFF_SHIFT 10
4222#define BYPASS_WDTIMEOUT_SHIFT 12
4223#define BYPASS_WDT_ENABLE_SHIFT 14
4224#define BYPASS_WDT_TIME_SHIFT 16
4225
4226#define BYPASS_WDT_1 0x0
4227#define BYPASS_WDT_1_5 0x1
4228#define BYPASS_WDT_2 0x2
4229#define BYPASS_WDT_3 0x3
4230#define BYPASS_WDT_4 0x4
4231#define BYPASS_WDT_8 0x5
4232#define BYPASS_WDT_16 0x6
4233#define BYPASS_WDT_32 0x7
4234#define BYPASS_WDT_OFF 0xffff
4235
4236#define BYPASS_CTL1_TIME_M 0x01ffffff
4237#define BYPASS_CTL1_VALID_M 0x02000000
4238#define BYPASS_CTL1_OFFTRST_M 0x04000000
4239#define BYPASS_CTL1_WDT_PET_M 0x08000000
4240
4241#define BYPASS_CTL1_VALID 0x02000000
4242#define BYPASS_CTL1_OFFTRST 0x04000000
4243#define BYPASS_CTL1_WDT_PET 0x08000000
4244
4245#define BYPASS_CTL2_DATA_M 0x000000ff
4246#define BYPASS_CTL2_OFFSET_M 0x0000ff00
4247#define BYPASS_CTL2_RW_M 0x00010000
4248#define BYPASS_CTL2_HEAD_M 0x0ff00000
4249
4250#define BYPASS_CTL2_OFFSET_SHIFT 8
4251#define BYPASS_CTL2_HEAD_SHIFT 20
4252
4253#define BYPASS_CTL2_RW 0x00010000
4254
4255struct ixgbe_bypass_eeprom {
4256 u32 logs;
4257 u32 clear_off;
4258 u8 actions;
4259};
4260
4261#define BYPASS_MAX_LOGS 43
4262#define BYPASS_LOG_SIZE 5
4263#define BYPASS_LOG_LINE_SIZE 37
4264
4265#define BYPASS_EEPROM_VER_ADD 0x02
4266
4267#define BYPASS_LOG_TIME_M 0x01ffffff
4268#define BYPASS_LOG_TIME_VALID_M 0x02000000
4269#define BYPASS_LOG_HEAD_M 0x04000000
4270#define BYPASS_LOG_CLEAR_M 0x08000000
4271#define BYPASS_LOG_EVENT_M 0xf0000000
4272#define BYPASS_LOG_ACTION_M 0x03
4273
4274#define BYPASS_LOG_EVENT_SHIFT 28
4275#define BYPASS_LOG_CLEAR_SHIFT 24 /* bit offset */
4276
4277

4278#define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4))
4279#define IXGBE_FUSES0_300MHZ (1 << 5)

~~3952~~#define IXGBE_FUSES0_REV1 (1 << 6)

4280#define IXGBE_FUSES0_REV_MASK (3 << 6)

4281
4282#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)

4283#define IXGBE_KRM_LINK_S1(P) ((P) ? 0x8200 : 0x4200)

4284#define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)
4285#define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C)

4286#define IXGBE_KRM_AN_CNTL_4(P) ((P) ? 0x8238 : 0x4238)
4287#define IXGBE_KRM_AN_CNTL_8(P) ((P) ? 0x8248 : 0x4248)
4288#define IXGBE_KRM_PCS_KX_AN(P) ((P) ? 0x9918 : 0x5918)
4289#define IXGBE_KRM_PCS_KX_AN_LP(P) ((P) ? 0x991C : 0x591C)
4290#define IXGBE_KRM_SGMII_CTRL(P) ((P) ? 0x82A0 : 0x42A0)
4291#define IXGBE_KRM_LP_BASE_PAGE_HIGH(P) ((P) ? 0x836C : 0x436C)

4292#define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634)
4293#define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638)
4294#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00)
4295#define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00)

4296#define IXGBE_KRM_PMD_FLX_MASK_ST20(P) ((P) ? 0x9054 : 0x5054)

4297#define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520)
4298#define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00)
4299

4300#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA ~(0x3 << 20)
4301#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR (1u << 20)
4302#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_LR (0x2 << 20)
4303#define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN (1u << 25)
4304#define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN (1u << 26)
4305#define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN (1u << 27)
4306#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M ~(0x7 << 28)
4307#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M (1u << 28)
4308#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G (0x2 << 28)
4309#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G (0x3 << 28)
4310#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN (0x4 << 28)
4311#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G (0x7 << 28)
4312#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK (0x7 << 28)
4313#define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART (1u << 31)
4314

4315#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9)
4316#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11)
4317
4318#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8)
4319#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8)
4320#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8)

4321#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN (1 << 12)
4322#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN (1 << 13)

4323#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14)
4324#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15)
4325#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16)
4326#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18)
4327#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24)
4328#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26)

4329#define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE (1 << 28)

4330#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29)
4331#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31)
4332
4333#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE (1 << 28)
4334#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE (1 << 29)

4335#define IXGBE_KRM_PCS_KX_AN_SYM_PAUSE (1 << 1)
4336#define IXGBE_KRM_PCS_KX_AN_ASM_PAUSE (1 << 2)
4337#define IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE (1 << 2)
4338#define IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE (1 << 3)
4339#define IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73 (1 << 29)
4340#define IXGBE_KRM_AN_CNTL_8_LINEAR (1 << 0)
4341#define IXGBE_KRM_AN_CNTL_8_LIMITING (1 << 1)

4342

4343#define IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE (1 << 10)
4344#define IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE (1 << 11)
4345
4346#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D (1 << 12)
4347#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D (1 << 19)
4348

4349#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6)
4350#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15)
4351#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16)
4352
4353#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4)
4354#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2)
4355
4356#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16)
4357
4358#define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN (1 << 1)
4359#define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN (1 << 2)
4360#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN (1 << 3)
4361#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1 << 31)
4362
4363#define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144
4364#define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148
4365
4366#define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT 0
4367#define IXGBE_SB_IOSF_CTRL_ADDR_MASK 0xFF
4368#define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT 18
4369#define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \
4370 (0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT)
4371#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT 20
4372#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \
4373 (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
4374#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28
4375#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7
4376#define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31
4377#define IXGBE_SB_IOSF_CTRL_BUSY (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
4378#define IXGBE_SB_IOSF_TARGET_KR_PHY 0
4379
4380#define IXGBE_NW_MNG_IF_SEL 0x00011178

~~4014~~#define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24)

4381#define IXGBE_NW_MNG_IF_SEL_MDIO_ACT (1u << 1)
4382#define IXGBE_NW_MNG_IF_SEL_MDIO_IF_MODE (1u << 2)
4383#define IXGBE_NW_MNG_IF_SEL_EN_SHARED_MDIO (1u << 13)
4384#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M (1u << 17)
4385#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M (1u << 18)
4386#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G (1u << 19)
4387#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G (1u << 20)
4388#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G (1u << 21)
4389#define IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE (1u << 25)
4390#define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24) /* X552 reg field only */
4391#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3
4392#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \
4393 (0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)

4394
4395#endif /* _IXGBE_TYPE_H_ */