| ixgbe_phy.h (230775) | ixgbe_phy.h (247822) |
|---|---|
| 1/****************************************************************************** 2 | 1/****************************************************************************** 2 |
| 3 Copyright (c) 2001-2012, Intel Corporation | 3 Copyright (c) 2001-2013, Intel Corporation |
| 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 --- 13 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ | 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 --- 13 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.h 230775 2012-01-30 16:42:02Z jfv $*/ | 33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.h 247822 2013-03-04 23:07:40Z jfv $*/ |
| 34 35#ifndef _IXGBE_PHY_H_ 36#define _IXGBE_PHY_H_ 37 38#include "ixgbe_type.h" | 34 35#ifndef _IXGBE_PHY_H_ 36#define _IXGBE_PHY_H_ 37 38#include "ixgbe_type.h" |
| 39#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0 | 39#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0 40#define IXGBE_I2C_EEPROM_DEV_ADDR2 0xA2 41#define IXGBE_I2C_EEPROM_BANK_LEN 0xFF |
| 40 41/* EEPROM byte offsets */ 42#define IXGBE_SFF_IDENTIFIER 0x0 43#define IXGBE_SFF_IDENTIFIER_SFP 0x3 44#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25 45#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26 46#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27 47#define IXGBE_SFF_1GBE_COMP_CODES 0x6 48#define IXGBE_SFF_10GBE_COMP_CODES 0x3 49#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8 50#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C | 42 43/* EEPROM byte offsets */ 44#define IXGBE_SFF_IDENTIFIER 0x0 45#define IXGBE_SFF_IDENTIFIER_SFP 0x3 46#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25 47#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26 48#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27 49#define IXGBE_SFF_1GBE_COMP_CODES 0x6 50#define IXGBE_SFF_10GBE_COMP_CODES 0x3 51#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8 52#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C |
| 53#define IXGBE_SFF_SFF_8472_SWAP 0x5C 54#define IXGBE_SFF_SFF_8472_COMP 0x5E 55#define IXGBE_SFF_SFF_8472_OSCB 0x6E 56#define IXGBE_SFF_SFF_8472_ESCB 0x76 |
|
| 51 52/* Bitmasks */ 53#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4 54#define IXGBE_SFF_DA_ACTIVE_CABLE 0x8 55#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4 56#define IXGBE_SFF_1GBASESX_CAPABLE 0x1 57#define IXGBE_SFF_1GBASELX_CAPABLE 0x2 58#define IXGBE_SFF_1GBASET_CAPABLE 0x8 59#define IXGBE_SFF_10GBASESR_CAPABLE 0x10 60#define IXGBE_SFF_10GBASELR_CAPABLE 0x20 | 57 58/* Bitmasks */ 59#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4 60#define IXGBE_SFF_DA_ACTIVE_CABLE 0x8 61#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4 62#define IXGBE_SFF_1GBASESX_CAPABLE 0x1 63#define IXGBE_SFF_1GBASELX_CAPABLE 0x2 64#define IXGBE_SFF_1GBASET_CAPABLE 0x8 65#define IXGBE_SFF_10GBASESR_CAPABLE 0x10 66#define IXGBE_SFF_10GBASELR_CAPABLE 0x20 |
| 67#define IXGBE_SFF_SOFT_RS_SELECT_MASK 0x8 68#define IXGBE_SFF_SOFT_RS_SELECT_10G 0x8 69#define IXGBE_SFF_SOFT_RS_SELECT_1G 0x0 |
|
| 61#define IXGBE_I2C_EEPROM_READ_MASK 0x100 62#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 63#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 64#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 65#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 66#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 67 68/* Flow control defines */ --- 21 unchanged lines hidden (view full) --- 90#define IXGBE_I2C_T_RISE 1 91#define IXGBE_I2C_T_FALL 1 92#define IXGBE_I2C_T_SU_STO 4 93#define IXGBE_I2C_T_BUF 5 94 95#define IXGBE_TN_LASI_STATUS_REG 0x9005 96#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008 97 | 70#define IXGBE_I2C_EEPROM_READ_MASK 0x100 71#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 72#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 73#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 74#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 75#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 76 77/* Flow control defines */ --- 21 unchanged lines hidden (view full) --- 99#define IXGBE_I2C_T_RISE 1 100#define IXGBE_I2C_T_FALL 1 101#define IXGBE_I2C_T_SU_STO 4 102#define IXGBE_I2C_T_BUF 5 103 104#define IXGBE_TN_LASI_STATUS_REG 0x9005 105#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008 106 |
| 107/* SFP+ SFF-8472 Compliance */ 108#define IXGBE_SFF_SFF_8472_UNSUP 0x00 109#define IXGBE_SFF_SFF_8472_REV_9_3 0x01 110#define IXGBE_SFF_SFF_8472_REV_9_5 0x02 111#define IXGBE_SFF_SFF_8472_REV_10_2 0x03 112#define IXGBE_SFF_SFF_8472_REV_10_4 0x04 113#define IXGBE_SFF_SFF_8472_REV_11_0 0x05 114 |
|
| 98s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); 99bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr); 100enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 101s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 102s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); 103s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw); 104s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 105 u32 device_type, u16 *phy_data); 106s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 107 u32 device_type, u16 phy_data); 108s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw); 109s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 110 ixgbe_link_speed speed, | 115s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); 116bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr); 117enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 118s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 119s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); 120s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw); 121s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 122 u32 device_type, u16 *phy_data); 123s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 124 u32 device_type, u16 phy_data); 125s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw); 126s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 127 ixgbe_link_speed speed, |
| 111 bool autoneg, | |
| 112 bool autoneg_wait_to_complete); 113s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 114 ixgbe_link_speed *speed, 115 bool *autoneg); 116 117/* PHY specific */ 118s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, 119 ixgbe_link_speed *speed, --- 24 unchanged lines hidden --- | 128 bool autoneg_wait_to_complete); 129s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 130 ixgbe_link_speed *speed, 131 bool *autoneg); 132 133/* PHY specific */ 134s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, 135 ixgbe_link_speed *speed, --- 24 unchanged lines hidden --- |